1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_TIM_H 22 #define STM32L4xx_HAL_TIM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TIM_Exported_Types TIM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TIM Time base Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 58 59 uint32_t ClockDivision; /*!< Specifies the clock division. 60 This parameter can be a value of @ref TIM_ClockDivision */ 61 62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 63 reaches zero, an update event is generated and counting restarts 64 from the RCR value (N). 65 This means in PWM mode that (N+1) corresponds to: 66 - the number of PWM periods in edge-aligned mode 67 - the number of half PWM period in center-aligned mode 68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 70 71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 72 This parameter can be a value of @ref TIM_AutoReloadPreload */ 73 } TIM_Base_InitTypeDef; 74 75 /** 76 * @brief TIM Output Compare Configuration Structure definition 77 */ 78 typedef struct 79 { 80 uint32_t OCMode; /*!< Specifies the TIM mode. 81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 82 83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 85 86 uint32_t OCPolarity; /*!< Specifies the output polarity. 87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 88 89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 91 @note This parameter is valid only for timer instances supporting break feature. */ 92 93 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 94 This parameter can be a value of @ref TIM_Output_Fast_State 95 @note This parameter is valid only in PWM1 and PWM2 mode. */ 96 97 98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 100 @note This parameter is valid only for timer instances supporting break feature. */ 101 102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 104 @note This parameter is valid only for timer instances supporting break feature. */ 105 } TIM_OC_InitTypeDef; 106 107 /** 108 * @brief TIM One Pulse Mode Configuration Structure definition 109 */ 110 typedef struct 111 { 112 uint32_t OCMode; /*!< Specifies the TIM mode. 113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 114 115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 117 118 uint32_t OCPolarity; /*!< Specifies the output polarity. 119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 120 121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 123 @note This parameter is valid only for timer instances supporting break feature. */ 124 125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 127 @note This parameter is valid only for timer instances supporting break feature. */ 128 129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 131 @note This parameter is valid only for timer instances supporting break feature. */ 132 133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 135 136 uint32_t ICSelection; /*!< Specifies the input. 137 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 138 139 uint32_t ICFilter; /*!< Specifies the input capture filter. 140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 141 } TIM_OnePulse_InitTypeDef; 142 143 /** 144 * @brief TIM Input Capture Configuration Structure definition 145 */ 146 typedef struct 147 { 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 150 151 uint32_t ICSelection; /*!< Specifies the input. 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 153 154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 156 157 uint32_t ICFilter; /*!< Specifies the input capture filter. 158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 159 } TIM_IC_InitTypeDef; 160 161 /** 162 * @brief TIM Encoder Configuration Structure definition 163 */ 164 typedef struct 165 { 166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 167 This parameter can be a value of @ref TIM_Encoder_Mode */ 168 169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 170 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 171 172 uint32_t IC1Selection; /*!< Specifies the input. 173 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 174 175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 177 178 uint32_t IC1Filter; /*!< Specifies the input capture filter. 179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 180 181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 182 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 183 184 uint32_t IC2Selection; /*!< Specifies the input. 185 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 186 187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 189 190 uint32_t IC2Filter; /*!< Specifies the input capture filter. 191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 192 } TIM_Encoder_InitTypeDef; 193 194 /** 195 * @brief Clock Configuration Handle Structure definition 196 */ 197 typedef struct 198 { 199 uint32_t ClockSource; /*!< TIM clock sources 200 This parameter can be a value of @ref TIM_Clock_Source */ 201 uint32_t ClockPolarity; /*!< TIM clock polarity 202 This parameter can be a value of @ref TIM_Clock_Polarity */ 203 uint32_t ClockPrescaler; /*!< TIM clock prescaler 204 This parameter can be a value of @ref TIM_Clock_Prescaler */ 205 uint32_t ClockFilter; /*!< TIM clock filter 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 207 } TIM_ClockConfigTypeDef; 208 209 /** 210 * @brief TIM Clear Input Configuration Handle Structure definition 211 */ 212 typedef struct 213 { 214 uint32_t ClearInputState; /*!< TIM clear Input state 215 This parameter can be ENABLE or DISABLE */ 216 uint32_t ClearInputSource; /*!< TIM clear Input sources 217 This parameter can be a value of @ref TIM_ClearInput_Source */ 218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 219 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 224 } TIM_ClearInputConfigTypeDef; 225 226 /** 227 * @brief TIM Master configuration Structure definition 228 * @note Advanced timers provide TRGO2 internal line which is redirected 229 * to the ADC 230 */ 231 typedef struct 232 { 233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 234 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 238 This parameter can be a value of @ref TIM_Master_Slave_Mode 239 @note When the Master/slave mode is enabled, the effect of 240 an event on the trigger input (TRGI) is delayed to allow a 241 perfect synchronization between the current timer and its 242 slaves (through TRGO). It is not mandatory in case of timer 243 synchronization mode. */ 244 } TIM_MasterConfigTypeDef; 245 246 /** 247 * @brief TIM Slave configuration Structure definition 248 */ 249 typedef struct 250 { 251 uint32_t SlaveMode; /*!< Slave mode selection 252 This parameter can be a value of @ref TIM_Slave_Mode */ 253 uint32_t InputTrigger; /*!< Input Trigger source 254 This parameter can be a value of @ref TIM_Trigger_Selection */ 255 uint32_t TriggerPolarity; /*!< Input Trigger polarity 256 This parameter can be a value of @ref TIM_Trigger_Polarity */ 257 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 258 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 259 uint32_t TriggerFilter; /*!< Input trigger filter 260 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 261 262 } TIM_SlaveConfigTypeDef; 263 264 /** 265 * @brief TIM Break input(s) and Dead time configuration Structure definition 266 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 267 * filter and polarity. 268 */ 269 typedef struct 270 { 271 uint32_t OffStateRunMode; /*!< TIM off state in run mode 272 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 273 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 274 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 275 uint32_t LockLevel; /*!< TIM Lock level 276 This parameter can be a value of @ref TIM_Lock_level */ 277 uint32_t DeadTime; /*!< TIM dead Time 278 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 279 uint32_t BreakState; /*!< TIM Break State 280 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 281 uint32_t BreakPolarity; /*!< TIM Break input polarity 282 This parameter can be a value of @ref TIM_Break_Polarity */ 283 uint32_t BreakFilter; /*!< Specifies the break input filter. 284 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 285 uint32_t Break2State; /*!< TIM Break2 State 286 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 287 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 288 This parameter can be a value of @ref TIM_Break2_Polarity */ 289 uint32_t Break2Filter; /*!< TIM break2 input filter. 290 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 291 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 292 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 293 } TIM_BreakDeadTimeConfigTypeDef; 294 295 /** 296 * @brief HAL State structures definition 297 */ 298 typedef enum 299 { 300 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 301 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 302 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 303 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 304 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 305 } HAL_TIM_StateTypeDef; 306 307 /** 308 * @brief HAL Active channel structures definition 309 */ 310 typedef enum 311 { 312 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 313 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 314 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 315 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 316 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 317 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 318 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 319 } HAL_TIM_ActiveChannel; 320 321 /** 322 * @brief TIM Time Base Handle Structure definition 323 */ 324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 325 typedef struct __TIM_HandleTypeDef 326 #else 327 typedef struct 328 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 329 { 330 TIM_TypeDef *Instance; /*!< Register base address */ 331 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 332 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 333 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 334 This array is accessed by a @ref DMA_Handle_index */ 335 HAL_LockTypeDef Lock; /*!< Locking object */ 336 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 337 338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 339 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 340 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 341 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 342 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 343 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 344 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 345 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 346 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 347 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 348 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 349 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 350 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 351 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 352 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 353 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 354 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 355 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 356 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 357 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 358 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 359 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 360 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 361 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 362 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 363 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 364 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 365 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 366 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 368 } TIM_HandleTypeDef; 369 370 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 371 /** 372 * @brief HAL TIM Callback ID enumeration definition 373 */ 374 typedef enum 375 { 376 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 377 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 378 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 379 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 380 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 381 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 382 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 383 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 384 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 385 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 386 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 387 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 388 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 389 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 390 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 391 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 392 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 393 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 394 395 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 396 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 397 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 398 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 399 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 400 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 401 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 402 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 403 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 404 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 405 } HAL_TIM_CallbackIDTypeDef; 406 407 /** 408 * @brief HAL TIM Callback pointer definition 409 */ 410 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 411 412 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 413 414 /** 415 * @} 416 */ 417 /* End of exported types -----------------------------------------------------*/ 418 419 /* Exported constants --------------------------------------------------------*/ 420 /** @defgroup TIM_Exported_Constants TIM Exported Constants 421 * @{ 422 */ 423 424 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 425 * @{ 426 */ 427 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 428 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 429 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 435 * @{ 436 */ 437 #define TIM_DMABASE_CR1 0x00000000U 438 #define TIM_DMABASE_CR2 0x00000001U 439 #define TIM_DMABASE_SMCR 0x00000002U 440 #define TIM_DMABASE_DIER 0x00000003U 441 #define TIM_DMABASE_SR 0x00000004U 442 #define TIM_DMABASE_EGR 0x00000005U 443 #define TIM_DMABASE_CCMR1 0x00000006U 444 #define TIM_DMABASE_CCMR2 0x00000007U 445 #define TIM_DMABASE_CCER 0x00000008U 446 #define TIM_DMABASE_CNT 0x00000009U 447 #define TIM_DMABASE_PSC 0x0000000AU 448 #define TIM_DMABASE_ARR 0x0000000BU 449 #define TIM_DMABASE_RCR 0x0000000CU 450 #define TIM_DMABASE_CCR1 0x0000000DU 451 #define TIM_DMABASE_CCR2 0x0000000EU 452 #define TIM_DMABASE_CCR3 0x0000000FU 453 #define TIM_DMABASE_CCR4 0x00000010U 454 #define TIM_DMABASE_BDTR 0x00000011U 455 #define TIM_DMABASE_DCR 0x00000012U 456 #define TIM_DMABASE_DMAR 0x00000013U 457 #define TIM_DMABASE_OR1 0x00000014U 458 #define TIM_DMABASE_CCMR3 0x00000015U 459 #define TIM_DMABASE_CCR5 0x00000016U 460 #define TIM_DMABASE_CCR6 0x00000017U 461 #define TIM_DMABASE_OR2 0x00000018U 462 #define TIM_DMABASE_OR3 0x00000019U 463 /** 464 * @} 465 */ 466 467 /** @defgroup TIM_Event_Source TIM Event Source 468 * @{ 469 */ 470 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 471 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 472 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 473 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 474 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 475 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 476 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 477 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 478 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 479 /** 480 * @} 481 */ 482 483 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 484 * @{ 485 */ 486 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 487 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 488 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 494 * @{ 495 */ 496 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 497 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 498 /** 499 * @} 500 */ 501 502 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 503 * @{ 504 */ 505 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 506 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 507 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 508 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 509 /** 510 * @} 511 */ 512 513 /** @defgroup TIM_Counter_Mode TIM Counter Mode 514 * @{ 515 */ 516 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 517 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 518 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 519 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 520 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 521 /** 522 * @} 523 */ 524 525 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 526 * @{ 527 */ 528 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 529 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 530 /** 531 * @} 532 */ 533 534 /** @defgroup TIM_ClockDivision TIM Clock Division 535 * @{ 536 */ 537 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 538 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 539 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 540 /** 541 * @} 542 */ 543 544 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 545 * @{ 546 */ 547 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 548 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 554 * @{ 555 */ 556 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 557 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 558 559 /** 560 * @} 561 */ 562 563 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 564 * @{ 565 */ 566 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 567 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 573 * @{ 574 */ 575 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 576 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 582 * @{ 583 */ 584 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 585 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 591 * @{ 592 */ 593 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 594 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 600 * @{ 601 */ 602 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 603 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 604 /** 605 * @} 606 */ 607 608 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 609 * @{ 610 */ 611 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 612 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 613 /** 614 * @} 615 */ 616 617 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 618 * @{ 619 */ 620 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 621 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 622 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 623 /** 624 * @} 625 */ 626 627 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 628 * @{ 629 */ 630 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 631 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 632 /** 633 * @} 634 */ 635 636 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 637 * @{ 638 */ 639 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 640 connected to IC1, IC2, IC3 or IC4, respectively */ 641 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 642 connected to IC2, IC1, IC4 or IC3, respectively */ 643 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 644 /** 645 * @} 646 */ 647 648 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 649 * @{ 650 */ 651 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 652 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 653 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 654 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 660 * @{ 661 */ 662 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 663 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 664 /** 665 * @} 666 */ 667 668 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 669 * @{ 670 */ 671 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 672 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 673 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 674 /** 675 * @} 676 */ 677 678 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 679 * @{ 680 */ 681 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 682 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 683 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 684 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 685 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 686 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 687 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 688 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup TIM_Commutation_Source TIM Commutation Source 694 * @{ 695 */ 696 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 697 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup TIM_DMA_sources TIM DMA Sources 703 * @{ 704 */ 705 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 706 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 707 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 708 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 709 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 710 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 711 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 712 /** 713 * @} 714 */ 715 716 /** @defgroup TIM_Flag_definition TIM Flag Definition 717 * @{ 718 */ 719 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 720 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 721 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 722 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 723 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 724 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 725 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 726 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 727 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 728 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 729 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 730 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 731 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 732 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 733 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 734 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 735 /** 736 * @} 737 */ 738 739 /** @defgroup TIM_Channel TIM Channel 740 * @{ 741 */ 742 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 743 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 744 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 745 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 746 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 747 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 748 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 749 /** 750 * @} 751 */ 752 753 /** @defgroup TIM_Clock_Source TIM Clock Source 754 * @{ 755 */ 756 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 757 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 758 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 759 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 760 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 761 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 762 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 763 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 764 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 765 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 766 /** 767 * @} 768 */ 769 770 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 771 * @{ 772 */ 773 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 774 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 775 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 776 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 777 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 778 /** 779 * @} 780 */ 781 782 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 783 * @{ 784 */ 785 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 786 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 787 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 788 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 789 /** 790 * @} 791 */ 792 793 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 794 * @{ 795 */ 796 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 797 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 798 /** 799 * @} 800 */ 801 802 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 803 * @{ 804 */ 805 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 806 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 807 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 808 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 809 /** 810 * @} 811 */ 812 813 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 814 * @{ 815 */ 816 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 817 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 823 * @{ 824 */ 825 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 826 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 827 /** 828 * @} 829 */ 830 /** @defgroup TIM_Lock_level TIM Lock level 831 * @{ 832 */ 833 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 834 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 835 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 836 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 837 /** 838 * @} 839 */ 840 841 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 842 * @{ 843 */ 844 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 845 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 846 /** 847 * @} 848 */ 849 850 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 851 * @{ 852 */ 853 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 854 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 855 /** 856 * @} 857 */ 858 859 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 860 * @{ 861 */ 862 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 863 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 864 /** 865 * @} 866 */ 867 868 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 869 * @{ 870 */ 871 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 872 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 873 /** 874 * @} 875 */ 876 877 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 878 * @{ 879 */ 880 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 881 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 882 (if none of the break inputs BRK and BRK2 is active) */ 883 /** 884 * @} 885 */ 886 887 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 888 * @{ 889 */ 890 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 891 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 892 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 893 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 894 /** 895 * @} 896 */ 897 898 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 899 * @{ 900 */ 901 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 902 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 903 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 904 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 905 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 906 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 907 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 908 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 909 /** 910 * @} 911 */ 912 913 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 914 * @{ 915 */ 916 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 917 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 918 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 919 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 920 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 921 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 922 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 923 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 924 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 925 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 926 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 927 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 928 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 929 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 930 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 931 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 932 /** 933 * @} 934 */ 935 936 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 937 * @{ 938 */ 939 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 940 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 941 /** 942 * @} 943 */ 944 945 /** @defgroup TIM_Slave_Mode TIM Slave mode 946 * @{ 947 */ 948 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 949 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 950 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 951 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 952 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 953 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 954 /** 955 * @} 956 */ 957 958 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 959 * @{ 960 */ 961 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 962 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 963 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 964 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 965 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 966 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 967 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 968 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 969 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 970 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 971 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 972 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 973 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 974 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 975 /** 976 * @} 977 */ 978 979 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 980 * @{ 981 */ 982 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 983 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 984 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 985 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 986 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 987 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 988 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 989 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 990 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 991 /** 992 * @} 993 */ 994 995 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 996 * @{ 997 */ 998 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 999 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1000 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1001 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1002 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1003 /** 1004 * @} 1005 */ 1006 1007 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1008 * @{ 1009 */ 1010 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1011 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1012 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1013 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1014 /** 1015 * @} 1016 */ 1017 1018 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1019 * @{ 1020 */ 1021 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1022 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1023 /** 1024 * @} 1025 */ 1026 1027 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1028 * @{ 1029 */ 1030 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1031 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1032 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1033 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1034 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1035 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1036 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1037 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1038 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1039 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1040 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1041 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1042 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1043 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1044 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1045 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1046 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1047 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1048 /** 1049 * @} 1050 */ 1051 1052 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1053 * @{ 1054 */ 1055 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1056 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1057 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1058 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1059 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1060 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1061 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1062 /** 1063 * @} 1064 */ 1065 1066 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1067 * @{ 1068 */ 1069 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1070 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1071 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1072 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup TIM_Break_System TIM Break System 1078 * @{ 1079 */ 1080 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 1081 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1082 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 1083 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1084 /** 1085 * @} 1086 */ 1087 1088 /** 1089 * @} 1090 */ 1091 /* End of exported constants -------------------------------------------------*/ 1092 1093 /* Exported macros -----------------------------------------------------------*/ 1094 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1095 * @{ 1096 */ 1097 1098 /** @brief Reset TIM handle state. 1099 * @param __HANDLE__ TIM handle. 1100 * @retval None 1101 */ 1102 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1103 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1104 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1105 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1106 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1107 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1108 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1109 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1110 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1111 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1112 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1113 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1114 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1115 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1116 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1117 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1118 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1119 } while(0) 1120 #else 1121 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1122 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1123 1124 /** 1125 * @brief Enable the TIM peripheral. 1126 * @param __HANDLE__ TIM handle 1127 * @retval None 1128 */ 1129 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1130 1131 /** 1132 * @brief Enable the TIM main Output. 1133 * @param __HANDLE__ TIM handle 1134 * @retval None 1135 */ 1136 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1137 1138 /** 1139 * @brief Disable the TIM peripheral. 1140 * @param __HANDLE__ TIM handle 1141 * @retval None 1142 */ 1143 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1144 do { \ 1145 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1146 { \ 1147 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1148 { \ 1149 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1150 } \ 1151 } \ 1152 } while(0) 1153 1154 /** 1155 * @brief Disable the TIM main Output. 1156 * @param __HANDLE__ TIM handle 1157 * @retval None 1158 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1159 */ 1160 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1161 do { \ 1162 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1163 { \ 1164 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1165 { \ 1166 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1167 } \ 1168 } \ 1169 } while(0) 1170 1171 /** 1172 * @brief Disable the TIM main Output. 1173 * @param __HANDLE__ TIM handle 1174 * @retval None 1175 * @note The Main Output Enable of a timer instance is disabled unconditionally 1176 */ 1177 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1178 1179 /** @brief Enable the specified TIM interrupt. 1180 * @param __HANDLE__ specifies the TIM Handle. 1181 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1182 * This parameter can be one of the following values: 1183 * @arg TIM_IT_UPDATE: Update interrupt 1184 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1185 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1186 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1187 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1188 * @arg TIM_IT_COM: Commutation interrupt 1189 * @arg TIM_IT_TRIGGER: Trigger interrupt 1190 * @arg TIM_IT_BREAK: Break interrupt 1191 * @retval None 1192 */ 1193 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1194 1195 /** @brief Disable the specified TIM interrupt. 1196 * @param __HANDLE__ specifies the TIM Handle. 1197 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1198 * This parameter can be one of the following values: 1199 * @arg TIM_IT_UPDATE: Update interrupt 1200 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1201 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1202 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1203 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1204 * @arg TIM_IT_COM: Commutation interrupt 1205 * @arg TIM_IT_TRIGGER: Trigger interrupt 1206 * @arg TIM_IT_BREAK: Break interrupt 1207 * @retval None 1208 */ 1209 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1210 1211 /** @brief Enable the specified DMA request. 1212 * @param __HANDLE__ specifies the TIM Handle. 1213 * @param __DMA__ specifies the TIM DMA request to enable. 1214 * This parameter can be one of the following values: 1215 * @arg TIM_DMA_UPDATE: Update DMA request 1216 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1217 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1218 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1219 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1220 * @arg TIM_DMA_COM: Commutation DMA request 1221 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1222 * @retval None 1223 */ 1224 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1225 1226 /** @brief Disable the specified DMA request. 1227 * @param __HANDLE__ specifies the TIM Handle. 1228 * @param __DMA__ specifies the TIM DMA request to disable. 1229 * This parameter can be one of the following values: 1230 * @arg TIM_DMA_UPDATE: Update DMA request 1231 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1232 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1233 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1234 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1235 * @arg TIM_DMA_COM: Commutation DMA request 1236 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1237 * @retval None 1238 */ 1239 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1240 1241 /** @brief Check whether the specified TIM interrupt flag is set or not. 1242 * @param __HANDLE__ specifies the TIM Handle. 1243 * @param __FLAG__ specifies the TIM interrupt flag to check. 1244 * This parameter can be one of the following values: 1245 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1246 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1247 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1248 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1249 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1250 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1251 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1252 * @arg TIM_FLAG_COM: Commutation interrupt flag 1253 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1254 * @arg TIM_FLAG_BREAK: Break interrupt flag 1255 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1256 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1257 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1258 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1259 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1260 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1261 * @retval The new state of __FLAG__ (TRUE or FALSE). 1262 */ 1263 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1264 1265 /** @brief Clear the specified TIM interrupt flag. 1266 * @param __HANDLE__ specifies the TIM Handle. 1267 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1268 * This parameter can be one of the following values: 1269 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1270 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1271 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1272 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1273 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1274 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1275 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1276 * @arg TIM_FLAG_COM: Commutation interrupt flag 1277 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1278 * @arg TIM_FLAG_BREAK: Break interrupt flag 1279 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1280 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1281 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1282 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1283 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1284 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1285 * @retval The new state of __FLAG__ (TRUE or FALSE). 1286 */ 1287 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1288 1289 /** 1290 * @brief Check whether the specified TIM interrupt source is enabled or not. 1291 * @param __HANDLE__ TIM handle 1292 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1293 * This parameter can be one of the following values: 1294 * @arg TIM_IT_UPDATE: Update interrupt 1295 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1296 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1297 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1298 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1299 * @arg TIM_IT_COM: Commutation interrupt 1300 * @arg TIM_IT_TRIGGER: Trigger interrupt 1301 * @arg TIM_IT_BREAK: Break interrupt 1302 * @retval The state of TIM_IT (SET or RESET). 1303 */ 1304 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1305 == (__INTERRUPT__)) ? SET : RESET) 1306 1307 /** @brief Clear the TIM interrupt pending bits. 1308 * @param __HANDLE__ TIM handle 1309 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1310 * This parameter can be one of the following values: 1311 * @arg TIM_IT_UPDATE: Update interrupt 1312 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1313 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1314 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1315 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1316 * @arg TIM_IT_COM: Commutation interrupt 1317 * @arg TIM_IT_TRIGGER: Trigger interrupt 1318 * @arg TIM_IT_BREAK: Break interrupt 1319 * @retval None 1320 */ 1321 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1322 1323 /** 1324 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1325 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. 1326 * @param __HANDLE__ TIM handle. 1327 * @retval None 1328 mode. 1329 */ 1330 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1331 1332 /** 1333 * @brief Disable update interrupt flag (UIF) remapping. 1334 * @param __HANDLE__ TIM handle. 1335 * @retval None 1336 mode. 1337 */ 1338 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1339 1340 /** 1341 * @brief Get update interrupt flag (UIF) copy status. 1342 * @param __COUNTER__ Counter value. 1343 * @retval The state of UIFCPY (TRUE or FALSE). 1344 mode. 1345 */ 1346 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1347 1348 /** 1349 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1350 * @param __HANDLE__ TIM handle. 1351 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1352 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1353 mode. 1354 */ 1355 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1356 1357 /** 1358 * @brief Set the TIM Prescaler on runtime. 1359 * @param __HANDLE__ TIM handle. 1360 * @param __PRESC__ specifies the Prescaler new value. 1361 * @retval None 1362 */ 1363 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1364 1365 /** 1366 * @brief Set the TIM Counter Register value on runtime. 1367 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. 1368 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1369 * @param __HANDLE__ TIM handle. 1370 * @param __COUNTER__ specifies the Counter register new value. 1371 * @retval None 1372 */ 1373 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1374 1375 /** 1376 * @brief Get the TIM Counter Register value on runtime. 1377 * @param __HANDLE__ TIM handle. 1378 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1379 */ 1380 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1381 1382 /** 1383 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1384 * @param __HANDLE__ TIM handle. 1385 * @param __AUTORELOAD__ specifies the Counter register new value. 1386 * @retval None 1387 */ 1388 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1389 do{ \ 1390 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1391 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1392 } while(0) 1393 1394 /** 1395 * @brief Get the TIM Autoreload Register value on runtime. 1396 * @param __HANDLE__ TIM handle. 1397 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1398 */ 1399 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1400 1401 /** 1402 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1403 * @param __HANDLE__ TIM handle. 1404 * @param __CKD__ specifies the clock division value. 1405 * This parameter can be one of the following value: 1406 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1407 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1408 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1409 * @retval None 1410 */ 1411 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1412 do{ \ 1413 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1414 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1415 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1416 } while(0) 1417 1418 /** 1419 * @brief Get the TIM Clock Division value on runtime. 1420 * @param __HANDLE__ TIM handle. 1421 * @retval The clock division can be one of the following values: 1422 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1423 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1424 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1425 */ 1426 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1427 1428 /** 1429 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1430 * @param __HANDLE__ TIM handle. 1431 * @param __CHANNEL__ TIM Channels to be configured. 1432 * This parameter can be one of the following values: 1433 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1434 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1435 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1436 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1437 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1438 * This parameter can be one of the following values: 1439 * @arg TIM_ICPSC_DIV1: no prescaler 1440 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1441 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1442 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1443 * @retval None 1444 */ 1445 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1446 do{ \ 1447 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1448 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1449 } while(0) 1450 1451 /** 1452 * @brief Get the TIM Input Capture prescaler on runtime. 1453 * @param __HANDLE__ TIM handle. 1454 * @param __CHANNEL__ TIM Channels to be configured. 1455 * This parameter can be one of the following values: 1456 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1457 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1458 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1459 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1460 * @retval The input capture prescaler can be one of the following values: 1461 * @arg TIM_ICPSC_DIV1: no prescaler 1462 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1463 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1464 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1465 */ 1466 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1467 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1468 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1469 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1470 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1471 1472 /** 1473 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1474 * @param __HANDLE__ TIM handle. 1475 * @param __CHANNEL__ TIM Channels to be configured. 1476 * This parameter can be one of the following values: 1477 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1478 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1479 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1480 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1481 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1482 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1483 * @param __COMPARE__ specifies the Capture Compare register new value. 1484 * @retval None 1485 */ 1486 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1487 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1488 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1489 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1490 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1491 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1492 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1493 1494 /** 1495 * @brief Get the TIM Capture Compare Register value on runtime. 1496 * @param __HANDLE__ TIM handle. 1497 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1498 * This parameter can be one of the following values: 1499 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1500 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1501 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1502 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1503 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1504 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1505 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1506 */ 1507 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1508 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1509 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1510 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1511 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1512 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1513 ((__HANDLE__)->Instance->CCR6)) 1514 1515 /** 1516 * @brief Set the TIM Output compare preload. 1517 * @param __HANDLE__ TIM handle. 1518 * @param __CHANNEL__ TIM Channels to be configured. 1519 * This parameter can be one of the following values: 1520 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1521 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1522 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1523 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1524 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1525 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1526 * @retval None 1527 */ 1528 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1529 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1530 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1531 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1532 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1533 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1534 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1535 1536 /** 1537 * @brief Reset the TIM Output compare preload. 1538 * @param __HANDLE__ TIM handle. 1539 * @param __CHANNEL__ TIM Channels to be configured. 1540 * This parameter can be one of the following values: 1541 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1542 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1543 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1544 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1545 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1546 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1547 * @retval None 1548 */ 1549 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1550 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1551 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1552 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1553 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1554 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1555 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1556 1557 /** 1558 * @brief Enable fast mode for a given channel. 1559 * @param __HANDLE__ TIM handle. 1560 * @param __CHANNEL__ TIM Channels to be configured. 1561 * This parameter can be one of the following values: 1562 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1563 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1564 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1565 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1566 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1567 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1568 * @note When fast mode is enabled an active edge on the trigger input acts 1569 * like a compare match on CCx output. Delay to sample the trigger 1570 * input and to activate CCx output is reduced to 3 clock cycles. 1571 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1572 * @retval None 1573 */ 1574 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1575 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1576 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1577 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1578 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1579 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1580 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1581 1582 /** 1583 * @brief Disable fast mode for a given channel. 1584 * @param __HANDLE__ TIM handle. 1585 * @param __CHANNEL__ TIM Channels to be configured. 1586 * This parameter can be one of the following values: 1587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1591 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1592 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1593 * @note When fast mode is disabled CCx output behaves normally depending 1594 * on counter and CCRx values even when the trigger is ON. The minimum 1595 * delay to activate CCx output when an active edge occurs on the 1596 * trigger input is 5 clock cycles. 1597 * @retval None 1598 */ 1599 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1600 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1601 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1602 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1603 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1604 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1605 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1606 1607 /** 1608 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1609 * @param __HANDLE__ TIM handle. 1610 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1611 * overflow/underflow generates an update interrupt or DMA request (if 1612 * enabled) 1613 * @retval None 1614 */ 1615 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1616 1617 /** 1618 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1619 * @param __HANDLE__ TIM handle. 1620 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1621 * following events generate an update interrupt or DMA request (if 1622 * enabled): 1623 * _ Counter overflow underflow 1624 * _ Setting the UG bit 1625 * _ Update generation through the slave mode controller 1626 * @retval None 1627 */ 1628 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1629 1630 /** 1631 * @brief Set the TIM Capture x input polarity on runtime. 1632 * @param __HANDLE__ TIM handle. 1633 * @param __CHANNEL__ TIM Channels to be configured. 1634 * This parameter can be one of the following values: 1635 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1636 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1637 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1638 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1639 * @param __POLARITY__ Polarity for TIx source 1640 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1641 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1642 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1643 * @retval None 1644 */ 1645 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1646 do{ \ 1647 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1648 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1649 }while(0) 1650 1651 /** 1652 * @} 1653 */ 1654 /* End of exported macros ----------------------------------------------------*/ 1655 1656 /* Private constants ---------------------------------------------------------*/ 1657 /** @defgroup TIM_Private_Constants TIM Private Constants 1658 * @{ 1659 */ 1660 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1661 channels have been disabled */ 1662 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1663 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1664 /** 1665 * @} 1666 */ 1667 /* End of private constants --------------------------------------------------*/ 1668 1669 /* Private macros ------------------------------------------------------------*/ 1670 /** @defgroup TIM_Private_Macros TIM Private Macros 1671 * @{ 1672 */ 1673 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1674 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ 1675 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1676 1677 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1678 ((__BASE__) == TIM_DMABASE_CR2) || \ 1679 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1680 ((__BASE__) == TIM_DMABASE_DIER) || \ 1681 ((__BASE__) == TIM_DMABASE_SR) || \ 1682 ((__BASE__) == TIM_DMABASE_EGR) || \ 1683 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1684 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1685 ((__BASE__) == TIM_DMABASE_CCER) || \ 1686 ((__BASE__) == TIM_DMABASE_CNT) || \ 1687 ((__BASE__) == TIM_DMABASE_PSC) || \ 1688 ((__BASE__) == TIM_DMABASE_ARR) || \ 1689 ((__BASE__) == TIM_DMABASE_RCR) || \ 1690 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1691 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1692 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1693 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1694 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1695 ((__BASE__) == TIM_DMABASE_OR1) || \ 1696 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1697 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1698 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1699 ((__BASE__) == TIM_DMABASE_OR2) || \ 1700 ((__BASE__) == TIM_DMABASE_OR3)) 1701 1702 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1703 1704 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1705 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1706 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1707 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1708 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1709 1710 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1711 ((__MODE__) == TIM_UIFREMAP_ENALE)) 1712 1713 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1714 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1715 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1716 1717 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1718 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1719 1720 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1721 ((__STATE__) == TIM_OCFAST_ENABLE)) 1722 1723 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1724 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1725 1726 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1727 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1728 1729 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1730 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1731 1732 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1733 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1734 1735 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1736 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1737 1738 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1739 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1740 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1741 1742 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1743 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1744 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1745 1746 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1747 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1748 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1749 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1750 1751 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1752 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1753 1754 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1755 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1756 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1757 1758 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1759 1760 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1761 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1762 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1763 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1764 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1765 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1766 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1767 1768 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1769 ((__CHANNEL__) == TIM_CHANNEL_2)) 1770 1771 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1772 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1773 ((__CHANNEL__) == TIM_CHANNEL_3)) 1774 1775 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1776 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1777 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1778 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1779 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1780 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1781 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1782 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1783 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1784 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1785 1786 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1787 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1788 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1789 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1790 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1791 1792 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1793 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1794 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1795 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1796 1797 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1798 1799 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1800 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1801 1802 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1803 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1804 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1805 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1806 1807 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1808 1809 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1810 ((__STATE__) == TIM_OSSR_DISABLE)) 1811 1812 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1813 ((__STATE__) == TIM_OSSI_DISABLE)) 1814 1815 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1816 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1817 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1818 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1819 1820 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1821 1822 1823 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1824 ((__STATE__) == TIM_BREAK_DISABLE)) 1825 1826 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1827 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1828 1829 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1830 ((__STATE__) == TIM_BREAK2_DISABLE)) 1831 1832 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1833 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1834 1835 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1836 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1837 1838 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1839 1840 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1841 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1842 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1843 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1844 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1845 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1846 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1847 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1848 1849 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1850 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1851 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1852 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1853 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1854 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1855 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1856 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1857 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1858 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1859 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1860 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1861 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1862 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1863 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1864 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1865 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1866 1867 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1868 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1869 1870 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1871 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1872 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1873 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1874 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1875 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1876 1877 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1878 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1879 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1880 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1881 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1882 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1883 1884 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1885 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1886 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1887 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1888 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1889 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1890 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1891 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1892 1893 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1894 ((__SELECTION__) == TIM_TS_ITR1) || \ 1895 ((__SELECTION__) == TIM_TS_ITR2) || \ 1896 ((__SELECTION__) == TIM_TS_ITR3) || \ 1897 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1898 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1899 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1900 ((__SELECTION__) == TIM_TS_ETRF)) 1901 1902 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1903 ((__SELECTION__) == TIM_TS_ITR1) || \ 1904 ((__SELECTION__) == TIM_TS_ITR2) || \ 1905 ((__SELECTION__) == TIM_TS_ITR3) || \ 1906 ((__SELECTION__) == TIM_TS_NONE)) 1907 1908 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1909 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1910 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1911 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1912 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1913 1914 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1915 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1916 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1917 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1918 1919 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1920 1921 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1922 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1923 1924 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1925 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1926 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1927 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1928 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1929 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1930 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1931 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1932 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1933 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1934 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1935 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1936 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1937 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1938 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1939 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1940 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1941 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1942 1943 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1944 1945 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1946 1947 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 1948 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 1949 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ 1950 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 1951 1952 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 1953 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1954 1955 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1956 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1957 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1958 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1959 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1960 1961 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1962 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 1963 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 1964 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 1965 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 1966 1967 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1968 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1969 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1970 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1971 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1972 1973 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1974 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1975 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1976 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1977 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1978 1979 /** 1980 * @} 1981 */ 1982 /* End of private macros -----------------------------------------------------*/ 1983 1984 /* Include TIM HAL Extended module */ 1985 #include "stm32l4xx_hal_tim_ex.h" 1986 1987 /* Exported functions --------------------------------------------------------*/ 1988 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1989 * @{ 1990 */ 1991 1992 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1993 * @brief Time Base functions 1994 * @{ 1995 */ 1996 /* Time Base functions ********************************************************/ 1997 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1998 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1999 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2000 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2001 /* Blocking mode: Polling */ 2002 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2003 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2004 /* Non-Blocking mode: Interrupt */ 2005 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2006 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2007 /* Non-Blocking mode: DMA */ 2008 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 2009 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2010 /** 2011 * @} 2012 */ 2013 2014 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2015 * @brief TIM Output Compare functions 2016 * @{ 2017 */ 2018 /* Timer Output Compare functions *********************************************/ 2019 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2020 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2021 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2022 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2023 /* Blocking mode: Polling */ 2024 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2025 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2026 /* Non-Blocking mode: Interrupt */ 2027 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2028 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2029 /* Non-Blocking mode: DMA */ 2030 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2031 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2032 /** 2033 * @} 2034 */ 2035 2036 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2037 * @brief TIM PWM functions 2038 * @{ 2039 */ 2040 /* Timer PWM functions ********************************************************/ 2041 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2042 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2043 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2044 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2045 /* Blocking mode: Polling */ 2046 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2047 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2048 /* Non-Blocking mode: Interrupt */ 2049 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2050 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2051 /* Non-Blocking mode: DMA */ 2052 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2053 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2054 /** 2055 * @} 2056 */ 2057 2058 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2059 * @brief TIM Input Capture functions 2060 * @{ 2061 */ 2062 /* Timer Input Capture functions **********************************************/ 2063 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2064 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2065 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2066 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2067 /* Blocking mode: Polling */ 2068 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2069 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2070 /* Non-Blocking mode: Interrupt */ 2071 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2072 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2073 /* Non-Blocking mode: DMA */ 2074 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2075 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2076 /** 2077 * @} 2078 */ 2079 2080 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2081 * @brief TIM One Pulse functions 2082 * @{ 2083 */ 2084 /* Timer One Pulse functions **************************************************/ 2085 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2086 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2087 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2088 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2089 /* Blocking mode: Polling */ 2090 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2091 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2092 /* Non-Blocking mode: Interrupt */ 2093 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2094 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2095 /** 2096 * @} 2097 */ 2098 2099 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2100 * @brief TIM Encoder functions 2101 * @{ 2102 */ 2103 /* Timer Encoder functions ****************************************************/ 2104 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2105 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2106 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2107 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2108 /* Blocking mode: Polling */ 2109 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2110 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2111 /* Non-Blocking mode: Interrupt */ 2112 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2113 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2114 /* Non-Blocking mode: DMA */ 2115 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2116 uint32_t *pData2, uint16_t Length); 2117 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2118 /** 2119 * @} 2120 */ 2121 2122 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2123 * @brief IRQ handler management 2124 * @{ 2125 */ 2126 /* Interrupt Handler functions ***********************************************/ 2127 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2128 /** 2129 * @} 2130 */ 2131 2132 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2133 * @brief Peripheral Control functions 2134 * @{ 2135 */ 2136 /* Control functions *********************************************************/ 2137 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2138 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2139 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2140 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2141 uint32_t OutputChannel, uint32_t InputChannel); 2142 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2143 uint32_t Channel); 2144 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2145 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2146 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2147 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2148 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2149 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2150 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2151 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2152 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2153 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2154 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2155 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2156 /** 2157 * @} 2158 */ 2159 2160 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2161 * @brief TIM Callbacks functions 2162 * @{ 2163 */ 2164 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2165 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2166 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2167 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2168 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2169 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2170 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2171 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2172 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2173 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2174 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2175 2176 /* Callbacks Register/UnRegister functions ***********************************/ 2177 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2178 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2179 pTIM_CallbackTypeDef pCallback); 2180 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2181 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2182 2183 /** 2184 * @} 2185 */ 2186 2187 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2188 * @brief Peripheral State functions 2189 * @{ 2190 */ 2191 /* Peripheral State functions ************************************************/ 2192 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2193 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2194 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2195 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2196 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2197 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2198 /** 2199 * @} 2200 */ 2201 2202 /** 2203 * @} 2204 */ 2205 /* End of exported functions -------------------------------------------------*/ 2206 2207 /* Private functions----------------------------------------------------------*/ 2208 /** @defgroup TIM_Private_Functions TIM Private Functions 2209 * @{ 2210 */ 2211 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2212 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2213 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2214 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2215 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2216 2217 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 2218 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2219 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2220 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2221 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2222 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2223 2224 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2225 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2226 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2227 2228 /** 2229 * @} 2230 */ 2231 /* End of private functions --------------------------------------------------*/ 2232 2233 /** 2234 * @} 2235 */ 2236 2237 /** 2238 * @} 2239 */ 2240 2241 #ifdef __cplusplus 2242 } 2243 #endif 2244 2245 #endif /* STM32L4xx_HAL_TIM_H */ 2246 2247 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2248