1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_RCC_H 22 #define STM32L4xx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCC_Exported_Types RCC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL. 50 This parameter can be a value of @ref RCC_PLL_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 53 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 56 This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 57 This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ 58 59 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 60 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 61 62 #if defined(RCC_PLLP_SUPPORT) 63 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 64 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 65 #endif /* RCC_PLLP_SUPPORT */ 66 67 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 68 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 69 70 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 71 User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ 72 on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. 73 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 74 75 }RCC_PLLInitTypeDef; 76 77 /** 78 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 79 */ 80 typedef struct 81 { 82 uint32_t OscillatorType; /*!< The oscillators to be configured. 83 This parameter can be a value of @ref RCC_Oscillator_Type */ 84 85 uint32_t HSEState; /*!< The new state of the HSE. 86 This parameter can be a value of @ref RCC_HSE_Config */ 87 88 uint32_t LSEState; /*!< The new state of the LSE. 89 This parameter can be a value of @ref RCC_LSE_Config */ 90 91 uint32_t HSIState; /*!< The new state of the HSI. 92 This parameter can be a value of @ref RCC_HSI_Config */ 93 94 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 95 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. 96 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ 97 98 uint32_t LSIState; /*!< The new state of the LSI. 99 This parameter can be a value of @ref RCC_LSI_Config */ 100 #if defined(RCC_CSR_LSIPREDIV) 101 102 uint32_t LSIDiv; /*!< The division factor of the LSI. 103 This parameter can be a value of @ref RCC_LSI_Div */ 104 #endif /* RCC_CSR_LSIPREDIV */ 105 106 uint32_t MSIState; /*!< The new state of the MSI. 107 This parameter can be a value of @ref RCC_MSI_Config */ 108 109 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 111 112 uint32_t MSIClockRange; /*!< The MSI frequency range. 113 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 114 115 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). 116 This parameter can be a value of @ref RCC_HSI48_Config */ 117 118 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 119 120 }RCC_OscInitTypeDef; 121 122 /** 123 * @brief RCC System, AHB and APB busses clock configuration structure definition 124 */ 125 typedef struct 126 { 127 uint32_t ClockType; /*!< The clock to be configured. 128 This parameter can be a value of @ref RCC_System_Clock_Type */ 129 130 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 131 This parameter can be a value of @ref RCC_System_Clock_Source */ 132 133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 134 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 135 136 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 137 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 138 139 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 140 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 141 142 }RCC_ClkInitTypeDef; 143 144 /** 145 * @} 146 */ 147 148 /* Exported constants --------------------------------------------------------*/ 149 /** @defgroup RCC_Exported_Constants RCC Exported Constants 150 * @{ 151 */ 152 153 /** @defgroup RCC_Timeout_Value Timeout Values 154 * @{ 155 */ 156 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 157 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 158 /** 159 * @} 160 */ 161 162 /** @defgroup RCC_Oscillator_Type Oscillator Type 163 * @{ 164 */ 165 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 166 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 167 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 168 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 169 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 170 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 171 #if defined(RCC_HSI48_SUPPORT) 172 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 173 #endif /* RCC_HSI48_SUPPORT */ 174 /** 175 * @} 176 */ 177 178 /** @defgroup RCC_HSE_Config HSE Config 179 * @{ 180 */ 181 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 182 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 183 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup RCC_LSE_Config LSE Config 189 * @{ 190 */ 191 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 192 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 193 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 194 #if defined(RCC_BDCR_LSESYSDIS) 195 #define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */ 196 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */ 197 #endif /* RCC_BDCR_LSESYSDIS */ 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_HSI_Config HSI Config 203 * @{ 204 */ 205 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 206 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 207 208 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ 209 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 210 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 211 #else 212 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ 213 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ 214 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup RCC_LSI_Config LSI Config 220 * @{ 221 */ 222 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 223 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 224 /** 225 * @} 226 */ 227 #if defined(RCC_CSR_LSIPREDIV) 228 229 /** @defgroup RCC_LSI_Div LSI Div 230 * @{ 231 */ 232 #define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */ 233 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */ 234 /** 235 * @} 236 */ 237 #endif /* RCC_CSR_LSIPREDIV */ 238 239 /** @defgroup RCC_MSI_Config MSI Config 240 * @{ 241 */ 242 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 243 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 244 245 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 246 /** 247 * @} 248 */ 249 250 #if defined(RCC_HSI48_SUPPORT) 251 /** @defgroup RCC_HSI48_Config HSI48 Config 252 * @{ 253 */ 254 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 255 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 256 /** 257 * @} 258 */ 259 #else 260 /** @defgroup RCC_HSI48_Config HSI48 Config 261 * @{ 262 */ 263 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 264 /** 265 * @} 266 */ 267 #endif /* RCC_HSI48_SUPPORT */ 268 269 /** @defgroup RCC_PLL_Config PLL Config 270 * @{ 271 */ 272 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 273 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 274 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 275 /** 276 * @} 277 */ 278 279 #if defined(RCC_PLLP_SUPPORT) 280 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 281 * @{ 282 */ 283 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 284 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 285 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 286 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 287 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 288 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 289 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 290 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 291 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 292 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 293 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 294 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 295 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 296 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 297 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 298 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 299 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 300 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 301 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 302 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 303 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 304 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 305 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 306 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 307 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 308 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 309 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 310 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 311 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 312 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 313 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 314 #else 315 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 316 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 317 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 318 /** 319 * @} 320 */ 321 #endif /* RCC_PLLP_SUPPORT */ 322 323 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 324 * @{ 325 */ 326 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 327 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 328 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 329 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 330 /** 331 * @} 332 */ 333 334 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 335 * @{ 336 */ 337 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 338 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 339 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 340 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 346 * @{ 347 */ 348 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 349 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 350 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 351 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 357 * @{ 358 */ 359 #if defined(RCC_PLLSAI2_SUPPORT) 360 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ 361 #elif defined(RCC_PLLSAI1_SUPPORT) 362 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ 363 #endif /* RCC_PLLSAI2_SUPPORT */ 364 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 365 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 366 /** 367 * @} 368 */ 369 #if defined(RCC_PLLSAI1_SUPPORT) 370 371 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 372 * @{ 373 */ 374 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 375 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 376 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 377 /** 378 * @} 379 */ 380 #endif /* RCC_PLLSAI1_SUPPORT */ 381 382 #if defined(RCC_PLLSAI2_SUPPORT) 383 384 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 385 * @{ 386 */ 387 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 388 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 389 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ 390 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 391 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 392 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ 393 #else 394 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ 395 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 396 /** 397 * @} 398 */ 399 400 #endif /* RCC_PLLSAI2_SUPPORT */ 401 402 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 403 * @{ 404 */ 405 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 406 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 407 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 408 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 409 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 410 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 411 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 412 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 413 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 414 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 415 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 416 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup RCC_System_Clock_Type System Clock Type 422 * @{ 423 */ 424 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 425 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 426 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 427 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup RCC_System_Clock_Source System Clock Source 433 * @{ 434 */ 435 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 436 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 437 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 438 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 439 /** 440 * @} 441 */ 442 443 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 444 * @{ 445 */ 446 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 447 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 448 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 449 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 455 * @{ 456 */ 457 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 458 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 459 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 460 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 461 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 462 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 463 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 464 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 465 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 466 /** 467 * @} 468 */ 469 470 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 471 * @{ 472 */ 473 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 474 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 475 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 476 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 477 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 478 /** 479 * @} 480 */ 481 482 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 483 * @{ 484 */ 485 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 486 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 487 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 488 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup RCC_MCO_Index MCO Index 494 * @{ 495 */ 496 #define RCC_MCO1 0x00000000U 497 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 498 /** 499 * @} 500 */ 501 502 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 503 * @{ 504 */ 505 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 506 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 507 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 508 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 509 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 510 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 511 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 512 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 513 #if defined(RCC_HSI48_SUPPORT) 514 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ 515 #endif /* RCC_HSI48_SUPPORT */ 516 /** 517 * @} 518 */ 519 520 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 521 * @{ 522 */ 523 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 524 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 525 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 526 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 527 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 528 /** 529 * @} 530 */ 531 532 /** @defgroup RCC_Interrupt Interrupts 533 * @{ 534 */ 535 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 536 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 537 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 538 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 539 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 540 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 541 #if defined(RCC_PLLSAI1_SUPPORT) 542 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 543 #endif /* RCC_PLLSAI1_SUPPORT */ 544 #if defined(RCC_PLLSAI2_SUPPORT) 545 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 546 #endif /* RCC_PLLSAI2_SUPPORT */ 547 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 548 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 549 #if defined(RCC_HSI48_SUPPORT) 550 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 551 #endif /* RCC_HSI48_SUPPORT */ 552 /** 553 * @} 554 */ 555 556 /** @defgroup RCC_Flag Flags 557 * Elements values convention: XXXYYYYYb 558 * - YYYYY : Flag position in the register 559 * - XXX : Register index 560 * - 001: CR register 561 * - 010: BDCR register 562 * - 011: CSR register 563 * - 100: CRRCR register 564 * @{ 565 */ 566 /* Flags in the CR register */ 567 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 568 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 569 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 570 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 571 #if defined(RCC_PLLSAI1_SUPPORT) 572 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 573 #endif /* RCC_PLLSAI1_SUPPORT */ 574 #if defined(RCC_PLLSAI2_SUPPORT) 575 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 576 #endif /* RCC_PLLSAI2_SUPPORT */ 577 578 /* Flags in the BDCR register */ 579 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 580 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 581 582 /* Flags in the CSR register */ 583 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 584 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ 585 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 586 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 587 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 588 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 589 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 590 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 591 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 592 593 #if defined(RCC_HSI48_SUPPORT) 594 /* Flags in the CRRCR register */ 595 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 596 #endif /* RCC_HSI48_SUPPORT */ 597 /** 598 * @} 599 */ 600 601 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 602 * @{ 603 */ 604 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 605 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 606 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 607 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 613 * @{ 614 */ 615 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 616 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 617 /** 618 * @} 619 */ 620 621 /** 622 * @} 623 */ 624 625 /* Exported macros -----------------------------------------------------------*/ 626 627 /** @defgroup RCC_Exported_Macros RCC Exported Macros 628 * @{ 629 */ 630 631 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 632 * @brief Enable or disable the AHB1 peripheral clock. 633 * @note After reset, the peripheral clock (used for registers read/write access) 634 * is disabled and the application software has to enable this clock before 635 * using it. 636 * @{ 637 */ 638 639 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 640 __IO uint32_t tmpreg; \ 641 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 642 /* Delay after an RCC peripheral clock enabling */ \ 643 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 644 UNUSED(tmpreg); \ 645 } while(0) 646 647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 648 __IO uint32_t tmpreg; \ 649 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 650 /* Delay after an RCC peripheral clock enabling */ \ 651 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 652 UNUSED(tmpreg); \ 653 } while(0) 654 655 #if defined(DMAMUX1) 656 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 657 __IO uint32_t tmpreg; \ 658 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 659 /* Delay after an RCC peripheral clock enabling */ \ 660 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 661 UNUSED(tmpreg); \ 662 } while(0) 663 #endif /* DMAMUX1 */ 664 665 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 666 __IO uint32_t tmpreg; \ 667 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 668 /* Delay after an RCC peripheral clock enabling */ \ 669 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 670 UNUSED(tmpreg); \ 671 } while(0) 672 673 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 674 __IO uint32_t tmpreg; \ 675 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 676 /* Delay after an RCC peripheral clock enabling */ \ 677 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 678 UNUSED(tmpreg); \ 679 } while(0) 680 681 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 682 __IO uint32_t tmpreg; \ 683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 684 /* Delay after an RCC peripheral clock enabling */ \ 685 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 686 UNUSED(tmpreg); \ 687 } while(0) 688 689 #if defined(DMA2D) 690 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 691 __IO uint32_t tmpreg; \ 692 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 693 /* Delay after an RCC peripheral clock enabling */ \ 694 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 695 UNUSED(tmpreg); \ 696 } while(0) 697 #endif /* DMA2D */ 698 699 #if defined(GFXMMU) 700 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 701 __IO uint32_t tmpreg; \ 702 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 703 /* Delay after an RCC peripheral clock enabling */ \ 704 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 705 UNUSED(tmpreg); \ 706 } while(0) 707 #endif /* GFXMMU */ 708 709 710 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 711 712 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 713 714 #if defined(DMAMUX1) 715 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 716 #endif /* DMAMUX1 */ 717 718 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 719 720 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 721 722 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 723 724 #if defined(DMA2D) 725 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 726 #endif /* DMA2D */ 727 728 #if defined(GFXMMU) 729 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 730 #endif /* GFXMMU */ 731 732 /** 733 * @} 734 */ 735 736 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 737 * @brief Enable or disable the AHB2 peripheral clock. 738 * @note After reset, the peripheral clock (used for registers read/write access) 739 * is disabled and the application software has to enable this clock before 740 * using it. 741 * @{ 742 */ 743 744 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 745 __IO uint32_t tmpreg; \ 746 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 747 /* Delay after an RCC peripheral clock enabling */ \ 748 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 749 UNUSED(tmpreg); \ 750 } while(0) 751 752 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 753 __IO uint32_t tmpreg; \ 754 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 755 /* Delay after an RCC peripheral clock enabling */ \ 756 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 757 UNUSED(tmpreg); \ 758 } while(0) 759 760 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 761 __IO uint32_t tmpreg; \ 762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 763 /* Delay after an RCC peripheral clock enabling */ \ 764 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 765 UNUSED(tmpreg); \ 766 } while(0) 767 768 #if defined(GPIOD) 769 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 770 __IO uint32_t tmpreg; \ 771 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 772 /* Delay after an RCC peripheral clock enabling */ \ 773 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 774 UNUSED(tmpreg); \ 775 } while(0) 776 #endif /* GPIOD */ 777 778 #if defined(GPIOE) 779 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 780 __IO uint32_t tmpreg; \ 781 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 782 /* Delay after an RCC peripheral clock enabling */ \ 783 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 784 UNUSED(tmpreg); \ 785 } while(0) 786 #endif /* GPIOE */ 787 788 #if defined(GPIOF) 789 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 790 __IO uint32_t tmpreg; \ 791 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 792 /* Delay after an RCC peripheral clock enabling */ \ 793 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 794 UNUSED(tmpreg); \ 795 } while(0) 796 #endif /* GPIOF */ 797 798 #if defined(GPIOG) 799 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 800 __IO uint32_t tmpreg; \ 801 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 802 /* Delay after an RCC peripheral clock enabling */ \ 803 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 804 UNUSED(tmpreg); \ 805 } while(0) 806 #endif /* GPIOG */ 807 808 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 809 __IO uint32_t tmpreg; \ 810 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 811 /* Delay after an RCC peripheral clock enabling */ \ 812 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 813 UNUSED(tmpreg); \ 814 } while(0) 815 816 #if defined(GPIOI) 817 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 818 __IO uint32_t tmpreg; \ 819 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 820 /* Delay after an RCC peripheral clock enabling */ \ 821 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 822 UNUSED(tmpreg); \ 823 } while(0) 824 #endif /* GPIOI */ 825 826 #if defined(USB_OTG_FS) 827 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 828 __IO uint32_t tmpreg; \ 829 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 830 /* Delay after an RCC peripheral clock enabling */ \ 831 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 832 UNUSED(tmpreg); \ 833 } while(0) 834 #endif /* USB_OTG_FS */ 835 836 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 837 __IO uint32_t tmpreg; \ 838 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 839 /* Delay after an RCC peripheral clock enabling */ \ 840 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 841 UNUSED(tmpreg); \ 842 } while(0) 843 844 #if defined(DCMI) 845 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 846 __IO uint32_t tmpreg; \ 847 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 848 /* Delay after an RCC peripheral clock enabling */ \ 849 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 850 UNUSED(tmpreg); \ 851 } while(0) 852 #endif /* DCMI */ 853 854 #if defined(PKA) 855 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 856 __IO uint32_t tmpreg; \ 857 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 858 /* Delay after an RCC peripheral clock enabling */ \ 859 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 860 UNUSED(tmpreg); \ 861 } while(0) 862 #endif /* PKA */ 863 864 #if defined(AES) 865 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 866 __IO uint32_t tmpreg; \ 867 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 868 /* Delay after an RCC peripheral clock enabling */ \ 869 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 870 UNUSED(tmpreg); \ 871 } while(0) 872 #endif /* AES */ 873 874 #if defined(HASH) 875 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 876 __IO uint32_t tmpreg; \ 877 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 878 /* Delay after an RCC peripheral clock enabling */ \ 879 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 880 UNUSED(tmpreg); \ 881 } while(0) 882 #endif /* HASH */ 883 884 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 885 __IO uint32_t tmpreg; \ 886 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 887 /* Delay after an RCC peripheral clock enabling */ \ 888 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 889 UNUSED(tmpreg); \ 890 } while(0) 891 892 #if defined(OCTOSPIM) 893 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 894 __IO uint32_t tmpreg; \ 895 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 896 /* Delay after an RCC peripheral clock enabling */ \ 897 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 898 UNUSED(tmpreg); \ 899 } while(0) 900 #endif /* OCTOSPIM */ 901 902 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 903 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 904 __IO uint32_t tmpreg; \ 905 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 906 /* Delay after an RCC peripheral clock enabling */ \ 907 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 908 UNUSED(tmpreg); \ 909 } while(0) 910 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 911 912 #if defined(SDMMC2) 913 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 914 __IO uint32_t tmpreg; \ 915 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \ 916 /* Delay after an RCC peripheral clock enabling */ \ 917 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN); \ 918 UNUSED(tmpreg); \ 919 } while(0) 920 #endif /* SDMMC2 */ 921 922 923 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 924 925 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 926 927 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 928 929 #if defined(GPIOD) 930 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 931 #endif /* GPIOD */ 932 933 #if defined(GPIOE) 934 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 935 #endif /* GPIOE */ 936 937 #if defined(GPIOF) 938 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 939 #endif /* GPIOF */ 940 941 #if defined(GPIOG) 942 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 943 #endif /* GPIOG */ 944 945 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 946 947 #if defined(GPIOI) 948 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 949 #endif /* GPIOI */ 950 951 #if defined(USB_OTG_FS) 952 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); 953 #endif /* USB_OTG_FS */ 954 955 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 956 957 #if defined(DCMI) 958 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) 959 #endif /* DCMI */ 960 961 #if defined(PKA) 962 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 963 #endif /* PKA */ 964 965 #if defined(AES) 966 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 967 #endif /* AES */ 968 969 #if defined(HASH) 970 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 971 #endif /* HASH */ 972 973 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 974 975 #if defined(OCTOSPIM) 976 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) 977 #endif /* OCTOSPIM */ 978 979 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 980 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 981 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 982 983 #if defined(SDMMC2) 984 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) 985 #endif /* SDMMC2 */ 986 987 /** 988 * @} 989 */ 990 991 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 992 * @brief Enable or disable the AHB3 peripheral clock. 993 * @note After reset, the peripheral clock (used for registers read/write access) 994 * is disabled and the application software has to enable this clock before 995 * using it. 996 * @{ 997 */ 998 999 #if defined(FMC_BANK1) 1000 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1001 __IO uint32_t tmpreg; \ 1002 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 1003 /* Delay after an RCC peripheral clock enabling */ \ 1004 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 1005 UNUSED(tmpreg); \ 1006 } while(0) 1007 #endif /* FMC_BANK1 */ 1008 1009 #if defined(QUADSPI) 1010 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 1011 __IO uint32_t tmpreg; \ 1012 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 1013 /* Delay after an RCC peripheral clock enabling */ \ 1014 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 1015 UNUSED(tmpreg); \ 1016 } while(0) 1017 #endif /* QUADSPI */ 1018 1019 #if defined(OCTOSPI1) 1020 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1021 __IO uint32_t tmpreg; \ 1022 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 1023 /* Delay after an RCC peripheral clock enabling */ \ 1024 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 1025 UNUSED(tmpreg); \ 1026 } while(0) 1027 #endif /* OCTOSPI1 */ 1028 1029 #if defined(OCTOSPI2) 1030 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1031 __IO uint32_t tmpreg; \ 1032 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 1033 /* Delay after an RCC peripheral clock enabling */ \ 1034 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 1035 UNUSED(tmpreg); \ 1036 } while(0) 1037 #endif /* OCTOSPI2 */ 1038 1039 #if defined(FMC_BANK1) 1040 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 1041 #endif /* FMC_BANK1 */ 1042 1043 #if defined(QUADSPI) 1044 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 1045 #endif /* QUADSPI */ 1046 1047 #if defined(OCTOSPI1) 1048 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 1049 #endif /* OCTOSPI1 */ 1050 1051 #if defined(OCTOSPI2) 1052 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) 1053 #endif /* OCTOSPI2 */ 1054 1055 /** 1056 * @} 1057 */ 1058 1059 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1060 * @brief Enable or disable the APB1 peripheral clock. 1061 * @note After reset, the peripheral clock (used for registers read/write access) 1062 * is disabled and the application software has to enable this clock before 1063 * using it. 1064 * @{ 1065 */ 1066 1067 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1068 __IO uint32_t tmpreg; \ 1069 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1070 /* Delay after an RCC peripheral clock enabling */ \ 1071 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1072 UNUSED(tmpreg); \ 1073 } while(0) 1074 1075 #if defined(TIM3) 1076 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1077 __IO uint32_t tmpreg; \ 1078 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1079 /* Delay after an RCC peripheral clock enabling */ \ 1080 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1081 UNUSED(tmpreg); \ 1082 } while(0) 1083 #endif /* TIM3 */ 1084 1085 #if defined(TIM4) 1086 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1087 __IO uint32_t tmpreg; \ 1088 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1089 /* Delay after an RCC peripheral clock enabling */ \ 1090 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1091 UNUSED(tmpreg); \ 1092 } while(0) 1093 #endif /* TIM4 */ 1094 1095 #if defined(TIM5) 1096 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1097 __IO uint32_t tmpreg; \ 1098 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1099 /* Delay after an RCC peripheral clock enabling */ \ 1100 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1101 UNUSED(tmpreg); \ 1102 } while(0) 1103 #endif /* TIM5 */ 1104 1105 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1106 __IO uint32_t tmpreg; \ 1107 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1108 /* Delay after an RCC peripheral clock enabling */ \ 1109 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1110 UNUSED(tmpreg); \ 1111 } while(0) 1112 1113 #if defined(TIM7) 1114 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1115 __IO uint32_t tmpreg; \ 1116 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1117 /* Delay after an RCC peripheral clock enabling */ \ 1118 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1119 UNUSED(tmpreg); \ 1120 } while(0) 1121 #endif /* TIM7 */ 1122 1123 #if defined(LCD) 1124 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 1125 __IO uint32_t tmpreg; \ 1126 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 1127 /* Delay after an RCC peripheral clock enabling */ \ 1128 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 1129 UNUSED(tmpreg); \ 1130 } while(0) 1131 #endif /* LCD */ 1132 1133 #if defined(RCC_APB1ENR1_RTCAPBEN) 1134 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1135 __IO uint32_t tmpreg; \ 1136 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 1137 /* Delay after an RCC peripheral clock enabling */ \ 1138 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 1139 UNUSED(tmpreg); \ 1140 } while(0) 1141 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1142 1143 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1144 __IO uint32_t tmpreg; \ 1145 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1146 /* Delay after an RCC peripheral clock enabling */ \ 1147 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1148 UNUSED(tmpreg); \ 1149 } while(0) 1150 1151 #if defined(SPI2) 1152 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1153 __IO uint32_t tmpreg; \ 1154 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1155 /* Delay after an RCC peripheral clock enabling */ \ 1156 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1157 UNUSED(tmpreg); \ 1158 } while(0) 1159 #endif /* SPI2 */ 1160 1161 #if defined(SPI3) 1162 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1163 __IO uint32_t tmpreg; \ 1164 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1165 /* Delay after an RCC peripheral clock enabling */ \ 1166 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1167 UNUSED(tmpreg); \ 1168 } while(0) 1169 #endif /* SPI3 */ 1170 1171 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1172 __IO uint32_t tmpreg; \ 1173 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1174 /* Delay after an RCC peripheral clock enabling */ \ 1175 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1176 UNUSED(tmpreg); \ 1177 } while(0) 1178 1179 #if defined(USART3) 1180 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1181 __IO uint32_t tmpreg; \ 1182 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1183 /* Delay after an RCC peripheral clock enabling */ \ 1184 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1185 UNUSED(tmpreg); \ 1186 } while(0) 1187 #endif /* USART3 */ 1188 1189 #if defined(UART4) 1190 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1191 __IO uint32_t tmpreg; \ 1192 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1193 /* Delay after an RCC peripheral clock enabling */ \ 1194 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1195 UNUSED(tmpreg); \ 1196 } while(0) 1197 #endif /* UART4 */ 1198 1199 #if defined(UART5) 1200 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1201 __IO uint32_t tmpreg; \ 1202 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1203 /* Delay after an RCC peripheral clock enabling */ \ 1204 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1205 UNUSED(tmpreg); \ 1206 } while(0) 1207 #endif /* UART5 */ 1208 1209 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1210 __IO uint32_t tmpreg; \ 1211 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1212 /* Delay after an RCC peripheral clock enabling */ \ 1213 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1214 UNUSED(tmpreg); \ 1215 } while(0) 1216 1217 #if defined(I2C2) 1218 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1219 __IO uint32_t tmpreg; \ 1220 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1221 /* Delay after an RCC peripheral clock enabling */ \ 1222 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1223 UNUSED(tmpreg); \ 1224 } while(0) 1225 #endif /* I2C2 */ 1226 1227 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1228 __IO uint32_t tmpreg; \ 1229 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1230 /* Delay after an RCC peripheral clock enabling */ \ 1231 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1232 UNUSED(tmpreg); \ 1233 } while(0) 1234 1235 #if defined(I2C4) 1236 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1237 __IO uint32_t tmpreg; \ 1238 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1239 /* Delay after an RCC peripheral clock enabling */ \ 1240 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1241 UNUSED(tmpreg); \ 1242 } while(0) 1243 #endif /* I2C4 */ 1244 1245 #if defined(CRS) 1246 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1247 __IO uint32_t tmpreg; \ 1248 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1249 /* Delay after an RCC peripheral clock enabling */ \ 1250 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1251 UNUSED(tmpreg); \ 1252 } while(0) 1253 #endif /* CRS */ 1254 1255 #if defined(CAN1) 1256 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 1257 __IO uint32_t tmpreg; \ 1258 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 1259 /* Delay after an RCC peripheral clock enabling */ \ 1260 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 1261 UNUSED(tmpreg); \ 1262 } while(0) 1263 #endif /* CAN1 */ 1264 1265 #if defined(CAN2) 1266 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1267 __IO uint32_t tmpreg; \ 1268 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 1269 /* Delay after an RCC peripheral clock enabling */ \ 1270 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 1271 UNUSED(tmpreg); \ 1272 } while(0) 1273 #endif /* CAN2 */ 1274 1275 #if defined(USB) 1276 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1277 __IO uint32_t tmpreg; \ 1278 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 1279 /* Delay after an RCC peripheral clock enabling */ \ 1280 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 1281 UNUSED(tmpreg); \ 1282 } while(0) 1283 #endif /* USB */ 1284 1285 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1286 __IO uint32_t tmpreg; \ 1287 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1288 /* Delay after an RCC peripheral clock enabling */ \ 1289 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1290 UNUSED(tmpreg); \ 1291 } while(0) 1292 1293 #if defined(DAC1) 1294 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1295 __IO uint32_t tmpreg; \ 1296 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1297 /* Delay after an RCC peripheral clock enabling */ \ 1298 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1299 UNUSED(tmpreg); \ 1300 } while(0) 1301 #endif /* DAC1 */ 1302 1303 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1304 __IO uint32_t tmpreg; \ 1305 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1306 /* Delay after an RCC peripheral clock enabling */ \ 1307 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1308 UNUSED(tmpreg); \ 1309 } while(0) 1310 1311 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1312 __IO uint32_t tmpreg; \ 1313 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1314 /* Delay after an RCC peripheral clock enabling */ \ 1315 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1316 UNUSED(tmpreg); \ 1317 } while(0) 1318 1319 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1320 __IO uint32_t tmpreg; \ 1321 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1322 /* Delay after an RCC peripheral clock enabling */ \ 1323 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1324 UNUSED(tmpreg); \ 1325 } while(0) 1326 1327 #if defined(SWPMI1) 1328 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 1329 __IO uint32_t tmpreg; \ 1330 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 1331 /* Delay after an RCC peripheral clock enabling */ \ 1332 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 1333 UNUSED(tmpreg); \ 1334 } while(0) 1335 #endif /* SWPMI1 */ 1336 1337 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1338 __IO uint32_t tmpreg; \ 1339 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1340 /* Delay after an RCC peripheral clock enabling */ \ 1341 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1342 UNUSED(tmpreg); \ 1343 } while(0) 1344 1345 1346 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1347 1348 #if defined(TIM3) 1349 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1350 #endif /* TIM3 */ 1351 1352 #if defined(TIM4) 1353 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1354 #endif /* TIM4 */ 1355 1356 #if defined(TIM5) 1357 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1358 #endif /* TIM5 */ 1359 1360 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1361 1362 #if defined(TIM7) 1363 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1364 #endif /* TIM7 */ 1365 1366 #if defined(LCD) 1367 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); 1368 #endif /* LCD */ 1369 1370 #if defined(RCC_APB1ENR1_RTCAPBEN) 1371 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 1372 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1373 1374 #if defined(SPI2) 1375 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1376 #endif /* SPI2 */ 1377 1378 #if defined(SPI3) 1379 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1380 #endif /* SPI3 */ 1381 1382 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1383 1384 #if defined(USART3) 1385 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1386 #endif /* USART3 */ 1387 1388 #if defined(UART4) 1389 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1390 #endif /* UART4 */ 1391 1392 #if defined(UART5) 1393 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1394 #endif /* UART5 */ 1395 1396 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1397 1398 #if defined(I2C2) 1399 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1400 #endif /* I2C2 */ 1401 1402 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1403 1404 #if defined(I2C4) 1405 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1406 #endif /* I2C4 */ 1407 1408 #if defined(CRS) 1409 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 1410 #endif /* CRS */ 1411 1412 #if defined(CAN1) 1413 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) 1414 #endif /* CAN1 */ 1415 1416 #if defined(CAN2) 1417 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) 1418 #endif /* CAN2 */ 1419 1420 #if defined(USB) 1421 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); 1422 #endif /* USB */ 1423 1424 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 1425 1426 #if defined(DAC1) 1427 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 1428 #endif /* DAC1 */ 1429 1430 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 1431 1432 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1433 1434 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 1435 1436 #if defined(SWPMI1) 1437 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) 1438 #endif /* SWPMI1 */ 1439 1440 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1441 1442 /** 1443 * @} 1444 */ 1445 1446 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1447 * @brief Enable or disable the APB2 peripheral clock. 1448 * @note After reset, the peripheral clock (used for registers read/write access) 1449 * is disabled and the application software has to enable this clock before 1450 * using it. 1451 * @{ 1452 */ 1453 1454 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1455 __IO uint32_t tmpreg; \ 1456 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1457 /* Delay after an RCC peripheral clock enabling */ \ 1458 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1459 UNUSED(tmpreg); \ 1460 } while(0) 1461 1462 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ 1463 __IO uint32_t tmpreg; \ 1464 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 1465 /* Delay after an RCC peripheral clock enabling */ \ 1466 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 1467 UNUSED(tmpreg); \ 1468 } while(0) 1469 1470 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 1471 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1472 __IO uint32_t tmpreg; \ 1473 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 1474 /* Delay after an RCC peripheral clock enabling */ \ 1475 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 1476 UNUSED(tmpreg); \ 1477 } while(0) 1478 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 1479 1480 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1481 __IO uint32_t tmpreg; \ 1482 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1483 /* Delay after an RCC peripheral clock enabling */ \ 1484 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1485 UNUSED(tmpreg); \ 1486 } while(0) 1487 1488 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1489 __IO uint32_t tmpreg; \ 1490 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1491 /* Delay after an RCC peripheral clock enabling */ \ 1492 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1493 UNUSED(tmpreg); \ 1494 } while(0) 1495 1496 #if defined(TIM8) 1497 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1498 __IO uint32_t tmpreg; \ 1499 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1500 /* Delay after an RCC peripheral clock enabling */ \ 1501 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1502 UNUSED(tmpreg); \ 1503 } while(0) 1504 #endif /* TIM8 */ 1505 1506 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1507 __IO uint32_t tmpreg; \ 1508 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1509 /* Delay after an RCC peripheral clock enabling */ \ 1510 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1511 UNUSED(tmpreg); \ 1512 } while(0) 1513 1514 1515 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1516 __IO uint32_t tmpreg; \ 1517 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1518 /* Delay after an RCC peripheral clock enabling */ \ 1519 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1520 UNUSED(tmpreg); \ 1521 } while(0) 1522 1523 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1524 __IO uint32_t tmpreg; \ 1525 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1526 /* Delay after an RCC peripheral clock enabling */ \ 1527 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1528 UNUSED(tmpreg); \ 1529 } while(0) 1530 1531 #if defined(TIM17) 1532 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1533 __IO uint32_t tmpreg; \ 1534 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1535 /* Delay after an RCC peripheral clock enabling */ \ 1536 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1537 UNUSED(tmpreg); \ 1538 } while(0) 1539 #endif /* TIM17 */ 1540 1541 #if defined(SAI1) 1542 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1543 __IO uint32_t tmpreg; \ 1544 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1545 /* Delay after an RCC peripheral clock enabling */ \ 1546 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1547 UNUSED(tmpreg); \ 1548 } while(0) 1549 #endif /* SAI1 */ 1550 1551 #if defined(SAI2) 1552 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1553 __IO uint32_t tmpreg; \ 1554 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1555 /* Delay after an RCC peripheral clock enabling */ \ 1556 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1557 UNUSED(tmpreg); \ 1558 } while(0) 1559 #endif /* SAI2 */ 1560 1561 #if defined(DFSDM1_Filter0) 1562 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 1563 __IO uint32_t tmpreg; \ 1564 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1565 /* Delay after an RCC peripheral clock enabling */ \ 1566 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1567 UNUSED(tmpreg); \ 1568 } while(0) 1569 #endif /* DFSDM1_Filter0 */ 1570 1571 #if defined(LTDC) 1572 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1573 __IO uint32_t tmpreg; \ 1574 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1575 /* Delay after an RCC peripheral clock enabling */ \ 1576 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1577 UNUSED(tmpreg); \ 1578 } while(0) 1579 #endif /* LTDC */ 1580 1581 #if defined(DSI) 1582 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1583 __IO uint32_t tmpreg; \ 1584 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 1585 /* Delay after an RCC peripheral clock enabling */ \ 1586 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 1587 UNUSED(tmpreg); \ 1588 } while(0) 1589 #endif /* DSI */ 1590 1591 1592 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 1593 1594 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 1595 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) 1596 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 1597 1598 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1599 1600 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1601 1602 #if defined(TIM8) 1603 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1604 #endif /* TIM8 */ 1605 1606 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1607 1608 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1609 1610 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1611 1612 #if defined(TIM17) 1613 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1614 #endif /* TIM17 */ 1615 1616 #if defined(SAI1) 1617 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1618 #endif /* SAI1 */ 1619 1620 #if defined(SAI2) 1621 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1622 #endif /* SAI2 */ 1623 1624 #if defined(DFSDM1_Filter0) 1625 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 1626 #endif /* DFSDM1_Filter0 */ 1627 1628 #if defined(LTDC) 1629 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 1630 #endif /* LTDC */ 1631 1632 #if defined(DSI) 1633 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) 1634 #endif /* DSI */ 1635 1636 /** 1637 * @} 1638 */ 1639 1640 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1641 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1642 * @note After reset, the peripheral clock (used for registers read/write access) 1643 * is disabled and the application software has to enable this clock before 1644 * using it. 1645 * @{ 1646 */ 1647 1648 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 1649 1650 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 1651 1652 #if defined(DMAMUX1) 1653 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 1654 #endif /* DMAMUX1 */ 1655 1656 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1657 1658 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1659 1660 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1661 1662 #if defined(DMA2D) 1663 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 1664 #endif /* DMA2D */ 1665 1666 #if defined(GFXMMU) 1667 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) 1668 #endif /* GFXMMU */ 1669 1670 1671 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 1672 1673 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 1674 1675 #if defined(DMAMUX1) 1676 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 1677 #endif /* DMAMUX1 */ 1678 1679 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1680 1681 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1682 1683 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1684 1685 #if defined(DMA2D) 1686 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 1687 #endif /* DMA2D */ 1688 1689 #if defined(GFXMMU) 1690 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) 1691 #endif /* GFXMMU */ 1692 1693 /** 1694 * @} 1695 */ 1696 1697 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1698 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1699 * @note After reset, the peripheral clock (used for registers read/write access) 1700 * is disabled and the application software has to enable this clock before 1701 * using it. 1702 * @{ 1703 */ 1704 1705 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1706 1707 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 1708 1709 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1710 1711 #if defined(GPIOD) 1712 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 1713 #endif /* GPIOD */ 1714 1715 #if defined(GPIOE) 1716 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 1717 #endif /* GPIOE */ 1718 1719 #if defined(GPIOF) 1720 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 1721 #endif /* GPIOF */ 1722 1723 #if defined(GPIOG) 1724 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 1725 #endif /* GPIOG */ 1726 1727 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 1728 1729 #if defined(GPIOI) 1730 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 1731 #endif /* GPIOI */ 1732 1733 #if defined(USB_OTG_FS) 1734 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) 1735 #endif /* USB_OTG_FS */ 1736 1737 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 1738 1739 #if defined(DCMI) 1740 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U) 1741 #endif /* DCMI */ 1742 1743 #if defined(PKA) 1744 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 1745 #endif /* PKA */ 1746 1747 #if defined(AES) 1748 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1749 #endif /* AES */ 1750 1751 #if defined(HASH) 1752 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 1753 #endif /* HASH */ 1754 1755 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1756 1757 #if defined(OCTOSPIM) 1758 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) != 0U) 1759 #endif /* OCTOSPIM */ 1760 1761 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 1762 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) != 0U) 1763 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 1764 1765 #if defined(SDMMC2) 1766 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U) 1767 #endif /* SDMMC2 */ 1768 1769 1770 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 1771 1772 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 1773 1774 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 1775 1776 #if defined(GPIOD) 1777 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 1778 #endif /* GPIOD */ 1779 1780 #if defined(GPIOE) 1781 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 1782 #endif /* GPIOE */ 1783 1784 #if defined(GPIOF) 1785 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 1786 #endif /* GPIOF */ 1787 1788 #if defined(GPIOG) 1789 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 1790 #endif /* GPIOG */ 1791 1792 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 1793 1794 #if defined(GPIOI) 1795 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 1796 #endif /* GPIOI */ 1797 1798 #if defined(USB_OTG_FS) 1799 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) 1800 #endif /* USB_OTG_FS */ 1801 1802 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 1803 1804 #if defined(DCMI) 1805 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U) 1806 #endif /* DCMI */ 1807 1808 #if defined(PKA) 1809 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 1810 #endif /* PKA */ 1811 1812 #if defined(AES) 1813 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 1814 #endif /* AES */ 1815 1816 #if defined(HASH) 1817 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 1818 #endif /* HASH */ 1819 1820 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 1821 1822 #if defined(OCTOSPIM) 1823 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) == 0U) 1824 #endif /* OCTOSPIM */ 1825 1826 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 1827 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) == 0U) 1828 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 1829 1830 #if defined(SDMMC2) 1831 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) == 0U) 1832 #endif /* SDMMC2 */ 1833 1834 /** 1835 * @} 1836 */ 1837 1838 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1839 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1840 * @note After reset, the peripheral clock (used for registers read/write access) 1841 * is disabled and the application software has to enable this clock before 1842 * using it. 1843 * @{ 1844 */ 1845 1846 #if defined(FMC_BANK1) 1847 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 1848 #endif /* FMC_BANK1 */ 1849 1850 #if defined(QUADSPI) 1851 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) 1852 #endif /* QUADSPI */ 1853 1854 #if defined(OCTOSPI1) 1855 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) != 0U) 1856 #endif /* OCTOSPI1 */ 1857 1858 #if defined(OCTOSPI2) 1859 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) != 0U) 1860 #endif /* OCTOSPI2 */ 1861 1862 #if defined(FMC_BANK1) 1863 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 1864 #endif /* FMC_BANK1 */ 1865 1866 #if defined(QUADSPI) 1867 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) 1868 #endif /* QUADSPI */ 1869 1870 #if defined(OCTOSPI1) 1871 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) == 0U) 1872 #endif /* OCTOSPI1 */ 1873 1874 #if defined(OCTOSPI2) 1875 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) == 0U) 1876 #endif /* OCTOSPI2 */ 1877 1878 /** 1879 * @} 1880 */ 1881 1882 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1883 * @brief Check whether the APB1 peripheral clock is enabled or not. 1884 * @note After reset, the peripheral clock (used for registers read/write access) 1885 * is disabled and the application software has to enable this clock before 1886 * using it. 1887 * @{ 1888 */ 1889 1890 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1891 1892 #if defined(TIM3) 1893 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1894 #endif /* TIM3 */ 1895 1896 #if defined(TIM4) 1897 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1898 #endif /* TIM4 */ 1899 1900 #if defined(TIM5) 1901 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1902 #endif /* TIM5 */ 1903 1904 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1905 1906 #if defined(TIM7) 1907 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1908 #endif /* TIM7 */ 1909 1910 #if defined(LCD) 1911 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U) 1912 #endif /* LCD */ 1913 1914 #if defined(RCC_APB1ENR1_RTCAPBEN) 1915 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 1916 #endif /* RCC_APB1ENR1_RTCAPBEN */ 1917 1918 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1919 1920 #if defined(SPI2) 1921 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1922 #endif /* SPI2 */ 1923 1924 #if defined(SPI3) 1925 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 1926 #endif /* SPI3 */ 1927 1928 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1929 1930 #if defined(USART3) 1931 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1932 #endif /* USART3 */ 1933 1934 #if defined(UART4) 1935 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1936 #endif /* UART4 */ 1937 1938 #if defined(UART5) 1939 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1940 #endif /* UART5 */ 1941 1942 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1943 1944 #if defined(I2C2) 1945 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1946 #endif /* I2C2 */ 1947 1948 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 1949 1950 #if defined(I2C4) 1951 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1952 #endif /* I2C4 */ 1953 1954 #if defined(CRS) 1955 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1956 #endif /* CRS */ 1957 1958 #if defined(CAN1) 1959 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U) 1960 #endif /* CAN1 */ 1961 1962 #if defined(CAN2) 1963 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U) 1964 #endif /* CAN2 */ 1965 1966 #if defined(USB) 1967 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) 1968 #endif /* USB */ 1969 1970 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 1971 1972 #if defined(DAC1) 1973 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) 1974 #endif /* DAC1 */ 1975 1976 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) 1977 1978 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 1979 1980 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 1981 1982 #if defined(SWPMI1) 1983 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U) 1984 #endif /* SWPMI1 */ 1985 1986 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1987 1988 1989 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1990 1991 #if defined(TIM3) 1992 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1993 #endif /* TIM3 */ 1994 1995 #if defined(TIM4) 1996 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1997 #endif /* TIM4 */ 1998 1999 #if defined(TIM5) 2000 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 2001 #endif /* TIM5 */ 2002 2003 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 2004 2005 #if defined(TIM7) 2006 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 2007 #endif /* TIM7 */ 2008 2009 #if defined(LCD) 2010 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U) 2011 #endif /* LCD */ 2012 2013 #if defined(RCC_APB1ENR1_RTCAPBEN) 2014 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 2015 #endif /* RCC_APB1ENR1_RTCAPBEN */ 2016 2017 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 2018 2019 #if defined(SPI2) 2020 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 2021 #endif /* SPI2 */ 2022 2023 #if defined(SPI3) 2024 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 2025 #endif /* SPI3 */ 2026 2027 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 2028 2029 #if defined(USART3) 2030 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 2031 #endif /* USART3 */ 2032 2033 #if defined(UART4) 2034 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 2035 #endif /* UART4 */ 2036 2037 #if defined(UART5) 2038 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 2039 #endif /* UART5 */ 2040 2041 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 2042 2043 #if defined(I2C2) 2044 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 2045 #endif /* I2C2 */ 2046 2047 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 2048 2049 #if defined(I2C4) 2050 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 2051 #endif /* I2C4 */ 2052 2053 #if defined(CRS) 2054 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 2055 #endif /* CRS */ 2056 2057 #if defined(CAN1) 2058 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U) 2059 #endif /* CAN1 */ 2060 2061 #if defined(CAN2) 2062 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U) 2063 #endif /* CAN2 */ 2064 2065 #if defined(USB) 2066 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) 2067 #endif /* USB */ 2068 2069 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 2070 2071 #if defined(DAC1) 2072 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) 2073 #endif /* DAC1 */ 2074 2075 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) 2076 2077 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 2078 2079 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 2080 2081 #if defined(SWPMI1) 2082 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U) 2083 #endif /* SWPMI1 */ 2084 2085 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 2086 2087 /** 2088 * @} 2089 */ 2090 2091 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2092 * @brief Check whether the APB2 peripheral clock is enabled or not. 2093 * @note After reset, the peripheral clock (used for registers read/write access) 2094 * is disabled and the application software has to enable this clock before 2095 * using it. 2096 * @{ 2097 */ 2098 2099 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 2100 2101 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) 2102 2103 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 2104 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U) 2105 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 2106 2107 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2108 2109 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2110 2111 #if defined(TIM8) 2112 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2113 #endif /* TIM8 */ 2114 2115 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2116 2117 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2118 2119 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2120 2121 #if defined(TIM17) 2122 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2123 #endif /* TIM17 */ 2124 2125 #if defined(SAI1) 2126 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2127 #endif /* SAI1 */ 2128 2129 #if defined(SAI2) 2130 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2131 #endif /* SAI2 */ 2132 2133 #if defined(DFSDM1_Filter0) 2134 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) 2135 #endif /* DFSDM1_Filter0 */ 2136 2137 #if defined(LTDC) 2138 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) 2139 #endif /* LTDC */ 2140 2141 #if defined(DSI) 2142 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U) 2143 #endif /* DSI */ 2144 2145 2146 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 2147 2148 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 2149 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U) 2150 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 2151 2152 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2153 2154 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2155 2156 #if defined(TIM8) 2157 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2158 #endif /* TIM8 */ 2159 2160 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2161 2162 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2163 2164 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2165 2166 #if defined(TIM17) 2167 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2168 #endif /* TIM17 */ 2169 2170 #if defined(SAI1) 2171 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2172 #endif /* SAI1 */ 2173 2174 #if defined(SAI2) 2175 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2176 #endif /* SAI2 */ 2177 2178 #if defined(DFSDM1_Filter0) 2179 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) 2180 #endif /* DFSDM1_Filter0 */ 2181 2182 #if defined(LTDC) 2183 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) 2184 #endif /* LTDC */ 2185 2186 #if defined(DSI) 2187 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U) 2188 #endif /* DSI */ 2189 2190 /** 2191 * @} 2192 */ 2193 2194 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2195 * @brief Force or release AHB1 peripheral reset. 2196 * @{ 2197 */ 2198 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) 2199 2200 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 2201 2202 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 2203 2204 #if defined(DMAMUX1) 2205 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 2206 #endif /* DMAMUX1 */ 2207 2208 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 2209 2210 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2211 2212 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2213 2214 #if defined(DMA2D) 2215 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2216 #endif /* DMA2D */ 2217 2218 #if defined(GFXMMU) 2219 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2220 #endif /* GFXMMU */ 2221 2222 2223 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2224 2225 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 2226 2227 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 2228 2229 #if defined(DMAMUX1) 2230 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 2231 #endif /* DMAMUX1 */ 2232 2233 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 2234 2235 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2236 2237 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2238 2239 #if defined(DMA2D) 2240 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2241 #endif /* DMA2D */ 2242 2243 #if defined(GFXMMU) 2244 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2245 #endif /* GFXMMU */ 2246 2247 /** 2248 * @} 2249 */ 2250 2251 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2252 * @brief Force or release AHB2 peripheral reset. 2253 * @{ 2254 */ 2255 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) 2256 2257 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2258 2259 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2260 2261 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2262 2263 #if defined(GPIOD) 2264 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2265 #endif /* GPIOD */ 2266 2267 #if defined(GPIOE) 2268 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2269 #endif /* GPIOE */ 2270 2271 #if defined(GPIOF) 2272 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2273 #endif /* GPIOF */ 2274 2275 #if defined(GPIOG) 2276 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2277 #endif /* GPIOG */ 2278 2279 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2280 2281 #if defined(GPIOI) 2282 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2283 #endif /* GPIOI */ 2284 2285 #if defined(USB_OTG_FS) 2286 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 2287 #endif /* USB_OTG_FS */ 2288 2289 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2290 2291 #if defined(DCMI) 2292 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 2293 #endif /* DCMI */ 2294 2295 #if defined(PKA) 2296 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2297 #endif /* PKA */ 2298 2299 #if defined(AES) 2300 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2301 #endif /* AES */ 2302 2303 #if defined(HASH) 2304 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2305 #endif /* HASH */ 2306 2307 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2308 2309 #if defined(OCTOSPIM) 2310 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 2311 #endif /* OCTOSPIM */ 2312 2313 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 2314 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 2315 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 2316 2317 #if defined(SDMMC2) 2318 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 2319 #endif /* SDMMC2 */ 2320 2321 2322 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 2323 2324 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2325 2326 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2327 2328 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2329 2330 #if defined(GPIOD) 2331 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2332 #endif /* GPIOD */ 2333 2334 #if defined(GPIOE) 2335 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2336 #endif /* GPIOE */ 2337 2338 #if defined(GPIOF) 2339 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2340 #endif /* GPIOF */ 2341 2342 #if defined(GPIOG) 2343 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2344 #endif /* GPIOG */ 2345 2346 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2347 2348 #if defined(GPIOI) 2349 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2350 #endif /* GPIOI */ 2351 2352 #if defined(USB_OTG_FS) 2353 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 2354 #endif /* USB_OTG_FS */ 2355 2356 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2357 2358 #if defined(DCMI) 2359 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 2360 #endif /* DCMI */ 2361 2362 #if defined(PKA) 2363 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2364 #endif /* PKA */ 2365 2366 #if defined(AES) 2367 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2368 #endif /* AES */ 2369 2370 #if defined(HASH) 2371 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2372 #endif /* HASH */ 2373 2374 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2375 2376 #if defined(OCTOSPIM) 2377 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 2378 #endif /* OCTOSPIM */ 2379 2380 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 2381 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 2382 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 2383 2384 #if defined(SDMMC2) 2385 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 2386 #endif /* SDMMC2 */ 2387 2388 /** 2389 * @} 2390 */ 2391 2392 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2393 * @brief Force or release AHB3 peripheral reset. 2394 * @{ 2395 */ 2396 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) 2397 2398 #if defined(FMC_BANK1) 2399 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 2400 #endif /* FMC_BANK1 */ 2401 2402 #if defined(QUADSPI) 2403 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 2404 #endif /* QUADSPI */ 2405 2406 #if defined(OCTOSPI1) 2407 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 2408 #endif /* OCTOSPI1 */ 2409 2410 #if defined(OCTOSPI2) 2411 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 2412 #endif /* OCTOSPI2 */ 2413 2414 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 2415 2416 #if defined(FMC_BANK1) 2417 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 2418 #endif /* FMC_BANK1 */ 2419 2420 #if defined(QUADSPI) 2421 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 2422 #endif /* QUADSPI */ 2423 2424 #if defined(OCTOSPI1) 2425 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 2426 #endif /* OCTOSPI1 */ 2427 2428 #if defined(OCTOSPI2) 2429 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 2430 #endif /* OCTOSPI2 */ 2431 2432 /** 2433 * @} 2434 */ 2435 2436 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2437 * @brief Force or release APB1 peripheral reset. 2438 * @{ 2439 */ 2440 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) 2441 2442 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2443 2444 #if defined(TIM3) 2445 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2446 #endif /* TIM3 */ 2447 2448 #if defined(TIM4) 2449 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2450 #endif /* TIM4 */ 2451 2452 #if defined(TIM5) 2453 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2454 #endif /* TIM5 */ 2455 2456 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2457 2458 #if defined(TIM7) 2459 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2460 #endif /* TIM7 */ 2461 2462 #if defined(LCD) 2463 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 2464 #endif /* LCD */ 2465 2466 #if defined(SPI2) 2467 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2468 #endif /* SPI2 */ 2469 2470 #if defined(SPI3) 2471 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2472 #endif /* SPI3 */ 2473 2474 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2475 2476 #if defined(USART3) 2477 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2478 #endif /* USART3 */ 2479 2480 #if defined(UART4) 2481 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2482 #endif /* UART4 */ 2483 2484 #if defined(UART5) 2485 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2486 #endif /* UART5 */ 2487 2488 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2489 2490 #if defined(I2C2) 2491 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2492 #endif /* I2C2 */ 2493 2494 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2495 2496 #if defined(I2C4) 2497 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2498 #endif /* I2C4 */ 2499 2500 #if defined(CRS) 2501 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2502 #endif /* CRS */ 2503 2504 #if defined(CAN1) 2505 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 2506 #endif /* CAN1 */ 2507 2508 #if defined(CAN2) 2509 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 2510 #endif /* CAN2 */ 2511 2512 #if defined(USB) 2513 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 2514 #endif /* USB */ 2515 2516 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 2517 2518 #if defined(DAC1) 2519 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 2520 #endif /* DAC1 */ 2521 2522 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 2523 2524 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2525 2526 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 2527 2528 #if defined(SWPMI1) 2529 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 2530 #endif /* SWPMI1 */ 2531 2532 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2533 2534 2535 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) 2536 2537 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2538 2539 #if defined(TIM3) 2540 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2541 #endif /* TIM3 */ 2542 2543 #if defined(TIM4) 2544 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2545 #endif /* TIM4 */ 2546 2547 #if defined(TIM5) 2548 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2549 #endif /* TIM5 */ 2550 2551 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2552 2553 #if defined(TIM7) 2554 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2555 #endif /* TIM7 */ 2556 2557 #if defined(LCD) 2558 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 2559 #endif /* LCD */ 2560 2561 #if defined(SPI2) 2562 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2563 #endif /* SPI2 */ 2564 2565 #if defined(SPI3) 2566 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2567 #endif /* SPI3 */ 2568 2569 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2570 2571 #if defined(USART3) 2572 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2573 #endif /* USART3 */ 2574 2575 #if defined(UART4) 2576 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2577 #endif /* UART4 */ 2578 2579 #if defined(UART5) 2580 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2581 #endif /* UART5 */ 2582 2583 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2584 2585 #if defined(I2C2) 2586 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2587 #endif /* I2C2 */ 2588 2589 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2590 2591 #if defined(I2C4) 2592 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2593 #endif /* I2C4 */ 2594 2595 #if defined(CRS) 2596 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2597 #endif /* CRS */ 2598 2599 #if defined(CAN1) 2600 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 2601 #endif /* CAN1 */ 2602 2603 #if defined(CAN2) 2604 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 2605 #endif /* CAN2 */ 2606 2607 #if defined(USB) 2608 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 2609 #endif /* USB */ 2610 2611 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 2612 2613 #if defined(DAC1) 2614 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 2615 #endif /* DAC1 */ 2616 2617 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 2618 2619 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2620 2621 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 2622 2623 #if defined(SWPMI1) 2624 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 2625 #endif /* SWPMI1 */ 2626 2627 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2628 2629 /** 2630 * @} 2631 */ 2632 2633 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2634 * @brief Force or release APB2 peripheral reset. 2635 * @{ 2636 */ 2637 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) 2638 2639 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 2640 2641 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 2642 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 2643 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 2644 2645 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2646 2647 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2648 2649 #if defined(TIM8) 2650 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2651 #endif /* TIM8 */ 2652 2653 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2654 2655 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2656 2657 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2658 2659 #if defined(TIM17) 2660 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2661 #endif /* TIM17 */ 2662 2663 #if defined(SAI1) 2664 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2665 #endif /* SAI1 */ 2666 2667 #if defined(SAI2) 2668 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2669 #endif /* SAI2 */ 2670 2671 #if defined(DFSDM1_Filter0) 2672 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 2673 #endif /* DFSDM1_Filter0 */ 2674 2675 #if defined(LTDC) 2676 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 2677 #endif /* LTDC */ 2678 2679 #if defined(DSI) 2680 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 2681 #endif /* DSI */ 2682 2683 2684 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 2685 2686 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 2687 2688 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 2689 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 2690 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 2691 2692 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2693 2694 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2695 2696 #if defined(TIM8) 2697 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 2698 #endif /* TIM8 */ 2699 2700 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2701 2702 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2703 2704 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2705 2706 #if defined(TIM17) 2707 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2708 #endif /* TIM17 */ 2709 2710 #if defined(SAI1) 2711 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2712 #endif /* SAI1 */ 2713 2714 #if defined(SAI2) 2715 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2716 #endif /* SAI2 */ 2717 2718 #if defined(DFSDM1_Filter0) 2719 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 2720 #endif /* DFSDM1_Filter0 */ 2721 2722 #if defined(LTDC) 2723 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 2724 #endif /* LTDC */ 2725 2726 #if defined(DSI) 2727 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 2728 #endif /* DSI */ 2729 2730 /** 2731 * @} 2732 */ 2733 2734 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2735 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2736 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2737 * power consumption. 2738 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2739 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2740 * @{ 2741 */ 2742 2743 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2744 2745 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2746 2747 #if defined(DMAMUX1) 2748 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2749 #endif /* DMAMUX1 */ 2750 2751 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2752 2753 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2754 2755 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2756 2757 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2758 2759 #if defined(DMA2D) 2760 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2761 #endif /* DMA2D */ 2762 2763 #if defined(GFXMMU) 2764 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 2765 #endif /* GFXMMU */ 2766 2767 2768 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2769 2770 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2771 2772 #if defined(DMAMUX1) 2773 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2774 #endif /* DMAMUX1 */ 2775 2776 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2777 2778 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2779 2780 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2781 2782 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2783 2784 #if defined(DMA2D) 2785 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 2786 #endif /* DMA2D */ 2787 2788 #if defined(GFXMMU) 2789 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 2790 #endif /* GFXMMU */ 2791 2792 /** 2793 * @} 2794 */ 2795 2796 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2797 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2798 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2799 * power consumption. 2800 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2801 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2802 * @{ 2803 */ 2804 2805 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2806 2807 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2808 2809 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2810 2811 #if defined(GPIOD) 2812 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2813 #endif /* GPIOD */ 2814 2815 #if defined(GPIOE) 2816 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2817 #endif /* GPIOE */ 2818 2819 #if defined(GPIOF) 2820 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2821 #endif /* GPIOF */ 2822 2823 #if defined(GPIOG) 2824 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2825 #endif /* GPIOG */ 2826 2827 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2828 2829 #if defined(GPIOI) 2830 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 2831 #endif /* GPIOI */ 2832 2833 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2834 2835 #if defined(SRAM3) 2836 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 2837 #endif /* SRAM3 */ 2838 2839 #if defined(USB_OTG_FS) 2840 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 2841 #endif /* USB_OTG_FS */ 2842 2843 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2844 2845 #if defined(DCMI) 2846 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 2847 #endif /* DCMI */ 2848 2849 #if defined(PKA) 2850 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2851 #endif /* PKA */ 2852 2853 #if defined(AES) 2854 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2855 #endif /* AES */ 2856 2857 #if defined(HASH) 2858 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2859 #endif /* HASH */ 2860 2861 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2862 2863 #if defined(OCTOSPIM) 2864 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 2865 #endif /* OCTOSPIM */ 2866 2867 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 2868 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2869 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 2870 2871 #if defined(SDMMC2) 2872 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) 2873 #endif /* SDMMC2 */ 2874 2875 2876 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2877 2878 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2879 2880 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2881 2882 #if defined(GPIOD) 2883 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2884 #endif /* GPIOD */ 2885 2886 #if defined(GPIOE) 2887 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2888 #endif /* GPIOE */ 2889 2890 #if defined(GPIOF) 2891 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2892 #endif /* GPIOF */ 2893 2894 #if defined(GPIOG) 2895 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2896 #endif /* GPIOG */ 2897 2898 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2899 2900 #if defined(GPIOI) 2901 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 2902 #endif /* GPIOI */ 2903 2904 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2905 2906 #if defined(SRAM3) 2907 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 2908 #endif /* SRAM3 */ 2909 2910 #if defined(USB_OTG_FS) 2911 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 2912 #endif /* USB_OTG_FS */ 2913 2914 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2915 2916 #if defined(DCMI) 2917 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 2918 #endif /* DCMI */ 2919 2920 #if defined(PKA) 2921 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2922 #endif /* PKA */ 2923 2924 #if defined(AES) 2925 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2926 #endif /* AES */ 2927 2928 #if defined(HASH) 2929 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2930 #endif /* HASH */ 2931 2932 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2933 2934 #if defined(OCTOSPIM) 2935 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 2936 #endif /* OCTOSPIM */ 2937 2938 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 2939 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2940 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 2941 2942 #if defined(SDMMC2) 2943 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) 2944 #endif /* SDMMC2 */ 2945 2946 /** 2947 * @} 2948 */ 2949 2950 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2951 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2952 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2953 * power consumption. 2954 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2955 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2956 * @{ 2957 */ 2958 2959 #if defined(QUADSPI) 2960 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2961 #endif /* QUADSPI */ 2962 2963 #if defined(OCTOSPI1) 2964 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2965 #endif /* OCTOSPI1 */ 2966 2967 #if defined(OCTOSPI2) 2968 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 2969 #endif /* OCTOSPI2 */ 2970 2971 #if defined(FMC_BANK1) 2972 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2973 #endif /* FMC_BANK1 */ 2974 2975 #if defined(QUADSPI) 2976 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2977 #endif /* QUADSPI */ 2978 2979 #if defined(OCTOSPI1) 2980 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2981 #endif /* OCTOSPI1 */ 2982 2983 #if defined(OCTOSPI2) 2984 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 2985 #endif /* OCTOSPI2 */ 2986 2987 #if defined(FMC_BANK1) 2988 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2989 #endif /* FMC_BANK1 */ 2990 2991 /** 2992 * @} 2993 */ 2994 2995 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2996 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2997 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2998 * power consumption. 2999 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3000 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3001 * @{ 3002 */ 3003 3004 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3005 3006 #if defined(TIM3) 3007 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3008 #endif /* TIM3 */ 3009 3010 #if defined(TIM4) 3011 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3012 #endif /* TIM4 */ 3013 3014 #if defined(TIM5) 3015 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3016 #endif /* TIM5 */ 3017 3018 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3019 3020 #if defined(TIM7) 3021 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3022 #endif /* TIM7 */ 3023 3024 #if defined(LCD) 3025 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 3026 #endif /* LCD */ 3027 3028 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3029 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 3030 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3031 3032 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3033 3034 #if defined(SPI2) 3035 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3036 #endif /* SPI2 */ 3037 3038 #if defined(SPI3) 3039 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 3040 #endif /* SPI3 */ 3041 3042 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3043 3044 #if defined(USART3) 3045 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3046 #endif /* USART3 */ 3047 3048 #if defined(UART4) 3049 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3050 #endif /* UART4 */ 3051 3052 #if defined(UART5) 3053 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3054 #endif /* UART5 */ 3055 3056 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3057 3058 #if defined(I2C2) 3059 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3060 #endif /* I2C2 */ 3061 3062 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 3063 3064 #if defined(I2C4) 3065 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3066 #endif /* I2C4 */ 3067 3068 #if defined(CRS) 3069 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3070 #endif /* CRS */ 3071 3072 #if defined(CAN1) 3073 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 3074 #endif /* CAN1 */ 3075 3076 #if defined(CAN2) 3077 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 3078 #endif /* CAN2 */ 3079 3080 #if defined(USB) 3081 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 3082 #endif /* USB */ 3083 3084 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 3085 3086 #if defined(DAC1) 3087 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 3088 #endif /* DAC1 */ 3089 3090 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 3091 3092 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 3093 3094 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 3095 3096 #if defined(SWPMI1) 3097 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 3098 #endif /* SWPMI1 */ 3099 3100 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3101 3102 3103 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3104 3105 #if defined(TIM3) 3106 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3107 #endif /* TIM3 */ 3108 3109 #if defined(TIM4) 3110 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3111 #endif /* TIM4 */ 3112 3113 #if defined(TIM5) 3114 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3115 #endif /* TIM5 */ 3116 3117 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3118 3119 #if defined(TIM7) 3120 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3121 #endif /* TIM7 */ 3122 3123 #if defined(LCD) 3124 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 3125 #endif /* LCD */ 3126 3127 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3128 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 3129 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3130 3131 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3132 3133 #if defined(SPI2) 3134 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3135 #endif /* SPI2 */ 3136 3137 #if defined(SPI3) 3138 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 3139 #endif /* SPI3 */ 3140 3141 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3142 3143 #if defined(USART3) 3144 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3145 #endif /* USART3 */ 3146 3147 #if defined(UART4) 3148 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3149 #endif /* UART4 */ 3150 3151 #if defined(UART5) 3152 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3153 #endif /* UART5 */ 3154 3155 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3156 3157 #if defined(I2C2) 3158 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3159 #endif /* I2C2 */ 3160 3161 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 3162 3163 #if defined(I2C4) 3164 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3165 #endif /* I2C4 */ 3166 3167 #if defined(CRS) 3168 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3169 #endif /* CRS */ 3170 3171 #if defined(CAN1) 3172 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 3173 #endif /* CAN1 */ 3174 3175 #if defined(CAN2) 3176 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 3177 #endif /* CAN2 */ 3178 3179 #if defined(USB) 3180 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 3181 #endif /* USB */ 3182 3183 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 3184 3185 #if defined(DAC1) 3186 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 3187 #endif /* DAC1 */ 3188 3189 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 3190 3191 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 3192 3193 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 3194 3195 #if defined(SWPMI1) 3196 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 3197 #endif /* SWPMI1 */ 3198 3199 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3200 3201 /** 3202 * @} 3203 */ 3204 3205 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3206 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3207 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3208 * power consumption. 3209 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3210 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3211 * @{ 3212 */ 3213 3214 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 3215 3216 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3217 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 3218 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3219 3220 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3221 3222 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3223 3224 #if defined(TIM8) 3225 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3226 #endif /* TIM8 */ 3227 3228 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3229 3230 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3231 3232 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3233 3234 #if defined(TIM17) 3235 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3236 #endif /* TIM17 */ 3237 3238 #if defined(SAI1) 3239 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3240 #endif /* SAI1 */ 3241 3242 #if defined(SAI2) 3243 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3244 #endif /* SAI2 */ 3245 3246 #if defined(DFSDM1_Filter0) 3247 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 3248 #endif /* DFSDM1_Filter0 */ 3249 3250 #if defined(LTDC) 3251 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3252 #endif /* LTDC */ 3253 3254 #if defined(DSI) 3255 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 3256 #endif /* DSI */ 3257 3258 3259 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 3260 3261 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3262 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 3263 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3264 3265 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3266 3267 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3268 3269 #if defined(TIM8) 3270 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3271 #endif /* TIM8 */ 3272 3273 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3274 3275 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3276 3277 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3278 3279 #if defined(TIM17) 3280 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3281 #endif /* TIM17 */ 3282 3283 #if defined(SAI1) 3284 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3285 #endif /* SAI1 */ 3286 3287 #if defined(SAI2) 3288 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3289 #endif /* SAI2 */ 3290 3291 #if defined(DFSDM1_Filter0) 3292 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 3293 #endif /* DFSDM1_Filter0 */ 3294 3295 #if defined(LTDC) 3296 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3297 #endif /* LTDC */ 3298 3299 #if defined(DSI) 3300 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 3301 #endif /* DSI */ 3302 3303 /** 3304 * @} 3305 */ 3306 3307 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 3308 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3309 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3310 * power consumption. 3311 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3312 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3313 * @{ 3314 */ 3315 3316 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 3317 3318 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 3319 3320 #if defined(DMAMUX1) 3321 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 3322 #endif /* DMAMUX1 */ 3323 3324 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 3325 3326 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 3327 3328 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 3329 3330 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 3331 3332 #if defined(DMA2D) 3333 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U) 3334 #endif /* DMA2D */ 3335 3336 #if defined(GFXMMU) 3337 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U) 3338 #endif /* GFXMMU */ 3339 3340 3341 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 3342 3343 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 3344 3345 #if defined(DMAMUX1) 3346 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 3347 #endif /* DMAMUX1 */ 3348 3349 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 3350 3351 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 3352 3353 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 3354 3355 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) 3356 3357 #if defined(DMA2D) 3358 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U) 3359 #endif /* DMA2D */ 3360 3361 #if defined(GFXMMU) 3362 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U) 3363 #endif /* GFXMMU */ 3364 3365 /** 3366 * @} 3367 */ 3368 3369 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 3370 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3371 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3372 * power consumption. 3373 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3374 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3375 * @{ 3376 */ 3377 3378 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 3379 3380 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 3381 3382 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 3383 3384 #if defined(GPIOD) 3385 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 3386 #endif /* GPIOD */ 3387 3388 #if defined(GPIOE) 3389 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 3390 #endif /* GPIOE */ 3391 3392 #if defined(GPIOF) 3393 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 3394 #endif /* GPIOF */ 3395 3396 #if defined(GPIOG) 3397 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 3398 #endif /* GPIOG */ 3399 3400 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 3401 3402 #if defined(GPIOI) 3403 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U) 3404 #endif /* GPIOI */ 3405 3406 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 3407 3408 #if defined(SRAM3) 3409 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U) 3410 #endif /* SRAM3 */ 3411 3412 #if defined(USB_OTG_FS) 3413 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U) 3414 #endif /* USB_OTG_FS */ 3415 3416 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) 3417 3418 #if defined(DCMI) 3419 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U) 3420 #endif /* DCMI */ 3421 3422 #if defined(PKA) 3423 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) 3424 #endif /* PKA */ 3425 3426 #if defined(AES) 3427 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 3428 #endif /* AES */ 3429 3430 #if defined(HASH) 3431 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 3432 #endif /* HASH */ 3433 3434 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 3435 3436 #if defined(OCTOSPIM) 3437 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U) 3438 #endif /* OCTOSPIM */ 3439 3440 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 3441 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) 3442 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 3443 3444 #if defined(SDMMC2) 3445 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) != 0U) 3446 #endif /* SDMMC2 */ 3447 3448 3449 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 3450 3451 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 3452 3453 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 3454 3455 #if defined(GPIOD) 3456 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 3457 #endif /* GPIOD */ 3458 3459 #if defined(GPIOE) 3460 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 3461 #endif /* GPIOE */ 3462 3463 #if defined(GPIOF) 3464 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 3465 #endif /* GPIOF */ 3466 3467 #if defined(GPIOG) 3468 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 3469 #endif /* GPIOG */ 3470 3471 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) 3472 3473 #if defined(GPIOI) 3474 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U) 3475 #endif /* GPIOI */ 3476 3477 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 3478 3479 #if defined(SRAM3) 3480 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U) 3481 #endif /* SRAM3 */ 3482 3483 #if defined(USB_OTG_FS) 3484 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U) 3485 #endif /* USB_OTG_FS */ 3486 3487 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) 3488 3489 #if defined(DCMI) 3490 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U) 3491 #endif /* DCMI */ 3492 3493 #if defined(PKA) 3494 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) == 0U) 3495 #endif /* PKA */ 3496 3497 #if defined(AES) 3498 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 3499 #endif /* AES */ 3500 3501 #if defined(HASH) 3502 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) 3503 #endif /* HASH */ 3504 3505 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 3506 3507 #if defined(OCTOSPIM) 3508 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U) 3509 #endif /* OCTOSPIM */ 3510 3511 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 3512 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) 3513 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 3514 3515 #if defined(SDMMC2) 3516 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC2SMEN) == 0U) 3517 #endif /* SDMMC2 */ 3518 3519 /** 3520 * @} 3521 */ 3522 3523 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 3524 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 3525 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3526 * power consumption. 3527 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3528 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3529 * @{ 3530 */ 3531 3532 #if defined(QUADSPI) 3533 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) 3534 #endif /* QUADSPI */ 3535 3536 #if defined(OCTOSPI1) 3537 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U) 3538 #endif /* OCTOSPI1 */ 3539 3540 #if defined(OCTOSPI2) 3541 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U) 3542 #endif /* OCTOSPI2 */ 3543 3544 #if defined(FMC_BANK1) 3545 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 3546 #endif /* FMC_BANK1 */ 3547 3548 3549 #if defined(QUADSPI) 3550 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) 3551 #endif /* QUADSPI */ 3552 3553 #if defined(OCTOSPI1) 3554 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U) 3555 #endif /* OCTOSPI1 */ 3556 3557 #if defined(OCTOSPI2) 3558 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U) 3559 #endif /* OCTOSPI2 */ 3560 3561 #if defined(FMC_BANK1) 3562 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 3563 #endif /* FMC_BANK1 */ 3564 3565 /** 3566 * @} 3567 */ 3568 3569 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 3570 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3571 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3572 * power consumption. 3573 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3574 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3575 * @{ 3576 */ 3577 3578 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 3579 3580 #if defined(TIM3) 3581 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 3582 #endif /* TIM3 */ 3583 3584 #if defined(TIM4) 3585 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 3586 #endif /* TIM4 */ 3587 3588 #if defined(TIM5) 3589 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 3590 #endif /* TIM5 */ 3591 3592 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 3593 3594 #if defined(TIM7) 3595 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 3596 #endif /* TIM7 */ 3597 3598 #if defined(LCD) 3599 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U) 3600 #endif /* LCD */ 3601 3602 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3603 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 3604 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3605 3606 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 3607 3608 #if defined(SPI2) 3609 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 3610 #endif /* SPI2 */ 3611 3612 #if defined(SPI3) 3613 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 3614 #endif /* SPI3 */ 3615 3616 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 3617 3618 #if defined(USART3) 3619 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 3620 #endif /* USART3 */ 3621 3622 #if defined(UART4) 3623 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 3624 #endif /* UART4 */ 3625 3626 #if defined(UART5) 3627 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 3628 #endif /* UART5 */ 3629 3630 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 3631 3632 #if defined(I2C2) 3633 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 3634 #endif /* I2C2 */ 3635 3636 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 3637 3638 #if defined(I2C4) 3639 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 3640 #endif /* I2C4 */ 3641 3642 #if defined(CRS) 3643 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 3644 #endif /* CRS */ 3645 3646 #if defined(CAN1) 3647 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U) 3648 #endif /* CAN1 */ 3649 3650 #if defined(CAN2) 3651 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U) 3652 #endif /* CAN2 */ 3653 3654 #if defined(USB) 3655 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) 3656 #endif /* USB */ 3657 3658 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 3659 3660 #if defined(DAC1) 3661 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) 3662 #endif /* DAC1 */ 3663 3664 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) 3665 3666 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 3667 3668 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 3669 3670 #if defined(SWPMI1) 3671 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U) 3672 #endif /* SWPMI1 */ 3673 3674 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 3675 3676 3677 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 3678 3679 #if defined(TIM3) 3680 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 3681 #endif /* TIM3 */ 3682 3683 #if defined(TIM4) 3684 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 3685 #endif /* TIM4 */ 3686 3687 #if defined(TIM5) 3688 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 3689 #endif /* TIM5 */ 3690 3691 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 3692 3693 #if defined(TIM7) 3694 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 3695 #endif /* TIM7 */ 3696 3697 #if defined(LCD) 3698 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U) 3699 #endif /* LCD */ 3700 3701 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 3702 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 3703 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 3704 3705 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 3706 3707 #if defined(SPI2) 3708 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 3709 #endif /* SPI2 */ 3710 3711 #if defined(SPI3) 3712 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 3713 #endif /* SPI3 */ 3714 3715 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 3716 3717 #if defined(USART3) 3718 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 3719 #endif /* USART3 */ 3720 3721 #if defined(UART4) 3722 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 3723 #endif /* UART4 */ 3724 3725 #if defined(UART5) 3726 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 3727 #endif /* UART5 */ 3728 3729 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 3730 3731 #if defined(I2C2) 3732 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 3733 #endif /* I2C2 */ 3734 3735 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 3736 3737 #if defined(I2C4) 3738 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 3739 #endif /* I2C4 */ 3740 3741 #if defined(CRS) 3742 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 3743 #endif /* CRS */ 3744 3745 #if defined(CAN1) 3746 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U) 3747 #endif /* CAN1 */ 3748 3749 #if defined(CAN2) 3750 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U) 3751 #endif /* CAN2 */ 3752 3753 #if defined(USB) 3754 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) 3755 #endif /* USB */ 3756 3757 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 3758 3759 #if defined(DAC1) 3760 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) 3761 #endif /* DAC1 */ 3762 3763 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) 3764 3765 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 3766 3767 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 3768 3769 #if defined(SWPMI1) 3770 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U) 3771 #endif /* SWPMI1 */ 3772 3773 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) 3774 3775 /** 3776 * @} 3777 */ 3778 3779 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 3780 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3781 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3782 * power consumption. 3783 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3784 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3785 * @{ 3786 */ 3787 3788 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 3789 3790 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3791 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U) 3792 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3793 3794 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 3795 3796 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 3797 3798 #if defined(TIM8) 3799 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 3800 #endif /* TIM8 */ 3801 3802 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 3803 3804 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 3805 3806 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 3807 3808 #if defined(TIM17) 3809 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 3810 #endif /* TIM17 */ 3811 3812 #if defined(SAI1) 3813 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 3814 #endif /* SAI1 */ 3815 3816 #if defined(SAI2) 3817 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) 3818 #endif /* SAI2 */ 3819 3820 #if defined(DFSDM1_Filter0) 3821 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) 3822 #endif /* DFSDM1_Filter0 */ 3823 3824 #if defined(LTDC) 3825 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U) 3826 #endif /* LTDC */ 3827 3828 #if defined(DSI) 3829 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U) 3830 #endif /* DSI */ 3831 3832 3833 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 3834 3835 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 3836 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U) 3837 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 3838 3839 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 3840 3841 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 3842 3843 #if defined(TIM8) 3844 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 3845 #endif /* TIM8 */ 3846 3847 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 3848 3849 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 3850 3851 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 3852 3853 #if defined(TIM17) 3854 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 3855 #endif /* TIM17 */ 3856 3857 #if defined(SAI1) 3858 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 3859 #endif /* SAI1 */ 3860 3861 #if defined(SAI2) 3862 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) 3863 #endif /* SAI2 */ 3864 3865 #if defined(DFSDM1_Filter0) 3866 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) 3867 #endif /* DFSDM1_Filter0 */ 3868 3869 #if defined(LTDC) 3870 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U) 3871 #endif /* LTDC */ 3872 3873 #if defined(DSI) 3874 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U) 3875 #endif /* DSI */ 3876 3877 /** 3878 * @} 3879 */ 3880 3881 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 3882 * @{ 3883 */ 3884 3885 /** @brief Macros to force or release the Backup domain reset. 3886 * @note This function resets the RTC peripheral (including the backup registers) 3887 * and the RTC clock source selection in RCC_CSR register. 3888 * @note The BKPSRAM is not affected by this reset. 3889 * @retval None 3890 */ 3891 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3892 3893 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3894 3895 /** 3896 * @} 3897 */ 3898 3899 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 3900 * @{ 3901 */ 3902 3903 /** @brief Macros to enable or disable the RTC clock. 3904 * @note As the RTC is in the Backup domain and write access is denied to 3905 * this domain after reset, you have to enable write access using 3906 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3907 * (to be done once after reset). 3908 * @note These macros must be used after the RTC clock source was selected. 3909 * @retval None 3910 */ 3911 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3912 3913 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3914 3915 /** 3916 * @} 3917 */ 3918 3919 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3920 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3921 * It is used (enabled by hardware) as system clock source after startup 3922 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3923 * of the HSE used directly or indirectly as system clock (if the Clock 3924 * Security System CSS is enabled). 3925 * @note HSI can not be stopped if it is used as system clock source. In this case, 3926 * you have to select another source of the system clock then stop the HSI. 3927 * @note After enabling the HSI, the application software should wait on HSIRDY 3928 * flag to be set indicating that HSI clock is stable and can be used as 3929 * system clock source. 3930 * This parameter can be: ENABLE or DISABLE. 3931 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3932 * clock cycles. 3933 * @retval None 3934 */ 3935 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3936 3937 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3938 3939 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3940 * @note The calibration is used to compensate for the variations in voltage 3941 * and temperature that influence the frequency of the internal HSI RC. 3942 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 3943 * (default is RCC_HSICALIBRATION_DEFAULT). 3944 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). 3945 * @retval None 3946 */ 3947 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3948 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 3949 3950 /** 3951 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 3952 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 3953 * @note The enable of this function has not effect on the HSION bit. 3954 * This parameter can be: ENABLE or DISABLE. 3955 * @retval None 3956 */ 3957 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 3958 3959 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 3960 3961 /** 3962 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3963 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 3964 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3965 * speed because of the HSI startup time. 3966 * @note The enable of this function has not effect on the HSION bit. 3967 * This parameter can be: ENABLE or DISABLE. 3968 * @retval None 3969 */ 3970 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3971 3972 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3973 3974 /** 3975 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3976 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3977 * It is used (enabled by hardware) as system clock source after 3978 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3979 * of failure of the HSE used directly or indirectly as system clock 3980 * (if the Clock Security System CSS is enabled). 3981 * @note MSI can not be stopped if it is used as system clock source. 3982 * In this case, you have to select another source of the system 3983 * clock then stop the MSI. 3984 * @note After enabling the MSI, the application software should wait on 3985 * MSIRDY flag to be set indicating that MSI clock is stable and can 3986 * be used as system clock source. 3987 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3988 * clock cycles. 3989 * @retval None 3990 */ 3991 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 3992 3993 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 3994 3995 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 3996 * @note The calibration is used to compensate for the variations in voltage 3997 * and temperature that influence the frequency of the internal MSI RC. 3998 * Refer to the Application Note AN3300 for more details on how to 3999 * calibrate the MSI. 4000 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 4001 * (default is RCC_MSICALIBRATION_DEFAULT). 4002 * This parameter must be a number between 0 and 255. 4003 * @retval None 4004 */ 4005 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 4006 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) 4007 4008 /** 4009 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 4010 * @note After restart from Reset , the MSI clock is around 4 MHz. 4011 * After stop the startup clock can be MSI (at any of its possible 4012 * frequencies, the one that was used before entering stop mode) or HSI. 4013 * After Standby its frequency can be selected between 4 possible values 4014 * (1, 2, 4 or 8 MHz). 4015 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 4016 * (MSIRDY=1). 4017 * @note The MSI clock range after reset can be modified on the fly. 4018 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 4019 * This parameter must be one of the following values: 4020 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 4021 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 4022 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 4023 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 4024 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 4025 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4026 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 4027 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 4028 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 4029 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 4030 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 4031 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 4032 * @retval None 4033 */ 4034 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 4035 do { \ 4036 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 4037 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 4038 } while(0) 4039 4040 /** 4041 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 4042 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 4043 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 4044 * This parameter must be one of the following values: 4045 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 4046 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4047 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 4048 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 4049 * @retval None 4050 */ 4051 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 4052 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 4053 4054 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 4055 * @retval MSI clock range. 4056 * This parameter must be one of the following values: 4057 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 4058 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 4059 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 4060 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 4061 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 4062 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4063 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 4064 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 4065 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 4066 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 4067 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 4068 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 4069 */ 4070 #define __HAL_RCC_GET_MSI_RANGE() \ 4071 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 4072 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ 4073 (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)) 4074 4075 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4076 * @note After enabling the LSI, the application software should wait on 4077 * LSIRDY flag to be set indicating that LSI clock is stable and can 4078 * be used to clock the IWDG and/or the RTC. 4079 * @note LSI can not be disabled if the IWDG is running. 4080 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4081 * clock cycles. 4082 * @retval None 4083 */ 4084 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 4085 4086 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 4087 4088 /** 4089 * @brief Macro to configure the External High Speed oscillator (HSE). 4090 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4091 * supported by this macro. User should request a transition to HSE Off 4092 * first and then HSE On or HSE Bypass. 4093 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4094 * software should wait on HSERDY flag to be set indicating that HSE clock 4095 * is stable and can be used to clock the PLL and/or system clock. 4096 * @note HSE state can not be changed if it is used directly or through the 4097 * PLL as system clock. In this case, you have to select another source 4098 * of the system clock then change the HSE state (ex. disable it). 4099 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 4100 * @note This function reset the CSSON bit, so if the clock security system(CSS) 4101 * was previously enabled you have to enable it again after calling this 4102 * function. 4103 * @param __STATE__ specifies the new state of the HSE. 4104 * This parameter can be one of the following values: 4105 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4106 * 6 HSE oscillator clock cycles. 4107 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4108 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4109 * @retval None 4110 */ 4111 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4112 do { \ 4113 if((__STATE__) == RCC_HSE_ON) \ 4114 { \ 4115 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4116 } \ 4117 else if((__STATE__) == RCC_HSE_BYPASS) \ 4118 { \ 4119 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4120 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4121 } \ 4122 else \ 4123 { \ 4124 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4125 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4126 } \ 4127 } while(0) 4128 4129 /** 4130 * @brief Macro to configure the External Low Speed oscillator (LSE). 4131 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4132 * supported by this macro. User should request a transition to LSE Off 4133 * first and then LSE On or LSE Bypass. 4134 * @note As the LSE is in the Backup domain and write access is denied to 4135 * this domain after reset, you have to enable write access using 4136 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4137 * (to be done once after reset). 4138 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4139 * software should wait on LSERDY flag to be set indicating that LSE clock 4140 * is stable and can be used to clock the RTC. 4141 * @param __STATE__ specifies the new state of the LSE. 4142 * This parameter can be one of the following values: 4143 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4144 * 6 LSE oscillator clock cycles. 4145 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 4146 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 4147 * @retval None 4148 */ 4149 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4150 do { \ 4151 if((__STATE__) == RCC_LSE_ON) \ 4152 { \ 4153 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4154 } \ 4155 else if((__STATE__) == RCC_LSE_BYPASS) \ 4156 { \ 4157 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4158 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4159 } \ 4160 else \ 4161 { \ 4162 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4163 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4164 } \ 4165 } while(0) 4166 4167 #if defined(RCC_HSI48_SUPPORT) 4168 4169 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4170 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4171 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4172 * flag to be set indicating that HSI48 clock is stable. 4173 * This parameter can be: ENABLE or DISABLE. 4174 * @retval None 4175 */ 4176 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 4177 4178 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 4179 4180 #endif /* RCC_HSI48_SUPPORT */ 4181 4182 /** @brief Macros to configure the RTC clock (RTCCLK). 4183 * @note As the RTC clock configuration bits are in the Backup domain and write 4184 * access is denied to this domain after reset, you have to enable write 4185 * access using the Power Backup Access macro before to configure 4186 * the RTC clock source (to be done once after reset). 4187 * @note Once the RTC clock is configured it cannot be changed unless the 4188 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 4189 * a Power On Reset (POR). 4190 * 4191 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 4192 * This parameter can be one of the following values: 4193 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 4194 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4195 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4196 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4197 * 4198 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4199 * work in STOP and STANDBY modes, and can be used as wakeup source. 4200 * However, when the HSE clock is used as RTC clock source, the RTC 4201 * cannot be used in STOP and STANDBY modes. 4202 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4203 * RTC clock source). 4204 * @retval None 4205 */ 4206 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 4207 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 4208 4209 4210 /** @brief Macro to get the RTC clock source. 4211 * @retval The returned value can be one of the following: 4212 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 4213 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4214 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4215 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4216 */ 4217 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 4218 4219 /** @brief Macros to enable or disable the main PLL. 4220 * @note After enabling the main PLL, the application software should wait on 4221 * PLLRDY flag to be set indicating that PLL clock is stable and can 4222 * be used as system clock source. 4223 * @note The main PLL can not be disabled if it is used as system clock source 4224 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4225 * @retval None 4226 */ 4227 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 4228 4229 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 4230 4231 /** @brief Macro to configure the PLL clock source. 4232 * @note This function must be used only when the main PLL is disabled. 4233 * @param __PLLSOURCE__ specifies the PLL entry clock source. 4234 * This parameter can be one of the following values: 4235 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 4236 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 4237 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 4238 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 4239 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 4240 * @retval None 4241 * 4242 */ 4243 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 4244 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 4245 4246 /** @brief Macro to configure the PLL source division factor M. 4247 * @note This function must be used only when the main PLL is disabled. 4248 * @param __PLLM__ specifies the division factor for PLL VCO input clock 4249 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 4250 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 4251 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4252 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 4253 * of 16 MHz to limit PLL jitter. 4254 * @retval None 4255 * 4256 */ 4257 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 4258 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) 4259 4260 /** 4261 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 4262 * @note This function must be used only when the main PLL is disabled. 4263 * 4264 * @param __PLLSOURCE__ specifies the PLL entry clock source. 4265 * This parameter can be one of the following values: 4266 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 4267 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 4268 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 4269 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 4270 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 4271 * 4272 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 4273 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 4274 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 4275 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4276 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 4277 * of 16 MHz to limit PLL jitter. 4278 * 4279 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 4280 * This parameter must be a number between 8 and 86. 4281 * @note You have to set the PLLN parameter correctly to ensure that the VCO 4282 * output frequency is between 64 and 344 MHz. 4283 * 4284 * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device. 4285 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x 4286 * else (2 to 31). 4287 * 4288 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 4289 * This parameter must be in the range (2, 4, 6 or 8). 4290 * @note If the USB OTG FS is used in your application, you have to set the 4291 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 4292 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 4293 * correctly. 4294 * @param __PLLR__ specifies the division factor for the main system clock. 4295 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 4296 * This parameter must be in the range (2, 4, 6 or 8). 4297 * @retval None 4298 */ 4299 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 4300 4301 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 4302 MODIFY_REG(RCC->PLLCFGR, \ 4303 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 4304 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \ 4305 ((__PLLSOURCE__) | \ 4306 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 4307 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 4308 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 4309 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 4310 ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) 4311 4312 #elif defined(RCC_PLLP_SUPPORT) 4313 4314 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 4315 MODIFY_REG(RCC->PLLCFGR, \ 4316 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 4317 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \ 4318 ((__PLLSOURCE__) | \ 4319 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 4320 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 4321 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 4322 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 4323 (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos))) 4324 4325 #else 4326 4327 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \ 4328 MODIFY_REG(RCC->PLLCFGR, \ 4329 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 4330 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ 4331 ((__PLLSOURCE__) | \ 4332 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 4333 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 4334 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 4335 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 4336 4337 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 4338 4339 /** @brief Macro to get the oscillator used as PLL clock source. 4340 * @retval The oscillator used as PLL clock source. The returned value can be one 4341 * of the following: 4342 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 4343 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 4344 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 4345 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 4346 */ 4347 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) 4348 4349 /** 4350 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 4351 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 4352 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 4353 * be stopped if used as System Clock. 4354 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 4355 * This parameter can be one or a combination of the following values: 4356 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 4357 * high-quality audio performance on SAI interface in case. 4358 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 4359 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 4360 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 4361 * @retval None 4362 */ 4363 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4364 4365 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4366 4367 /** 4368 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 4369 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 4370 * This parameter can be one of the following values: 4371 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 4372 * high-quality audio performance on SAI interface in case. 4373 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 4374 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 4375 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 4376 * @retval SET / RESET 4377 */ 4378 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 4379 4380 /** 4381 * @brief Macro to configure the system clock source. 4382 * @param __SYSCLKSOURCE__ specifies the system clock source. 4383 * This parameter can be one of the following values: 4384 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 4385 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4386 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4387 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 4388 * @retval None 4389 */ 4390 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4391 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 4392 4393 /** @brief Macro to get the clock source used as system clock. 4394 * @retval The clock source used as system clock. The returned value can be one 4395 * of the following: 4396 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 4397 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4398 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4399 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 4400 */ 4401 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) 4402 4403 /** 4404 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4405 * @note As the LSE is in the Backup domain and write access is denied to 4406 * this domain after reset, you have to enable write access using 4407 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4408 * (to be done once after reset). 4409 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 4410 * This parameter can be one of the following values: 4411 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4412 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4413 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4414 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4415 * @retval None 4416 */ 4417 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4418 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) 4419 4420 /** 4421 * @brief Macro to configure the wake up from stop clock. 4422 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 4423 * This parameter can be one of the following values: 4424 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 4425 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4426 * @retval None 4427 */ 4428 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4429 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 4430 4431 4432 /** @brief Macro to configure the MCO clock. 4433 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4434 * This parameter can be one of the following values: 4435 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 4436 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 4437 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 4438 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 4439 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 4440 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 4441 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 4442 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 4443 @if STM32L443xx 4444 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4445 @endif 4446 @if STM32L4A6xx 4447 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4448 @endif 4449 * @param __MCODIV__ specifies the MCO clock prescaler. 4450 * This parameter can be one of the following values: 4451 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 4452 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 4453 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 4454 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 4455 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 4456 */ 4457 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4458 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4459 4460 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4461 * @brief macros to manage the specified RCC Flags and interrupts. 4462 * @{ 4463 */ 4464 4465 /** @brief Enable RCC interrupt(s). 4466 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 4467 * This parameter can be any combination of the following values: 4468 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4469 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4470 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4471 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4472 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4473 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4474 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4475 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4476 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4477 @if STM32L443xx 4478 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4479 @endif 4480 @if STM32L4A6xx 4481 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4482 @endif 4483 * @retval None 4484 */ 4485 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4486 4487 /** @brief Disable RCC interrupt(s). 4488 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 4489 * This parameter can be any combination of the following values: 4490 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4491 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4492 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4493 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4494 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4495 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4496 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4497 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4498 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4499 @if STM32L443xx 4500 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4501 @endif 4502 @if STM32L4A6xx 4503 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4504 @endif 4505 * @retval None 4506 */ 4507 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4508 4509 /** @brief Clear the RCC's interrupt pending bits. 4510 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4511 * This parameter can be any combination of the following values: 4512 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4513 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4514 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4515 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4516 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4517 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4518 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4519 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4520 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4521 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4522 @if STM32L443xx 4523 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4524 @endif 4525 @if STM32L4A6xx 4526 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4527 @endif 4528 * @retval None 4529 */ 4530 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4531 4532 /** @brief Check whether the RCC interrupt has occurred or not. 4533 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 4534 * This parameter can be one of the following values: 4535 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4536 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4537 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4538 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4539 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4540 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4541 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 4542 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 4543 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4544 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4545 @if STM32L443xx 4546 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4547 @endif 4548 @if STM32L4A6xx 4549 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 4550 @endif 4551 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4552 */ 4553 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 4554 4555 /** @brief Set RMVF bit to clear the reset flags. 4556 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4557 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4558 * @retval None 4559 */ 4560 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 4561 4562 /** @brief Check whether the selected RCC flag is set or not. 4563 * @param __FLAG__ specifies the flag to check. 4564 * This parameter can be one of the following values: 4565 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 4566 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4567 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4568 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 4569 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1 4570 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 4571 @if STM32L443xx 4572 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 4573 @endif 4574 @if STM32L4A6xx 4575 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 4576 @endif 4577 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4578 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4579 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4580 * @arg @ref RCC_FLAG_BORRST BOR reset 4581 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 4582 * @arg @ref RCC_FLAG_PINRST Pin reset 4583 * @arg @ref RCC_FLAG_FWRST FIREWALL reset 4584 * @arg @ref RCC_FLAG_SFTRST Software reset 4585 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4586 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4587 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4588 * @retval The new state of __FLAG__ (TRUE or FALSE). 4589 */ 4590 #if defined(RCC_HSI48_SUPPORT) 4591 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4592 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 4593 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4594 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 4595 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4596 #else 4597 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4598 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4599 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ 4600 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4601 #endif /* RCC_HSI48_SUPPORT */ 4602 4603 /** 4604 * @} 4605 */ 4606 4607 /** 4608 * @} 4609 */ 4610 4611 /* Private constants ---------------------------------------------------------*/ 4612 /** @defgroup RCC_Private_Constants RCC Private Constants 4613 * @{ 4614 */ 4615 /* Defines used for Flags */ 4616 #define CR_REG_INDEX 1U 4617 #define BDCR_REG_INDEX 2U 4618 #define CSR_REG_INDEX 3U 4619 #if defined(RCC_HSI48_SUPPORT) 4620 #define CRRCR_REG_INDEX 4U 4621 #endif /* RCC_HSI48_SUPPORT */ 4622 4623 #define RCC_FLAG_MASK 0x1FU 4624 /** 4625 * @} 4626 */ 4627 4628 /* Private macros ------------------------------------------------------------*/ 4629 /** @addtogroup RCC_Private_Macros 4630 * @{ 4631 */ 4632 4633 #if defined(RCC_HSI48_SUPPORT) 4634 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4635 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 4636 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 4637 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 4638 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 4639 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 4640 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 4641 #else 4642 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4643 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 4644 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 4645 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 4646 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 4647 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 4648 #endif /* RCC_HSI48_SUPPORT */ 4649 4650 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4651 ((__HSE__) == RCC_HSE_BYPASS)) 4652 4653 #if defined(RCC_BDCR_LSESYSDIS) 4654 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ 4655 ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS)) 4656 #else 4657 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4658 ((__LSE__) == RCC_LSE_BYPASS)) 4659 #endif /* RCC_BDCR_LSESYSDIS */ 4660 4661 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4662 4663 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 4664 4665 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4666 4667 #if defined(RCC_CSR_LSIPREDIV) 4668 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) 4669 #endif /* RCC_CSR_LSIPREDIV */ 4670 4671 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 4672 4673 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) 4674 4675 #if defined(RCC_HSI48_SUPPORT) 4676 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4677 #endif /* RCC_HSI48_SUPPORT */ 4678 4679 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 4680 ((__PLL__) == RCC_PLL_ON)) 4681 4682 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 4683 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 4684 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 4685 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 4686 4687 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 4688 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 4689 #else 4690 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 4691 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */ 4692 4693 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 4694 4695 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 4696 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 4697 #else 4698 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 4699 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ 4700 4701 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 4702 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 4703 4704 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 4705 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 4706 4707 #if defined(RCC_PLLSAI1_SUPPORT) 4708 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 4709 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 4710 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 4711 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 4712 #endif /* RCC_PLLSAI1_SUPPORT */ 4713 4714 #if defined(RCC_PLLSAI2_SUPPORT) 4715 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 4716 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 4717 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ 4718 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) 4719 #elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 4720 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 4721 (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ 4722 (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ 4723 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) 4724 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 4725 #endif /* RCC_PLLSAI2_SUPPORT */ 4726 4727 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 4728 ((__RANGE__) == RCC_MSIRANGE_1) || \ 4729 ((__RANGE__) == RCC_MSIRANGE_2) || \ 4730 ((__RANGE__) == RCC_MSIRANGE_3) || \ 4731 ((__RANGE__) == RCC_MSIRANGE_4) || \ 4732 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4733 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4734 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4735 ((__RANGE__) == RCC_MSIRANGE_8) || \ 4736 ((__RANGE__) == RCC_MSIRANGE_9) || \ 4737 ((__RANGE__) == RCC_MSIRANGE_10) || \ 4738 ((__RANGE__) == RCC_MSIRANGE_11)) 4739 4740 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 4741 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4742 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4743 ((__RANGE__) == RCC_MSIRANGE_7)) 4744 4745 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 4746 4747 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 4748 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4749 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4750 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 4751 4752 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 4753 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 4754 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 4755 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 4756 ((__HCLK__) == RCC_SYSCLK_DIV512)) 4757 4758 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 4759 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 4760 ((__PCLK__) == RCC_HCLK_DIV16)) 4761 4762 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 4763 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 4764 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 4765 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 4766 4767 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 4768 4769 #if defined(RCC_HSI48_SUPPORT) 4770 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 4771 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 4772 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 4773 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4774 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 4775 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 4776 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 4777 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 4778 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 4779 #else 4780 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 4781 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 4782 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 4783 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4784 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 4785 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 4786 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 4787 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 4788 #endif /* RCC_HSI48_SUPPORT */ 4789 4790 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 4791 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 4792 ((__DIV__) == RCC_MCODIV_16)) 4793 4794 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 4795 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 4796 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 4797 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 4798 4799 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 4800 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4801 /** 4802 * @} 4803 */ 4804 4805 /* Include RCC HAL Extended module */ 4806 #include "stm32l4xx_hal_rcc_ex.h" 4807 4808 /* Exported functions --------------------------------------------------------*/ 4809 /** @addtogroup RCC_Exported_Functions 4810 * @{ 4811 */ 4812 4813 4814 /** @addtogroup RCC_Exported_Functions_Group1 4815 * @{ 4816 */ 4817 4818 /* Initialization and de-initialization functions ******************************/ 4819 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4820 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4821 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 4822 4823 /** 4824 * @} 4825 */ 4826 4827 /** @addtogroup RCC_Exported_Functions_Group2 4828 * @{ 4829 */ 4830 4831 /* Peripheral Control functions ************************************************/ 4832 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4833 void HAL_RCC_EnableCSS(void); 4834 uint32_t HAL_RCC_GetSysClockFreq(void); 4835 uint32_t HAL_RCC_GetHCLKFreq(void); 4836 uint32_t HAL_RCC_GetPCLK1Freq(void); 4837 uint32_t HAL_RCC_GetPCLK2Freq(void); 4838 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4839 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 4840 /* CSS NMI IRQ handler */ 4841 void HAL_RCC_NMI_IRQHandler(void); 4842 /* User Callbacks in non blocking mode (IT mode) */ 4843 void HAL_RCC_CSSCallback(void); 4844 4845 /** 4846 * @} 4847 */ 4848 4849 /** 4850 * @} 4851 */ 4852 4853 /** 4854 * @} 4855 */ 4856 4857 /** 4858 * @} 4859 */ 4860 4861 #ifdef __cplusplus 4862 } 4863 #endif 4864 4865 #endif /* STM32L4xx_HAL_RCC_H */ 4866 4867 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4868