1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_QSPI_H 22 #define STM32L4xx_HAL_QSPI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 #if defined(QUADSPI) 32 33 /** @addtogroup STM32L4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup QSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup QSPI_Exported_Types QSPI Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief QSPI Init structure definition 48 */ 49 typedef struct 50 { 51 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 52 This parameter can be a number between 0 and 255 */ 53 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 54 This parameter can be a value between 1 and 16 */ 55 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 56 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 57 This parameter can be a value of @ref QSPI_SampleShifting */ 58 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 59 required to address the flash memory. The flash capacity can be up to 4GB 60 (addressed using 32 bits) in indirect mode, but the addressable space in 61 memory-mapped mode is limited to 256MB 62 This parameter can be a number between 0 and 31 */ 63 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 64 of clock cycles which the chip select must remain high between commands. 65 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 66 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 67 This parameter can be a value of @ref QSPI_ClockMode */ 68 #if defined(QUADSPI_CR_DFM) 69 uint32_t FlashID; /* Specifies the Flash which will be used, 70 This parameter can be a value of @ref QSPI_Flash_Select */ 71 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 72 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 73 #endif 74 }QSPI_InitTypeDef; 75 76 /** 77 * @brief HAL QSPI State structures definition 78 */ 79 typedef enum 80 { 81 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 82 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 83 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 84 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 85 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 86 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 87 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 88 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 89 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 90 }HAL_QSPI_StateTypeDef; 91 92 /** 93 * @brief QSPI Handle Structure definition 94 */ 95 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 96 typedef struct __QSPI_HandleTypeDef 97 #else 98 typedef struct 99 #endif 100 { 101 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 102 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 103 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 104 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 105 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 106 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 107 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 108 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 109 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 110 __IO HAL_LockTypeDef Lock; /* Locking object */ 111 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 112 __IO uint32_t ErrorCode; /* QSPI Error code */ 113 uint32_t Timeout; /* Timeout for the QSPI memory access */ 114 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 115 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 116 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 117 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 118 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 119 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 121 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 122 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 123 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 124 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 125 126 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 127 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 128 #endif 129 }QSPI_HandleTypeDef; 130 131 /** 132 * @brief QSPI Command structure definition 133 */ 134 typedef struct 135 { 136 uint32_t Instruction; /* Specifies the Instruction to be sent 137 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 138 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 139 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 140 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 141 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 142 uint32_t AddressSize; /* Specifies the Address Size 143 This parameter can be a value of @ref QSPI_AddressSize */ 144 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 145 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 146 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 147 This parameter can be a number between 0 and 31 */ 148 uint32_t InstructionMode; /* Specifies the Instruction Mode 149 This parameter can be a value of @ref QSPI_InstructionMode */ 150 uint32_t AddressMode; /* Specifies the Address Mode 151 This parameter can be a value of @ref QSPI_AddressMode */ 152 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 153 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 154 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 155 This parameter can be a value of @ref QSPI_DataMode */ 156 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 157 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 158 until end of memory)*/ 159 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 160 This parameter can be a value of @ref QSPI_DdrMode */ 161 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 162 output by one half of system clock in DDR mode. 163 Not available on all devices. 164 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 165 uint32_t SIOOMode; /* Specifies the send instruction only once mode 166 This parameter can be a value of @ref QSPI_SIOOMode */ 167 }QSPI_CommandTypeDef; 168 169 /** 170 * @brief QSPI Auto Polling mode configuration structure definition 171 */ 172 typedef struct 173 { 174 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 175 This parameter can be any value between 0 and 0xFFFFFFFF */ 176 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 177 This parameter can be any value between 0 and 0xFFFFFFFF */ 178 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 179 This parameter can be any value between 0 and 0xFFFF */ 180 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 181 This parameter can be any value between 1 and 4 */ 182 uint32_t MatchMode; /* Specifies the method used for determining a match. 183 This parameter can be a value of @ref QSPI_MatchMode */ 184 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 185 This parameter can be a value of @ref QSPI_AutomaticStop */ 186 }QSPI_AutoPollingTypeDef; 187 188 /** 189 * @brief QSPI Memory Mapped mode configuration structure definition 190 */ 191 typedef struct 192 { 193 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 194 This parameter can be any value between 0 and 0xFFFF */ 195 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 196 This parameter can be a value of @ref QSPI_TimeOutActivation */ 197 }QSPI_MemoryMappedTypeDef; 198 199 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 200 /** 201 * @brief HAL QSPI Callback ID enumeration definition 202 */ 203 typedef enum 204 { 205 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 206 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 207 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 208 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 209 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 210 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 211 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 212 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 213 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 214 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 215 216 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 217 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 218 }HAL_QSPI_CallbackIDTypeDef; 219 220 /** 221 * @brief HAL QSPI Callback pointer definition 222 */ 223 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 224 #endif 225 /** 226 * @} 227 */ 228 229 /* Exported constants --------------------------------------------------------*/ 230 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 231 * @{ 232 */ 233 234 /** @defgroup QSPI_ErrorCode QSPI Error Code 235 * @{ 236 */ 237 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 238 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 239 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 240 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 241 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 242 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 243 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 244 #endif 245 /** 246 * @} 247 */ 248 249 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 250 * @{ 251 */ 252 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 253 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 254 /** 255 * @} 256 */ 257 258 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 259 * @{ 260 */ 261 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 262 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 263 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 264 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 265 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 266 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 267 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 268 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 269 /** 270 * @} 271 */ 272 273 /** @defgroup QSPI_ClockMode QSPI Clock Mode 274 * @{ 275 */ 276 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 277 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 278 /** 279 * @} 280 */ 281 282 #if defined(QUADSPI_CR_DFM) 283 /** @defgroup QSPI_Flash_Select QSPI Flash Select 284 * @{ 285 */ 286 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 287 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 288 /** 289 * @} 290 */ 291 292 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 293 * @{ 294 */ 295 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 296 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 297 /** 298 * @} 299 */ 300 301 #endif 302 /** @defgroup QSPI_AddressSize QSPI Address Size 303 * @{ 304 */ 305 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 306 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 307 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 308 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 309 /** 310 * @} 311 */ 312 313 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 314 * @{ 315 */ 316 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 317 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 318 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 319 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 320 /** 321 * @} 322 */ 323 324 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 325 * @{ 326 */ 327 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 328 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 329 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 330 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 331 /** 332 * @} 333 */ 334 335 /** @defgroup QSPI_AddressMode QSPI Address Mode 336 * @{ 337 */ 338 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 339 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 340 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 341 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 342 /** 343 * @} 344 */ 345 346 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 347 * @{ 348 */ 349 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 350 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 351 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 352 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 353 /** 354 * @} 355 */ 356 357 /** @defgroup QSPI_DataMode QSPI Data Mode 358 * @{ 359 */ 360 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 361 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 362 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 363 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 364 /** 365 * @} 366 */ 367 368 /** @defgroup QSPI_DdrMode QSPI DDR Mode 369 * @{ 370 */ 371 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 372 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 373 /** 374 * @} 375 */ 376 377 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 378 * @{ 379 */ 380 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 381 #if defined(QUADSPI_CCR_DHHC) 382 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 383 #endif 384 /** 385 * @} 386 */ 387 388 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 389 * @{ 390 */ 391 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 392 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 393 /** 394 * @} 395 */ 396 397 /** @defgroup QSPI_MatchMode QSPI Match Mode 398 * @{ 399 */ 400 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 401 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 402 /** 403 * @} 404 */ 405 406 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 407 * @{ 408 */ 409 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 410 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 411 /** 412 * @} 413 */ 414 415 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 416 * @{ 417 */ 418 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 419 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 420 /** 421 * @} 422 */ 423 424 /** @defgroup QSPI_Flags QSPI Flags 425 * @{ 426 */ 427 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 428 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 429 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 430 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 431 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 432 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 433 /** 434 * @} 435 */ 436 437 /** @defgroup QSPI_Interrupts QSPI Interrupts 438 * @{ 439 */ 440 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 441 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 442 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 443 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 444 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 445 /** 446 * @} 447 */ 448 449 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 450 * @brief QSPI Timeout definition 451 * @{ 452 */ 453 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 454 /** 455 * @} 456 */ 457 458 /** 459 * @} 460 */ 461 462 /* Exported macros -----------------------------------------------------------*/ 463 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 464 * @{ 465 */ 466 /** @brief Reset QSPI handle state. 467 * @param __HANDLE__ : QSPI handle. 468 * @retval None 469 */ 470 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 471 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 472 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 473 (__HANDLE__)->MspInitCallback = NULL; \ 474 (__HANDLE__)->MspDeInitCallback = NULL; \ 475 } while(0) 476 #else 477 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 478 #endif 479 480 /** @brief Enable the QSPI peripheral. 481 * @param __HANDLE__ : specifies the QSPI Handle. 482 * @retval None 483 */ 484 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 485 486 /** @brief Disable the QSPI peripheral. 487 * @param __HANDLE__ : specifies the QSPI Handle. 488 * @retval None 489 */ 490 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 491 492 /** @brief Enable the specified QSPI interrupt. 493 * @param __HANDLE__ : specifies the QSPI Handle. 494 * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. 495 * This parameter can be one of the following values: 496 * @arg QSPI_IT_TO: QSPI Timeout interrupt 497 * @arg QSPI_IT_SM: QSPI Status match interrupt 498 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 499 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 500 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 501 * @retval None 502 */ 503 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 504 505 506 /** @brief Disable the specified QSPI interrupt. 507 * @param __HANDLE__ : specifies the QSPI Handle. 508 * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. 509 * This parameter can be one of the following values: 510 * @arg QSPI_IT_TO: QSPI Timeout interrupt 511 * @arg QSPI_IT_SM: QSPI Status match interrupt 512 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 513 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 514 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 515 * @retval None 516 */ 517 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 518 519 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 520 * @param __HANDLE__ : specifies the QSPI Handle. 521 * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. 522 * This parameter can be one of the following values: 523 * @arg QSPI_IT_TO: QSPI Timeout interrupt 524 * @arg QSPI_IT_SM: QSPI Status match interrupt 525 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 526 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 527 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 528 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 529 */ 530 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 531 532 /** 533 * @brief Check whether the selected QSPI flag is set or not. 534 * @param __HANDLE__ : specifies the QSPI Handle. 535 * @param __FLAG__ : specifies the QSPI flag to check. 536 * This parameter can be one of the following values: 537 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 538 * @arg QSPI_FLAG_TO: QSPI Timeout flag 539 * @arg QSPI_FLAG_SM: QSPI Status match flag 540 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 541 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 542 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 543 * @retval None 544 */ 545 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 546 547 /** @brief Clears the specified QSPI's flag status. 548 * @param __HANDLE__ : specifies the QSPI Handle. 549 * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set 550 * This parameter can be one of the following values: 551 * @arg QSPI_FLAG_TO: QSPI Timeout flag 552 * @arg QSPI_FLAG_SM: QSPI Status match flag 553 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 554 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 555 * @retval None 556 */ 557 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 558 /** 559 * @} 560 */ 561 562 /* Exported functions --------------------------------------------------------*/ 563 /** @addtogroup QSPI_Exported_Functions 564 * @{ 565 */ 566 567 /** @addtogroup QSPI_Exported_Functions_Group1 568 * @{ 569 */ 570 /* Initialization/de-initialization functions ********************************/ 571 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 572 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 573 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 574 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 575 /** 576 * @} 577 */ 578 579 /** @addtogroup QSPI_Exported_Functions_Group2 580 * @{ 581 */ 582 /* IO operation functions *****************************************************/ 583 /* QSPI IRQ handler method */ 584 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 585 586 /* QSPI indirect mode */ 587 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 588 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 589 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 590 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 591 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 592 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 593 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 594 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 595 596 /* QSPI status flag polling mode */ 597 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 598 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 599 600 /* QSPI memory-mapped mode */ 601 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 602 603 /* Callback functions in non-blocking modes ***********************************/ 604 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 605 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 606 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 607 608 /* QSPI indirect mode */ 609 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 610 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 611 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 612 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 613 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 614 615 /* QSPI status flag polling mode */ 616 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 617 618 /* QSPI memory-mapped mode */ 619 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 620 621 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 622 /* QSPI callback registering/unregistering */ 623 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 624 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 625 #endif 626 /** 627 * @} 628 */ 629 630 /** @addtogroup QSPI_Exported_Functions_Group3 631 * @{ 632 */ 633 /* Peripheral Control and State functions ************************************/ 634 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 635 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 636 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 637 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 638 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 639 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 640 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 641 #if defined(QUADSPI_CR_DFM) 642 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 643 #endif 644 /** 645 * @} 646 */ 647 648 /** 649 * @} 650 */ 651 /* End of exported functions -------------------------------------------------*/ 652 653 /* Private macros ------------------------------------------------------------*/ 654 /** @defgroup QSPI_Private_Macros QSPI Private Macros 655 * @{ 656 */ 657 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 658 659 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) 660 661 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 662 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 663 664 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 665 666 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 667 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 668 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 669 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 670 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 671 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 672 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 673 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 674 675 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 676 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 677 678 #if defined(QUADSPI_CR_DFM) 679 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 680 ((FLASH_ID) == QSPI_FLASH_ID_2)) 681 682 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 683 ((MODE) == QSPI_DUALFLASH_DISABLE)) 684 685 #endif 686 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 687 688 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 689 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 690 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 691 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 692 693 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 694 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 695 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 696 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 697 698 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 699 700 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 701 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 702 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 703 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 704 705 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 706 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 707 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 708 ((MODE) == QSPI_ADDRESS_4_LINES)) 709 710 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 711 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 712 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 713 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 714 715 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 716 ((MODE) == QSPI_DATA_1_LINE) || \ 717 ((MODE) == QSPI_DATA_2_LINES) || \ 718 ((MODE) == QSPI_DATA_4_LINES)) 719 720 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 721 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 722 723 #if defined(QUADSPI_CCR_DHHC) 724 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 725 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 726 727 #else 728 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) 729 730 #endif 731 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 732 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 733 734 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 735 736 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 737 738 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 739 ((MODE) == QSPI_MATCH_MODE_OR)) 740 741 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 742 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 743 744 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 745 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 746 747 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 748 /** 749 * @} 750 */ 751 /* End of private macros -----------------------------------------------------*/ 752 753 /** 754 * @} 755 */ 756 757 /** 758 * @} 759 */ 760 761 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ 762 763 #ifdef __cplusplus 764 } 765 #endif 766 767 #endif /* STM32L4xx_HAL_QSPI_H */ 768 769 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 770