1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_FLASH_H 22 #define STM32L4xx_HAL_FLASH_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FLASH 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FLASH_Exported_Types FLASH Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief FLASH Erase structure definition 46 */ 47 typedef struct 48 { 49 uint32_t TypeErase; /*!< Mass erase or page erase. 50 This parameter can be a value of @ref FLASH_Type_Erase */ 51 uint32_t Banks; /*!< Select bank to erase. 52 This parameter must be a value of @ref FLASH_Banks 53 (FLASH_BANK_BOTH should be used only for mass erase) */ 54 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 55 This parameter must be a value between 0 and (max number of pages in the bank - 1) 56 (eg : 255 for 1MB dual bank) */ 57 uint32_t NbPages; /*!< Number of pages to be erased. 58 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 59 } FLASH_EraseInitTypeDef; 60 61 /** 62 * @brief FLASH Option Bytes Program structure definition 63 */ 64 typedef struct 65 { 66 uint32_t OptionType; /*!< Option byte to be configured. 67 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 68 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 69 Only one WRP area could be programmed at the same time. 70 This parameter can be value of @ref FLASH_OB_WRP_Area */ 71 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 72 This parameter must be a value between 0 and (max number of pages in the bank - 1) 73 (eg : 25 for 1MB dual bank) */ 74 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 75 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 76 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 77 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 78 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 79 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 80 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 81 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 82 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 83 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 84 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 85 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 86 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 87 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ 88 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 89 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 90 and @ref FLASH_OB_PCROP_RDP */ 91 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 92 This parameter must be a value between begin and end of bank 93 => Be careful of the bank swapping for the address */ 94 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 95 This parameter must be a value between PCROP Start address and end of bank */ 96 } FLASH_OBProgramInitTypeDef; 97 98 /** 99 * @brief FLASH Procedure structure definition 100 */ 101 typedef enum 102 { 103 FLASH_PROC_NONE = 0, 104 FLASH_PROC_PAGE_ERASE, 105 FLASH_PROC_MASS_ERASE, 106 FLASH_PROC_PROGRAM, 107 FLASH_PROC_PROGRAM_LAST 108 } FLASH_ProcedureTypeDef; 109 110 /** 111 * @brief FLASH Cache structure definition 112 */ 113 typedef enum 114 { 115 FLASH_CACHE_DISABLED = 0, 116 FLASH_CACHE_ICACHE_ENABLED, 117 FLASH_CACHE_DCACHE_ENABLED, 118 FLASH_CACHE_ICACHE_DCACHE_ENABLED 119 } FLASH_CacheTypeDef; 120 121 /** 122 * @brief FLASH handle Structure definition 123 */ 124 typedef struct 125 { 126 HAL_LockTypeDef Lock; /* FLASH locking object */ 127 __IO uint32_t ErrorCode; /* FLASH error code */ 128 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 129 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ 130 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ 131 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 132 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 133 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ 134 }FLASH_ProcessTypeDef; 135 136 /** 137 * @} 138 */ 139 140 /* Exported constants --------------------------------------------------------*/ 141 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 142 * @{ 143 */ 144 145 /** @defgroup FLASH_Error FLASH Error 146 * @{ 147 */ 148 #define HAL_FLASH_ERROR_NONE 0x00000000U 149 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 150 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 151 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 152 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 153 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 154 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 155 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 156 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 157 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 158 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 159 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC 160 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 161 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 162 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 163 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 164 defined (STM32L4S7xx) || defined (STM32L4S9xx) 165 #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY 166 #endif 167 /** 168 * @} 169 */ 170 171 /** @defgroup FLASH_Type_Erase FLASH Erase Type 172 * @{ 173 */ 174 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ 175 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/ 176 /** 177 * @} 178 */ 179 180 /** @defgroup FLASH_Banks FLASH Banks 181 * @{ 182 */ 183 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ 184 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 185 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 186 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 187 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ 188 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ 189 #else 190 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */ 191 #endif 192 /** 193 * @} 194 */ 195 196 197 /** @defgroup FLASH_Type_Program FLASH Program Type 198 * @{ 199 */ 200 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/ 201 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 202 And another 32 row double-word (64-bit) will be programmed */ 203 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 204 And this is the last 32 row double-word (64-bit) programmed */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 210 * @{ 211 */ 212 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ 213 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ 214 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ 215 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */ 216 /** 217 * @} 218 */ 219 220 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 221 * @{ 222 */ 223 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ 224 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ 225 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 226 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 227 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 228 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ 229 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ 230 #endif 231 /** 232 * @} 233 */ 234 235 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 236 * @{ 237 */ 238 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) 239 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) 240 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 241 it's no more possible to go back to level 1 or 0 */ 242 /** 243 * @} 244 */ 245 246 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 247 * @{ 248 */ 249 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */ 250 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */ 251 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */ 252 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */ 253 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */ 254 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ 255 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ 256 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 257 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 258 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 259 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ 260 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 261 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ 262 #else 263 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ 264 #endif 265 #endif 266 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ 267 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ 268 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ 269 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ 270 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 271 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 272 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 273 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 274 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ 275 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ 276 #endif 277 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 278 #define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ 279 #endif 280 /** 281 * @} 282 */ 283 284 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 285 * @{ 286 */ 287 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */ 288 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */ 289 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */ 290 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */ 291 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */ 292 /** 293 * @} 294 */ 295 296 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 297 * @{ 298 */ 299 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */ 300 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ 301 /** 302 * @} 303 */ 304 305 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 306 * @{ 307 */ 308 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */ 309 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 315 * @{ 316 */ 317 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */ 318 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ 319 /** 320 * @} 321 */ 322 323 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 324 * @{ 325 */ 326 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */ 327 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 333 * @{ 334 */ 335 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */ 336 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 342 * @{ 343 */ 344 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */ 345 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 351 * @{ 352 */ 353 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */ 354 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ 355 /** 356 * @} 357 */ 358 359 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 360 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 361 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 362 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode 363 * @{ 364 */ 365 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */ 366 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */ 367 /** 368 * @} 369 */ 370 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 371 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 372 * @{ 373 */ 374 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ 375 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ 376 /** 377 * @} 378 */ 379 #else 380 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 381 * @{ 382 */ 383 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */ 384 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */ 385 /** 386 * @} 387 */ 388 #endif 389 #endif 390 391 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 392 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 393 * @{ 394 */ 395 #define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ 396 #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ 397 #endif 398 /** 399 * @} 400 */ 401 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 402 * @{ 403 */ 404 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ 405 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type 411 * @{ 412 */ 413 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */ 414 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */ 415 /** 416 * @} 417 */ 418 419 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 420 * @{ 421 */ 422 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */ 423 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */ 424 /** 425 * @} 426 */ 427 428 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 429 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 430 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 431 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 432 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 433 * @{ 434 */ 435 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */ 436 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 442 * @{ 443 */ 444 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */ 445 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ 446 /** 447 * @} 448 */ 449 #endif 450 451 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 452 * @{ 453 */ 454 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level 455 is decreased from Level 1 to Level 0 */ 456 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 457 decreased from Level 1 to Level 0 (full mass erase) */ 458 /** 459 * @} 460 */ 461 462 /** @defgroup FLASH_Latency FLASH Latency 463 * @{ 464 */ 465 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 466 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 467 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 468 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 469 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 470 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 471 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 472 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 473 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 474 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 475 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 476 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 477 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 478 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 479 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 480 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 481 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 482 #endif 483 /** 484 * @} 485 */ 486 487 /** @defgroup FLASH_Keys FLASH Keys 488 * @{ 489 */ 490 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 491 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 492 to unlock the FLASH registers access */ 493 494 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 495 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 496 to unlock the RUN_PD bit in FLASH_ACR */ 497 498 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 499 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 500 to allow option bytes operations */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup FLASH_Flags FLASH Flags Definition 506 * @{ 507 */ 508 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 509 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 510 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 511 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 512 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 513 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 514 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 515 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 516 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 517 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 518 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 519 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 520 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 521 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 522 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 523 defined (STM32L4S7xx) || defined (STM32L4S9xx) 524 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ 525 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 526 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 527 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 528 FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY) 529 #else 530 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 531 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 532 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 533 FLASH_FLAG_OPTVERR) 534 #endif 535 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ 536 defined (STM32L4S7xx) || defined (STM32L4S9xx) 537 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 538 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 539 #else 540 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 541 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 542 #endif 543 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) 544 545 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 546 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 547 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 548 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCR_ERRORS) 549 /** 550 * @} 551 */ 552 553 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 554 * @brief FLASH Interrupt definition 555 * @{ 556 */ 557 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 558 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 559 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ 560 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 561 /** 562 * @} 563 */ 564 565 /* Exported macros -----------------------------------------------------------*/ 566 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 567 * @brief macros to control FLASH features 568 * @{ 569 */ 570 571 /** 572 * @brief Set the FLASH Latency. 573 * @param __LATENCY__ FLASH Latency 574 * This parameter can be one of the following values : 575 * @arg FLASH_LATENCY_0: FLASH Zero wait state 576 * @arg FLASH_LATENCY_1: FLASH One wait state 577 * @arg FLASH_LATENCY_2: FLASH Two wait states 578 * @arg FLASH_LATENCY_3: FLASH Three wait states 579 * @arg FLASH_LATENCY_4: FLASH Four wait states 580 * @retval None 581 */ 582 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 583 584 /** 585 * @brief Get the FLASH Latency. 586 * @retval FLASH Latency 587 * This parameter can be one of the following values : 588 * @arg FLASH_LATENCY_0: FLASH Zero wait state 589 * @arg FLASH_LATENCY_1: FLASH One wait state 590 * @arg FLASH_LATENCY_2: FLASH Two wait states 591 * @arg FLASH_LATENCY_3: FLASH Three wait states 592 * @arg FLASH_LATENCY_4: FLASH Four wait states 593 */ 594 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 595 596 /** 597 * @brief Enable the FLASH prefetch buffer. 598 * @retval None 599 */ 600 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 601 602 /** 603 * @brief Disable the FLASH prefetch buffer. 604 * @retval None 605 */ 606 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 607 608 /** 609 * @brief Enable the FLASH instruction cache. 610 * @retval none 611 */ 612 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 613 614 /** 615 * @brief Disable the FLASH instruction cache. 616 * @retval none 617 */ 618 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 619 620 /** 621 * @brief Enable the FLASH data cache. 622 * @retval none 623 */ 624 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 625 626 /** 627 * @brief Disable the FLASH data cache. 628 * @retval none 629 */ 630 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 631 632 /** 633 * @brief Reset the FLASH instruction Cache. 634 * @note This function must be used only when the Instruction Cache is disabled. 635 * @retval None 636 */ 637 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 638 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 639 } while (0) 640 641 /** 642 * @brief Reset the FLASH data Cache. 643 * @note This function must be used only when the data Cache is disabled. 644 * @retval None 645 */ 646 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 647 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 648 } while (0) 649 650 /** 651 * @brief Enable the FLASH power down during Low-power run mode. 652 * @note Writing this bit to 0 this bit, automatically the keys are 653 * loss and a new unlock sequence is necessary to re-write it to 1. 654 */ 655 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 656 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 657 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 658 } while (0) 659 660 /** 661 * @brief Disable the FLASH power down during Low-power run mode. 662 * @note Writing this bit to 0 this bit, automatically the keys are 663 * loss and a new unlock sequence is necessary to re-write it to 1. 664 */ 665 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 666 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 667 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 668 } while (0) 669 670 /** 671 * @brief Enable the FLASH power down during Low-Power sleep mode 672 * @retval none 673 */ 674 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 675 676 /** 677 * @brief Disable the FLASH power down during Low-Power sleep mode 678 * @retval none 679 */ 680 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 681 682 /** 683 * @} 684 */ 685 686 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 687 * @brief macros to handle FLASH interrupts 688 * @{ 689 */ 690 691 /** 692 * @brief Enable the specified FLASH interrupt. 693 * @param __INTERRUPT__ FLASH interrupt 694 * This parameter can be any combination of the following values: 695 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 696 * @arg FLASH_IT_OPERR: Error Interrupt 697 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 698 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 699 * @retval none 700 */ 701 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 702 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 703 } while(0) 704 705 /** 706 * @brief Disable the specified FLASH interrupt. 707 * @param __INTERRUPT__ FLASH interrupt 708 * This parameter can be any combination of the following values: 709 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 710 * @arg FLASH_IT_OPERR: Error Interrupt 711 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 712 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 713 * @retval none 714 */ 715 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 716 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 717 } while(0) 718 719 /** 720 * @brief Check whether the specified FLASH flag is set or not. 721 * @param __FLAG__ specifies the FLASH flag to check. 722 * This parameter can be one of the following values: 723 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 724 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 725 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 726 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 727 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 728 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 729 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 730 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 731 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 732 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 733 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 734 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 735 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) 736 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 737 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 738 * @retval The new state of FLASH_FLAG (SET or RESET). 739 */ 740 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 741 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 742 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 743 744 /** 745 * @brief Clear the FLASH's pending flags. 746 * @param __FLAG__ specifies the FLASH flags to clear. 747 * This parameter can be any combination of the following values: 748 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 749 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 750 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 751 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 752 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 753 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 754 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 755 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 756 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 757 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 758 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 759 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 760 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 761 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 762 * @retval None 763 */ 764 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 765 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 766 } while(0) 767 /** 768 * @} 769 */ 770 771 /* Include FLASH HAL Extended module */ 772 #include "stm32l4xx_hal_flash_ex.h" 773 #include "stm32l4xx_hal_flash_ramfunc.h" 774 775 /* Exported functions --------------------------------------------------------*/ 776 /** @addtogroup FLASH_Exported_Functions 777 * @{ 778 */ 779 780 /* Program operation functions ***********************************************/ 781 /** @addtogroup FLASH_Exported_Functions_Group1 782 * @{ 783 */ 784 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 785 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 786 /* FLASH IRQ handler method */ 787 void HAL_FLASH_IRQHandler(void); 788 /* Callbacks in non blocking modes */ 789 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 790 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 791 /** 792 * @} 793 */ 794 795 /* Peripheral Control functions **********************************************/ 796 /** @addtogroup FLASH_Exported_Functions_Group2 797 * @{ 798 */ 799 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 800 HAL_StatusTypeDef HAL_FLASH_Lock(void); 801 /* Option bytes control */ 802 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 803 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 804 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 805 /** 806 * @} 807 */ 808 809 /* Peripheral State functions ************************************************/ 810 /** @addtogroup FLASH_Exported_Functions_Group3 811 * @{ 812 */ 813 uint32_t HAL_FLASH_GetError(void); 814 /** 815 * @} 816 */ 817 818 /** 819 * @} 820 */ 821 822 /* Private variables ---------------------------------------------------------*/ 823 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 824 * @{ 825 */ 826 extern FLASH_ProcessTypeDef pFlash; 827 /** 828 * @} 829 */ 830 831 /* Private function ----------------------------------------------------------*/ 832 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 833 * @{ 834 */ 835 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 836 /** 837 * @} 838 */ 839 840 /* Private constants --------------------------------------------------------*/ 841 /** @defgroup FLASH_Private_Constants FLASH Private Constants 842 * @{ 843 */ 844 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 845 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 846 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 847 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) 848 #else 849 #define FLASH_BANK_SIZE (FLASH_SIZE) 850 #endif 851 852 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 853 #define FLASH_PAGE_SIZE ((uint32_t)0x1000) 854 #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) 855 #else 856 #define FLASH_PAGE_SIZE ((uint32_t)0x800) 857 #endif 858 859 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ 860 /** 861 * @} 862 */ 863 864 /* Private macros ------------------------------------------------------------*/ 865 /** @defgroup FLASH_Private_Macros FLASH Private Macros 866 * @{ 867 */ 868 869 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 870 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 871 872 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 873 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 874 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 875 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 876 ((BANK) == FLASH_BANK_2) || \ 877 ((BANK) == FLASH_BANK_BOTH)) 878 879 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 880 ((BANK) == FLASH_BANK_2)) 881 #else 882 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 883 884 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 885 #endif 886 887 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 888 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ 889 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) 890 891 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 892 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) 893 #else 894 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ 895 ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ 896 ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ 897 ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ 898 ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) 899 #endif 900 901 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) 902 903 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 904 905 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 906 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) 907 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 908 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ 909 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ 910 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ 911 ((PAGE) < 256U))))) 912 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 913 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ 914 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 915 ((PAGE) < 256U)))) 916 #else 917 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 918 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ 919 ((PAGE) < 128U)))) 920 #endif 921 922 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) 923 924 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 925 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 926 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 927 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 928 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 929 #else 930 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 931 #endif 932 933 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 934 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ 935 ((LEVEL) == OB_RDP_LEVEL_2)*/) 936 937 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 938 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) 939 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 940 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) 941 #else 942 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) 943 #endif 944 945 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 946 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 947 ((LEVEL) == OB_BOR_LEVEL_4)) 948 949 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 950 951 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 952 953 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 954 955 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 956 957 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 958 959 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 960 961 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 962 963 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 964 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 965 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 966 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) 967 968 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 969 #endif 970 971 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 972 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 973 #endif 974 975 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) 976 977 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 978 979 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 980 981 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 982 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 983 defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || \ 984 defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 985 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 986 987 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) 988 #endif 989 990 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) 991 992 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 993 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 994 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 995 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 996 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 997 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 998 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 999 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1000 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1001 #else 1002 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 1003 ((LATENCY) == FLASH_LATENCY_1) || \ 1004 ((LATENCY) == FLASH_LATENCY_2) || \ 1005 ((LATENCY) == FLASH_LATENCY_3) || \ 1006 ((LATENCY) == FLASH_LATENCY_4)) 1007 #endif 1008 /** 1009 * @} 1010 */ 1011 1012 /** 1013 * @} 1014 */ 1015 1016 /** 1017 * @} 1018 */ 1019 1020 /** 1021 * @} 1022 */ 1023 1024 #ifdef __cplusplus 1025 } 1026 #endif 1027 1028 #endif /* STM32L4xx_HAL_FLASH_H */ 1029 1030 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1031