1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_DMA_H 22 #define STM32L4xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 }HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 }HAL_DMA_LevelCompleteTypeDef; 96 97 98 /** 99 * @brief HAL DMA Callback ID structure definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 104 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 105 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 106 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 107 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 108 }HAL_DMA_CallbackIDTypeDef; 109 110 /** 111 * @brief DMA handle Structure definition 112 */ 113 typedef struct __DMA_HandleTypeDef 114 { 115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 116 117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 118 119 HAL_LockTypeDef Lock; /*!< DMA locking object */ 120 121 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 122 123 void *Parent; /*!< Parent object state */ 124 125 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 126 127 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 128 129 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 130 131 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 132 133 __IO uint32_t ErrorCode; /*!< DMA Error code */ 134 135 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 136 137 uint32_t ChannelIndex; /*!< DMA Channel Index */ 138 139 #if defined(DMAMUX1) 140 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 141 142 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 143 144 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 145 146 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 147 148 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 149 150 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 151 152 #endif /* DMAMUX1 */ 153 154 }DMA_HandleTypeDef; 155 /** 156 * @} 157 */ 158 159 /* Exported constants --------------------------------------------------------*/ 160 161 /** @defgroup DMA_Exported_Constants DMA Exported Constants 162 * @{ 163 */ 164 165 /** @defgroup DMA_Error_Code DMA Error Code 166 * @{ 167 */ 168 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 169 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 170 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 171 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 172 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 173 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 174 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup DMA_request DMA request 181 * @{ 182 */ 183 #if !defined (DMAMUX1) 184 185 #define DMA_REQUEST_0 0U 186 #define DMA_REQUEST_1 1U 187 #define DMA_REQUEST_2 2U 188 #define DMA_REQUEST_3 3U 189 #define DMA_REQUEST_4 4U 190 #define DMA_REQUEST_5 5U 191 #define DMA_REQUEST_6 6U 192 #define DMA_REQUEST_7 7U 193 194 #endif 195 196 #if defined(DMAMUX1) 197 198 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 199 200 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 201 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 202 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 203 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 204 205 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 206 207 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) 208 209 #define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC1 request */ 210 211 #define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */ 212 #define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */ 213 214 #define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */ 215 #define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */ 216 217 #define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */ 218 #define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */ 219 #define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */ 220 #define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */ 221 #define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */ 222 #define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */ 223 224 #define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */ 225 #define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */ 226 #define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */ 227 #define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */ 228 #define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */ 229 #define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */ 230 #define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */ 231 #define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */ 232 233 #define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */ 234 #define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */ 235 #define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */ 236 #define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */ 237 #define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */ 238 #define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */ 239 240 #define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */ 241 #define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */ 242 #define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */ 243 #define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */ 244 245 #define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */ 246 #define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */ 247 248 #define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */ 249 #define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */ 250 #define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */ 251 #define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */ 252 253 #define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */ 254 #define DMA_REQUEST_OCTOSPI2 42U /*!< DMAMUX1 OCTOSPI2 request */ 255 256 #define DMA_REQUEST_TIM1_CH1 43U /*!< DMAMUX1 TIM1 CH1 request */ 257 #define DMA_REQUEST_TIM1_CH2 44U /*!< DMAMUX1 TIM1 CH2 request */ 258 #define DMA_REQUEST_TIM1_CH3 45U /*!< DMAMUX1 TIM1 CH3 request */ 259 #define DMA_REQUEST_TIM1_CH4 46U /*!< DMAMUX1 TIM1 CH4 request */ 260 #define DMA_REQUEST_TIM1_UP 47U /*!< DMAMUX1 TIM1 UP request */ 261 #define DMA_REQUEST_TIM1_TRIG 48U /*!< DMAMUX1 TIM1 TRIG request */ 262 #define DMA_REQUEST_TIM1_COM 49U /*!< DMAMUX1 TIM1 COM request */ 263 264 #define DMA_REQUEST_TIM8_CH1 50U /*!< DMAMUX1 TIM8 CH1 request */ 265 #define DMA_REQUEST_TIM8_CH2 51U /*!< DMAMUX1 TIM8 CH2 request */ 266 #define DMA_REQUEST_TIM8_CH3 52U /*!< DMAMUX1 TIM8 CH3 request */ 267 #define DMA_REQUEST_TIM8_CH4 53U /*!< DMAMUX1 TIM8 CH4 request */ 268 #define DMA_REQUEST_TIM8_UP 54U /*!< DMAMUX1 TIM8 UP request */ 269 #define DMA_REQUEST_TIM8_TRIG 55U /*!< DMAMUX1 TIM8 TRIG request */ 270 #define DMA_REQUEST_TIM8_COM 56U /*!< DMAMUX1 TIM8 COM request */ 271 272 #define DMA_REQUEST_TIM2_CH1 57U /*!< DMAMUX1 TIM2 CH1 request */ 273 #define DMA_REQUEST_TIM2_CH2 58U /*!< DMAMUX1 TIM2 CH2 request */ 274 #define DMA_REQUEST_TIM2_CH3 59U /*!< DMAMUX1 TIM2 CH3 request */ 275 #define DMA_REQUEST_TIM2_CH4 60U /*!< DMAMUX1 TIM2 CH4 request */ 276 #define DMA_REQUEST_TIM2_UP 61U /*!< DMAMUX1 TIM2 UP request */ 277 278 #define DMA_REQUEST_TIM3_CH1 62U /*!< DMAMUX1 TIM3 CH1 request */ 279 #define DMA_REQUEST_TIM3_CH2 63U /*!< DMAMUX1 TIM3 CH2 request */ 280 #define DMA_REQUEST_TIM3_CH3 64U /*!< DMAMUX1 TIM3 CH3 request */ 281 #define DMA_REQUEST_TIM3_CH4 65U /*!< DMAMUX1 TIM3 CH4 request */ 282 #define DMA_REQUEST_TIM3_UP 66U /*!< DMAMUX1 TIM3 UP request */ 283 #define DMA_REQUEST_TIM3_TRIG 67U /*!< DMAMUX1 TIM3 TRIG request */ 284 285 #define DMA_REQUEST_TIM4_CH1 68U /*!< DMAMUX1 TIM4 CH1 request */ 286 #define DMA_REQUEST_TIM4_CH2 69U /*!< DMAMUX1 TIM4 CH2 request */ 287 #define DMA_REQUEST_TIM4_CH3 70U /*!< DMAMUX1 TIM4 CH3 request */ 288 #define DMA_REQUEST_TIM4_CH4 71U /*!< DMAMUX1 TIM4 CH4 request */ 289 #define DMA_REQUEST_TIM4_UP 72U /*!< DMAMUX1 TIM4 UP request */ 290 291 #define DMA_REQUEST_TIM5_CH1 73U /*!< DMAMUX1 TIM5 CH1 request */ 292 #define DMA_REQUEST_TIM5_CH2 74U /*!< DMAMUX1 TIM5 CH2 request */ 293 #define DMA_REQUEST_TIM5_CH3 75U /*!< DMAMUX1 TIM5 CH3 request */ 294 #define DMA_REQUEST_TIM5_CH4 76U /*!< DMAMUX1 TIM5 CH4 request */ 295 #define DMA_REQUEST_TIM5_UP 77U /*!< DMAMUX1 TIM5 UP request */ 296 #define DMA_REQUEST_TIM5_TRIG 78U /*!< DMAMUX1 TIM5 TRIG request */ 297 298 #define DMA_REQUEST_TIM15_CH1 79U /*!< DMAMUX1 TIM15 CH1 request */ 299 #define DMA_REQUEST_TIM15_UP 80U /*!< DMAMUX1 TIM15 UP request */ 300 #define DMA_REQUEST_TIM15_TRIG 81U /*!< DMAMUX1 TIM15 TRIG request */ 301 #define DMA_REQUEST_TIM15_COM 82U /*!< DMAMUX1 TIM15 COM request */ 302 303 #define DMA_REQUEST_TIM16_CH1 83U /*!< DMAMUX1 TIM16 CH1 request */ 304 #define DMA_REQUEST_TIM16_UP 84U /*!< DMAMUX1 TIM16 UP request */ 305 #define DMA_REQUEST_TIM17_CH1 85U /*!< DMAMUX1 TIM17 CH1 request */ 306 #define DMA_REQUEST_TIM17_UP 86U /*!< DMAMUX1 TIM17 UP request */ 307 308 #define DMA_REQUEST_DFSDM1_FLT0 87U /*!< DMAMUX1 DFSDM1 Filter0 request */ 309 #define DMA_REQUEST_DFSDM1_FLT1 88U /*!< DMAMUX1 DFSDM1 Filter1 request */ 310 311 #define DMA_REQUEST_DCMI 91U /*!< DMAMUX1 DCMI request */ 312 #define DMA_REQUEST_DCMI_PSSI 91U /*!< DMAMUX1 DCMI/PSSI request */ 313 314 #define DMA_REQUEST_AES_IN 92U /*!< DMAMUX1 AES IN request */ 315 #define DMA_REQUEST_AES_OUT 93U /*!< DMAMUX1 AES OUT request */ 316 317 #define DMA_REQUEST_HASH_IN 94U /*!< DMAMUX1 HASH IN request */ 318 319 #else 320 321 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ 322 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ 323 324 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ 325 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ 326 327 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ 328 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ 329 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ 330 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ 331 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ 332 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ 333 334 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ 335 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ 336 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ 337 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ 338 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ 339 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ 340 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ 341 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ 342 343 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ 344 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ 345 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ 346 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ 347 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ 348 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ 349 350 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ 351 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ 352 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ 353 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ 354 355 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ 356 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ 357 358 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ 359 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ 360 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ 361 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ 362 363 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ 364 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ 365 366 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 367 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 368 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 369 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 370 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 371 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 372 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 373 374 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 375 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 376 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 377 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 378 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 379 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 380 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 381 382 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 383 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 384 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 385 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 386 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 387 388 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 389 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 390 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 391 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 392 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 393 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 394 395 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 396 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 397 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 398 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 399 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 400 401 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 402 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 403 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 404 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 405 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 406 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 407 408 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 409 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 410 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 411 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 412 413 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 414 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 415 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 416 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 417 418 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 419 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 420 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 421 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 422 423 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ 424 425 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ 426 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ 427 428 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ 429 #endif /* STM32L4P5xx || STM32L4Q5xx */ 430 431 #endif /* DMAMUX1 */ 432 433 /** 434 * @} 435 */ 436 437 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 438 * @{ 439 */ 440 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 441 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 442 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 448 * @{ 449 */ 450 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 451 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 452 /** 453 * @} 454 */ 455 456 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 457 * @{ 458 */ 459 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 460 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 461 /** 462 * @} 463 */ 464 465 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 466 * @{ 467 */ 468 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 469 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 470 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 471 /** 472 * @} 473 */ 474 475 /** @defgroup DMA_Memory_data_size DMA Memory data size 476 * @{ 477 */ 478 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 479 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 480 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup DMA_mode DMA mode 486 * @{ 487 */ 488 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 489 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 490 /** 491 * @} 492 */ 493 494 /** @defgroup DMA_Priority_level DMA Priority level 495 * @{ 496 */ 497 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 498 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 499 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 500 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 501 /** 502 * @} 503 */ 504 505 506 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 507 * @{ 508 */ 509 #define DMA_IT_TC DMA_CCR_TCIE 510 #define DMA_IT_HT DMA_CCR_HTIE 511 #define DMA_IT_TE DMA_CCR_TEIE 512 /** 513 * @} 514 */ 515 516 /** @defgroup DMA_flag_definitions DMA flag definitions 517 * @{ 518 */ 519 #define DMA_FLAG_GL1 DMA_ISR_GIF1 520 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 521 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 522 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 523 #define DMA_FLAG_GL2 DMA_ISR_GIF2 524 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 525 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 526 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 527 #define DMA_FLAG_GL3 DMA_ISR_GIF3 528 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 529 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 530 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 531 #define DMA_FLAG_GL4 DMA_ISR_GIF4 532 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 533 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 534 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 535 #define DMA_FLAG_GL5 DMA_ISR_GIF5 536 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 537 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 538 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 539 #define DMA_FLAG_GL6 DMA_ISR_GIF6 540 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 541 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 542 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 543 #define DMA_FLAG_GL7 DMA_ISR_GIF7 544 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 545 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 546 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 547 /** 548 * @} 549 */ 550 551 /** 552 * @} 553 */ 554 555 /* Exported macros -----------------------------------------------------------*/ 556 /** @defgroup DMA_Exported_Macros DMA Exported Macros 557 * @{ 558 */ 559 560 /** @brief Reset DMA handle state. 561 * @param __HANDLE__ DMA handle 562 * @retval None 563 */ 564 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 565 566 /** 567 * @brief Enable the specified DMA Channel. 568 * @param __HANDLE__ DMA handle 569 * @retval None 570 */ 571 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 572 573 /** 574 * @brief Disable the specified DMA Channel. 575 * @param __HANDLE__ DMA handle 576 * @retval None 577 */ 578 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 579 580 581 /* Interrupt & Flag management */ 582 583 /** 584 * @brief Return the current DMA Channel transfer complete flag. 585 * @param __HANDLE__ DMA handle 586 * @retval The specified transfer complete flag index. 587 */ 588 589 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 590 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 591 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 592 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 593 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 594 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 595 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 602 DMA_FLAG_TC7) 603 604 /** 605 * @brief Return the current DMA Channel half transfer complete flag. 606 * @param __HANDLE__ DMA handle 607 * @retval The specified half transfer complete flag index. 608 */ 609 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 610 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 611 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 612 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 613 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 614 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 622 DMA_FLAG_HT7) 623 624 /** 625 * @brief Return the current DMA Channel transfer error flag. 626 * @param __HANDLE__ DMA handle 627 * @retval The specified transfer error flag index. 628 */ 629 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 630 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 631 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 642 DMA_FLAG_TE7) 643 644 /** 645 * @brief Return the current DMA Channel Global interrupt flag. 646 * @param __HANDLE__ DMA handle 647 * @retval The specified transfer error flag index. 648 */ 649 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 650 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 651 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 652 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 661 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 662 DMA_ISR_GIF7) 663 664 /** 665 * @brief Get the DMA Channel pending flags. 666 * @param __HANDLE__ DMA handle 667 * @param __FLAG__ Get the specified flag. 668 * This parameter can be any combination of the following values: 669 * @arg DMA_FLAG_TCx: Transfer complete flag 670 * @arg DMA_FLAG_HTx: Half transfer complete flag 671 * @arg DMA_FLAG_TEx: Transfer error flag 672 * @arg DMA_FLAG_GLx: Global interrupt flag 673 * Where x can be from 1 to 7 to select the DMA Channel x flag. 674 * @retval The state of FLAG (SET or RESET). 675 */ 676 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 677 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 678 679 /** 680 * @brief Clear the DMA Channel pending flags. 681 * @param __HANDLE__ DMA handle 682 * @param __FLAG__ specifies the flag to clear. 683 * This parameter can be any combination of the following values: 684 * @arg DMA_FLAG_TCx: Transfer complete flag 685 * @arg DMA_FLAG_HTx: Half transfer complete flag 686 * @arg DMA_FLAG_TEx: Transfer error flag 687 * @arg DMA_FLAG_GLx: Global interrupt flag 688 * Where x can be from 1 to 7 to select the DMA Channel x flag. 689 * @retval None 690 */ 691 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 692 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 693 694 /** 695 * @brief Enable the specified DMA Channel interrupts. 696 * @param __HANDLE__ DMA handle 697 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 698 * This parameter can be any combination of the following values: 699 * @arg DMA_IT_TC: Transfer complete interrupt mask 700 * @arg DMA_IT_HT: Half transfer complete interrupt mask 701 * @arg DMA_IT_TE: Transfer error interrupt mask 702 * @retval None 703 */ 704 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 705 706 /** 707 * @brief Disable the specified DMA Channel interrupts. 708 * @param __HANDLE__ DMA handle 709 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 710 * This parameter can be any combination of the following values: 711 * @arg DMA_IT_TC: Transfer complete interrupt mask 712 * @arg DMA_IT_HT: Half transfer complete interrupt mask 713 * @arg DMA_IT_TE: Transfer error interrupt mask 714 * @retval None 715 */ 716 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 717 718 /** 719 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 720 * @param __HANDLE__ DMA handle 721 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 722 * This parameter can be one of the following values: 723 * @arg DMA_IT_TC: Transfer complete interrupt mask 724 * @arg DMA_IT_HT: Half transfer complete interrupt mask 725 * @arg DMA_IT_TE: Transfer error interrupt mask 726 * @retval The state of DMA_IT (SET or RESET). 727 */ 728 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 729 730 /** 731 * @brief Return the number of remaining data units in the current DMA Channel transfer. 732 * @param __HANDLE__ DMA handle 733 * @retval The number of remaining data units in the current DMA Channel transfer. 734 */ 735 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 736 737 /** 738 * @} 739 */ 740 741 #if defined(DMAMUX1) 742 /* Include DMA HAL Extension module */ 743 #include "stm32l4xx_hal_dma_ex.h" 744 #endif /* DMAMUX1 */ 745 746 /* Exported functions --------------------------------------------------------*/ 747 748 /** @addtogroup DMA_Exported_Functions 749 * @{ 750 */ 751 752 /** @addtogroup DMA_Exported_Functions_Group1 753 * @{ 754 */ 755 /* Initialization and de-initialization functions *****************************/ 756 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 757 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 758 /** 759 * @} 760 */ 761 762 /** @addtogroup DMA_Exported_Functions_Group2 763 * @{ 764 */ 765 /* IO operation functions *****************************************************/ 766 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 767 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 768 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 769 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 770 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 771 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 772 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 773 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 774 775 /** 776 * @} 777 */ 778 779 /** @addtogroup DMA_Exported_Functions_Group3 780 * @{ 781 */ 782 /* Peripheral State and Error functions ***************************************/ 783 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 784 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 785 /** 786 * @} 787 */ 788 789 /** 790 * @} 791 */ 792 793 /* Private macros ------------------------------------------------------------*/ 794 /** @defgroup DMA_Private_Macros DMA Private Macros 795 * @{ 796 */ 797 798 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 799 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 800 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 801 802 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 803 804 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 805 ((STATE) == DMA_PINC_DISABLE)) 806 807 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 808 ((STATE) == DMA_MINC_DISABLE)) 809 810 #if !defined (DMAMUX1) 811 812 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 813 ((REQUEST) == DMA_REQUEST_1) || \ 814 ((REQUEST) == DMA_REQUEST_2) || \ 815 ((REQUEST) == DMA_REQUEST_3) || \ 816 ((REQUEST) == DMA_REQUEST_4) || \ 817 ((REQUEST) == DMA_REQUEST_5) || \ 818 ((REQUEST) == DMA_REQUEST_6) || \ 819 ((REQUEST) == DMA_REQUEST_7)) 820 #endif 821 822 #if defined(DMAMUX1) 823 824 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) 825 826 #endif /* DMAMUX1 */ 827 828 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 829 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 830 ((SIZE) == DMA_PDATAALIGN_WORD)) 831 832 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 833 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 834 ((SIZE) == DMA_MDATAALIGN_WORD )) 835 836 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 837 ((MODE) == DMA_CIRCULAR)) 838 839 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 840 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 841 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 842 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 843 844 /** 845 * @} 846 */ 847 848 /* Private functions ---------------------------------------------------------*/ 849 850 /** 851 * @} 852 */ 853 854 /** 855 * @} 856 */ 857 858 #ifdef __cplusplus 859 } 860 #endif 861 862 #endif /* STM32L4xx_HAL_DMA_H */ 863 864 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 865