1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32L4xx_HAL_H 23 #define STM32L4xx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l4xx_hal_conf.h" 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /* Exported constants --------------------------------------------------------*/ 42 43 /** @defgroup HAL_Exported_Constants HAL Exported Constants 44 * @{ 45 */ 46 47 /** @defgroup HAL_TICK_FREQ Tick Frequency 48 * @{ 49 */ 50 #define HAL_TICK_FREQ_10HZ 100U 51 #define HAL_TICK_FREQ_100HZ 10U 52 #define HAL_TICK_FREQ_1KHZ 1U 53 #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ 54 55 /** 56 * @} 57 */ 58 59 /** 60 * @} 61 */ 62 63 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 64 * @{ 65 */ 66 67 /** @defgroup SYSCFG_BootMode Boot Mode 68 * @{ 69 */ 70 #define SYSCFG_BOOT_MAINFLASH 0U 71 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 72 73 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 74 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 75 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 76 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 77 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 78 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 79 /* STM32L496xx || STM32L4A6xx || */ 80 /* STM32L4P5xx || STM32L4Q5xx || */ 81 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 82 83 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 84 85 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 86 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) 87 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) 88 #else 89 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 90 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 91 92 /** 93 * @} 94 */ 95 96 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 97 * @{ 98 */ 99 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 100 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 101 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 102 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 103 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 104 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 111 * @{ 112 */ 113 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 114 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 115 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 116 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 117 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 118 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 119 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 120 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 121 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 122 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 123 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 124 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 125 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 126 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 127 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 128 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 129 #if defined(SYSCFG_SWPR_PAGE31) 130 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 131 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 132 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 133 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 134 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 135 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 136 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 137 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 138 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 139 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 140 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 141 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 142 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 143 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 144 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 145 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 146 #endif /* SYSCFG_SWPR_PAGE31 */ 147 148 /** 149 * @} 150 */ 151 152 #if defined(SYSCFG_SWPR2_PAGE63) 153 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 154 * @{ 155 */ 156 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 157 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 158 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 159 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 160 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 161 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 162 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 163 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 164 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 165 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 166 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 167 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 168 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 169 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 170 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 171 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 172 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 173 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 174 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 175 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 176 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 177 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 178 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 179 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 180 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 181 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 182 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 183 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 184 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 185 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 186 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 187 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 188 189 /** 190 * @} 191 */ 192 #endif /* SYSCFG_SWPR2_PAGE63 */ 193 194 #if defined(VREFBUF) 195 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 196 * @{ 197 */ 198 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ 199 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 200 201 /** 202 * @} 203 */ 204 205 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 206 * @{ 207 */ 208 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 209 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 210 211 /** 212 * @} 213 */ 214 #endif /* VREFBUF */ 215 216 /** @defgroup SYSCFG_flags_definition Flags 217 * @{ 218 */ 219 220 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 221 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 222 223 /** 224 * @} 225 */ 226 227 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 228 * @{ 229 */ 230 231 /** @brief Fast-mode Plus driving capability on a specific GPIO 232 */ 233 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 234 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 235 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 236 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 237 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 238 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 239 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 240 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 241 242 /** 243 * @} 244 */ 245 246 /** 247 * @} 248 */ 249 250 /* Exported macros -----------------------------------------------------------*/ 251 252 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 253 * @{ 254 */ 255 256 /** @brief Freeze/Unfreeze Peripherals in Debug mode 257 */ 258 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 259 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 260 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 261 #endif 262 263 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 264 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 265 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 266 #endif 267 268 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 269 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 270 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 271 #endif 272 273 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 274 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 275 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 276 #endif 277 278 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 279 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 280 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 281 #endif 282 283 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 284 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 285 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 286 #endif 287 288 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 289 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 290 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 291 #endif 292 293 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 294 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 295 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 296 #endif 297 298 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 299 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 300 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 301 #endif 302 303 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 304 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 305 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 306 #endif 307 308 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 309 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 310 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 311 #endif 312 313 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 314 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 315 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 316 #endif 317 318 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 319 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 320 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 321 #endif 322 323 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 324 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 325 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 326 #endif 327 328 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) 329 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 330 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 331 #endif 332 333 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 334 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 335 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 336 #endif 337 338 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 339 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 340 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 341 #endif 342 343 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 344 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 345 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 346 #endif 347 348 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 349 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 350 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 351 #endif 352 353 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 354 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 355 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 356 #endif 357 358 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 359 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 360 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 361 #endif 362 363 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 364 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 365 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 366 #endif 367 368 /** 369 * @} 370 */ 371 372 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 373 * @{ 374 */ 375 376 /** @brief Main Flash memory mapped at 0x00000000. 377 */ 378 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 379 380 /** @brief System Flash memory mapped at 0x00000000. 381 */ 382 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 383 384 /** @brief Embedded SRAM mapped at 0x00000000. 385 */ 386 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 387 388 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 389 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 390 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 391 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 392 393 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 394 */ 395 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 396 397 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 398 /* STM32L496xx || STM32L4A6xx || */ 399 /* STM32L4P5xx || STM32L4Q5xx || */ 400 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 401 402 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 403 404 /** @brief OCTOSPI mapped at 0x00000000. 405 */ 406 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) 407 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) 408 409 #else 410 411 /** @brief QUADSPI mapped at 0x00000000. 412 */ 413 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 414 415 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 416 417 /** 418 * @brief Return the boot mode as configured by user. 419 * @retval The boot mode as configured by user. The returned value can be one 420 * of the following values: 421 * @arg @ref SYSCFG_BOOT_MAINFLASH 422 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 423 @if STM32L486xx 424 * @arg @ref SYSCFG_BOOT_FMC 425 @endif 426 * @arg @ref SYSCFG_BOOT_SRAM 427 @if STM32L422xx 428 * @arg @ref SYSCFG_BOOT_QUADSPI 429 @endif 430 @if STM32L443xx 431 * @arg @ref SYSCFG_BOOT_QUADSPI 432 @endif 433 @if STM32L462xx 434 * @arg @ref SYSCFG_BOOT_QUADSPI 435 @endif 436 @if STM32L486xx 437 * @arg @ref SYSCFG_BOOT_QUADSPI 438 @endif 439 */ 440 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 441 442 /** @brief SRAM2 page 0 to 31 write protection enable macro 443 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 444 * @note Write protection can only be disabled by a system reset 445 */ 446 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 447 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 448 }while(0) 449 450 #if defined(SYSCFG_SWPR2_PAGE63) 451 /** @brief SRAM2 page 32 to 63 write protection enable macro 452 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 453 * @note Write protection can only be disabled by a system reset 454 */ 455 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 456 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 457 }while(0) 458 #endif /* SYSCFG_SWPR2_PAGE63 */ 459 460 /** @brief SRAM2 page write protection unlock prior to erase 461 * @note Writing a wrong key reactivates the write protection 462 */ 463 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 464 SYSCFG->SKR = 0x53;\ 465 }while(0) 466 467 /** @brief SRAM2 erase 468 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 469 */ 470 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 471 472 /** @brief Floating Point Unit interrupt enable/disable macros 473 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 474 */ 475 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 476 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 477 }while(0) 478 479 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 480 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 481 }while(0) 482 483 /** @brief SYSCFG Break ECC lock. 484 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 485 * @note The selected configuration is locked and can be unlocked only by system reset. 486 */ 487 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 488 489 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 490 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 491 * @note The selected configuration is locked and can be unlocked only by system reset. 492 */ 493 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 494 495 /** @brief SYSCFG Break PVD lock. 496 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 497 * @note The selected configuration is locked and can be unlocked only by system reset. 498 */ 499 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 500 501 /** @brief SYSCFG Break SRAM2 parity lock. 502 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 503 * @note The selected configuration is locked and can be unlocked by system reset. 504 */ 505 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 506 507 /** @brief Check SYSCFG flag is set or not. 508 * @param __FLAG__ specifies the flag to check. 509 * This parameter can be one of the following values: 510 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 511 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 512 * @retval The new state of __FLAG__ (TRUE or FALSE). 513 */ 514 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) 515 516 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 517 */ 518 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 519 520 /** @brief Fast-mode Plus driving capability enable/disable macros 521 * @param __FASTMODEPLUS__ This parameter can be a value of : 522 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 523 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 524 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 525 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 526 */ 527 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 528 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 529 }while(0) 530 531 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 532 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 533 }while(0) 534 535 /** 536 * @} 537 */ 538 539 /* Private macros ------------------------------------------------------------*/ 540 /** @defgroup HAL_Private_Macros HAL Private Macros 541 * @{ 542 */ 543 544 #define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \ 545 ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \ 546 ((__FREQ__) == HAL_TICK_FREQ_1KHZ)) 547 548 /** 549 * @} 550 */ 551 552 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 553 * @{ 554 */ 555 556 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 557 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 558 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 559 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 560 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 561 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 562 563 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 564 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 565 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 566 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 567 568 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) 569 570 #if defined(VREFBUF) 571 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 572 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 573 574 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 575 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 576 577 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 578 #endif /* VREFBUF */ 579 580 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 581 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 582 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 583 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 584 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 585 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 586 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 587 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 588 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 589 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 590 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 591 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 592 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 593 #else 594 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 595 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 596 #endif 597 /** 598 * @} 599 */ 600 601 /* Exported variables --------------------------------------------------------*/ 602 603 /** @addtogroup HAL_Exported_Variables 604 * @{ 605 */ 606 extern __IO uint32_t uwTick; 607 extern uint32_t uwTickPrio; 608 extern uint32_t uwTickFreq; 609 /** 610 * @} 611 */ 612 613 /* Exported functions --------------------------------------------------------*/ 614 615 /** @addtogroup HAL_Exported_Functions 616 * @{ 617 */ 618 619 /** @addtogroup HAL_Exported_Functions_Group1 620 * @{ 621 */ 622 623 /* Initialization and de-initialization functions ******************************/ 624 HAL_StatusTypeDef HAL_Init(void); 625 HAL_StatusTypeDef HAL_DeInit(void); 626 void HAL_MspInit(void); 627 void HAL_MspDeInit(void); 628 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 629 630 /** 631 * @} 632 */ 633 634 /** @addtogroup HAL_Exported_Functions_Group2 635 * @{ 636 */ 637 638 /* Peripheral Control functions ************************************************/ 639 void HAL_IncTick(void); 640 void HAL_Delay(uint32_t Delay); 641 uint32_t HAL_GetTick(void); 642 uint32_t HAL_GetTickPrio(void); 643 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); 644 uint32_t HAL_GetTickFreq(void); 645 void HAL_SuspendTick(void); 646 void HAL_ResumeTick(void); 647 uint32_t HAL_GetHalVersion(void); 648 uint32_t HAL_GetREVID(void); 649 uint32_t HAL_GetDEVID(void); 650 uint32_t HAL_GetUIDw0(void); 651 uint32_t HAL_GetUIDw1(void); 652 uint32_t HAL_GetUIDw2(void); 653 654 /** 655 * @} 656 */ 657 658 /** @addtogroup HAL_Exported_Functions_Group3 659 * @{ 660 */ 661 662 /* DBGMCU Peripheral Control functions *****************************************/ 663 void HAL_DBGMCU_EnableDBGSleepMode(void); 664 void HAL_DBGMCU_DisableDBGSleepMode(void); 665 void HAL_DBGMCU_EnableDBGStopMode(void); 666 void HAL_DBGMCU_DisableDBGStopMode(void); 667 void HAL_DBGMCU_EnableDBGStandbyMode(void); 668 void HAL_DBGMCU_DisableDBGStandbyMode(void); 669 670 /** 671 * @} 672 */ 673 674 /** @addtogroup HAL_Exported_Functions_Group4 675 * @{ 676 */ 677 678 /* SYSCFG Control functions ****************************************************/ 679 void HAL_SYSCFG_SRAM2Erase(void); 680 void HAL_SYSCFG_EnableMemorySwappingBank(void); 681 void HAL_SYSCFG_DisableMemorySwappingBank(void); 682 683 #if defined(VREFBUF) 684 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 685 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 686 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 687 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 688 void HAL_SYSCFG_DisableVREFBUF(void); 689 #endif /* VREFBUF */ 690 691 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 692 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 693 694 /** 695 * @} 696 */ 697 698 /** 699 * @} 700 */ 701 702 /** 703 * @} 704 */ 705 706 /** 707 * @} 708 */ 709 710 #ifdef __cplusplus 711 } 712 #endif 713 714 #endif /* STM32L4xx_HAL_H */ 715 716 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 717