xref: /btstack/port/stm32-l073rz-nucleo-em9304/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h (revision e838079242074edcbcbb400962776e15fe6ca6cb)
1 /**
2   ******************************************************************************
3   * @file    stm32l0xx_hal_tim.h
4   * @author  MCD Application Team
5   * @brief   Header file of TIM HAL module.
6   ******************************************************************************
7     * @attention
8   *
9   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10   * All rights reserved.</center></h2>
11   *
12   * This software component is licensed by ST under BSD 3-Clause license,
13   * the "License"; You may not use this file except in compliance with the
14   * License. You may obtain a copy of the License at:
15   *                        opensource.org/licenses/BSD-3-Clause
16   *
17   ******************************************************************************
18   */
19 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L0xx_HAL_TIM_H
22 #define STM32L0xx_HAL_TIM_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l0xx_hal_def.h"
30 
31 /** @addtogroup STM32L0xx_HAL_Driver
32   * @{
33   */
34 
35 /** @addtogroup TIM
36   * @{
37   */
38 
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup TIM_Exported_Types TIM Exported Types
41   * @{
42   */
43 
44 /**
45   * @brief  TIM Time base Configuration Structure definition
46   */
47 typedef struct
48 {
49   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
50                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
51 
52   uint32_t CounterMode;       /*!< Specifies the counter mode.
53                                    This parameter can be a value of @ref TIM_Counter_Mode */
54 
55   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
56                                    Auto-Reload Register at the next update event.
57                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
58 
59   uint32_t ClockDivision;     /*!< Specifies the clock division.
60                                    This parameter can be a value of @ref TIM_ClockDivision */
61 
62   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
63                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
64 } TIM_Base_InitTypeDef;
65 
66 /**
67   * @brief  TIM Output Compare Configuration Structure definition
68   */
69 typedef struct
70 {
71   uint32_t OCMode;        /*!< Specifies the TIM mode.
72                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
73 
74   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
75                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
76 
77   uint32_t OCPolarity;    /*!< Specifies the output polarity.
78                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
79 
80   uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
81                                This parameter can be a value of @ref TIM_Output_Fast_State
82                                @note This parameter is valid only in PWM1 and PWM2 mode. */
83 } TIM_OC_InitTypeDef;
84 
85 /**
86   * @brief  TIM One Pulse Mode Configuration Structure definition
87   */
88 typedef struct
89 {
90   uint32_t OCMode;        /*!< Specifies the TIM mode.
91                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
92 
93   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
94                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
95 
96   uint32_t OCPolarity;    /*!< Specifies the output polarity.
97                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
98 
99   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
100                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
101 
102   uint32_t ICSelection;   /*!< Specifies the input.
103                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
104 
105   uint32_t ICFilter;      /*!< Specifies the input capture filter.
106                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
107 } TIM_OnePulse_InitTypeDef;
108 
109 /**
110   * @brief  TIM Input Capture Configuration Structure definition
111   */
112 typedef struct
113 {
114   uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
115                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
116 
117   uint32_t ICSelection;  /*!< Specifies the input.
118                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
119 
120   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
121                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
122 
123   uint32_t ICFilter;     /*!< Specifies the input capture filter.
124                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
125 } TIM_IC_InitTypeDef;
126 
127 /**
128   * @brief  TIM Encoder Configuration Structure definition
129   */
130 typedef struct
131 {
132   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
133                                This parameter can be a value of @ref TIM_Encoder_Mode */
134 
135   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
136                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
137 
138   uint32_t IC1Selection;  /*!< Specifies the input.
139                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
140 
141   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
142                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
143 
144   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
145                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
146 
147   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
148                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
149 
150   uint32_t IC2Selection;  /*!< Specifies the input.
151                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
152 
153   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
154                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
155 
156   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
157                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
158 } TIM_Encoder_InitTypeDef;
159 
160 /**
161   * @brief  Clock Configuration Handle Structure definition
162   */
163 typedef struct
164 {
165   uint32_t ClockSource;     /*!< TIM clock sources
166                                  This parameter can be a value of @ref TIM_Clock_Source */
167   uint32_t ClockPolarity;   /*!< TIM clock polarity
168                                  This parameter can be a value of @ref TIM_Clock_Polarity */
169   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
170                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
171   uint32_t ClockFilter;     /*!< TIM clock filter
172                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
173 } TIM_ClockConfigTypeDef;
174 
175 /**
176   * @brief  TIM Clear Input Configuration Handle Structure definition
177   */
178 typedef struct
179 {
180   uint32_t ClearInputState;      /*!< TIM clear Input state
181                                       This parameter can be ENABLE or DISABLE */
182   uint32_t ClearInputSource;     /*!< TIM clear Input sources
183                                       This parameter can be a value of @ref TIM_ClearInput_Source */
184   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
185                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
186   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
187                                       This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
188   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
189                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
190 } TIM_ClearInputConfigTypeDef;
191 
192 /**
193   * @brief  TIM Master configuration Structure definition
194   */
195 typedef struct
196 {
197   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
198                                         This parameter can be a value of @ref TIM_Master_Mode_Selection */
199   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
200                                         This parameter can be a value of @ref TIM_Master_Slave_Mode */
201 } TIM_MasterConfigTypeDef;
202 
203 /**
204   * @brief  TIM Slave configuration Structure definition
205   */
206 typedef struct
207 {
208   uint32_t  SlaveMode;         /*!< Slave mode selection
209                                     This parameter can be a value of @ref TIM_Slave_Mode */
210   uint32_t  InputTrigger;      /*!< Input Trigger source
211                                     This parameter can be a value of @ref TIM_Trigger_Selection */
212   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
213                                     This parameter can be a value of @ref TIM_Trigger_Polarity */
214   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
215                                     This parameter can be a value of @ref TIM_Trigger_Prescaler */
216   uint32_t  TriggerFilter;     /*!< Input trigger filter
217                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
218 
219 } TIM_SlaveConfigTypeDef;
220 
221 /**
222   * @brief  HAL State structures definition
223   */
224 typedef enum
225 {
226   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
227   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
228   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
229   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
230   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
231 } HAL_TIM_StateTypeDef;
232 
233 /**
234   * @brief  HAL Active channel structures definition
235   */
236 typedef enum
237 {
238   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
239   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
240   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
241   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
242   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
243 } HAL_TIM_ActiveChannel;
244 
245 /**
246   * @brief  TIM Time Base Handle Structure definition
247   */
248 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
249 typedef struct __TIM_HandleTypeDef
250 #else
251 typedef struct
252 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
253 {
254   TIM_TypeDef                 *Instance;     /*!< Register base address             */
255   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
256   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
257   DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
258                                                   This array is accessed by a @ref DMA_Handle_index */
259   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
260   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
261 
262 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
263   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
264   void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
265   void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
266   void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
267   void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
268   void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
269   void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
270   void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
271   void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
272   void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
273   void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
274   void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
275   void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
276   void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
277   void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
278   void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
279   void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
280   void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
281   void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
282   void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
283   void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
284   void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
285 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
286 } TIM_HandleTypeDef;
287 
288 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
289 /**
290   * @brief  HAL TIM Callback ID enumeration definition
291   */
292 typedef enum
293 {
294    HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
295   ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
296   ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
297   ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
298   ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
299   ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
300   ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
301   ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
302   ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
303   ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
304   ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
305   ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
306   ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
307   ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
308   ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
309   ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
310 
311   ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
312   ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
313   ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
314   ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
315   ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
316   ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
317 } HAL_TIM_CallbackIDTypeDef;
318 
319 /**
320   * @brief  HAL TIM Callback pointer definition
321   */
322 typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
323 
324 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
325 
326 /**
327   * @}
328   */
329 /* End of exported types -----------------------------------------------------*/
330 
331 /* Exported constants --------------------------------------------------------*/
332 /** @defgroup TIM_Exported_Constants TIM Exported Constants
333   * @{
334   */
335 
336 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
337   * @{
338   */
339 #define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
340 #define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
341 /**
342   * @}
343   */
344 
345 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
346   * @{
347   */
348 #define TIM_DMABASE_CR1                    0x00000000U
349 #define TIM_DMABASE_CR2                    0x00000001U
350 #define TIM_DMABASE_SMCR                   0x00000002U
351 #define TIM_DMABASE_DIER                   0x00000003U
352 #define TIM_DMABASE_SR                     0x00000004U
353 #define TIM_DMABASE_EGR                    0x00000005U
354 #define TIM_DMABASE_CCMR1                  0x00000006U
355 #define TIM_DMABASE_CCMR2                  0x00000007U
356 #define TIM_DMABASE_CCER                   0x00000008U
357 #define TIM_DMABASE_CNT                    0x00000009U
358 #define TIM_DMABASE_PSC                    0x0000000AU
359 #define TIM_DMABASE_ARR                    0x0000000BU
360 #define TIM_DMABASE_CCR1                   0x0000000DU
361 #define TIM_DMABASE_CCR2                   0x0000000EU
362 #define TIM_DMABASE_CCR3                   0x0000000FU
363 #define TIM_DMABASE_CCR4                   0x00000010U
364 #define TIM_DMABASE_DCR                    0x00000012U
365 #define TIM_DMABASE_DMAR                   0x00000013U
366 #define TIM_DMABASE_OR                     0x00000014U
367 /**
368   * @}
369   */
370 
371 /** @defgroup TIM_Event_Source TIM Event Source
372   * @{
373   */
374 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
375 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
376 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
377 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
378 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
379 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
380 /**
381   * @}
382   */
383 
384 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
385   * @{
386   */
387 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
388 #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
389 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
390 /**
391   * @}
392   */
393 
394 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
395   * @{
396   */
397 #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
398 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
399 /**
400   * @}
401   */
402 
403 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
404   * @{
405   */
406 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
407 #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
408 #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
409 #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
410 /**
411   * @}
412   */
413 
414 /** @defgroup TIM_Counter_Mode TIM Counter Mode
415   * @{
416   */
417 #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
418 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
419 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
420 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
421 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
422 /**
423   * @}
424   */
425 
426 /** @defgroup TIM_ClockDivision TIM Clock Division
427   * @{
428   */
429 #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
430 #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
431 #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
432 /**
433   * @}
434   */
435 
436 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
437   * @{
438   */
439 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
440 #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
441 /**
442   * @}
443   */
444 
445 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
446   * @{
447   */
448 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
449 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
450 
451 /**
452   * @}
453   */
454 
455 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
456   * @{
457   */
458 #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
459 #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
460 /**
461   * @}
462   */
463 
464 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
465   * @{
466   */
467 #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
468 #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
469 /**
470   * @}
471   */
472 
473 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
474   * @{
475   */
476 #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
477 #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
478 /**
479   * @}
480   */
481 
482 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
483   * @{
484   */
485 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
486 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
487 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
488 /**
489   * @}
490   */
491 
492 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
493   * @{
494   */
495 #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
496                                                                                      connected to IC1, IC2, IC3 or IC4, respectively */
497 #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
498                                                                                      connected to IC2, IC1, IC4 or IC3, respectively */
499 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
500 /**
501   * @}
502   */
503 
504 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
505   * @{
506   */
507 #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
508 #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
509 #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
510 #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
511 /**
512   * @}
513   */
514 
515 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
516   * @{
517   */
518 #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
519 #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
520 /**
521   * @}
522   */
523 
524 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
525   * @{
526   */
527 #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
528 #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
529 #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
530 /**
531   * @}
532   */
533 
534 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
535   * @{
536   */
537 #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
538 #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
539 #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
540 #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
541 #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
542 #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
543 /**
544   * @}
545   */
546 
547 /** @defgroup TIM_DMA_sources TIM DMA Sources
548   * @{
549   */
550 #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
551 #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
552 #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
553 #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
554 #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
555 #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
556 /**
557   * @}
558   */
559 
560 /** @defgroup TIM_Flag_definition TIM Flag Definition
561   * @{
562   */
563 #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
564 #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
565 #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
566 #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
567 #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
568 #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
569 #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
570 #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
571 #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
572 #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
573 /**
574   * @}
575   */
576 
577 /** @defgroup TIM_Channel TIM Channel
578   * @{
579   */
580 #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
581 #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
582 #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
583 #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
584 #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
585 /**
586   * @}
587   */
588 
589 /** @defgroup TIM_Clock_Source TIM Clock Source
590   * @{
591   */
592 #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
593 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
594 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
595 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
596 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
597 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
598 #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
599 #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
600 #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
601 #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
602 /**
603   * @}
604   */
605 
606 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
607   * @{
608   */
609 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
610 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
611 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
612 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
613 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
614 /**
615   * @}
616   */
617 
618 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
619   * @{
620   */
621 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
622 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
623 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
624 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
625 /**
626   * @}
627   */
628 
629 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
630   * @{
631   */
632 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
633 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
634 /**
635   * @}
636   */
637 
638 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
639   * @{
640   */
641 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
642 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
643 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
644 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
645 /**
646   * @}
647   */
648 
649 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
650   * @{
651   */
652 #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
653 #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
654 #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
655 #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
656 #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
657 #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
658 #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
659 #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
660 /**
661   * @}
662   */
663 
664 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
665   * @{
666   */
667 #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
668 #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
669 /**
670   * @}
671   */
672 
673 /** @defgroup TIM_Slave_Mode TIM Slave mode
674   * @{
675   */
676 #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
677 #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
678 #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
679 #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
680 #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
681 /**
682   * @}
683   */
684 
685 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
686   * @{
687   */
688 #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
689 #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
690 #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
691 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
692 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
693 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
694 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
695 #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
696 /**
697   * @}
698   */
699 
700 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
701   * @{
702   */
703 #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
704 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
705 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
706 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
707 #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
708 #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
709 #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
710 #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
711 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
712 /**
713   * @}
714   */
715 
716 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
717   * @{
718   */
719 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
720 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
721 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
722 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
723 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
724 /**
725   * @}
726   */
727 
728 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
729   * @{
730   */
731 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
732 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
733 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
734 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
735 /**
736   * @}
737   */
738 
739 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
740   * @{
741   */
742 #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
743 #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
744 /**
745   * @}
746   */
747 
748 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
749   * @{
750   */
751 #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
752 #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
753 #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
754 #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
755 #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
756 #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
757 #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
758 #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
759 #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
760 #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
761 #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
762 #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
763 #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
764 #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
765 #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
766 #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
767 #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
768 #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
769 /**
770   * @}
771   */
772 
773 /** @defgroup DMA_Handle_index TIM DMA Handle Index
774   * @{
775   */
776 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
777 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
778 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
779 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
780 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
781 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
782 /**
783   * @}
784   */
785 
786 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
787   * @{
788   */
789 #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
790 #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
791 /**
792   * @}
793   */
794 
795 /**
796   * @}
797   */
798 /* End of exported constants -------------------------------------------------*/
799 
800 /* Exported macros -----------------------------------------------------------*/
801 /** @defgroup TIM_Exported_Macros TIM Exported Macros
802   * @{
803   */
804 
805 /** @brief  Reset TIM handle state.
806   * @param  __HANDLE__ TIM handle.
807   * @retval None
808   */
809 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
810 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
811                                                       (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
812                                                       (__HANDLE__)->Base_MspInitCallback         = NULL;     \
813                                                       (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
814                                                       (__HANDLE__)->IC_MspInitCallback           = NULL;     \
815                                                       (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
816                                                       (__HANDLE__)->OC_MspInitCallback           = NULL;     \
817                                                       (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
818                                                       (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
819                                                       (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
820                                                       (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
821                                                       (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
822                                                       (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
823                                                       (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
824                                                      } while(0)
825 #else
826 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
827 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
828 
829 /**
830   * @brief  Enable the TIM peripheral.
831   * @param  __HANDLE__ TIM handle
832   * @retval None
833   */
834 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
835 
836 /**
837   * @brief  Disable the TIM peripheral.
838   * @param  __HANDLE__ TIM handle
839   * @retval None
840   */
841 #define __HAL_TIM_DISABLE(__HANDLE__) \
842                         do { \
843                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
844                           { \
845                             (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
846                           } \
847                         } while(0)
848 
849 /** @brief  Enable the specified TIM interrupt.
850   * @param  __HANDLE__ specifies the TIM Handle.
851   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
852   *          This parameter can be one of the following values:
853   *            @arg TIM_IT_UPDATE: Update interrupt
854   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
855   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
856   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
857   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
858   *            @arg TIM_IT_TRIGGER: Trigger interrupt
859   * @retval None
860   */
861 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
862 
863 /** @brief  Disable the specified TIM interrupt.
864   * @param  __HANDLE__ specifies the TIM Handle.
865   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
866   *          This parameter can be one of the following values:
867   *            @arg TIM_IT_UPDATE: Update interrupt
868   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
869   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
870   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
871   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
872   *            @arg TIM_IT_TRIGGER: Trigger interrupt
873   * @retval None
874   */
875 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
876 
877 /** @brief  Enable the specified DMA request.
878   * @param  __HANDLE__ specifies the TIM Handle.
879   * @param  __DMA__ specifies the TIM DMA request to enable.
880   *          This parameter can be one of the following values:
881   *            @arg TIM_DMA_UPDATE: Update DMA request
882   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
883   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
884   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
885   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
886   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
887   * @retval None
888   */
889 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
890 
891 /** @brief  Disable the specified DMA request.
892   * @param  __HANDLE__ specifies the TIM Handle.
893   * @param  __DMA__ specifies the TIM DMA request to disable.
894   *          This parameter can be one of the following values:
895   *            @arg TIM_DMA_UPDATE: Update DMA request
896   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
897   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
898   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
899   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
900   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
901   * @retval None
902   */
903 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
904 
905 /** @brief  Check whether the specified TIM interrupt flag is set or not.
906   * @param  __HANDLE__ specifies the TIM Handle.
907   * @param  __FLAG__ specifies the TIM interrupt flag to check.
908   *        This parameter can be one of the following values:
909   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
910   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
911   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
912   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
913   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
914   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
915   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
916   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
917   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
918   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
919   * @retval The new state of __FLAG__ (TRUE or FALSE).
920   */
921 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
922 
923 /** @brief  Clear the specified TIM interrupt flag.
924   * @param  __HANDLE__ specifies the TIM Handle.
925   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
926   *        This parameter can be one of the following values:
927   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
928   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
929   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
930   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
931   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
932   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
933   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
934   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
935   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
936   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
937   * @retval The new state of __FLAG__ (TRUE or FALSE).
938   */
939 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
940 
941 /**
942   * @brief  Check whether the specified TIM interrupt source is enabled or not.
943   * @param  __HANDLE__ TIM handle
944   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
945   *          This parameter can be one of the following values:
946   *            @arg TIM_IT_UPDATE: Update interrupt
947   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
948   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
949   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
950   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
951   *            @arg TIM_IT_TRIGGER: Trigger interrupt
952   * @retval The state of TIM_IT (SET or RESET).
953   */
954 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
955 
956 /** @brief Clear the TIM interrupt pending bits.
957   * @param  __HANDLE__ TIM handle
958   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
959   *          This parameter can be one of the following values:
960   *            @arg TIM_IT_UPDATE: Update interrupt
961   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
962   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
963   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
964   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
965   *            @arg TIM_IT_TRIGGER: Trigger interrupt
966   * @retval None
967   */
968 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
969 
970 /**
971   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
972   * @param  __HANDLE__ TIM handle.
973   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
974   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
975 mode.
976   */
977 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
978 
979 /**
980   * @brief  Set the TIM Prescaler on runtime.
981   * @param  __HANDLE__ TIM handle.
982   * @param  __PRESC__ specifies the Prescaler new value.
983   * @retval None
984   */
985 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
986 
987 /**
988   * @brief  Set the TIM Counter Register value on runtime.
989   * @param  __HANDLE__ TIM handle.
990   * @param  __COUNTER__ specifies the Counter register new value.
991   * @retval None
992   */
993 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
994 
995 /**
996   * @brief  Get the TIM Counter Register value on runtime.
997   * @param  __HANDLE__ TIM handle.
998   * @retval 16-bit value of the timer counter register (TIMx_CNT)
999   */
1000 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
1001    ((__HANDLE__)->Instance->CNT)
1002 
1003 /**
1004   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1005   * @param  __HANDLE__ TIM handle.
1006   * @param  __AUTORELOAD__ specifies the Counter register new value.
1007   * @retval None
1008   */
1009 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1010                         do{                                                    \
1011                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
1012                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
1013                           } while(0)
1014 
1015 /**
1016   * @brief  Get the TIM Autoreload Register value on runtime.
1017   * @param  __HANDLE__ TIM handle.
1018   * @retval 16-bit value of the timer auto-reload register(TIMx_ARR)
1019   */
1020 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
1021    ((__HANDLE__)->Instance->ARR)
1022 
1023 /**
1024   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
1025   * @param  __HANDLE__ TIM handle.
1026   * @param  __CKD__ specifies the clock division value.
1027   *          This parameter can be one of the following value:
1028   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1029   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1030   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1031   * @retval None
1032   */
1033 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1034                         do{                                                   \
1035                               (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
1036                               (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
1037                               (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
1038                           } while(0)
1039 
1040 /**
1041   * @brief  Get the TIM Clock Division value on runtime.
1042   * @param  __HANDLE__ TIM handle.
1043   * @retval The clock division can be one of the following values:
1044   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1045   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1046   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1047   */
1048 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
1049    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1050 
1051 /**
1052   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
1053   * @param  __HANDLE__ TIM handle.
1054   * @param  __CHANNEL__ TIM Channels to be configured.
1055   *          This parameter can be one of the following values:
1056   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1057   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1058   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1059   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1060   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
1061   *          This parameter can be one of the following values:
1062   *            @arg TIM_ICPSC_DIV1: no prescaler
1063   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1064   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1065   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1066   * @retval None
1067   */
1068 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1069                         do{                                                    \
1070                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
1071                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1072                           } while(0)
1073 
1074 /**
1075   * @brief  Get the TIM Input Capture prescaler on runtime.
1076   * @param  __HANDLE__ TIM handle.
1077   * @param  __CHANNEL__ TIM Channels to be configured.
1078   *          This parameter can be one of the following values:
1079   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1080   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1081   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1082   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1083   * @retval The input capture prescaler can be one of the following values:
1084   *            @arg TIM_ICPSC_DIV1: no prescaler
1085   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1086   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1087   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1088   */
1089 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
1090   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1091    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1092    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1093    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1094 
1095 /**
1096   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1097   * @param  __HANDLE__ TIM handle.
1098   * @param  __CHANNEL__ TIM Channels to be configured.
1099   *          This parameter can be one of the following values:
1100   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1101   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1102   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1103   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1104   * @param  __COMPARE__ specifies the Capture Compare register new value.
1105   * @retval None
1106   */
1107 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1108 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1109  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1110  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1111  ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
1112 
1113 /**
1114   * @brief  Get the TIM Capture Compare Register value on runtime.
1115   * @param  __HANDLE__ TIM handle.
1116   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
1117   *          This parameter can be one of the following values:
1118   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
1119   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
1120   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
1121   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
1122   * @retval 16-bit value of the capture/compare register (TIMx_CCRy)
1123   */
1124 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1125 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1126  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1127  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1128  ((__HANDLE__)->Instance->CCR4))
1129 
1130 /**
1131   * @brief  Set the TIM Output compare preload.
1132   * @param  __HANDLE__ TIM handle.
1133   * @param  __CHANNEL__ TIM Channels to be configured.
1134   *          This parameter can be one of the following values:
1135   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1136   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1137   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1138   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1139   * @retval None
1140   */
1141 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
1142         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1143          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1144          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1145          ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
1146 
1147 /**
1148   * @brief  Reset the TIM Output compare preload.
1149   * @param  __HANDLE__ TIM handle.
1150   * @param  __CHANNEL__ TIM Channels to be configured.
1151   *          This parameter can be one of the following values:
1152   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1153   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1154   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1155   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1156   * @retval None
1157   */
1158 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
1159         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
1160          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
1161          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
1162          ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
1163 
1164 /**
1165   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1166   * @param  __HANDLE__ TIM handle.
1167   * @note  When the URS bit of the TIMx_CR1 register is set, only counter
1168   *        overflow/underflow generates an update interrupt or DMA request (if
1169   *        enabled)
1170   * @retval None
1171   */
1172 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1173     ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1174 
1175 /**
1176   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1177   * @param  __HANDLE__ TIM handle.
1178   * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
1179   *        following events generate an update interrupt or DMA request (if
1180   *        enabled):
1181   *           _ Counter overflow underflow
1182   *           _ Setting the UG bit
1183   *           _ Update generation through the slave mode controller
1184   * @retval None
1185   */
1186 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1187       ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1188 
1189 /**
1190   * @brief  Set the TIM Capture x input polarity on runtime.
1191   * @param  __HANDLE__ TIM handle.
1192   * @param  __CHANNEL__ TIM Channels to be configured.
1193   *          This parameter can be one of the following values:
1194   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1195   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1196   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1197   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1198   * @param  __POLARITY__ Polarity for TIx source
1199   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1200   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1201   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1202   * @retval None
1203   */
1204 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
1205         do{                                                                     \
1206           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
1207           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1208         }while(0)
1209 
1210 /**
1211   * @}
1212   */
1213 /* End of exported macros ----------------------------------------------------*/
1214 
1215 /* Private constants ---------------------------------------------------------*/
1216 /** @defgroup TIM_Private_Constants TIM Private Constants
1217   * @{
1218   */
1219 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1220    channels have been disabled */
1221 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1222 /**
1223   * @}
1224   */
1225 /* End of private constants --------------------------------------------------*/
1226 
1227 /* Private macros ------------------------------------------------------------*/
1228 /** @defgroup TIM_Private_Macros TIM Private Macros
1229   * @{
1230   */
1231 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
1232                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1233 
1234 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
1235                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
1236                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
1237                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
1238                                    ((__BASE__) == TIM_DMABASE_SR)    || \
1239                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
1240                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
1241                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
1242                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
1243                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
1244                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
1245                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
1246                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
1247                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
1248                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
1249                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
1250                                    ((__BASE__) == TIM_DMABASE_OR))
1251 
1252 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1253 
1254 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
1255                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
1256                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
1257                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
1258                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1259 
1260 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1261                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1262                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1263 
1264 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1265                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1266 
1267 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
1268                                             ((__STATE__) == TIM_OCFAST_ENABLE))
1269 
1270 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1271                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1272 
1273 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
1274                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
1275                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1276 
1277 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1278                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1279                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
1280 
1281 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1282                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1283                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1284                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
1285 
1286 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
1287                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
1288 
1289 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1290                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1291                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
1292 
1293 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1294 
1295 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
1296                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
1297                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
1298                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
1299                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
1300 
1301 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
1302                                             ((__CHANNEL__) == TIM_CHANNEL_2))
1303 
1304 #define IS_TIM_PERIOD(__PERIOD__)      ((__PERIOD__) <= 0xFFFFU)
1305 
1306 #define IS_TIM_PRESCALER(__PRESCALER__)      ((__PRESCALER__) <= 0xFFFFU)
1307 
1308 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1309                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1310                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
1311                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
1312                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
1313                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
1314                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
1315                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
1316                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
1317                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1318 
1319 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
1320                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1321                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
1322                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
1323                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1324 
1325 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1326                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1327                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1328                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1329 
1330 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
1331 
1332 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1333                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1334 
1335 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1336                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1337                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1338                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1339 
1340 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1341 
1342 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
1343                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1344                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1345                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
1346                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1347                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1348                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1349                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
1350 
1351 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1352                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1353 
1354 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
1355                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
1356                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
1357                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
1358                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
1359 
1360 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
1361                                    ((__MODE__) == TIM_OCMODE_PWM2))
1362 
1363 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
1364                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
1365                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
1366                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
1367                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
1368                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
1369 
1370 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1371                                                  ((__SELECTION__) == TIM_TS_ITR1) || \
1372                                                  ((__SELECTION__) == TIM_TS_ITR2) || \
1373                                                  ((__SELECTION__) == TIM_TS_ITR3) || \
1374                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1375                                                  ((__SELECTION__) == TIM_TS_TI1FP1) || \
1376                                                  ((__SELECTION__) == TIM_TS_TI2FP2) || \
1377                                                  ((__SELECTION__) == TIM_TS_ETRF))
1378 
1379 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1380                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
1381                                                                ((__SELECTION__) == TIM_TS_ITR2) || \
1382                                                                ((__SELECTION__) == TIM_TS_ITR3) || \
1383                                                                ((__SELECTION__) == TIM_TS_NONE))
1384 
1385 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
1386                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1387                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
1388                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
1389                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
1390 
1391 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1392                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1393                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1394                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1395 
1396 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1397 
1398 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1399                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1400 
1401 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1402                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1403                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1404                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1405                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1406                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1407                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1408                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1409                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1410                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1411                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1412                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1413                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1414                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1415                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1416                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1417                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1418                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1419 
1420 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
1421 
1422 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
1423 
1424 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1425 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1426  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1427  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1428  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1429 
1430 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1431 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1432  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1433  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1434  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1435 
1436 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1437 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1438  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1439  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1440  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1441 
1442 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1443 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1444  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1445  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1446  ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
1447 
1448 /**
1449   * @}
1450   */
1451 /* End of private macros -----------------------------------------------------*/
1452 
1453 /* Include TIM HAL Extended module */
1454 #include "stm32l0xx_hal_tim_ex.h"
1455 
1456 /* Exported functions --------------------------------------------------------*/
1457 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
1458   * @{
1459   */
1460 
1461 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
1462   *  @brief   Time Base functions
1463   * @{
1464   */
1465 /* Time Base functions ********************************************************/
1466 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1467 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1468 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1469 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1470 /* Blocking mode: Polling */
1471 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1472 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1473 /* Non-Blocking mode: Interrupt */
1474 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1475 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1476 /* Non-Blocking mode: DMA */
1477 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1478 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1479 /**
1480   * @}
1481   */
1482 
1483 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
1484   *  @brief   TIM Output Compare functions
1485   * @{
1486   */
1487 /* Timer Output Compare functions *********************************************/
1488 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1489 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1490 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1491 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1492 /* Blocking mode: Polling */
1493 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1494 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1495 /* Non-Blocking mode: Interrupt */
1496 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1497 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1498 /* Non-Blocking mode: DMA */
1499 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1500 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1501 /**
1502   * @}
1503   */
1504 
1505 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
1506   *  @brief   TIM PWM functions
1507   * @{
1508   */
1509 /* Timer PWM functions ********************************************************/
1510 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1511 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1512 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1513 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1514 /* Blocking mode: Polling */
1515 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1516 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1517 /* Non-Blocking mode: Interrupt */
1518 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1519 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1520 /* Non-Blocking mode: DMA */
1521 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1522 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1523 /**
1524   * @}
1525   */
1526 
1527 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1528   *  @brief   TIM Input Capture functions
1529   * @{
1530   */
1531 /* Timer Input Capture functions **********************************************/
1532 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1533 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1534 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1535 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1536 /* Blocking mode: Polling */
1537 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1538 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1539 /* Non-Blocking mode: Interrupt */
1540 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1541 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1542 /* Non-Blocking mode: DMA */
1543 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1544 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1545 /**
1546   * @}
1547   */
1548 
1549 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
1550   *  @brief   TIM One Pulse functions
1551   * @{
1552   */
1553 /* Timer One Pulse functions **************************************************/
1554 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1555 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1556 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1557 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1558 /* Blocking mode: Polling */
1559 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1560 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1561 /* Non-Blocking mode: Interrupt */
1562 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1563 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1564 /**
1565   * @}
1566   */
1567 
1568 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
1569   *  @brief   TIM Encoder functions
1570   * @{
1571   */
1572 /* Timer Encoder functions ****************************************************/
1573 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
1574 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1575 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1576 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1577 /* Blocking mode: Polling */
1578 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1579 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1580 /* Non-Blocking mode: Interrupt */
1581 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1582 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1583 /* Non-Blocking mode: DMA */
1584 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1585 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1586 /**
1587   * @}
1588   */
1589 
1590 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
1591   *  @brief   IRQ handler management
1592   * @{
1593   */
1594 /* Interrupt Handler functions  ***********************************************/
1595 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1596 /**
1597   * @}
1598   */
1599 
1600 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
1601   *  @brief   Peripheral Control functions
1602   * @{
1603   */
1604 /* Control functions  *********************************************************/
1605 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
1606 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
1607 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
1608 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
1609 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
1610 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
1611 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1612 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
1613 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
1614 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1615                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
1616 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1617 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1618                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
1619 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1620 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1621 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1622 /**
1623   * @}
1624   */
1625 
1626 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
1627   *  @brief   TIM Callbacks functions
1628   * @{
1629   */
1630 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1631 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1632 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
1633 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1634 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1635 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
1636 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1637 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
1638 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1639 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
1640 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1641 
1642 /* Callbacks Register/UnRegister functions  ***********************************/
1643 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1644 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
1645 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
1646 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1647 
1648 /**
1649   * @}
1650   */
1651 
1652 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
1653   *  @brief  Peripheral State functions
1654   * @{
1655   */
1656 /* Peripheral State functions  ************************************************/
1657 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1658 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1659 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1660 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1661 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1662 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1663 /**
1664   * @}
1665   */
1666 
1667 /**
1668   * @}
1669   */
1670 /* End of exported functions -------------------------------------------------*/
1671 
1672 /* Private functions----------------------------------------------------------*/
1673 /** @defgroup TIM_Private_Functions TIM Private Functions
1674 * @{
1675 */
1676 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1677 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
1678 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1679 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1680 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
1681 
1682 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1683 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
1684 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1685 
1686 /**
1687 * @}
1688 */
1689 /* End of private functions --------------------------------------------------*/
1690 
1691 /**
1692   * @}
1693   */
1694 
1695 /**
1696   * @}
1697   */
1698 
1699 #ifdef __cplusplus
1700 }
1701 #endif
1702 
1703 #endif /* STM32L0xx_HAL_TIM_H */
1704 
1705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1706