xref: /btstack/port/stm32-l073rz-nucleo-em9304/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h (revision e838079242074edcbcbb400962776e15fe6ca6cb)
1 /**
2   ******************************************************************************
3   * @file    stm32l0xx_hal_rcc.h
4   * @author  MCD Application Team
5   * @brief   Header file of RCC HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
10   * All rights reserved.</center></h2>
11   *
12   * This software component is licensed by ST under BSD 3-Clause license,
13   * the "License"; You may not use this file except in compliance with the
14   * License. You may obtain a copy of the License at:
15   *                        opensource.org/licenses/BSD-3-Clause
16   *
17   ******************************************************************************
18   */
19 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L0xx_HAL_RCC_H
22 #define __STM32L0xx_HAL_RCC_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l0xx_hal_def.h"
30 
31 /** @addtogroup STM32L0xx_HAL_Driver
32   * @{
33   */
34 
35 /** @addtogroup RCC
36   * @{
37   */
38 
39 /** @addtogroup RCC_Private_Constants
40   * @{
41   */
42 
43 /** @defgroup RCC_Timeout RCC Timeout
44   * @{
45   */
46 
47 /* Disable Backup domain write protection state change timeout */
48 #define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
49 /* LSE state change timeout */
50 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
51 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
52 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
53 #define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
54 #define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
55 #define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
56 #define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
57 #if defined(RCC_HSI48_SUPPORT)
58 #define HSI48_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1) */
59 #endif /* RCC_HSI48_SUPPORT */
60 /**
61   * @}
62   */
63 
64 
65 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
66   * @brief RCC registers bit address in the alias region
67   * @{
68   */
69 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
70 /* --- CR Register ---*/
71 /* Alias word address of HSION bit */
72 #define RCC_CR_OFFSET             (RCC_OFFSET + 0x00U)
73 /* --- CFGR Register ---*/
74 /* Alias word address of I2SSRC bit */
75 #define RCC_CFGR_OFFSET           (RCC_OFFSET + 0x08U)
76 /* --- CSR Register ---*/
77 #define RCC_CSR_OFFSET            (RCC_OFFSET + 0x74U)
78 
79 /* CR register byte 3 (Bits[23:16]) base address */
80 #define RCC_CR_BYTE2_ADDRESS      (0x40023802U)
81 
82 /* CIER register byte 0 (Bits[0:8]) base address */
83 #define CIER_BYTE0_ADDRESS        ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
84 /**
85   * @}
86   */
87 
88 
89 /* Defines used for Flags */
90 #define CR_REG_INDEX                     ((uint8_t)1)
91 #define CSR_REG_INDEX                    ((uint8_t)2)
92 #define CRRCR_REG_INDEX                  ((uint8_t)3)
93 
94 #define RCC_FLAG_MASK                    ((uint8_t)0x1F)
95 
96 /**
97   * @}
98   */
99 
100 /** @addtogroup RCC_Private_Macros
101   * @{
102   */
103 #if defined(RCC_HSI48_SUPPORT)
104 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                               || \
105                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE)   == RCC_OSCILLATORTYPE_HSE)   || \
106                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI)   == RCC_OSCILLATORTYPE_HSI)   || \
107                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
108                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI)   == RCC_OSCILLATORTYPE_LSI)   || \
109                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE)   == RCC_OSCILLATORTYPE_LSE)   || \
110                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI)   == RCC_OSCILLATORTYPE_MSI))
111 
112 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
113 #else
114 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
115                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
116                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
117                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
118                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
119                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
120 #endif /* RCC_HSI48_SUPPORT */
121 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
122                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
123 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
124                              ((__HSE__) == RCC_HSE_BYPASS))
125 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
126                              ((__LSE__) == RCC_LSE_BYPASS))
127 #if defined(RCC_CR_HSIOUTEN)
128 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF)  || ((__HSI__) == RCC_HSI_ON)     || \
129                              ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN)  || \
130                              ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_ON)) || ((__HSI__) == (RCC_HSI_OUTEN|RCC_HSI_DIV4)))
131 #else
132 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
133                              ((__HSI__) == RCC_HSI_DIV4))
134 #endif /* RCC_CR_HSIOUTEN */
135 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
136 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
137 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
138                                             ((__RANGE__) == RCC_MSIRANGE_1) || \
139                                             ((__RANGE__) == RCC_MSIRANGE_2) || \
140                                             ((__RANGE__) == RCC_MSIRANGE_3) || \
141                                             ((__RANGE__) == RCC_MSIRANGE_4) || \
142                                             ((__RANGE__) == RCC_MSIRANGE_5) || \
143                                             ((__RANGE__) == RCC_MSIRANGE_6))
144 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
145 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
146 
147 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
148                              ((__PLL__) == RCC_PLL_ON))
149 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
150                                  ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
151 
152 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3)  || ((__MUL__) == RCC_PLL_MUL4)  || \
153                                  ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL8)  || \
154                                  ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
155                                  ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
156                                  ((__MUL__) == RCC_PLL_MUL48))
157 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
158                                (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
159                                (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
160                                (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
161 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
162                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
163                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
164                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
165 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \
166                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
167                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
168                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
169 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
170                                ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
171                                ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
172                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
173                                ((__HCLK__) == RCC_SYSCLK_DIV512))
174 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
175                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
176                                ((__PCLK__) == RCC_HCLK_DIV16))
177 #if  defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \
178   || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
179 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2) || ((__MCO__) == RCC_MCO3))
180 #else
181 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2))
182 
183 #endif
184 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
185                                 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
186                                 ((__DIV__) == RCC_MCODIV_16))
187 #if defined(RCC_CFGR_MCOSEL_HSI48)
188 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
189                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
190                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
191                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
192                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
193 #else
194 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
195                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
196                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
197                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
198 #endif /* RCC_CFGR_MCOSEL_HSI48 */
199 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK)   || \
200                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)      || \
201                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)      || \
202                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
203                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
204                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
205                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
206 
207 /**
208   * @}
209   */
210 
211 /* Exported types ------------------------------------------------------------*/
212 
213 /** @defgroup RCC_Exported_Types RCC Exported Types
214   * @{
215   */
216 
217 /**
218   * @brief  RCC PLL configuration structure definition
219   */
220 typedef struct
221 {
222   uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
223                               This parameter can be a value of @ref RCC_PLL_Config */
224 
225   uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
226                               This parameter must be a value of @ref RCC_PLL_Clock_Source */
227 
228   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
229                               This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
230 
231   uint32_t PLLDIV;        /*!< PLLDIV: Division factor for PLL VCO input clock
232                               This parameter must be a value of @ref RCC_PLL_Division_Factor*/
233 } RCC_PLLInitTypeDef;
234 
235 /**
236   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
237   */
238 typedef struct
239 {
240   uint32_t OscillatorType;        /*!< The oscillators to be configured.
241                                        This parameter can be a value of @ref RCC_Oscillator_Type */
242 
243   uint32_t HSEState;              /*!< The new state of the HSE.
244                                        This parameter can be a value of @ref RCC_HSE_Config */
245 
246   uint32_t LSEState;              /*!< The new state of the LSE.
247                                        This parameter can be a value of @ref RCC_LSE_Config */
248 
249   uint32_t HSIState;              /*!< The new state of the HSI.
250                                        This parameter can be a value of @ref RCC_HSI_Config */
251 
252   uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
253                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
254 
255   uint32_t LSIState;              /*!< The new state of the LSI.
256                                        This parameter can be a value of @ref RCC_LSI_Config */
257 
258 #if defined(RCC_HSI48_SUPPORT)
259   uint32_t HSI48State;            /*!< The new state of the HSI48.
260                                        This parameter can be a value of @ref RCC_HSI48_Config */
261 
262 #endif /* RCC_HSI48_SUPPORT */
263   uint32_t MSIState;              /*!< The new state of the MSI.
264                                        This parameter can be a value of @ref RCC_MSI_Config */
265 
266   uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
267                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
268 
269   uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
270                                         This parameter can be a value of @ref RCC_MSI_Clock_Range */
271 
272   RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
273 
274 } RCC_OscInitTypeDef;
275 
276 /**
277   * @brief  RCC System, AHB and APB busses clock configuration structure definition
278   */
279 typedef struct
280 {
281   uint32_t ClockType;             /*!< The clock to be configured.
282                                        This parameter can be a value of @ref RCC_System_Clock_Type */
283 
284   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
285                                        This parameter can be a value of @ref RCC_System_Clock_Source */
286 
287   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
288                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
289 
290   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
291                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
292 
293   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
294                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
295 } RCC_ClkInitTypeDef;
296 
297 /**
298   * @}
299   */
300 
301 /* Exported constants --------------------------------------------------------*/
302 /** @defgroup RCC_Exported_Constants RCC Exported Constants
303   * @{
304   */
305 
306 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
307   * @{
308   */
309 
310 #define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI        /*!< HSI clock selected as PLL entry clock source */
311 #define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE        /*!< HSE clock selected as PLL entry clock source */
312 
313 /**
314   * @}
315   */
316 
317 /** @defgroup RCC_Oscillator_Type Oscillator Type
318   * @{
319   */
320 #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
321 #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
322 #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
323 #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
324 #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
325 #define RCC_OSCILLATORTYPE_MSI             ((uint32_t)0x00000010)
326 #if defined(RCC_HSI48_SUPPORT)
327 #define RCC_OSCILLATORTYPE_HSI48           ((uint32_t)0x00000020)
328 #endif /* RCC_HSI48_SUPPORT */
329 /**
330   * @}
331   */
332 
333 /** @defgroup RCC_HSE_Config HSE Config
334   * @{
335   */
336 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)                     /*!< HSE clock deactivation */
337 #define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
338 #define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
339 /**
340   * @}
341   */
342 
343 /** @defgroup RCC_LSE_Config LSE Config
344   * @{
345   */
346 #define RCC_LSE_OFF                      ((uint32_t)0x00000000)                       /*!< LSE clock deactivation */
347 #define RCC_LSE_ON                       RCC_CSR_LSEON                                /*!< LSE clock activation */
348 #define RCC_LSE_BYPASS                   ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON)) /*!< External clock source for LSE clock */
349 
350 /**
351   * @}
352   */
353 
354 /** @defgroup RCC_HSI_Config HSI Config
355   * @{
356   */
357 #define RCC_HSI_OFF                      ((uint32_t)0x00000000)           /*!< HSI clock deactivation */
358 #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
359 #define RCC_HSI_DIV4                     (RCC_CR_HSIDIVEN | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
360 #if defined(RCC_CR_HSIOUTEN)
361 #define RCC_HSI_OUTEN                    RCC_CR_HSIOUTEN                  /*!< HSI_OUTEN clock activation */
362                                                                           /* This value is to be used in combination with RCC_HSI_ON/RCC_HSI_DIV4 */
363 #endif /* RCC_CR_HSIOUTEN */
364 
365 #define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
366 
367 /**
368   * @}
369   */
370 
371 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
372   * @{
373   */
374 
375 #define RCC_MSIRANGE_0                   RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz  */
376 #define RCC_MSIRANGE_1                   RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
377 #define RCC_MSIRANGE_2                   RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
378 #define RCC_MSIRANGE_3                   RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
379 #define RCC_MSIRANGE_4                   RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz   */
380 #define RCC_MSIRANGE_5                   RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz   */
381 #define RCC_MSIRANGE_6                   RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz   */
382 
383 /**
384   * @}
385   */
386 
387 /** @defgroup RCC_LSI_Config LSI Config
388   * @{
389   */
390 #define RCC_LSI_OFF                      ((uint32_t)0x00000000)   /*!< LSI clock deactivation */
391 #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
392 
393 /**
394   * @}
395   */
396 
397 /** @defgroup RCC_MSI_Config MSI Config
398   * @{
399   */
400 #define RCC_MSI_OFF                      ((uint32_t)0x00000000)
401 #define RCC_MSI_ON                       ((uint32_t)0x00000001)
402 
403 #define RCC_MSICALIBRATION_DEFAULT       ((uint32_t)0x00000000U)   /* Default MSI calibration trimming value */
404 
405 /**
406   * @}
407   */
408 
409 #if defined(RCC_HSI48_SUPPORT)
410 /** @defgroup RCC_HSI48_Config HSI48 Config
411   * @{
412   */
413 #define RCC_HSI48_OFF               ((uint8_t)0x00)
414 #define RCC_HSI48_ON                ((uint8_t)0x01)
415 
416 /**
417   * @}
418   */
419 #endif /* RCC_HSI48_SUPPORT */
420 
421 /** @defgroup RCC_PLL_Config PLL Config
422   * @{
423   */
424 #define RCC_PLL_NONE                      ((uint32_t)0x00000000)  /*!< PLL is not configured */
425 #define RCC_PLL_OFF                       ((uint32_t)0x00000001)  /*!< PLL deactivation */
426 #define RCC_PLL_ON                        ((uint32_t)0x00000002)  /*!< PLL activation */
427 
428 /**
429   * @}
430   */
431 
432 /** @defgroup RCC_System_Clock_Type System Clock Type
433   * @{
434   */
435 #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001) /*!< SYSCLK to configure */
436 #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002) /*!< HCLK to configure */
437 #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004) /*!< PCLK1 to configure */
438 #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008) /*!< PCLK2 to configure */
439 
440 /**
441   * @}
442   */
443 
444 /** @defgroup RCC_System_Clock_Source System Clock Source
445   * @{
446   */
447 #define RCC_SYSCLKSOURCE_MSI             RCC_CFGR_SW_MSI /*!< MSI selected as system clock */
448 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
449 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
450 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
451 
452 /**
453   * @}
454   */
455 
456 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
457   * @{
458   */
459 #define RCC_SYSCLKSOURCE_STATUS_MSI      RCC_CFGR_SWS_MSI            /*!< MSI used as system clock */
460 #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
461 #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
462 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
463 
464 /**
465   * @}
466   */
467 
468 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
469   * @{
470   */
471 #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
472 #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
473 #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
474 #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
475 #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
476 #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
477 #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
478 #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
479 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
480 
481 /**
482   * @}
483   */
484 
485 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
486   * @{
487   */
488 #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
489 #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
490 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
491 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
492 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
493 
494 /**
495   * @}
496   */
497 
498 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
499   * @{
500   */
501 #define RCC_RTC_HSE_DIV_2               (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock  */
502 #define RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0       /*!< HSE is divided by 4 for RTC clock  */
503 #define RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1       /*!< HSE is divided by 8 for RTC clock  */
504 #define RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE         /*!< HSE is divided by 16 for RTC clock */
505 /**
506   * @}
507   */
508 
509 /** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
510   * @{
511   */
512 #define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)                 /*!< No clock */
513 #define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
514 #define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
515 #define RCC_RTCCLKSOURCE_HSE_DIVX        RCC_CSR_RTCSEL_HSE                         /*!< HSE oscillator clock divided by X used as RTC clock */
516 #define RCC_RTCCLKSOURCE_HSE_DIV2        (RCC_RTC_HSE_DIV_2  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 2 used as RTC clock */
517 #define RCC_RTCCLKSOURCE_HSE_DIV4        (RCC_RTC_HSE_DIV_4  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 4 used as RTC clock */
518 #define RCC_RTCCLKSOURCE_HSE_DIV8        (RCC_RTC_HSE_DIV_8  | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 8 used as RTC clock */
519 #define RCC_RTCCLKSOURCE_HSE_DIV16       (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE)  /*!< HSE oscillator clock divided by 16 used as RTC clock */
520 /**
521   * @}
522   */
523 
524 /** @defgroup RCC_PLL_Division_Factor PLL Division Factor
525   * @{
526   */
527 
528 #define RCC_PLL_DIV2                    RCC_CFGR_PLLDIV2
529 #define RCC_PLL_DIV3                    RCC_CFGR_PLLDIV3
530 #define RCC_PLL_DIV4                    RCC_CFGR_PLLDIV4
531 
532 /**
533   * @}
534   */
535 
536 /** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
537   * @{
538   */
539 
540 #define RCC_PLL_MUL3                    RCC_CFGR_PLLMUL3
541 #define RCC_PLL_MUL4                    RCC_CFGR_PLLMUL4
542 #define RCC_PLL_MUL6                    RCC_CFGR_PLLMUL6
543 #define RCC_PLL_MUL8                    RCC_CFGR_PLLMUL8
544 #define RCC_PLL_MUL12                   RCC_CFGR_PLLMUL12
545 #define RCC_PLL_MUL16                   RCC_CFGR_PLLMUL16
546 #define RCC_PLL_MUL24                   RCC_CFGR_PLLMUL24
547 #define RCC_PLL_MUL32                   RCC_CFGR_PLLMUL32
548 #define RCC_PLL_MUL48                   RCC_CFGR_PLLMUL48
549 
550 /**
551   * @}
552   */
553 
554 /** @defgroup RCC_MCO_Index MCO Index
555   * @{
556   */
557 #define RCC_MCO1                         ((uint32_t)0x00000000)
558 #define RCC_MCO2                         ((uint32_t)0x00000001)
559 #if  defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \
560   || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
561 #define RCC_MCO3                         ((uint32_t)0x00000002)
562 #endif
563 
564 /**
565   * @}
566   */
567 
568 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
569   * @{
570   */
571 #define RCC_MCODIV_1                    RCC_CFGR_MCO_PRE_1
572 #define RCC_MCODIV_2                    RCC_CFGR_MCO_PRE_2
573 #define RCC_MCODIV_4                    RCC_CFGR_MCO_PRE_4
574 #define RCC_MCODIV_8                    RCC_CFGR_MCO_PRE_8
575 #define RCC_MCODIV_16                   RCC_CFGR_MCO_PRE_16
576 
577 /**
578   * @}
579   */
580 
581 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
582   * @{
583   */
584 #define RCC_MCO1SOURCE_NOCLOCK           RCC_CFGR_MCO_NOCLOCK
585 #define RCC_MCO1SOURCE_SYSCLK            RCC_CFGR_MCO_SYSCLK
586 #define RCC_MCO1SOURCE_MSI               RCC_CFGR_MCO_MSI
587 #define RCC_MCO1SOURCE_HSI               RCC_CFGR_MCO_HSI
588 #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO_LSE
589 #define RCC_MCO1SOURCE_LSI               RCC_CFGR_MCO_LSI
590 #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO_HSE
591 #define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO_PLL
592 #if defined(RCC_CFGR_MCOSEL_HSI48)
593 #define RCC_MCO1SOURCE_HSI48             RCC_CFGR_MCO_HSI48
594 #endif /* RCC_CFGR_MCOSEL_HSI48 */
595 
596 /**
597   * @}
598   */
599 /** @defgroup RCC_Interrupt Interrupts
600   * @{
601   */
602 #define RCC_IT_LSIRDY                    RCC_CIFR_LSIRDYF   /*!< LSI Ready Interrupt flag */
603 #define RCC_IT_LSERDY                    RCC_CIFR_LSERDYF   /*!< LSE Ready Interrupt flag */
604 #define RCC_IT_HSIRDY                    RCC_CIFR_HSIRDYF   /*!< HSI Ready Interrupt flag */
605 #define RCC_IT_HSERDY                    RCC_CIFR_HSERDYF   /*!< HSE Ready Interrupt flag */
606 #define RCC_IT_PLLRDY                    RCC_CIFR_PLLRDYF   /*!< PLL Ready Interrupt flag */
607 #define RCC_IT_MSIRDY                    RCC_CIFR_MSIRDYF   /*!< MSI Ready Interrupt flag */
608 #define RCC_IT_LSECSS                    RCC_CIFR_CSSLSEF   /*!< LSE Clock Security System Interrupt flag */
609 #if defined(RCC_HSECSS_SUPPORT)
610 #define RCC_IT_CSS                       RCC_CIFR_CSSHSEF   /*!< Clock Security System Interrupt flag */
611 #endif /* RCC_HSECSS_SUPPORT */
612 #if defined(RCC_HSI48_SUPPORT)
613 #define RCC_IT_HSI48RDY                  RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
614 #endif /* RCC_HSI48_SUPPORT */
615 /**
616   * @}
617   */
618 
619 /** @defgroup RCC_Flag Flags
620   *        Elements values convention: XXXYYYYYb
621   *           - YYYYY  : Flag position in the register
622   *           - XXX  : Register index
623   *                 - 001: CR register
624   *                 - 010: CSR register
625   *                 - 011: CRRCR register (*)
626   * (*)   Applicable only for STM32L052xx, STM32L053xx, (...), STM32L073xx & STM32L082xx
627   * @{
628   */
629 /* Flags in the CR register */
630 #define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_Pos))     /*!< Internal High Speed clock ready flag */
631 #define RCC_FLAG_HSIDIV                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIDIVF_Pos))    /*!< HSI16 divider flag */
632 #define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_MSIRDY_Pos))     /*!< MSI clock ready flag */
633 #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_Pos))     /*!< External High Speed clock ready flag */
634 #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_Pos))     /*!< PLL clock ready flag */
635 /* Flags in the CSR register */
636 #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
637 #define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSERDY_Pos))   /*!< External Low Speed oscillator Ready */
638 #define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSECSSD_Pos))  /*!< CSS on LSE failure Detection */
639 #define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_Pos))  /*!< Options bytes loading reset flag */
640 #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
641 #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
642 #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
643 #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
644 #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
645 #define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
646 #if defined(RCC_CSR_FWRSTF)
647 #define RCC_FLAG_FWRST                   ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_FWRSTF_Pos))   /*!< RCC flag FW reset */
648 #endif /* RCC_CSR_FWRSTF */
649 /* Flags in the CRRCR register */
650 #if defined(RCC_HSI48_SUPPORT)
651 #define RCC_FLAG_HSI48RDY                ((uint8_t)((CRRCR_REG_INDEX << 5) | RCC_CRRCR_HSI48RDY_Pos))  /*!< HSI48 clock ready flag */
652 #endif /* RCC_HSI48_SUPPORT */
653 
654 /**
655   * @}
656   */
657 
658 /**
659   * @}
660   */
661 
662 /* Exported macro ------------------------------------------------------------*/
663 
664 /** @defgroup RCC_Exported_Macros RCC Exported Macros
665   * @{
666   */
667 
668 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
669   * @brief  Enable or disable the AHB peripheral clock.
670   * @note   After reset, the peripheral clock (used for registers read/write access)
671   *         is disabled and the application software has to enable this clock before
672   *         using it.
673   * @{
674   */
675 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
676                                         __IO uint32_t tmpreg; \
677                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
678                                         /* Delay after an RCC peripheral clock enabling */ \
679                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
680                                         UNUSED(tmpreg); \
681                                       } while(0)
682 
683 #define __HAL_RCC_MIF_CLK_ENABLE()   do { \
684                                         __IO uint32_t tmpreg; \
685                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
686                                         /* Delay after an RCC peripheral clock enabling */ \
687                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
688                                         UNUSED(tmpreg); \
689                                       } while(0)
690 
691 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
692                                         __IO uint32_t tmpreg; \
693                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
694                                         /* Delay after an RCC peripheral clock enabling */ \
695                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
696                                         UNUSED(tmpreg); \
697                                       } while(0)
698 
699 
700 #define __HAL_RCC_DMA1_CLK_DISABLE()          CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
701 #define __HAL_RCC_MIF_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
702 #define __HAL_RCC_CRC_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
703 
704 /**
705   * @}
706   */
707 
708 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
709   * @brief  Enable or disable the IOPORT peripheral clock.
710   * @note   After reset, the peripheral clock (used for registers read/write access)
711   *         is disabled and the application software has to enable this clock before
712   *         using it.
713   * @{
714   */
715 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
716                                         __IO uint32_t tmpreg; \
717                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
718                                         /* Delay after an RCC peripheral clock enabling */ \
719                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
720                                         UNUSED(tmpreg); \
721                                       } while(0)
722 
723 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
724                                         __IO uint32_t tmpreg; \
725                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
726                                         /* Delay after an RCC peripheral clock enabling */ \
727                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
728                                         UNUSED(tmpreg); \
729                                       } while(0)
730 
731 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
732                                         __IO uint32_t tmpreg; \
733                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
734                                         /* Delay after an RCC peripheral clock enabling */ \
735                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
736                                         UNUSED(tmpreg); \
737                                       } while(0)
738 
739 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
740                                         __IO uint32_t tmpreg; \
741                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
742                                         /* Delay after an RCC peripheral clock enabling */ \
743                                         tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
744                                         UNUSED(tmpreg); \
745                                       } while(0)
746 
747 
748 #define __HAL_RCC_GPIOA_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
749 #define __HAL_RCC_GPIOB_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
750 #define __HAL_RCC_GPIOC_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
751 #define __HAL_RCC_GPIOH_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
752 
753 /**
754   * @}
755   */
756 
757 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
758   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
759   * @note   After reset, the peripheral clock (used for registers read/write access)
760   *         is disabled and the application software has to enable this clock before
761   *         using it.
762   * @{
763   */
764 #define __HAL_RCC_WWDG_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
765 #define __HAL_RCC_PWR_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
766 
767 #define __HAL_RCC_WWDG_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
768 #define __HAL_RCC_PWR_CLK_DISABLE()     CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
769 /**
770   * @}
771   */
772 
773 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
774   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
775   * @note   After reset, the peripheral clock (used for registers read/write access)
776   *         is disabled and the application software has to enable this clock before
777   *         using it.
778   * @{
779   */
780 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
781 #define __HAL_RCC_DBGMCU_CLK_ENABLE()   SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
782 
783 #define __HAL_RCC_SYSCFG_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
784 #define __HAL_RCC_DBGMCU_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
785 /**
786   * @}
787   */
788 
789 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
790   * @brief  Check whether the AHB peripheral clock is enabled or not.
791   * @note   After reset, the peripheral clock (used for registers read/write access)
792   *         is disabled and the application software has to enable this clock before
793   *         using it.
794   * @{
795   */
796 
797 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
798 #define __HAL_RCC_MIF_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != 0U)
799 #define __HAL_RCC_CRC_IS_CLK_ENABLED()         (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)
800 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()       (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)
801 #define __HAL_RCC_MIF_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == 0U)
802 #define __HAL_RCC_CRC_IS_CLK_DISABLED()        (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)
803 
804 /**
805   * @}
806   */
807 
808 /** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
809   * @brief  Check whether the IOPORT peripheral clock is enabled or not.
810   * @note   After reset, the peripheral clock (used for registers read/write access)
811   *         is disabled and the application software has to enable this clock before
812   *         using it.
813   * @{
814   */
815 
816 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != 0U)
817 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != 0U)
818 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != 0U)
819 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != 0U)
820 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == 0U)
821 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == 0U)
822 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == 0U)
823 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == 0U)
824 
825 /**
826   * @}
827   */
828 
829 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
830   * @brief  Check whether the APB1 peripheral clock is enabled or not.
831   * @note   After reset, the peripheral clock (used for registers read/write access)
832   *         is disabled and the application software has to enable this clock before
833   *         using it.
834   * @{
835   */
836 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != 0U)
837 #define __HAL_RCC_PWR_IS_CLK_ENABLED()         (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U)
838 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == 0U)
839 #define __HAL_RCC_PWR_IS_CLK_DISABLED()        (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U)
840 
841 /**
842   * @}
843   */
844 
845 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
846   * @brief  Check whether the APB2 peripheral clock is enabled or not.
847   * @note   After reset, the peripheral clock (used for registers read/write access)
848   *         is disabled and the application software has to enable this clock before
849   *         using it.
850   * @{
851   */
852 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
853 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED()        (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != 0U)
854 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
855 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED()       (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == 0U)
856 
857 /**
858   * @}
859   */
860 
861  /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
862   * @brief  Force or release AHB peripheral reset.
863   * @{
864   */
865 #define __HAL_RCC_AHB_FORCE_RESET()     (RCC->AHBRSTR = 0xFFFFFFFFU)
866 #define __HAL_RCC_DMA1_FORCE_RESET()    SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
867 #define __HAL_RCC_MIF_FORCE_RESET()     SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
868 #define __HAL_RCC_CRC_FORCE_RESET()     SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
869 
870 #define __HAL_RCC_AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00000000U)
871 #define __HAL_RCC_CRC_RELEASE_RESET()     CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
872 #define __HAL_RCC_DMA1_RELEASE_RESET()    CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
873 #define __HAL_RCC_MIF_RELEASE_RESET()     CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
874 /**
875   * @}
876   */
877 
878 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
879   * @brief  Force or release IOPORT peripheral reset.
880   * @{
881   */
882 #define __HAL_RCC_IOP_FORCE_RESET()     (RCC->IOPRSTR = 0xFFFFFFFFU)
883 #define __HAL_RCC_GPIOA_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
884 #define __HAL_RCC_GPIOB_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
885 #define __HAL_RCC_GPIOC_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
886 #define __HAL_RCC_GPIOH_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
887 
888 #define __HAL_RCC_IOP_RELEASE_RESET()   (RCC->IOPRSTR = 0x00000000U)
889 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
890 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
891 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
892 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
893 
894 /**
895   * @}
896   */
897 
898 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
899   * @brief  Force or release APB1 peripheral reset.
900   * @{
901   */
902 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
903 #define __HAL_RCC_WWDG_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
904 #define __HAL_RCC_PWR_FORCE_RESET()      SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
905 
906 #define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00000000U)
907 #define __HAL_RCC_WWDG_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
908 #define __HAL_RCC_PWR_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
909 
910 /**
911   * @}
912   */
913 
914 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
915   * @brief  Force or release APB2 peripheral reset.
916   * @{
917   */
918 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
919 #define __HAL_RCC_DBGMCU_FORCE_RESET()   SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
920 #define __HAL_RCC_SYSCFG_FORCE_RESET()   SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
921 
922 #define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00000000U)
923 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
924 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
925 /**
926   * @}
927   */
928 
929 
930 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
931   * @brief  Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
932   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
933   *         power consumption.
934   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
935   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
936   * @{
937   */
938 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
939 #define __HAL_RCC_MIF_CLK_SLEEP_ENABLE()      SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
940 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
941 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
942 
943 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
944 #define __HAL_RCC_MIF_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
945 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
946 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
947 /**
948   * @}
949   */
950 
951 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
952   * @brief  Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
953   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
954   *         power consumption.
955   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
956   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
957   * @{
958   */
959 
960 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
961 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
962 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
963 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
964 
965 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
966 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
967 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
968 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
969 /**
970   * @}
971   */
972 
973 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
974   * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
975   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
976   *         power consumption.
977   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
978   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
979   * @{
980   */
981 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
982 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
983 
984 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR,  (RCC_APB1SMENR_WWDGSMEN))
985 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR,  (RCC_APB1SMENR_PWRSMEN))
986 
987 /**
988   * @}
989   */
990 
991 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
992   * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
993   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
994   *         power consumption.
995   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
996   * @note   By default, all peripheral activated clocks remain enabled during SLEEP mode.
997   * @{
998   */
999 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
1000 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
1001 
1002 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,   (RCC_APB2SMENR_SYSCFGSMEN))
1003 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,   (RCC_APB2SMENR_DBGMCUSMEN))
1004 
1005 /**
1006   * @}
1007   */
1008 
1009 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
1010   * @brief  Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
1011   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1012   *         power consumption.
1013   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1014   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1015   * @{
1016   */
1017 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != 0U)
1018 #define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != 0U)
1019 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != 0U)
1020 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != 0U)
1021 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == 0U)
1022 #define __HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == 0U)
1023 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == 0U)
1024 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()  (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == 0U)
1025 
1026 /**
1027   * @}
1028   */
1029 
1030 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
1031   * @brief  Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
1032   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1033   *         power consumption.
1034   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1035   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1036   * @{
1037   */
1038 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != 0U)
1039 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != 0U)
1040 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != 0U)
1041 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != 0U)
1042 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == 0U)
1043 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == 0U)
1044 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == 0U)
1045 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == 0U)
1046 
1047 /**
1048   * @}
1049   */
1050 
1051 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
1052   * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
1053   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1054   *         power consumption.
1055   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1056   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1057   * @{
1058   */
1059 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != 0U)
1060 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != 0U)
1061 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == 0U)
1062 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()    (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == 0U)
1063 
1064 /**
1065   * @}
1066   */
1067 
1068 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
1069   * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
1070   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1071   *         power consumption.
1072   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1073   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1074   * @{
1075   */
1076 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
1077 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != 0U)
1078 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
1079 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED()   (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == 0U)
1080 
1081 /**
1082   * @}
1083   */
1084 /** @defgroup RCC_HSI_Configuration HSI Configuration
1085   * @{
1086   */
1087 
1088 /** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
1089   * @note     After enabling the HSI, the application software should wait on
1090   *           HSIRDY flag to be set indicating that HSI clock is stable and can
1091   *           be used to clock the PLL and/or system clock.
1092   * @note     HSI can not be stopped if it is used directly or through the PLL
1093   *           as system clock. In this case, you have to select another source
1094   *           of the system clock then stop the HSI.
1095   * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
1096   * @param    __STATE__ specifies the new state of the HSI.
1097   *           This parameter can be one of the following values:
1098   *            @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator
1099   *            @arg @ref RCC_HSI_ON turn ON the HSI oscillator
1100   *            @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
1101   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
1102   *         clock cycles.
1103   */
1104 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
1105                   MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
1106 
1107 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
1108   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
1109   *         It is used (enabled by hardware) as system clock source after startup
1110   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
1111   *         of the HSE used directly or indirectly as system clock (if the Clock
1112   *         Security System CSS is enabled).
1113   * @note   HSI can not be stopped if it is used as system clock source. In this case,
1114   *         you have to select another source of the system clock then stop the HSI.
1115   * @note   After enabling the HSI, the application software should wait on HSIRDY
1116   *         flag to be set indicating that HSI clock is stable and can be used as
1117   *         system clock source.
1118   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
1119   *         clock cycles.
1120   */
1121 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
1122 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
1123 
1124 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
1125   * @note   The calibration is used to compensate for the variations in voltage
1126   *         and temperature that influence the frequency of the internal HSI RC.
1127   * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
1128   *         (default is RCC_HSICALIBRATION_DEFAULT).
1129   *         This parameter must be a number between 0 and 0x1F.
1130   */
1131 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
1132           (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos))
1133 
1134 /**
1135   * @}
1136   */
1137 
1138 /** @defgroup RCC_LSI_Configuration  LSI Configuration
1139   * @{
1140   */
1141 
1142 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
1143   * @note   After enabling the LSI, the application software should wait on
1144   *         LSIRDY flag to be set indicating that LSI clock is stable and can
1145   *         be used to clock the IWDG and/or the RTC.
1146   */
1147 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
1148 
1149 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
1150   * @note   LSI can not be disabled if the IWDG is running.
1151   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
1152   *         clock cycles.
1153   */
1154 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
1155 
1156 /**
1157   * @}
1158   */
1159 
1160 /** @defgroup RCC_HSE_Configuration HSE Configuration
1161   * @{
1162   */
1163 
1164 /**
1165   * @brief  Macro to configure the External High Speed oscillator (HSE).
1166   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
1167   *         supported by this macro. User should request a transition to HSE Off
1168   *         first and then HSE On or HSE Bypass.
1169   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
1170   *         software should wait on HSERDY flag to be set indicating that HSE clock
1171   *         is stable and can be used to clock the PLL and/or system clock.
1172   * @note   HSE state can not be changed if it is used directly or through the
1173   *         PLL as system clock. In this case, you have to select another source
1174   *         of the system clock then change the HSE state (ex. disable it).
1175   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
1176   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
1177   *         was previously enabled you have to enable it again after calling this
1178   *         function.
1179   * @param  __STATE__ specifies the new state of the HSE.
1180   *          This parameter can be one of the following values:
1181   *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
1182   *                              6 HSE oscillator clock cycles.
1183   *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
1184   *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
1185   */
1186 #define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
1187                     do{                                                     \
1188                       __IO uint32_t tmpreg;                                 \
1189                       if ((__STATE__) == RCC_HSE_ON)                        \
1190                       {                                                     \
1191                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
1192                       }                                                     \
1193                       else if ((__STATE__) == RCC_HSE_BYPASS)               \
1194                       {                                                     \
1195                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
1196                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
1197                       }                                                     \
1198                       else                                                  \
1199                       {                                                     \
1200                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
1201                         /* Delay after an RCC peripheral clock */           \
1202                         tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON);           \
1203                         UNUSED(tmpreg);                                     \
1204                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
1205                       }                                                     \
1206                     }while(0)
1207 
1208 /**
1209   * @}
1210   */
1211 
1212 /** @defgroup RCC_LSE_Configuration LSE Configuration
1213   * @{
1214   */
1215 
1216 /**
1217   * @brief  Macro to configure the External Low Speed oscillator (LSE).
1218   * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
1219   * @note   As the LSE is in the Backup domain and write access is denied to
1220   *         this domain after reset, you have to enable write access using
1221   *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
1222   *         (to be done once after reset).
1223   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
1224   *         software should wait on LSERDY flag to be set indicating that LSE clock
1225   *         is stable and can be used to clock the RTC.
1226   * @param  __STATE__ specifies the new state of the LSE.
1227   *         This parameter can be one of the following values:
1228   *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
1229   *                              6 LSE oscillator clock cycles.
1230   *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
1231   *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
1232   */
1233 #define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
1234                     do{                                                     \
1235                       if ((__STATE__) == RCC_LSE_ON)                        \
1236                       {                                                     \
1237                         SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
1238                       }                                                     \
1239                       else if ((__STATE__) == RCC_LSE_OFF)                  \
1240                       {                                                     \
1241                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
1242                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
1243                       }                                                     \
1244                       else if ((__STATE__) == RCC_LSE_BYPASS)               \
1245                       {                                                     \
1246                         SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);                  \
1247                         SET_BIT(RCC->CSR, RCC_CSR_LSEON);                   \
1248                       }                                                     \
1249                       else                                                  \
1250                       {                                                     \
1251                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
1252                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
1253                       }                                                     \
1254                     }while(0)
1255 
1256 /**
1257   * @}
1258   */
1259 
1260 /** @defgroup RCC_MSI_Configuration  MSI Configuration
1261   * @{
1262   */
1263 
1264 /** @brief  Macro to enable Internal Multi Speed oscillator (MSI).
1265   * @note   After enabling the MSI, the application software should wait on MSIRDY
1266   *         flag to be set indicating that MSI clock is stable and can be used as
1267   *         system clock source.
1268   */
1269 #define __HAL_RCC_MSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_MSION)
1270 
1271 /** @brief  Macro to disable the Internal Multi Speed oscillator (MSI).
1272   * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
1273   *         It is used (enabled by hardware) as system clock source after startup
1274   *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
1275   *         of the HSE used directly or indirectly as system clock (if the Clock
1276   *         Security System CSS is enabled).
1277   * @note   MSI can not be stopped if it is used as system clock source. In this case,
1278   *         you have to select another source of the system clock then stop the MSI.
1279   * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
1280   *         clock cycles.
1281   */
1282 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
1283 
1284 /** @brief  Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
1285   * @note   The calibration is used to compensate for the variations in voltage
1286   *         and temperature that influence the frequency of the internal MSI RC.
1287   *         Refer to the Application Note AN3300 for more details on how to
1288   *         calibrate the MSI.
1289   * @param  _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
1290   *         (default is RCC_MSICALIBRATION_DEFAULT).
1291   *         This parameter must be a number between 0 and 0xFF.
1292   */
1293 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
1294           (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos))
1295 
1296 /* @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
1297   * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is
1298   *           around 2.097 MHz. The MSI clock does not change after wake-up from
1299   *           STOP mode.
1300   * @note    The MSI clock range can be modified on the fly.
1301   * @param  _MSIRANGEVALUE_ specifies the MSI Clock range.
1302   *   This parameter must be one of the following values:
1303   *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
1304   *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
1305   *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
1306   *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
1307   *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
1308   *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
1309   *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
1310   */
1311 #define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
1312           RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
1313 
1314 /** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
1315   * @retval MSI clock range.
1316   *         This parameter must be one of the following values:
1317   *     @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
1318   *     @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
1319   *     @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
1320   *     @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
1321   *     @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
1322   *     @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
1323   *     @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
1324   */
1325 #define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
1326 
1327 /**
1328   * @}
1329   */
1330 
1331 /** @defgroup RCC_PLL_Configuration PLL Configuration
1332   * @{
1333   */
1334 
1335 /** @brief Macro to enable the main PLL.
1336   * @note   After enabling the main PLL, the application software should wait on
1337   *         PLLRDY flag to be set indicating that PLL clock is stable and can
1338   *         be used as system clock source.
1339   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1340   */
1341 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
1342 
1343 /** @brief Macro to disable the main PLL.
1344   * @note   The main PLL can not be disabled if it is used as system clock source
1345   */
1346 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
1347 
1348 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
1349   * @note   This function must be used only when the main PLL is disabled.
1350   *
1351   * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
1352   *          This parameter can be one of the following values:
1353   *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
1354   *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
1355   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
1356   *          This parameter can be one of the following values:
1357   *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
1358   *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
1359   *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
1360   *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
1361   *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
1362   *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
1363   *             @arg @ref RCC_PLL_MUL24  PLLVCO = PLL clock entry x 24
1364   *             @arg @ref RCC_PLL_MUL32  PLLVCO = PLL clock entry x 32
1365   *             @arg @ref RCC_PLL_MUL48  PLLVCO = PLL clock entry x 48
1366   * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in Range 1,
1367   *       48 MHz when the product is in Range 2and 24 MHz when the product is in Range 3.
1368   *
1369   * @param  __PLLDIV__ specifies the division factor for PLL VCO input clock
1370   *          This parameter can be one of the following values:
1371   *             @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
1372   *             @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
1373   *             @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
1374   *
1375   */
1376 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
1377           MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
1378 
1379 /** @brief  Get oscillator clock selected as PLL input clock
1380   * @retval The clock source used for PLL entry. The returned value can be one
1381   *         of the following:
1382   *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
1383   *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
1384   */
1385 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
1386 
1387 /**
1388   * @}
1389   */
1390 
1391 /** @defgroup RCC_Get_Clock_source Get Clock source
1392   * @{
1393   */
1394 
1395 /**
1396   * @brief  Macro to configure the system clock source.
1397   * @param  __SYSCLKSOURCE__ specifies the system clock source.
1398   *          This parameter can be one of the following values:
1399   *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
1400   *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
1401   *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
1402   *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
1403   */
1404 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
1405                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
1406 
1407 /** @brief  Macro to get the clock source used as system clock.
1408   * @retval The clock source used as system clock. The returned value can be one
1409   *         of the following:
1410   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
1411   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
1412   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
1413   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
1414   */
1415 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
1416 
1417 /**
1418   * @}
1419   */
1420 
1421 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
1422   * @{
1423   */
1424 
1425 /** @brief  Macro to configure the MCO clock.
1426   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
1427   *          This parameter can be one of the following values:
1428   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
1429   *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
1430   *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
1431   *            @arg @ref RCC_MCO1SOURCE_MSI          MSI oscillator clock selected as MCO clock
1432   *            @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
1433   *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock selected as MCO clock
1434   *            @arg @ref RCC_MCO1SOURCE_LSI          LSI clock selected as MCO clock
1435   *            @arg @ref RCC_MCO1SOURCE_LSE          LSE clock selected as MCO clock
1436   @if STM32L052xx
1437   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1438   @elseif STM32L053xx
1439   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1440   @elseif STM32L062xx
1441   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1442   @elseif STM32L063xx
1443   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1444   @elseif STM32L072xx
1445   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1446   @elseif STM32L073xx
1447   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1448   @elseif STM32L082xx
1449   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1450   @elseif STM32L083xx
1451   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 clock selected as MCO clock
1452   @endif
1453   * @param  __MCODIV__ specifies the MCO clock prescaler.
1454   *          This parameter can be one of the following values:
1455   *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
1456   *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
1457   *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
1458   *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
1459   *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
1460   */
1461 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1462                  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1463 
1464 /**
1465   * @}
1466   */
1467 
1468   /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
1469   * @{
1470   */
1471 
1472 /** @brief Macro to configure the RTC clock (RTCCLK).
1473   * @note   As the RTC clock configuration bits are in the Backup domain and write
1474   *         access is denied to this domain after reset, you have to enable write
1475   *         access using the Power Backup Access macro before to configure
1476   *         the RTC clock source (to be done once after reset).
1477   * @note   Once the RTC clock is configured it cannot be changed unless the
1478   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
1479   *         a Power On Reset (POR).
1480   * @note   RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
1481   *
1482   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
1483   *          This parameter can be one of the following values:
1484   *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1485   *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1486   *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1487   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
1488   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
1489   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
1490   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
1491   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
1492   *         work in STOP and STANDBY modes, and can be used as wakeup source.
1493   *         However, when the HSE clock is used as RTC clock source, the RTC
1494   *         cannot be used in STOP and STANDBY modes.
1495   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
1496   *         RTC clock source).
1497   */
1498 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
1499             if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)          \
1500             {                                                                             \
1501               MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
1502             }                                                                             \
1503           } while (0)
1504 
1505 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
1506                                       __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
1507                                       RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
1508                                     } while (0)
1509 
1510 /** @brief Macro to get the RTC clock source.
1511   * @retval The clock source can be one of the following values:
1512   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1513   *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1514   *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1515   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
1516   */
1517 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
1518 
1519 /**
1520   * @brief   Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
1521   *
1522   * @retval Returned value can be one of the following values:
1523   *         @arg @ref RCC_RTC_HSE_DIV_2  HSE divided by 2 selected as RTC clock
1524   *         @arg @ref RCC_RTC_HSE_DIV_4  HSE divided by 4 selected as RTC clock
1525   *         @arg @ref RCC_RTC_HSE_DIV_8  HSE divided by 8 selected as RTC clock
1526   *         @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
1527   *
1528   */
1529 #define  __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
1530 
1531 /** @brief Macro to enable the the RTC clock.
1532   * @note   These macros must be used only after the RTC clock source was selected.
1533   */
1534 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
1535 
1536 /** @brief Macro to disable the the RTC clock.
1537   * @note  These macros must be used only after the RTC clock source was selected.
1538   */
1539 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
1540 
1541 /** @brief  Macro to force the Backup domain reset.
1542   * @note   This function resets the RTC peripheral (including the backup registers)
1543   *         and the RTC clock source selection in RCC_CSR register.
1544   * @note   The BKPSRAM is not affected by this reset.
1545   */
1546 #define __HAL_RCC_BACKUPRESET_FORCE()  SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
1547 
1548 /** @brief  Macros to release the Backup domain reset.
1549   */
1550 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
1551 
1552 /**
1553   * @}
1554   */
1555 
1556 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1557   * @brief macros to manage the specified RCC Flags and interrupts.
1558   * @{
1559   */
1560 
1561 /** @brief Enable RCC interrupt.
1562   * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
1563   *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
1564   *         automatically generated. The NMI will be executed indefinitely, and
1565   *         since NMI has higher priority than any other IRQ (and main program)
1566   *         the application will be stacked in the NMI ISR unless the CSS interrupt
1567   *         pending bit is cleared.
1568   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1569   *          This parameter can be any combination of the following values:
1570   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1571   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
1572   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1573   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
1574   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1575   *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1576   *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt
1577   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
1578   */
1579 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
1580 
1581 /** @brief Disable RCC interrupt.
1582   * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
1583   *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
1584   *         automatically generated. The NMI will be executed indefinitely, and
1585   *         since NMI has higher priority than any other IRQ (and main program)
1586   *         the application will be stacked in the NMI ISR unless the CSS interrupt
1587   *         pending bit is cleared.
1588   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1589   *          This parameter can be any combination of the following values:
1590   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1591   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
1592   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1593   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
1594   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1595   *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1596   *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt
1597   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
1598   */
1599 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
1600 
1601 /** @brief Clear the RCC's interrupt pending bits.
1602   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
1603   *          This parameter can be any combination of the following values:
1604   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1605   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1606   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1607   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1608   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1609   *            @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1610   *            @arg @ref RCC_IT_LSECSS LSE CSS interrupt
1611   *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
1612   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
1613   */
1614 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
1615 
1616 /** @brief  Check the RCC's interrupt has occurred or not.
1617   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
1618   *         This parameter can be one of the following values:
1619   *     @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1620   *     @arg @ref RCC_IT_LSERDY LSE ready interrupt
1621   *     @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1622   *     @arg @ref RCC_IT_HSERDY HSE ready interrupt
1623   *     @arg @ref RCC_IT_PLLRDY PLL ready interrupt
1624   *     @arg @ref RCC_IT_MSIRDY MSI ready interrupt
1625   *     @arg @ref RCC_IT_LSECSS LSE CSS interrupt
1626   *     @arg @ref RCC_IT_CSS Clock Security System interrupt
1627   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1628   */
1629 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
1630 
1631 
1632 /** @brief Set RMVF bit to clear the reset flags.
1633   *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1634   *         RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1635   */
1636 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1637 
1638 /** @brief  Check RCC flag is set or not.
1639   * @param  __FLAG__ specifies the flag to check.
1640   *         This parameter can be one of the following values:
1641   *     @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
1642   *     @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready (not available on all devices)
1643   *     @arg @ref RCC_FLAG_HSIDIV HSI16 divider flag
1644   *     @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
1645   *     @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
1646   *     @arg @ref RCC_FLAG_PLLRDY PLL clock ready
1647   *     @arg @ref RCC_FLAG_LSECSS LSE oscillator clock CSS detected
1648   *     @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
1649   *     @arg @ref RCC_FLAG_FWRST Firewall reset
1650   *     @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
1651   *     @arg @ref RCC_FLAG_OBLRST Option Byte Loader (OBL) reset
1652   *     @arg @ref RCC_FLAG_PINRST Pin reset
1653   *     @arg @ref RCC_FLAG_PORRST POR/PDR reset
1654   *     @arg @ref RCC_FLAG_SFTRST Software reset
1655   *     @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
1656   *     @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
1657   *     @arg @ref RCC_FLAG_LPWRRST Low Power reset
1658   * @retval The new state of __FLAG__ (TRUE or FALSE).
1659   */
1660 #if defined(RCC_HSI48_SUPPORT)
1661 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
1662 #else
1663 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
1664 #endif /* RCC_HSI48_SUPPORT */
1665 
1666 /**
1667   * @}
1668   */
1669 
1670 /**
1671   * @}
1672   */
1673 
1674 /* Include RCC HAL Extension module */
1675 #include "stm32l0xx_hal_rcc_ex.h"
1676 
1677 /* Exported functions --------------------------------------------------------*/
1678 /** @addtogroup RCC_Exported_Functions
1679   * @{
1680   */
1681 
1682 /** @addtogroup RCC_Exported_Functions_Group1
1683   * @{
1684   */
1685 
1686 /* Initialization and de-initialization functions  ******************************/
1687 HAL_StatusTypeDef HAL_RCC_DeInit(void);
1688 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1689 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
1690 
1691 /**
1692   * @}
1693   */
1694 
1695 /** @addtogroup RCC_Exported_Functions_Group2
1696   * @{
1697   */
1698 
1699 /* Peripheral Control functions  ************************************************/
1700 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1701 #if defined(RCC_HSECSS_SUPPORT)
1702 void              HAL_RCC_EnableCSS(void);
1703 /* CSS NMI IRQ handler */
1704 void              HAL_RCC_NMI_IRQHandler(void);
1705 /* User Callbacks in non blocking mode (IT mode) */
1706 void              HAL_RCC_CSSCallback(void);
1707 #endif /* RCC_HSECSS_SUPPORT */
1708 uint32_t          HAL_RCC_GetSysClockFreq(void);
1709 uint32_t          HAL_RCC_GetHCLKFreq(void);
1710 uint32_t          HAL_RCC_GetPCLK1Freq(void);
1711 uint32_t          HAL_RCC_GetPCLK2Freq(void);
1712 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1713 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
1714 
1715 /**
1716   * @}
1717   */
1718 
1719 /**
1720   * @}
1721   */
1722 
1723 /**
1724   * @}
1725   */
1726 
1727 /**
1728   * @}
1729   */
1730 
1731 #ifdef __cplusplus
1732 }
1733 #endif
1734 
1735 #endif /* __STM32L0xx_HAL_RCC_H */
1736 
1737 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1738 
1739