1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f4xx_ll_tim.h"
23 #include "stm32f4xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
36
37 /** @addtogroup TIM_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup TIM_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53
54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
66
67 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
68 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
69
70 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
71 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
72
73 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
74 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
75
76 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
77 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
78 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
79
80 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
81 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
82 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
83 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
84
85 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
101
102 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
103 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
104 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
105
106 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
107 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
108 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
109
110 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
111 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
112
113 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
114 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
115
116 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
117 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
118
119 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
120 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
121 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
122 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
123
124 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
125 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
126
127 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
128 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
129
130 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
131 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
132 /**
133 * @}
134 */
135
136
137 /* Private function prototypes -----------------------------------------------*/
138 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
139 * @{
140 */
141 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
145 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
149 /**
150 * @}
151 */
152
153 /* Exported functions --------------------------------------------------------*/
154 /** @addtogroup TIM_LL_Exported_Functions
155 * @{
156 */
157
158 /** @addtogroup TIM_LL_EF_Init
159 * @{
160 */
161
162 /**
163 * @brief Set TIMx registers to their reset values.
164 * @param TIMx Timer instance
165 * @retval An ErrorStatus enumeration value:
166 * - SUCCESS: TIMx registers are de-initialized
167 * - ERROR: invalid TIMx instance
168 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)169 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
170 {
171 ErrorStatus result = SUCCESS;
172
173 /* Check the parameters */
174 assert_param(IS_TIM_INSTANCE(TIMx));
175
176 if (TIMx == TIM1)
177 {
178 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
179 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
180 }
181 #if defined(TIM2)
182 else if (TIMx == TIM2)
183 {
184 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
185 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
186 }
187 #endif
188 #if defined(TIM3)
189 else if (TIMx == TIM3)
190 {
191 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
192 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
193 }
194 #endif
195 #if defined(TIM4)
196 else if (TIMx == TIM4)
197 {
198 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
199 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
200 }
201 #endif
202 #if defined(TIM5)
203 else if (TIMx == TIM5)
204 {
205 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
206 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
207 }
208 #endif
209 #if defined(TIM6)
210 else if (TIMx == TIM6)
211 {
212 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
213 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
214 }
215 #endif
216 #if defined (TIM7)
217 else if (TIMx == TIM7)
218 {
219 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
220 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
221 }
222 #endif
223 #if defined(TIM8)
224 else if (TIMx == TIM8)
225 {
226 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
227 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
228 }
229 #endif
230 #if defined(TIM9)
231 else if (TIMx == TIM9)
232 {
233 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
234 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
235 }
236 #endif
237 #if defined(TIM10)
238 else if (TIMx == TIM10)
239 {
240 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
241 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
242 }
243 #endif
244 #if defined(TIM11)
245 else if (TIMx == TIM11)
246 {
247 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
248 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
249 }
250 #endif
251 #if defined(TIM12)
252 else if (TIMx == TIM12)
253 {
254 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
255 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
256 }
257 #endif
258 #if defined(TIM13)
259 else if (TIMx == TIM13)
260 {
261 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
262 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
263 }
264 #endif
265 #if defined(TIM14)
266 else if (TIMx == TIM14)
267 {
268 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
269 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
270 }
271 #endif
272 else
273 {
274 result = ERROR;
275 }
276
277 return result;
278 }
279
280 /**
281 * @brief Set the fields of the time base unit configuration data structure
282 * to their default values.
283 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
284 * @retval None
285 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)286 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
287 {
288 /* Set the default configuration */
289 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
290 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
291 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
292 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
293 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
294 }
295
296 /**
297 * @brief Configure the TIMx time base unit.
298 * @param TIMx Timer Instance
299 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
300 * @retval An ErrorStatus enumeration value:
301 * - SUCCESS: TIMx registers are de-initialized
302 * - ERROR: not applicable
303 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)304 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
305 {
306 uint32_t tmpcr1;
307
308 /* Check the parameters */
309 assert_param(IS_TIM_INSTANCE(TIMx));
310 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
311 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
312
313 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
314
315 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
316 {
317 /* Select the Counter Mode */
318 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
319 }
320
321 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
322 {
323 /* Set the clock division */
324 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
325 }
326
327 /* Write to TIMx CR1 */
328 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
329
330 /* Set the Autoreload value */
331 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
332
333 /* Set the Prescaler value */
334 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
335
336 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
337 {
338 /* Set the Repetition Counter value */
339 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
340 }
341
342 /* Generate an update event to reload the Prescaler
343 and the repetition counter value (if applicable) immediately */
344 LL_TIM_GenerateEvent_UPDATE(TIMx);
345
346 return SUCCESS;
347 }
348
349 /**
350 * @brief Set the fields of the TIMx output channel configuration data
351 * structure to their default values.
352 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
353 * @retval None
354 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)355 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
356 {
357 /* Set the default configuration */
358 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
359 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
360 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
361 TIM_OC_InitStruct->CompareValue = 0x00000000U;
362 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
363 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
364 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
365 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
366 }
367
368 /**
369 * @brief Configure the TIMx output channel.
370 * @param TIMx Timer Instance
371 * @param Channel This parameter can be one of the following values:
372 * @arg @ref LL_TIM_CHANNEL_CH1
373 * @arg @ref LL_TIM_CHANNEL_CH2
374 * @arg @ref LL_TIM_CHANNEL_CH3
375 * @arg @ref LL_TIM_CHANNEL_CH4
376 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
377 * @retval An ErrorStatus enumeration value:
378 * - SUCCESS: TIMx output channel is initialized
379 * - ERROR: TIMx output channel is not initialized
380 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)381 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
382 {
383 ErrorStatus result = ERROR;
384
385 switch (Channel)
386 {
387 case LL_TIM_CHANNEL_CH1:
388 result = OC1Config(TIMx, TIM_OC_InitStruct);
389 break;
390 case LL_TIM_CHANNEL_CH2:
391 result = OC2Config(TIMx, TIM_OC_InitStruct);
392 break;
393 case LL_TIM_CHANNEL_CH3:
394 result = OC3Config(TIMx, TIM_OC_InitStruct);
395 break;
396 case LL_TIM_CHANNEL_CH4:
397 result = OC4Config(TIMx, TIM_OC_InitStruct);
398 break;
399 default:
400 break;
401 }
402
403 return result;
404 }
405
406 /**
407 * @brief Set the fields of the TIMx input channel configuration data
408 * structure to their default values.
409 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
410 * @retval None
411 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)412 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
413 {
414 /* Set the default configuration */
415 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
416 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
417 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
418 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
419 }
420
421 /**
422 * @brief Configure the TIMx input channel.
423 * @param TIMx Timer Instance
424 * @param Channel This parameter can be one of the following values:
425 * @arg @ref LL_TIM_CHANNEL_CH1
426 * @arg @ref LL_TIM_CHANNEL_CH2
427 * @arg @ref LL_TIM_CHANNEL_CH3
428 * @arg @ref LL_TIM_CHANNEL_CH4
429 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
430 * @retval An ErrorStatus enumeration value:
431 * - SUCCESS: TIMx output channel is initialized
432 * - ERROR: TIMx output channel is not initialized
433 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)434 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
435 {
436 ErrorStatus result = ERROR;
437
438 switch (Channel)
439 {
440 case LL_TIM_CHANNEL_CH1:
441 result = IC1Config(TIMx, TIM_IC_InitStruct);
442 break;
443 case LL_TIM_CHANNEL_CH2:
444 result = IC2Config(TIMx, TIM_IC_InitStruct);
445 break;
446 case LL_TIM_CHANNEL_CH3:
447 result = IC3Config(TIMx, TIM_IC_InitStruct);
448 break;
449 case LL_TIM_CHANNEL_CH4:
450 result = IC4Config(TIMx, TIM_IC_InitStruct);
451 break;
452 default:
453 break;
454 }
455
456 return result;
457 }
458
459 /**
460 * @brief Fills each TIM_EncoderInitStruct field with its default value
461 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
462 * @retval None
463 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)464 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
465 {
466 /* Set the default configuration */
467 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
468 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
469 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
470 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
471 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
472 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
473 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
474 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
475 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
476 }
477
478 /**
479 * @brief Configure the encoder interface of the timer instance.
480 * @param TIMx Timer Instance
481 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
482 * @retval An ErrorStatus enumeration value:
483 * - SUCCESS: TIMx registers are de-initialized
484 * - ERROR: not applicable
485 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)486 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
487 {
488 uint32_t tmpccmr1;
489 uint32_t tmpccer;
490
491 /* Check the parameters */
492 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
493 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
494 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
495 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
496 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
497 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
498 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
499 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
500 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
501 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
502
503 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
504 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
505
506 /* Get the TIMx CCMR1 register value */
507 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
508
509 /* Get the TIMx CCER register value */
510 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
511
512 /* Configure TI1 */
513 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
514 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
515 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
516 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
517
518 /* Configure TI2 */
519 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
520 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
521 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
522 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
523
524 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
525 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
526 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
527 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
528 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
529
530 /* Set encoder mode */
531 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
532
533 /* Write to TIMx CCMR1 */
534 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
535
536 /* Write to TIMx CCER */
537 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
538
539 return SUCCESS;
540 }
541
542 /**
543 * @brief Set the fields of the TIMx Hall sensor interface configuration data
544 * structure to their default values.
545 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
546 * @retval None
547 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)548 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
549 {
550 /* Set the default configuration */
551 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
552 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
553 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
554 TIM_HallSensorInitStruct->CommutationDelay = 0U;
555 }
556
557 /**
558 * @brief Configure the Hall sensor interface of the timer instance.
559 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
560 * to the TI1 input channel
561 * @note TIMx slave mode controller is configured in reset mode.
562 Selected internal trigger is TI1F_ED.
563 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
564 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
565 * between 2 changes on the inputs. It gives information about motor speed.
566 * @note Channel 2 is configured in output PWM 2 mode.
567 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
568 * @note OC2REF is selected as trigger output on TRGO.
569 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
570 * when TIMx operates in Hall sensor interface mode.
571 * @param TIMx Timer Instance
572 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
573 * @retval An ErrorStatus enumeration value:
574 * - SUCCESS: TIMx registers are de-initialized
575 * - ERROR: not applicable
576 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)577 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
578 {
579 uint32_t tmpcr2;
580 uint32_t tmpccmr1;
581 uint32_t tmpccer;
582 uint32_t tmpsmcr;
583
584 /* Check the parameters */
585 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
586 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
587 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
588 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
589
590 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
591 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
592
593 /* Get the TIMx CR2 register value */
594 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
595
596 /* Get the TIMx CCMR1 register value */
597 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
598
599 /* Get the TIMx CCER register value */
600 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
601
602 /* Get the TIMx SMCR register value */
603 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
604
605 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
606 tmpcr2 |= TIM_CR2_TI1S;
607
608 /* OC2REF signal is used as trigger output (TRGO) */
609 tmpcr2 |= LL_TIM_TRGO_OC2REF;
610
611 /* Configure the slave mode controller */
612 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
613 tmpsmcr |= LL_TIM_TS_TI1F_ED;
614 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
615
616 /* Configure input channel 1 */
617 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
618 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
619 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
620 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
621
622 /* Configure input channel 2 */
623 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
624 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
625
626 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
627 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
628 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
629 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
630
631 /* Write to TIMx CR2 */
632 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
633
634 /* Write to TIMx SMCR */
635 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
636
637 /* Write to TIMx CCMR1 */
638 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
639
640 /* Write to TIMx CCER */
641 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
642
643 /* Write to TIMx CCR2 */
644 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
645
646 return SUCCESS;
647 }
648
649 /**
650 * @brief Set the fields of the Break and Dead Time configuration data structure
651 * to their default values.
652 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
653 * @retval None
654 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)655 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
656 {
657 /* Set the default configuration */
658 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
659 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
660 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
661 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
662 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
663 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
664 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
665 }
666
667 /**
668 * @brief Configure the Break and Dead Time feature of the timer instance.
669 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
670 * depending on the LOCK configuration, it can be necessary to configure all of
671 * them during the first write access to the TIMx_BDTR register.
672 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
673 * a timer instance provides a break input.
674 * @param TIMx Timer Instance
675 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
676 * @retval An ErrorStatus enumeration value:
677 * - SUCCESS: Break and Dead Time is initialized
678 * - ERROR: not applicable
679 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)680 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
681 {
682 uint32_t tmpbdtr = 0;
683
684 /* Check the parameters */
685 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
686 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
687 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
688 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
689 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
690 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
691 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
692
693 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
694 the OSSI State, the dead time value and the Automatic Output Enable Bit */
695
696 /* Set the BDTR bits */
697 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
698 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
699 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
700 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
701 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
702 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
703 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
704 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
705
706 /* Set TIMx_BDTR */
707 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
708
709 return SUCCESS;
710 }
711 /**
712 * @}
713 */
714
715 /**
716 * @}
717 */
718
719 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
720 * @brief Private functions
721 * @{
722 */
723 /**
724 * @brief Configure the TIMx output channel 1.
725 * @param TIMx Timer Instance
726 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
727 * @retval An ErrorStatus enumeration value:
728 * - SUCCESS: TIMx registers are de-initialized
729 * - ERROR: not applicable
730 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)731 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
732 {
733 uint32_t tmpccmr1;
734 uint32_t tmpccer;
735 uint32_t tmpcr2;
736
737 /* Check the parameters */
738 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
739 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
740 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
741 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
742 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
743 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
744
745 /* Disable the Channel 1: Reset the CC1E Bit */
746 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
747
748 /* Get the TIMx CCER register value */
749 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
750
751 /* Get the TIMx CR2 register value */
752 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
753
754 /* Get the TIMx CCMR1 register value */
755 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
756
757 /* Reset Capture/Compare selection Bits */
758 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
759
760 /* Set the Output Compare Mode */
761 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
762
763 /* Set the Output Compare Polarity */
764 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
765
766 /* Set the Output State */
767 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
768
769 if (IS_TIM_BREAK_INSTANCE(TIMx))
770 {
771 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
772 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
773
774 /* Set the complementary output Polarity */
775 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
776
777 /* Set the complementary output State */
778 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
779
780 /* Set the Output Idle state */
781 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
782
783 /* Set the complementary output Idle state */
784 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
785 }
786
787 /* Write to TIMx CR2 */
788 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
789
790 /* Write to TIMx CCMR1 */
791 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
792
793 /* Set the Capture Compare Register value */
794 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
795
796 /* Write to TIMx CCER */
797 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
798
799 return SUCCESS;
800 }
801
802 /**
803 * @brief Configure the TIMx output channel 2.
804 * @param TIMx Timer Instance
805 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
806 * @retval An ErrorStatus enumeration value:
807 * - SUCCESS: TIMx registers are de-initialized
808 * - ERROR: not applicable
809 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)810 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
811 {
812 uint32_t tmpccmr1;
813 uint32_t tmpccer;
814 uint32_t tmpcr2;
815
816 /* Check the parameters */
817 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
818 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
819 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
820 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
821 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
822 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
823
824 /* Disable the Channel 2: Reset the CC2E Bit */
825 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
826
827 /* Get the TIMx CCER register value */
828 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
829
830 /* Get the TIMx CR2 register value */
831 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
832
833 /* Get the TIMx CCMR1 register value */
834 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
835
836 /* Reset Capture/Compare selection Bits */
837 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
838
839 /* Select the Output Compare Mode */
840 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
841
842 /* Set the Output Compare Polarity */
843 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
844
845 /* Set the Output State */
846 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
847
848 if (IS_TIM_BREAK_INSTANCE(TIMx))
849 {
850 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
851 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
852
853 /* Set the complementary output Polarity */
854 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
855
856 /* Set the complementary output State */
857 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
858
859 /* Set the Output Idle state */
860 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
861
862 /* Set the complementary output Idle state */
863 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
864 }
865
866 /* Write to TIMx CR2 */
867 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
868
869 /* Write to TIMx CCMR1 */
870 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
871
872 /* Set the Capture Compare Register value */
873 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
874
875 /* Write to TIMx CCER */
876 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
877
878 return SUCCESS;
879 }
880
881 /**
882 * @brief Configure the TIMx output channel 3.
883 * @param TIMx Timer Instance
884 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
885 * @retval An ErrorStatus enumeration value:
886 * - SUCCESS: TIMx registers are de-initialized
887 * - ERROR: not applicable
888 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)889 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
890 {
891 uint32_t tmpccmr2;
892 uint32_t tmpccer;
893 uint32_t tmpcr2;
894
895 /* Check the parameters */
896 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
897 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
898 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
899 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
900 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
901 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
902
903 /* Disable the Channel 3: Reset the CC3E Bit */
904 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
905
906 /* Get the TIMx CCER register value */
907 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
908
909 /* Get the TIMx CR2 register value */
910 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
911
912 /* Get the TIMx CCMR2 register value */
913 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
914
915 /* Reset Capture/Compare selection Bits */
916 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
917
918 /* Select the Output Compare Mode */
919 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
920
921 /* Set the Output Compare Polarity */
922 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
923
924 /* Set the Output State */
925 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
926
927 if (IS_TIM_BREAK_INSTANCE(TIMx))
928 {
929 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
930 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
931
932 /* Set the complementary output Polarity */
933 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
934
935 /* Set the complementary output State */
936 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
937
938 /* Set the Output Idle state */
939 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
940
941 /* Set the complementary output Idle state */
942 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
943 }
944
945 /* Write to TIMx CR2 */
946 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
947
948 /* Write to TIMx CCMR2 */
949 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
950
951 /* Set the Capture Compare Register value */
952 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
953
954 /* Write to TIMx CCER */
955 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
956
957 return SUCCESS;
958 }
959
960 /**
961 * @brief Configure the TIMx output channel 4.
962 * @param TIMx Timer Instance
963 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
964 * @retval An ErrorStatus enumeration value:
965 * - SUCCESS: TIMx registers are de-initialized
966 * - ERROR: not applicable
967 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)968 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
969 {
970 uint32_t tmpccmr2;
971 uint32_t tmpccer;
972 uint32_t tmpcr2;
973
974 /* Check the parameters */
975 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
976 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
977 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
978 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
979 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
980 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
981
982 /* Disable the Channel 4: Reset the CC4E Bit */
983 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
984
985 /* Get the TIMx CCER register value */
986 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
987
988 /* Get the TIMx CR2 register value */
989 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
990
991 /* Get the TIMx CCMR2 register value */
992 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
993
994 /* Reset Capture/Compare selection Bits */
995 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
996
997 /* Select the Output Compare Mode */
998 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
999
1000 /* Set the Output Compare Polarity */
1001 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1002
1003 /* Set the Output State */
1004 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1005
1006 if (IS_TIM_BREAK_INSTANCE(TIMx))
1007 {
1008 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1009 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1010
1011 /* Set the Output Idle state */
1012 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1013 }
1014
1015 /* Write to TIMx CR2 */
1016 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1017
1018 /* Write to TIMx CCMR2 */
1019 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1020
1021 /* Set the Capture Compare Register value */
1022 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1023
1024 /* Write to TIMx CCER */
1025 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1026
1027 return SUCCESS;
1028 }
1029
1030
1031 /**
1032 * @brief Configure the TIMx input channel 1.
1033 * @param TIMx Timer Instance
1034 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1035 * @retval An ErrorStatus enumeration value:
1036 * - SUCCESS: TIMx registers are de-initialized
1037 * - ERROR: not applicable
1038 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1039 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1040 {
1041 /* Check the parameters */
1042 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1043 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1044 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1045 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1046 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1047
1048 /* Disable the Channel 1: Reset the CC1E Bit */
1049 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1050
1051 /* Select the Input and set the filter and the prescaler value */
1052 MODIFY_REG(TIMx->CCMR1,
1053 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1054 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1055
1056 /* Select the Polarity and set the CC1E Bit */
1057 MODIFY_REG(TIMx->CCER,
1058 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1059 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1060
1061 return SUCCESS;
1062 }
1063
1064 /**
1065 * @brief Configure the TIMx input channel 2.
1066 * @param TIMx Timer Instance
1067 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1068 * @retval An ErrorStatus enumeration value:
1069 * - SUCCESS: TIMx registers are de-initialized
1070 * - ERROR: not applicable
1071 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1072 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1073 {
1074 /* Check the parameters */
1075 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1076 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1077 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1078 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1079 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1080
1081 /* Disable the Channel 2: Reset the CC2E Bit */
1082 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1083
1084 /* Select the Input and set the filter and the prescaler value */
1085 MODIFY_REG(TIMx->CCMR1,
1086 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1087 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1088
1089 /* Select the Polarity and set the CC2E Bit */
1090 MODIFY_REG(TIMx->CCER,
1091 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1092 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1093
1094 return SUCCESS;
1095 }
1096
1097 /**
1098 * @brief Configure the TIMx input channel 3.
1099 * @param TIMx Timer Instance
1100 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1101 * @retval An ErrorStatus enumeration value:
1102 * - SUCCESS: TIMx registers are de-initialized
1103 * - ERROR: not applicable
1104 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1105 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1106 {
1107 /* Check the parameters */
1108 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1109 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1110 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1111 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1112 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1113
1114 /* Disable the Channel 3: Reset the CC3E Bit */
1115 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1116
1117 /* Select the Input and set the filter and the prescaler value */
1118 MODIFY_REG(TIMx->CCMR2,
1119 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1120 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1121
1122 /* Select the Polarity and set the CC3E Bit */
1123 MODIFY_REG(TIMx->CCER,
1124 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1125 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1126
1127 return SUCCESS;
1128 }
1129
1130 /**
1131 * @brief Configure the TIMx input channel 4.
1132 * @param TIMx Timer Instance
1133 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1134 * @retval An ErrorStatus enumeration value:
1135 * - SUCCESS: TIMx registers are de-initialized
1136 * - ERROR: not applicable
1137 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1138 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1139 {
1140 /* Check the parameters */
1141 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1142 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1143 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1144 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1145 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1146
1147 /* Disable the Channel 4: Reset the CC4E Bit */
1148 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1149
1150 /* Select the Input and set the filter and the prescaler value */
1151 MODIFY_REG(TIMx->CCMR2,
1152 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1153 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1154
1155 /* Select the Polarity and set the CC2E Bit */
1156 MODIFY_REG(TIMx->CCER,
1157 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1158 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1159
1160 return SUCCESS;
1161 }
1162
1163
1164 /**
1165 * @}
1166 */
1167
1168 /**
1169 * @}
1170 */
1171
1172 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
1173
1174 /**
1175 * @}
1176 */
1177
1178 #endif /* USE_FULL_LL_DRIVER */
1179
1180 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1181