1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fsmc.c
4 * @author MCD Application Team
5 * @brief FSMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### FSMC peripheral features #####
16 ==============================================================================
17 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
18 (+) The NOR/PSRAM memory controller
19 (+) The NAND/PC Card memory controller
20
21 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
22 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
23 (+) to translate AHB transactions into the appropriate external device protocol.
24 (+) to meet the access time requirements of the external memory devices.
25
26 [..] All external memories share the addresses, data and control signals with the controller.
27 Each external device is accessed by means of a unique Chip Select. The FSMC performs
28 only one access at a time to an external device.
29 The main features of the FSMC controller are the following:
30 (+) Interface with static-memory mapped devices including:
31 (++) Static random access memory (SRAM).
32 (++) Read-only memory (ROM).
33 (++) NOR Flash memory/OneNAND Flash memory.
34 (++) PSRAM (4 memory banks).
35 (++) 16-bit PC Card compatible devices.
36 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
37 data.
38 (+) Independent Chip Select control for each memory bank.
39 (+) Independent configuration for each memory bank.
40
41 @endverbatim
42 ******************************************************************************
43 * @attention
44 *
45 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
46 * All rights reserved.</center></h2>
47 *
48 * This software component is licensed by ST under BSD 3-Clause license,
49 * the "License"; You may not use this file except in compliance with the
50 * License. You may obtain a copy of the License at:
51 * opensource.org/licenses/BSD-3-Clause
52 *
53 ******************************************************************************
54 */
55
56 /* Includes ------------------------------------------------------------------*/
57 #include "stm32f4xx_hal.h"
58
59 /** @addtogroup STM32F4xx_HAL_Driver
60 * @{
61 */
62
63 /** @defgroup FSMC_LL FSMC Low Layer
64 * @brief FSMC driver modules
65 * @{
66 */
67
68 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
69 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
70 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73 /* Private macro -------------------------------------------------------------*/
74 /* Private variables ---------------------------------------------------------*/
75 /* Private function prototypes -----------------------------------------------*/
76 /* Private functions ---------------------------------------------------------*/
77 /** @addtogroup FSMC_LL_Private_Functions
78 * @{
79 */
80
81 /** @addtogroup FSMC_LL_NORSRAM
82 * @brief NORSRAM Controller functions
83 *
84 @verbatim
85 ==============================================================================
86 ##### How to use NORSRAM device driver #####
87 ==============================================================================
88
89 [..]
90 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
91 to run the NORSRAM external devices.
92
93 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
94 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
95 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
96 (+) FSMC NORSRAM bank extended timing configuration using the function
97 FSMC_NORSRAM_Extended_Timing_Init()
98 (+) FSMC NORSRAM bank enable/disable write operation using the functions
99 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
100
101 @endverbatim
102 * @{
103 */
104
105 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
106 * @brief Initialization and Configuration functions
107 *
108 @verbatim
109 ==============================================================================
110 ##### Initialization and de_initialization functions #####
111 ==============================================================================
112 [..]
113 This section provides functions allowing to:
114 (+) Initialize and configure the FSMC NORSRAM interface
115 (+) De-initialize the FSMC NORSRAM interface
116 (+) Configure the FSMC clock and associated GPIOs
117
118 @endverbatim
119 * @{
120 */
121
122 /**
123 * @brief Initialize the FSMC_NORSRAM device according to the specified
124 * control parameters in the FSMC_NORSRAM_InitTypeDef
125 * @param Device Pointer to NORSRAM device instance
126 * @param Init Pointer to NORSRAM Initialization structure
127 * @retval HAL status
128 */
FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_InitTypeDef * Init)129 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
130 {
131 uint32_t tmpr = 0U;
132
133 /* Check the parameters */
134 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
135 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
136 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
137 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
138 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
139 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
140 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
141 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
142 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
143 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
144 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
145 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
146 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
147 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
148 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
149 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
150 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
151 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
152 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
153 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
154 #endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
155
156 /* Get the BTCR register value */
157 tmpr = Device->BTCR[Init->NSBank];
158
159 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
160 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
161 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
162 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
163 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
164 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
165 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
166 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW));
167 /* Set NORSRAM device control parameters */
168 tmpr |= (uint32_t)(Init->DataAddressMux |\
169 Init->MemoryType |\
170 Init->MemoryDataWidth |\
171 Init->BurstAccessMode |\
172 Init->WaitSignalPolarity |\
173 Init->WrapMode |\
174 Init->WaitSignalActive |\
175 Init->WriteOperation |\
176 Init->WaitSignal |\
177 Init->ExtendedMode |\
178 Init->AsynchronousWait |\
179 Init->PageSize |\
180 Init->WriteBurst
181 );
182 #else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
183 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
184 WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */
185 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
186 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
187 FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \
188 FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \
189 FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \
190 FSMC_BCR1_WFDIS));
191 /* Set NORSRAM device control parameters */
192 tmpr |= (uint32_t)(Init->DataAddressMux |\
193 Init->MemoryType |\
194 Init->MemoryDataWidth |\
195 Init->BurstAccessMode |\
196 Init->WaitSignalPolarity |\
197 Init->WaitSignalActive |\
198 Init->WriteOperation |\
199 Init->WaitSignal |\
200 Init->ExtendedMode |\
201 Init->AsynchronousWait |\
202 Init->WriteBurst |\
203 Init->ContinuousClock |\
204 Init->PageSize |\
205 Init->WriteFifo);
206 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
207
208 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
209 {
210 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
211 }
212
213 Device->BTCR[Init->NSBank] = tmpr;
214
215 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
216 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
217 if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
218 {
219 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
220 }
221
222 if(Init->NSBank != FSMC_NORSRAM_BANK1)
223 {
224 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
225 }
226 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
227
228 return HAL_OK;
229 }
230
231 /**
232 * @brief DeInitialize the FSMC_NORSRAM peripheral
233 * @param Device Pointer to NORSRAM device instance
234 * @param ExDevice Pointer to NORSRAM extended mode device instance
235 * @param Bank NORSRAM bank number
236 * @retval HAL status
237 */
FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)238 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
239 {
240 /* Check the parameters */
241 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
242 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
243 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
244
245 /* Disable the FSMC_NORSRAM device */
246 __FSMC_NORSRAM_DISABLE(Device, Bank);
247
248 /* De-initialize the FSMC_NORSRAM device */
249 /* FSMC_NORSRAM_BANK1 */
250 if(Bank == FSMC_NORSRAM_BANK1)
251 {
252 Device->BTCR[Bank] = 0x000030DBU;
253 }
254 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
255 else
256 {
257 Device->BTCR[Bank] = 0x000030D2U;
258 }
259
260 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
261 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
262
263 return HAL_OK;
264 }
265
266
267 /**
268 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
269 * parameters in the FSMC_NORSRAM_TimingTypeDef
270 * @param Device Pointer to NORSRAM device instance
271 * @param Timing Pointer to NORSRAM Timing structure
272 * @param Bank NORSRAM bank number
273 * @retval HAL status
274 */
FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)275 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
276 {
277 uint32_t tmpr = 0U;
278
279 /* Check the parameters */
280 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
281 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
282 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
283 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
284 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
285 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
286 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
287 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
288 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
289
290 /* Get the BTCR register value */
291 tmpr = Device->BTCR[Bank + 1U];
292
293 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
294 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
295 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
296 FSMC_BTR1_ACCMOD));
297
298 /* Set FSMC_NORSRAM device timing parameters */
299 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
300 ((Timing->AddressHoldTime) << 4U) |\
301 ((Timing->DataSetupTime) << 8U) |\
302 ((Timing->BusTurnAroundDuration) << 16U) |\
303 (((Timing->CLKDivision)-1U) << 20U) |\
304 (((Timing->DataLatency)-2U) << 24U) |\
305 (Timing->AccessMode));
306
307 Device->BTCR[Bank + 1] = tmpr;
308
309 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
310 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
311 if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
312 {
313 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
314 tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
315 Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
316 }
317 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
318
319 return HAL_OK;
320 }
321
322 /**
323 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
324 * parameters in the FSMC_NORSRAM_TimingTypeDef
325 * @param Device Pointer to NORSRAM device instance
326 * @param Timing Pointer to NORSRAM Timing structure
327 * @param Bank NORSRAM bank number
328 * @retval HAL status
329 */
FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)330 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
331 {
332 uint32_t tmpr = 0U;
333
334 /* Check the parameters */
335 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
336
337 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
338 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
339 {
340 /* Check the parameters */
341 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
342 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
343 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
344 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
345 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
346 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
347 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
348
349 /* Get the BWTR register value */
350 tmpr = Device->BWTR[Bank];
351
352 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
353 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
354 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
355
356 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
357 ((Timing->AddressHoldTime) << 4U) |\
358 ((Timing->DataSetupTime) << 8U) |\
359 ((Timing->BusTurnAroundDuration) << 16U) |\
360 (Timing->AccessMode));
361
362 Device->BWTR[Bank] = tmpr;
363 }
364 else
365 {
366 Device->BWTR[Bank] = 0x0FFFFFFFU;
367 }
368
369 return HAL_OK;
370 }
371 /**
372 * @}
373 */
374
375 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
376 * @brief management functions
377 *
378 @verbatim
379 ==============================================================================
380 ##### FSMC_NORSRAM Control functions #####
381 ==============================================================================
382 [..]
383 This subsection provides a set of functions allowing to control dynamically
384 the FSMC NORSRAM interface.
385
386 @endverbatim
387 * @{
388 */
389
390 /**
391 * @brief Enables dynamically FSMC_NORSRAM write operation.
392 * @param Device Pointer to NORSRAM device instance
393 * @param Bank NORSRAM bank number
394 * @retval HAL status
395 */
FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)396 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
397 {
398 /* Check the parameters */
399 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
400 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
401
402 /* Enable write operation */
403 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
404
405 return HAL_OK;
406 }
407
408 /**
409 * @brief Disables dynamically FSMC_NORSRAM write operation.
410 * @param Device Pointer to NORSRAM device instance
411 * @param Bank NORSRAM bank number
412 * @retval HAL status
413 */
FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)414 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
415 {
416 /* Check the parameters */
417 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
418 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
419
420 /* Disable write operation */
421 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
422
423 return HAL_OK;
424 }
425 /**
426 * @}
427 */
428
429 /**
430 * @}
431 */
432
433 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
434 /** @addtogroup FSMC_LL_NAND
435 * @brief NAND Controller functions
436 *
437 @verbatim
438 ==============================================================================
439 ##### How to use NAND device driver #####
440 ==============================================================================
441 [..]
442 This driver contains a set of APIs to interface with the FSMC NAND banks in order
443 to run the NAND external devices.
444
445 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
446 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
447 (+) FSMC NAND bank common space timing configuration using the function
448 FSMC_NAND_CommonSpace_Timing_Init()
449 (+) FSMC NAND bank attribute space timing configuration using the function
450 FSMC_NAND_AttributeSpace_Timing_Init()
451 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
452 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
453 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
454
455 @endverbatim
456 * @{
457 */
458
459 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
460 * @brief Initialization and Configuration functions
461 *
462 @verbatim
463 ==============================================================================
464 ##### Initialization and de_initialization functions #####
465 ==============================================================================
466 [..]
467 This section provides functions allowing to:
468 (+) Initialize and configure the FSMC NAND interface
469 (+) De-initialize the FSMC NAND interface
470 (+) Configure the FSMC clock and associated GPIOs
471
472 @endverbatim
473 * @{
474 */
475
476 /**
477 * @brief Initializes the FSMC_NAND device according to the specified
478 * control parameters in the FSMC_NAND_HandleTypeDef
479 * @param Device Pointer to NAND device instance
480 * @param Init Pointer to NAND Initialization structure
481 * @retval HAL status
482 */
FSMC_NAND_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_InitTypeDef * Init)483 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
484 {
485 uint32_t tmpr = 0U;
486
487 /* Check the parameters */
488 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
489 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
490 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
491 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
492 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
493 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
494 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
495
496 if(Init->NandBank == FSMC_NAND_BANK2)
497 {
498 /* Get the NAND bank 2 register value */
499 tmpr = Device->PCR2;
500 }
501 else
502 {
503 /* Get the NAND bank 3 register value */
504 tmpr = Device->PCR3;
505 }
506
507 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
508 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
509 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
510 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
511
512 /* Set NAND device control parameters */
513 tmpr |= (uint32_t)(Init->Waitfeature |\
514 FSMC_PCR_MEMORY_TYPE_NAND |\
515 Init->MemoryDataWidth |\
516 Init->EccComputation |\
517 Init->ECCPageSize |\
518 ((Init->TCLRSetupTime) << 9U) |\
519 ((Init->TARSetupTime) << 13U));
520
521 if(Init->NandBank == FSMC_NAND_BANK2)
522 {
523 /* NAND bank 2 registers configuration */
524 Device->PCR2 = tmpr;
525 }
526 else
527 {
528 /* NAND bank 3 registers configuration */
529 Device->PCR3 = tmpr;
530 }
531
532 return HAL_OK;
533 }
534
535 /**
536 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
537 * parameters in the FSMC_NAND_PCC_TimingTypeDef
538 * @param Device Pointer to NAND device instance
539 * @param Timing Pointer to NAND timing structure
540 * @param Bank NAND bank number
541 * @retval HAL status
542 */
FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)543 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
544 {
545 uint32_t tmpr = 0U;
546
547 /* Check the parameters */
548 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
549 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
550 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
551 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
552
553 if(Bank == FSMC_NAND_BANK2)
554 {
555 /* Get the NAND bank 2 register value */
556 tmpr = Device->PMEM2;
557 }
558 else
559 {
560 /* Get the NAND bank 3 register value */
561 tmpr = Device->PMEM3;
562 }
563
564 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
565 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
566 FSMC_PMEM2_MEMHIZ2));
567
568 /* Set FSMC_NAND device timing parameters */
569 tmpr |= (uint32_t)(Timing->SetupTime |\
570 ((Timing->WaitSetupTime) << 8U) |\
571 ((Timing->HoldSetupTime) << 16U) |\
572 ((Timing->HiZSetupTime) << 24U)
573 );
574
575 if(Bank == FSMC_NAND_BANK2)
576 {
577 /* NAND bank 2 registers configuration */
578 Device->PMEM2 = tmpr;
579 }
580 else
581 {
582 /* NAND bank 3 registers configuration */
583 Device->PMEM3 = tmpr;
584 }
585
586 return HAL_OK;
587 }
588
589 /**
590 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
591 * parameters in the FSMC_NAND_PCC_TimingTypeDef
592 * @param Device Pointer to NAND device instance
593 * @param Timing Pointer to NAND timing structure
594 * @param Bank NAND bank number
595 * @retval HAL status
596 */
FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)597 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
598 {
599 uint32_t tmpr = 0U;
600
601 /* Check the parameters */
602 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
603 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
604 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
605 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
606
607 if(Bank == FSMC_NAND_BANK2)
608 {
609 /* Get the NAND bank 2 register value */
610 tmpr = Device->PATT2;
611 }
612 else
613 {
614 /* Get the NAND bank 3 register value */
615 tmpr = Device->PATT3;
616 }
617
618 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
619 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
620 FSMC_PATT2_ATTHIZ2));
621
622 /* Set FSMC_NAND device timing parameters */
623 tmpr |= (uint32_t)(Timing->SetupTime |\
624 ((Timing->WaitSetupTime) << 8U) |\
625 ((Timing->HoldSetupTime) << 16U) |\
626 ((Timing->HiZSetupTime) << 24U)
627 );
628
629 if(Bank == FSMC_NAND_BANK2)
630 {
631 /* NAND bank 2 registers configuration */
632 Device->PATT2 = tmpr;
633 }
634 else
635 {
636 /* NAND bank 3 registers configuration */
637 Device->PATT3 = tmpr;
638 }
639
640 return HAL_OK;
641 }
642
643 /**
644 * @brief DeInitializes the FSMC_NAND device
645 * @param Device Pointer to NAND device instance
646 * @param Bank NAND bank number
647 * @retval HAL status
648 */
FSMC_NAND_DeInit(FSMC_NAND_TypeDef * Device,uint32_t Bank)649 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
650 {
651 /* Disable the NAND Bank */
652 __FSMC_NAND_DISABLE(Device, Bank);
653
654 /* De-initialize the NAND Bank */
655 if(Bank == FSMC_NAND_BANK2)
656 {
657 /* Set the FSMC_NAND_BANK2 registers to their reset values */
658 Device->PCR2 = 0x00000018U;
659 Device->SR2 = 0x00000040U;
660 Device->PMEM2 = 0xFCFCFCFCU;
661 Device->PATT2 = 0xFCFCFCFCU;
662 }
663 /* FSMC_Bank3_NAND */
664 else
665 {
666 /* Set the FSMC_NAND_BANK3 registers to their reset values */
667 Device->PCR3 = 0x00000018U;
668 Device->SR3 = 0x00000040U;
669 Device->PMEM3 = 0xFCFCFCFCU;
670 Device->PATT3 = 0xFCFCFCFCU;
671 }
672
673 return HAL_OK;
674 }
675 /**
676 * @}
677 */
678
679 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
680 * @brief management functions
681 *
682 @verbatim
683 ==============================================================================
684 ##### FSMC_NAND Control functions #####
685 ==============================================================================
686 [..]
687 This subsection provides a set of functions allowing to control dynamically
688 the FSMC NAND interface.
689
690 @endverbatim
691 * @{
692 */
693
694 /**
695 * @brief Enables dynamically FSMC_NAND ECC feature.
696 * @param Device Pointer to NAND device instance
697 * @param Bank NAND bank number
698 * @retval HAL status
699 */
FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef * Device,uint32_t Bank)700 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
701 {
702 /* Enable ECC feature */
703 if(Bank == FSMC_NAND_BANK2)
704 {
705 Device->PCR2 |= FSMC_PCR2_ECCEN;
706 }
707 else
708 {
709 Device->PCR3 |= FSMC_PCR3_ECCEN;
710 }
711
712 return HAL_OK;
713 }
714
715 /**
716 * @brief Disables dynamically FSMC_NAND ECC feature.
717 * @param Device Pointer to NAND device instance
718 * @param Bank NAND bank number
719 * @retval HAL status
720 */
FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef * Device,uint32_t Bank)721 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
722 {
723 /* Disable ECC feature */
724 if(Bank == FSMC_NAND_BANK2)
725 {
726 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
727 }
728 else
729 {
730 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
731 }
732
733 return HAL_OK;
734 }
735
736 /**
737 * @brief Disables dynamically FSMC_NAND ECC feature.
738 * @param Device Pointer to NAND device instance
739 * @param ECCval Pointer to ECC value
740 * @param Bank NAND bank number
741 * @param Timeout Timeout wait value
742 * @retval HAL status
743 */
FSMC_NAND_GetECC(FSMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)744 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
745 {
746 uint32_t tickstart = 0U;
747
748 /* Check the parameters */
749 assert_param(IS_FSMC_NAND_DEVICE(Device));
750 assert_param(IS_FSMC_NAND_BANK(Bank));
751
752 /* Get tick */
753 tickstart = HAL_GetTick();
754
755 /* Wait until FIFO is empty */
756 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
757 {
758 /* Check for the Timeout */
759 if(Timeout != HAL_MAX_DELAY)
760 {
761 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
762 {
763 return HAL_TIMEOUT;
764 }
765 }
766 }
767
768 if(Bank == FSMC_NAND_BANK2)
769 {
770 /* Get the ECCR2 register value */
771 *ECCval = (uint32_t)Device->ECCR2;
772 }
773 else
774 {
775 /* Get the ECCR3 register value */
776 *ECCval = (uint32_t)Device->ECCR3;
777 }
778
779 return HAL_OK;
780 }
781
782 /**
783 * @}
784 */
785
786 /**
787 * @}
788 */
789
790 /** @addtogroup FSMC_LL_PCCARD
791 * @brief PCCARD Controller functions
792 *
793 @verbatim
794 ==============================================================================
795 ##### How to use PCCARD device driver #####
796 ==============================================================================
797 [..]
798 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
799 to run the PCCARD/compact flash external devices.
800
801 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
802 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
803 (+) FSMC PCCARD bank common space timing configuration using the function
804 FSMC_PCCARD_CommonSpace_Timing_Init()
805 (+) FSMC PCCARD bank attribute space timing configuration using the function
806 FSMC_PCCARD_AttributeSpace_Timing_Init()
807 (+) FSMC PCCARD bank IO space timing configuration using the function
808 FSMC_PCCARD_IOSpace_Timing_Init()
809
810 @endverbatim
811 * @{
812 */
813
814 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
815 * @brief Initialization and Configuration functions
816 *
817 @verbatim
818 ==============================================================================
819 ##### Initialization and de_initialization functions #####
820 ==============================================================================
821 [..]
822 This section provides functions allowing to:
823 (+) Initialize and configure the FSMC PCCARD interface
824 (+) De-initialize the FSMC PCCARD interface
825 (+) Configure the FSMC clock and associated GPIOs
826
827 @endverbatim
828 * @{
829 */
830
831 /**
832 * @brief Initializes the FSMC_PCCARD device according to the specified
833 * control parameters in the FSMC_PCCARD_HandleTypeDef
834 * @param Device Pointer to PCCARD device instance
835 * @param Init Pointer to PCCARD Initialization structure
836 * @retval HAL status
837 */
FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef * Device,FSMC_PCCARD_InitTypeDef * Init)838 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
839 {
840 uint32_t tmpr = 0U;
841
842 /* Check the parameters */
843 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
844 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
845 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
846
847 /* Get PCCARD control register value */
848 tmpr = Device->PCR4;
849
850 /* Clear TAR, TCLR, PWAITEN and PWID bits */
851 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
852 FSMC_PCR4_PWID | FSMC_PCR4_PTYP));
853
854 /* Set FSMC_PCCARD device control parameters */
855 tmpr |= (uint32_t)(Init->Waitfeature |\
856 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
857 (Init->TCLRSetupTime << 9U) |\
858 (Init->TARSetupTime << 13U));
859
860 Device->PCR4 = tmpr;
861
862 return HAL_OK;
863 }
864
865 /**
866 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
867 * parameters in the FSMC_NAND_PCC_TimingTypeDef
868 * @param Device Pointer to PCCARD device instance
869 * @param Timing Pointer to PCCARD timing structure
870 * @retval HAL status
871 */
FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)872 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
873 {
874 uint32_t tmpr = 0U;
875
876 /* Check the parameters */
877 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
878 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
879 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
880 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
881
882 /* Get PCCARD common space timing register value */
883 tmpr = Device->PMEM4;
884
885 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
886 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
887 FSMC_PMEM4_MEMHIZ4));
888 /* Set PCCARD timing parameters */
889 tmpr |= (uint32_t)((Timing->SetupTime |\
890 ((Timing->WaitSetupTime) << 8U) |\
891 (Timing->HoldSetupTime) << 16U) |\
892 ((Timing->HiZSetupTime) << 24U));
893
894 Device->PMEM4 = tmpr;
895
896 return HAL_OK;
897 }
898
899 /**
900 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
901 * parameters in the FSMC_NAND_PCC_TimingTypeDef
902 * @param Device Pointer to PCCARD device instance
903 * @param Timing Pointer to PCCARD timing structure
904 * @retval HAL status
905 */
FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)906 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
907 {
908 uint32_t tmpr = 0U;
909
910 /* Check the parameters */
911 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
912 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
913 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
914 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
915
916 /* Get PCCARD timing parameters */
917 tmpr = Device->PATT4;
918
919 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
920 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
921 FSMC_PATT4_ATTHIZ4));
922
923 /* Set PCCARD timing parameters */
924 tmpr |= (uint32_t)(Timing->SetupTime |\
925 ((Timing->WaitSetupTime) << 8U) |\
926 ((Timing->HoldSetupTime) << 16U) |\
927 ((Timing->HiZSetupTime) << 24U));
928 Device->PATT4 = tmpr;
929
930 return HAL_OK;
931 }
932
933 /**
934 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
935 * parameters in the FSMC_NAND_PCC_TimingTypeDef
936 * @param Device Pointer to PCCARD device instance
937 * @param Timing Pointer to PCCARD timing structure
938 * @retval HAL status
939 */
FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef * Device,FSMC_NAND_PCC_TimingTypeDef * Timing)940 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
941 {
942 uint32_t tmpr = 0U;
943
944 /* Check the parameters */
945 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
946 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
947 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
948 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
949
950 /* Get FSMC_PCCARD device timing parameters */
951 tmpr = Device->PIO4;
952
953 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
954 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
955 FSMC_PIO4_IOHIZ4));
956
957 /* Set FSMC_PCCARD device timing parameters */
958 tmpr |= (uint32_t)(Timing->SetupTime |\
959 ((Timing->WaitSetupTime) << 8U) |\
960 ((Timing->HoldSetupTime) << 16U) |\
961 ((Timing->HiZSetupTime) << 24U));
962
963 Device->PIO4 = tmpr;
964
965 return HAL_OK;
966 }
967
968 /**
969 * @brief DeInitializes the FSMC_PCCARD device
970 * @param Device Pointer to PCCARD device instance
971 * @retval HAL status
972 */
FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef * Device)973 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
974 {
975 /* Disable the FSMC_PCCARD device */
976 __FSMC_PCCARD_DISABLE(Device);
977
978 /* De-initialize the FSMC_PCCARD device */
979 Device->PCR4 = 0x00000018U;
980 Device->SR4 = 0x00000000U;
981 Device->PMEM4 = 0xFCFCFCFCU;
982 Device->PATT4 = 0xFCFCFCFCU;
983 Device->PIO4 = 0xFCFCFCFCU;
984
985 return HAL_OK;
986 }
987 /**
988 * @}
989 */
990
991 /**
992 * @}
993 */
994 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
995
996 /**
997 * @}
998 */
999 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
1000 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
1001
1002 /**
1003 * @}
1004 */
1005
1006 /**
1007 * @}
1008 */
1009 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1010