1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (++) TxCpltCallback : SPI Tx Completed callback
69 (++) RxCpltCallback : SPI Rx Completed callback
70 (++) TxRxCpltCallback : SPI TxRx Completed callback
71 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (++) ErrorCallback : SPI Error callback
75 (++) AbortCpltCallback : SPI Abort callback
76 (++) MspInitCallback : SPI Msp Init callback
77 (++) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (++) TxCpltCallback : SPI Tx Completed callback
88 (++) RxCpltCallback : SPI Rx Completed callback
89 (++) TxRxCpltCallback : SPI TxRx Completed callback
90 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (++) ErrorCallback : SPI Error callback
94 (++) AbortCpltCallback : SPI Abort callback
95 (++) MspInitCallback : SPI Msp Init callback
96 (++) MspDeInitCallback : SPI Msp DeInit callback
97
98 [..]
99 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
100 all callbacks are set to the corresponding weak functions:
101 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
102 Exception done for MspInit and MspDeInit functions that are
103 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
104 these callbacks are null (not registered beforehand).
105 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
106 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
107
108 [..]
109 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
110 Exception done MspInit/MspDeInit functions that can be registered/unregistered
111 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
112 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
113 Then, the user first registers the MspInit/MspDeInit user callbacks
114 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
115 or HAL_SPI_Init() function.
116
117 [..]
118 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
119 not defined, the callback registering feature is not available
120 and weak (surcharged) callbacks are used.
121
122 [..]
123 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
124 the following table resume the max SPI frequency reached with data size 8bits/16bits,
125 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
126
127 @endverbatim
128
129 Additional table :
130
131 DataSize = SPI_DATASIZE_8BIT:
132 +----------------------------------------------------------------------------------------------+
133 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
134 | Process | Tranfert mode |---------------------|----------------------|----------------------|
135 | | | Master | Slave | Master | Slave | Master | Slave |
136 |==============================================================================================|
137 | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
138 | X |----------------|----------|----------|-----------|----------|-----------|----------|
139 | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
140 | R |----------------|----------|----------|-----------|----------|-----------|----------|
141 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
142 |=========|================|==========|==========|===========|==========|===========|==========|
143 | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
144 | |----------------|----------|----------|-----------|----------|-----------|----------|
145 | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
146 | X |----------------|----------|----------|-----------|----------|-----------|----------|
147 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
148 |=========|================|==========|==========|===========|==========|===========|==========|
149 | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
150 | |----------------|----------|----------|-----------|----------|-----------|----------|
151 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
152 | X |----------------|----------|----------|-----------|----------|-----------|----------|
153 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
154 +----------------------------------------------------------------------------------------------+
155
156 DataSize = SPI_DATASIZE_16BIT:
157 +----------------------------------------------------------------------------------------------+
158 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
159 | Process | Tranfert mode |---------------------|----------------------|----------------------|
160 | | | Master | Slave | Master | Slave | Master | Slave |
161 |==============================================================================================|
162 | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
163 | X |----------------|----------|----------|-----------|----------|-----------|----------|
164 | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
165 | R |----------------|----------|----------|-----------|----------|-----------|----------|
166 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
167 |=========|================|==========|==========|===========|==========|===========|==========|
168 | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
169 | |----------------|----------|----------|-----------|----------|-----------|----------|
170 | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
171 | X |----------------|----------|----------|-----------|----------|-----------|----------|
172 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
173 |=========|================|==========|==========|===========|==========|===========|==========|
174 | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
175 | |----------------|----------|----------|-----------|----------|-----------|----------|
176 | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
177 | X |----------------|----------|----------|-----------|----------|-----------|----------|
178 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
179 +----------------------------------------------------------------------------------------------+
180 @note The max SPI frequency depend on SPI data size (8bits, 16bits),
181 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
182 @note
183 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
184 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
185 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
186
187 ******************************************************************************
188 * @attention
189 *
190 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
191 * All rights reserved.</center></h2>
192 *
193 * This software component is licensed by ST under BSD 3-Clause license,
194 * the "License"; You may not use this file except in compliance with the
195 * License. You may obtain a copy of the License at:
196 * opensource.org/licenses/BSD-3-Clause
197 *
198 ******************************************************************************
199 */
200
201 /* Includes ------------------------------------------------------------------*/
202 #include "stm32f4xx_hal.h"
203
204 /** @addtogroup STM32F4xx_HAL_Driver
205 * @{
206 */
207
208 /** @defgroup SPI SPI
209 * @brief SPI HAL module driver
210 * @{
211 */
212 #ifdef HAL_SPI_MODULE_ENABLED
213
214 /* Private typedef -----------------------------------------------------------*/
215 /* Private defines -----------------------------------------------------------*/
216 /** @defgroup SPI_Private_Constants SPI Private Constants
217 * @{
218 */
219 #define SPI_DEFAULT_TIMEOUT 100U
220 #define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */
221 /**
222 * @}
223 */
224
225 /* Private macros ------------------------------------------------------------*/
226 /* Private variables ---------------------------------------------------------*/
227 /* Private function prototypes -----------------------------------------------*/
228 /** @defgroup SPI_Private_Functions SPI Private Functions
229 * @{
230 */
231 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
236 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
237 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
238 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
239 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
240 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
241 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
242 uint32_t Timeout, uint32_t Tickstart);
243 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
251 #if (USE_SPI_CRC != 0U)
252 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
255 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
256 #endif /* USE_SPI_CRC */
257 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
261 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
262 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
264 /**
265 * @}
266 */
267
268 /* Exported functions --------------------------------------------------------*/
269 /** @defgroup SPI_Exported_Functions SPI Exported Functions
270 * @{
271 */
272
273 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
274 * @brief Initialization and Configuration functions
275 *
276 @verbatim
277 ===============================================================================
278 ##### Initialization and de-initialization functions #####
279 ===============================================================================
280 [..] This subsection provides a set of functions allowing to initialize and
281 de-initialize the SPIx peripheral:
282
283 (+) User must implement HAL_SPI_MspInit() function in which he configures
284 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
285
286 (+) Call the function HAL_SPI_Init() to configure the selected device with
287 the selected configuration:
288 (++) Mode
289 (++) Direction
290 (++) Data Size
291 (++) Clock Polarity and Phase
292 (++) NSS Management
293 (++) BaudRate Prescaler
294 (++) FirstBit
295 (++) TIMode
296 (++) CRC Calculation
297 (++) CRC Polynomial if CRC enabled
298
299 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
300 of the selected SPIx peripheral.
301
302 @endverbatim
303 * @{
304 */
305
306 /**
307 * @brief Initialize the SPI according to the specified parameters
308 * in the SPI_InitTypeDef and initialize the associated handle.
309 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
310 * the configuration information for SPI module.
311 * @retval HAL status
312 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)313 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
314 {
315 /* Check the SPI handle allocation */
316 if (hspi == NULL)
317 {
318 return HAL_ERROR;
319 }
320
321 /* Check the parameters */
322 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
323 assert_param(IS_SPI_MODE(hspi->Init.Mode));
324 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
325 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
326 assert_param(IS_SPI_NSS(hspi->Init.NSS));
327 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
328 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
329 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
330 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
331 {
332 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
333 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
334 }
335 #if (USE_SPI_CRC != 0U)
336 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
337 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
338 {
339 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
340 }
341 #else
342 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
343 #endif /* USE_SPI_CRC */
344
345 if (hspi->State == HAL_SPI_STATE_RESET)
346 {
347 /* Allocate lock resource and initialize it */
348 hspi->Lock = HAL_UNLOCKED;
349
350 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
351 /* Init the SPI Callback settings */
352 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
353 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
354 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
355 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
356 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
357 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
358 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
359 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
360
361 if (hspi->MspInitCallback == NULL)
362 {
363 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
364 }
365
366 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
367 hspi->MspInitCallback(hspi);
368 #else
369 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
370 HAL_SPI_MspInit(hspi);
371 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
372 }
373
374 hspi->State = HAL_SPI_STATE_BUSY;
375
376 /* Disable the selected SPI peripheral */
377 __HAL_SPI_DISABLE(hspi);
378
379 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
380 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
381 Communication speed, First bit and CRC calculation state */
382 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
383 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
384 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
385
386 /* Configure : NSS management, TI Mode */
387 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
388
389 #if (USE_SPI_CRC != 0U)
390 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
391 /* Configure : CRC Polynomial */
392 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
393 {
394 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
395 }
396 #endif /* USE_SPI_CRC */
397
398 #if defined(SPI_I2SCFGR_I2SMOD)
399 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
400 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
401 #endif /* SPI_I2SCFGR_I2SMOD */
402
403 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
404 hspi->State = HAL_SPI_STATE_READY;
405
406 return HAL_OK;
407 }
408
409 /**
410 * @brief De-Initialize the SPI peripheral.
411 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
412 * the configuration information for SPI module.
413 * @retval HAL status
414 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)415 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
416 {
417 /* Check the SPI handle allocation */
418 if (hspi == NULL)
419 {
420 return HAL_ERROR;
421 }
422
423 /* Check SPI Instance parameter */
424 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
425
426 hspi->State = HAL_SPI_STATE_BUSY;
427
428 /* Disable the SPI Peripheral Clock */
429 __HAL_SPI_DISABLE(hspi);
430
431 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
432 if (hspi->MspDeInitCallback == NULL)
433 {
434 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
435 }
436
437 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
438 hspi->MspDeInitCallback(hspi);
439 #else
440 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
441 HAL_SPI_MspDeInit(hspi);
442 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
443
444 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
445 hspi->State = HAL_SPI_STATE_RESET;
446
447 /* Release Lock */
448 __HAL_UNLOCK(hspi);
449
450 return HAL_OK;
451 }
452
453 /**
454 * @brief Initialize the SPI MSP.
455 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
456 * the configuration information for SPI module.
457 * @retval None
458 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)459 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
460 {
461 /* Prevent unused argument(s) compilation warning */
462 UNUSED(hspi);
463
464 /* NOTE : This function should not be modified, when the callback is needed,
465 the HAL_SPI_MspInit should be implemented in the user file
466 */
467 }
468
469 /**
470 * @brief De-Initialize the SPI MSP.
471 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
472 * the configuration information for SPI module.
473 * @retval None
474 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)475 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
476 {
477 /* Prevent unused argument(s) compilation warning */
478 UNUSED(hspi);
479
480 /* NOTE : This function should not be modified, when the callback is needed,
481 the HAL_SPI_MspDeInit should be implemented in the user file
482 */
483 }
484
485 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
486 /**
487 * @brief Register a User SPI Callback
488 * To be used instead of the weak predefined callback
489 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
490 * the configuration information for the specified SPI.
491 * @param CallbackID ID of the callback to be registered
492 * @param pCallback pointer to the Callback function
493 * @retval HAL status
494 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)495 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
496 pSPI_CallbackTypeDef pCallback)
497 {
498 HAL_StatusTypeDef status = HAL_OK;
499
500 if (pCallback == NULL)
501 {
502 /* Update the error code */
503 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
504
505 return HAL_ERROR;
506 }
507 /* Process locked */
508 __HAL_LOCK(hspi);
509
510 if (HAL_SPI_STATE_READY == hspi->State)
511 {
512 switch (CallbackID)
513 {
514 case HAL_SPI_TX_COMPLETE_CB_ID :
515 hspi->TxCpltCallback = pCallback;
516 break;
517
518 case HAL_SPI_RX_COMPLETE_CB_ID :
519 hspi->RxCpltCallback = pCallback;
520 break;
521
522 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
523 hspi->TxRxCpltCallback = pCallback;
524 break;
525
526 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
527 hspi->TxHalfCpltCallback = pCallback;
528 break;
529
530 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
531 hspi->RxHalfCpltCallback = pCallback;
532 break;
533
534 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
535 hspi->TxRxHalfCpltCallback = pCallback;
536 break;
537
538 case HAL_SPI_ERROR_CB_ID :
539 hspi->ErrorCallback = pCallback;
540 break;
541
542 case HAL_SPI_ABORT_CB_ID :
543 hspi->AbortCpltCallback = pCallback;
544 break;
545
546 case HAL_SPI_MSPINIT_CB_ID :
547 hspi->MspInitCallback = pCallback;
548 break;
549
550 case HAL_SPI_MSPDEINIT_CB_ID :
551 hspi->MspDeInitCallback = pCallback;
552 break;
553
554 default :
555 /* Update the error code */
556 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
557
558 /* Return error status */
559 status = HAL_ERROR;
560 break;
561 }
562 }
563 else if (HAL_SPI_STATE_RESET == hspi->State)
564 {
565 switch (CallbackID)
566 {
567 case HAL_SPI_MSPINIT_CB_ID :
568 hspi->MspInitCallback = pCallback;
569 break;
570
571 case HAL_SPI_MSPDEINIT_CB_ID :
572 hspi->MspDeInitCallback = pCallback;
573 break;
574
575 default :
576 /* Update the error code */
577 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
578
579 /* Return error status */
580 status = HAL_ERROR;
581 break;
582 }
583 }
584 else
585 {
586 /* Update the error code */
587 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
588
589 /* Return error status */
590 status = HAL_ERROR;
591 }
592
593 /* Release Lock */
594 __HAL_UNLOCK(hspi);
595 return status;
596 }
597
598 /**
599 * @brief Unregister an SPI Callback
600 * SPI callback is redirected to the weak predefined callback
601 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
602 * the configuration information for the specified SPI.
603 * @param CallbackID ID of the callback to be unregistered
604 * @retval HAL status
605 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)606 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
607 {
608 HAL_StatusTypeDef status = HAL_OK;
609
610 /* Process locked */
611 __HAL_LOCK(hspi);
612
613 if (HAL_SPI_STATE_READY == hspi->State)
614 {
615 switch (CallbackID)
616 {
617 case HAL_SPI_TX_COMPLETE_CB_ID :
618 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
619 break;
620
621 case HAL_SPI_RX_COMPLETE_CB_ID :
622 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
623 break;
624
625 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
626 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
627 break;
628
629 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
630 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
631 break;
632
633 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
634 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
635 break;
636
637 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
638 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
639 break;
640
641 case HAL_SPI_ERROR_CB_ID :
642 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
643 break;
644
645 case HAL_SPI_ABORT_CB_ID :
646 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
647 break;
648
649 case HAL_SPI_MSPINIT_CB_ID :
650 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
651 break;
652
653 case HAL_SPI_MSPDEINIT_CB_ID :
654 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
655 break;
656
657 default :
658 /* Update the error code */
659 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
660
661 /* Return error status */
662 status = HAL_ERROR;
663 break;
664 }
665 }
666 else if (HAL_SPI_STATE_RESET == hspi->State)
667 {
668 switch (CallbackID)
669 {
670 case HAL_SPI_MSPINIT_CB_ID :
671 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
672 break;
673
674 case HAL_SPI_MSPDEINIT_CB_ID :
675 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
676 break;
677
678 default :
679 /* Update the error code */
680 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
681
682 /* Return error status */
683 status = HAL_ERROR;
684 break;
685 }
686 }
687 else
688 {
689 /* Update the error code */
690 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
691
692 /* Return error status */
693 status = HAL_ERROR;
694 }
695
696 /* Release Lock */
697 __HAL_UNLOCK(hspi);
698 return status;
699 }
700 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
701 /**
702 * @}
703 */
704
705 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
706 * @brief Data transfers functions
707 *
708 @verbatim
709 ==============================================================================
710 ##### IO operation functions #####
711 ===============================================================================
712 [..]
713 This subsection provides a set of functions allowing to manage the SPI
714 data transfers.
715
716 [..] The SPI supports master and slave mode :
717
718 (#) There are two modes of transfer:
719 (++) Blocking mode: The communication is performed in polling mode.
720 The HAL status of all data processing is returned by the same function
721 after finishing transfer.
722 (++) No-Blocking mode: The communication is performed using Interrupts
723 or DMA, These APIs return the HAL status.
724 The end of the data processing will be indicated through the
725 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
726 using DMA mode.
727 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
728 will be executed respectively at the end of the transmit or Receive process
729 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
730
731 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
732 exist for 1Line (simplex) and 2Lines (full duplex) modes.
733
734 @endverbatim
735 * @{
736 */
737
738 /**
739 * @brief Transmit an amount of data in blocking mode.
740 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
741 * the configuration information for SPI module.
742 * @param pData pointer to data buffer
743 * @param Size amount of data to be sent
744 * @param Timeout Timeout duration
745 * @retval HAL status
746 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)747 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
748 {
749 uint32_t tickstart;
750 HAL_StatusTypeDef errorcode = HAL_OK;
751 uint16_t initial_TxXferCount;
752
753 /* Check Direction parameter */
754 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
755
756 /* Process Locked */
757 __HAL_LOCK(hspi);
758
759 /* Init tickstart for timeout management*/
760 tickstart = HAL_GetTick();
761 initial_TxXferCount = Size;
762
763 if (hspi->State != HAL_SPI_STATE_READY)
764 {
765 errorcode = HAL_BUSY;
766 goto error;
767 }
768
769 if ((pData == NULL) || (Size == 0U))
770 {
771 errorcode = HAL_ERROR;
772 goto error;
773 }
774
775 /* Set the transaction information */
776 hspi->State = HAL_SPI_STATE_BUSY_TX;
777 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
778 hspi->pTxBuffPtr = (uint8_t *)pData;
779 hspi->TxXferSize = Size;
780 hspi->TxXferCount = Size;
781
782 /*Init field not used in handle to zero */
783 hspi->pRxBuffPtr = (uint8_t *)NULL;
784 hspi->RxXferSize = 0U;
785 hspi->RxXferCount = 0U;
786 hspi->TxISR = NULL;
787 hspi->RxISR = NULL;
788
789 /* Configure communication direction : 1Line */
790 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
791 {
792 SPI_1LINE_TX(hspi);
793 }
794
795 #if (USE_SPI_CRC != 0U)
796 /* Reset CRC Calculation */
797 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
798 {
799 SPI_RESET_CRC(hspi);
800 }
801 #endif /* USE_SPI_CRC */
802
803 /* Check if the SPI is already enabled */
804 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
805 {
806 /* Enable SPI peripheral */
807 __HAL_SPI_ENABLE(hspi);
808 }
809
810 /* Transmit data in 16 Bit mode */
811 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
812 {
813 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
814 {
815 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
816 hspi->pTxBuffPtr += sizeof(uint16_t);
817 hspi->TxXferCount--;
818 }
819 /* Transmit data in 16 Bit mode */
820 while (hspi->TxXferCount > 0U)
821 {
822 /* Wait until TXE flag is set to send data */
823 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
824 {
825 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
826 hspi->pTxBuffPtr += sizeof(uint16_t);
827 hspi->TxXferCount--;
828 }
829 else
830 {
831 /* Timeout management */
832 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
833 {
834 errorcode = HAL_TIMEOUT;
835 goto error;
836 }
837 }
838 }
839 }
840 /* Transmit data in 8 Bit mode */
841 else
842 {
843 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
844 {
845 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
846 hspi->pTxBuffPtr += sizeof(uint8_t);
847 hspi->TxXferCount--;
848 }
849 while (hspi->TxXferCount > 0U)
850 {
851 /* Wait until TXE flag is set to send data */
852 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
853 {
854 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
855 hspi->pTxBuffPtr += sizeof(uint8_t);
856 hspi->TxXferCount--;
857 }
858 else
859 {
860 /* Timeout management */
861 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
862 {
863 errorcode = HAL_TIMEOUT;
864 goto error;
865 }
866 }
867 }
868 }
869 #if (USE_SPI_CRC != 0U)
870 /* Enable CRC Transmission */
871 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
872 {
873 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
874 }
875 #endif /* USE_SPI_CRC */
876
877 /* Check the end of the transaction */
878 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
879 {
880 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
881 }
882
883 /* Clear overrun flag in 2 Lines communication mode because received is not read */
884 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
885 {
886 __HAL_SPI_CLEAR_OVRFLAG(hspi);
887 }
888
889 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
890 {
891 errorcode = HAL_ERROR;
892 }
893
894 error:
895 hspi->State = HAL_SPI_STATE_READY;
896 /* Process Unlocked */
897 __HAL_UNLOCK(hspi);
898 return errorcode;
899 }
900
901 /**
902 * @brief Receive an amount of data in blocking mode.
903 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
904 * the configuration information for SPI module.
905 * @param pData pointer to data buffer
906 * @param Size amount of data to be received
907 * @param Timeout Timeout duration
908 * @retval HAL status
909 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)910 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
911 {
912 uint32_t tickstart;
913 HAL_StatusTypeDef errorcode = HAL_OK;
914
915 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
916 {
917 hspi->State = HAL_SPI_STATE_BUSY_RX;
918 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
919 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
920 }
921
922 /* Process Locked */
923 __HAL_LOCK(hspi);
924
925 /* Init tickstart for timeout management*/
926 tickstart = HAL_GetTick();
927
928 if (hspi->State != HAL_SPI_STATE_READY)
929 {
930 errorcode = HAL_BUSY;
931 goto error;
932 }
933
934 if ((pData == NULL) || (Size == 0U))
935 {
936 errorcode = HAL_ERROR;
937 goto error;
938 }
939
940 /* Set the transaction information */
941 hspi->State = HAL_SPI_STATE_BUSY_RX;
942 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
943 hspi->pRxBuffPtr = (uint8_t *)pData;
944 hspi->RxXferSize = Size;
945 hspi->RxXferCount = Size;
946
947 /*Init field not used in handle to zero */
948 hspi->pTxBuffPtr = (uint8_t *)NULL;
949 hspi->TxXferSize = 0U;
950 hspi->TxXferCount = 0U;
951 hspi->RxISR = NULL;
952 hspi->TxISR = NULL;
953
954 #if (USE_SPI_CRC != 0U)
955 /* Reset CRC Calculation */
956 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
957 {
958 SPI_RESET_CRC(hspi);
959 /* this is done to handle the CRCNEXT before the latest data */
960 hspi->RxXferCount--;
961 }
962 #endif /* USE_SPI_CRC */
963
964 /* Configure communication direction: 1Line */
965 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
966 {
967 SPI_1LINE_RX(hspi);
968 }
969
970 /* Check if the SPI is already enabled */
971 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
972 {
973 /* Enable SPI peripheral */
974 __HAL_SPI_ENABLE(hspi);
975 }
976
977 /* Receive data in 8 Bit mode */
978 if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
979 {
980 /* Transfer loop */
981 while (hspi->RxXferCount > 0U)
982 {
983 /* Check the RXNE flag */
984 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
985 {
986 /* read the received data */
987 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
988 hspi->pRxBuffPtr += sizeof(uint8_t);
989 hspi->RxXferCount--;
990 }
991 else
992 {
993 /* Timeout management */
994 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
995 {
996 errorcode = HAL_TIMEOUT;
997 goto error;
998 }
999 }
1000 }
1001 }
1002 else
1003 {
1004 /* Transfer loop */
1005 while (hspi->RxXferCount > 0U)
1006 {
1007 /* Check the RXNE flag */
1008 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1009 {
1010 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1011 hspi->pRxBuffPtr += sizeof(uint16_t);
1012 hspi->RxXferCount--;
1013 }
1014 else
1015 {
1016 /* Timeout management */
1017 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1018 {
1019 errorcode = HAL_TIMEOUT;
1020 goto error;
1021 }
1022 }
1023 }
1024 }
1025
1026 #if (USE_SPI_CRC != 0U)
1027 /* Handle the CRC Transmission */
1028 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1029 {
1030 /* freeze the CRC before the latest data */
1031 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1032
1033 /* Read the latest data */
1034 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1035 {
1036 /* the latest data has not been received */
1037 errorcode = HAL_TIMEOUT;
1038 goto error;
1039 }
1040
1041 /* Receive last data in 16 Bit mode */
1042 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1043 {
1044 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1045 }
1046 /* Receive last data in 8 Bit mode */
1047 else
1048 {
1049 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1050 }
1051
1052 /* Wait the CRC data */
1053 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1054 {
1055 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1056 errorcode = HAL_TIMEOUT;
1057 goto error;
1058 }
1059
1060 /* Read CRC to Flush DR and RXNE flag */
1061 READ_REG(hspi->Instance->DR);
1062 }
1063 #endif /* USE_SPI_CRC */
1064
1065 /* Check the end of the transaction */
1066 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1067 {
1068 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1069 }
1070
1071 #if (USE_SPI_CRC != 0U)
1072 /* Check if CRC error occurred */
1073 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1074 {
1075 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1076 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1077 }
1078 #endif /* USE_SPI_CRC */
1079
1080 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1081 {
1082 errorcode = HAL_ERROR;
1083 }
1084
1085 error :
1086 hspi->State = HAL_SPI_STATE_READY;
1087 __HAL_UNLOCK(hspi);
1088 return errorcode;
1089 }
1090
1091 /**
1092 * @brief Transmit and Receive an amount of data in blocking mode.
1093 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1094 * the configuration information for SPI module.
1095 * @param pTxData pointer to transmission data buffer
1096 * @param pRxData pointer to reception data buffer
1097 * @param Size amount of data to be sent and received
1098 * @param Timeout Timeout duration
1099 * @retval HAL status
1100 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1101 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1102 uint32_t Timeout)
1103 {
1104 uint16_t initial_TxXferCount;
1105 uint32_t tmp_mode;
1106 HAL_SPI_StateTypeDef tmp_state;
1107 uint32_t tickstart;
1108
1109 /* Variable used to alternate Rx and Tx during transfer */
1110 uint32_t txallowed = 1U;
1111 HAL_StatusTypeDef errorcode = HAL_OK;
1112
1113 /* Check Direction parameter */
1114 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1115
1116 /* Process Locked */
1117 __HAL_LOCK(hspi);
1118
1119 /* Init tickstart for timeout management*/
1120 tickstart = HAL_GetTick();
1121
1122 /* Init temporary variables */
1123 tmp_state = hspi->State;
1124 tmp_mode = hspi->Init.Mode;
1125 initial_TxXferCount = Size;
1126
1127 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1128 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1129 {
1130 errorcode = HAL_BUSY;
1131 goto error;
1132 }
1133
1134 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1135 {
1136 errorcode = HAL_ERROR;
1137 goto error;
1138 }
1139
1140 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1141 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1142 {
1143 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1144 }
1145
1146 /* Set the transaction information */
1147 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1148 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1149 hspi->RxXferCount = Size;
1150 hspi->RxXferSize = Size;
1151 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1152 hspi->TxXferCount = Size;
1153 hspi->TxXferSize = Size;
1154
1155 /*Init field not used in handle to zero */
1156 hspi->RxISR = NULL;
1157 hspi->TxISR = NULL;
1158
1159 #if (USE_SPI_CRC != 0U)
1160 /* Reset CRC Calculation */
1161 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1162 {
1163 SPI_RESET_CRC(hspi);
1164 }
1165 #endif /* USE_SPI_CRC */
1166
1167 /* Check if the SPI is already enabled */
1168 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1169 {
1170 /* Enable SPI peripheral */
1171 __HAL_SPI_ENABLE(hspi);
1172 }
1173
1174 /* Transmit and Receive data in 16 Bit mode */
1175 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1176 {
1177 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1178 {
1179 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1180 hspi->pTxBuffPtr += sizeof(uint16_t);
1181 hspi->TxXferCount--;
1182 }
1183 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1184 {
1185 /* Check TXE flag */
1186 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1187 {
1188 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1189 hspi->pTxBuffPtr += sizeof(uint16_t);
1190 hspi->TxXferCount--;
1191 /* Next Data is a reception (Rx). Tx not allowed */
1192 txallowed = 0U;
1193
1194 #if (USE_SPI_CRC != 0U)
1195 /* Enable CRC Transmission */
1196 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1197 {
1198 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1199 }
1200 #endif /* USE_SPI_CRC */
1201 }
1202
1203 /* Check RXNE flag */
1204 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1205 {
1206 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1207 hspi->pRxBuffPtr += sizeof(uint16_t);
1208 hspi->RxXferCount--;
1209 /* Next Data is a Transmission (Tx). Tx is allowed */
1210 txallowed = 1U;
1211 }
1212 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1213 {
1214 errorcode = HAL_TIMEOUT;
1215 goto error;
1216 }
1217 }
1218 }
1219 /* Transmit and Receive data in 8 Bit mode */
1220 else
1221 {
1222 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1223 {
1224 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1225 hspi->pTxBuffPtr += sizeof(uint8_t);
1226 hspi->TxXferCount--;
1227 }
1228 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1229 {
1230 /* Check TXE flag */
1231 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1232 {
1233 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1234 hspi->pTxBuffPtr++;
1235 hspi->TxXferCount--;
1236 /* Next Data is a reception (Rx). Tx not allowed */
1237 txallowed = 0U;
1238
1239 #if (USE_SPI_CRC != 0U)
1240 /* Enable CRC Transmission */
1241 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1242 {
1243 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1244 }
1245 #endif /* USE_SPI_CRC */
1246 }
1247
1248 /* Wait until RXNE flag is reset */
1249 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1250 {
1251 (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
1252 hspi->pRxBuffPtr++;
1253 hspi->RxXferCount--;
1254 /* Next Data is a Transmission (Tx). Tx is allowed */
1255 txallowed = 1U;
1256 }
1257 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1258 {
1259 errorcode = HAL_TIMEOUT;
1260 goto error;
1261 }
1262 }
1263 }
1264
1265 #if (USE_SPI_CRC != 0U)
1266 /* Read CRC from DR to close CRC calculation process */
1267 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1268 {
1269 /* Wait until TXE flag */
1270 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1271 {
1272 /* Error on the CRC reception */
1273 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1274 errorcode = HAL_TIMEOUT;
1275 goto error;
1276 }
1277 /* Read CRC */
1278 READ_REG(hspi->Instance->DR);
1279 }
1280
1281 /* Check if CRC error occurred */
1282 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1283 {
1284 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1285 /* Clear CRC Flag */
1286 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1287
1288 errorcode = HAL_ERROR;
1289 }
1290 #endif /* USE_SPI_CRC */
1291
1292 /* Check the end of the transaction */
1293 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1294 {
1295 errorcode = HAL_ERROR;
1296 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1297 goto error;
1298 }
1299
1300 /* Clear overrun flag in 2 Lines communication mode because received is not read */
1301 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
1302 {
1303 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1304 }
1305
1306 error :
1307 hspi->State = HAL_SPI_STATE_READY;
1308 __HAL_UNLOCK(hspi);
1309 return errorcode;
1310 }
1311
1312 /**
1313 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1314 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1315 * the configuration information for SPI module.
1316 * @param pData pointer to data buffer
1317 * @param Size amount of data to be sent
1318 * @retval HAL status
1319 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1320 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1321 {
1322 HAL_StatusTypeDef errorcode = HAL_OK;
1323
1324 /* Check Direction parameter */
1325 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1326
1327 /* Process Locked */
1328 __HAL_LOCK(hspi);
1329
1330 if ((pData == NULL) || (Size == 0U))
1331 {
1332 errorcode = HAL_ERROR;
1333 goto error;
1334 }
1335
1336 if (hspi->State != HAL_SPI_STATE_READY)
1337 {
1338 errorcode = HAL_BUSY;
1339 goto error;
1340 }
1341
1342 /* Set the transaction information */
1343 hspi->State = HAL_SPI_STATE_BUSY_TX;
1344 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1345 hspi->pTxBuffPtr = (uint8_t *)pData;
1346 hspi->TxXferSize = Size;
1347 hspi->TxXferCount = Size;
1348
1349 /* Init field not used in handle to zero */
1350 hspi->pRxBuffPtr = (uint8_t *)NULL;
1351 hspi->RxXferSize = 0U;
1352 hspi->RxXferCount = 0U;
1353 hspi->RxISR = NULL;
1354
1355 /* Set the function for IT treatment */
1356 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1357 {
1358 hspi->TxISR = SPI_TxISR_16BIT;
1359 }
1360 else
1361 {
1362 hspi->TxISR = SPI_TxISR_8BIT;
1363 }
1364
1365 /* Configure communication direction : 1Line */
1366 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1367 {
1368 SPI_1LINE_TX(hspi);
1369 }
1370
1371 #if (USE_SPI_CRC != 0U)
1372 /* Reset CRC Calculation */
1373 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1374 {
1375 SPI_RESET_CRC(hspi);
1376 }
1377 #endif /* USE_SPI_CRC */
1378
1379 /* Enable TXE and ERR interrupt */
1380 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1381
1382
1383 /* Check if the SPI is already enabled */
1384 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1385 {
1386 /* Enable SPI peripheral */
1387 __HAL_SPI_ENABLE(hspi);
1388 }
1389
1390 error :
1391 __HAL_UNLOCK(hspi);
1392 return errorcode;
1393 }
1394
1395 /**
1396 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1397 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1398 * the configuration information for SPI module.
1399 * @param pData pointer to data buffer
1400 * @param Size amount of data to be sent
1401 * @retval HAL status
1402 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1403 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1404 {
1405 HAL_StatusTypeDef errorcode = HAL_OK;
1406
1407 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1408 {
1409 hspi->State = HAL_SPI_STATE_BUSY_RX;
1410 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1411 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1412 }
1413
1414 /* Process Locked */
1415 __HAL_LOCK(hspi);
1416
1417 if (hspi->State != HAL_SPI_STATE_READY)
1418 {
1419 errorcode = HAL_BUSY;
1420 goto error;
1421 }
1422
1423 if ((pData == NULL) || (Size == 0U))
1424 {
1425 errorcode = HAL_ERROR;
1426 goto error;
1427 }
1428
1429 /* Set the transaction information */
1430 hspi->State = HAL_SPI_STATE_BUSY_RX;
1431 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1432 hspi->pRxBuffPtr = (uint8_t *)pData;
1433 hspi->RxXferSize = Size;
1434 hspi->RxXferCount = Size;
1435
1436 /* Init field not used in handle to zero */
1437 hspi->pTxBuffPtr = (uint8_t *)NULL;
1438 hspi->TxXferSize = 0U;
1439 hspi->TxXferCount = 0U;
1440 hspi->TxISR = NULL;
1441
1442 /* Set the function for IT treatment */
1443 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1444 {
1445 hspi->RxISR = SPI_RxISR_16BIT;
1446 }
1447 else
1448 {
1449 hspi->RxISR = SPI_RxISR_8BIT;
1450 }
1451
1452 /* Configure communication direction : 1Line */
1453 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1454 {
1455 SPI_1LINE_RX(hspi);
1456 }
1457
1458 #if (USE_SPI_CRC != 0U)
1459 /* Reset CRC Calculation */
1460 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1461 {
1462 SPI_RESET_CRC(hspi);
1463 }
1464 #endif /* USE_SPI_CRC */
1465
1466 /* Enable TXE and ERR interrupt */
1467 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1468
1469 /* Note : The SPI must be enabled after unlocking current process
1470 to avoid the risk of SPI interrupt handle execution before current
1471 process unlock */
1472
1473 /* Check if the SPI is already enabled */
1474 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1475 {
1476 /* Enable SPI peripheral */
1477 __HAL_SPI_ENABLE(hspi);
1478 }
1479
1480 error :
1481 /* Process Unlocked */
1482 __HAL_UNLOCK(hspi);
1483 return errorcode;
1484 }
1485
1486 /**
1487 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1488 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1489 * the configuration information for SPI module.
1490 * @param pTxData pointer to transmission data buffer
1491 * @param pRxData pointer to reception data buffer
1492 * @param Size amount of data to be sent and received
1493 * @retval HAL status
1494 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1495 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1496 {
1497 uint32_t tmp_mode;
1498 HAL_SPI_StateTypeDef tmp_state;
1499 HAL_StatusTypeDef errorcode = HAL_OK;
1500
1501 /* Check Direction parameter */
1502 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1503
1504 /* Process locked */
1505 __HAL_LOCK(hspi);
1506
1507 /* Init temporary variables */
1508 tmp_state = hspi->State;
1509 tmp_mode = hspi->Init.Mode;
1510
1511 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1512 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1513 {
1514 errorcode = HAL_BUSY;
1515 goto error;
1516 }
1517
1518 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1519 {
1520 errorcode = HAL_ERROR;
1521 goto error;
1522 }
1523
1524 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1525 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1526 {
1527 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1528 }
1529
1530 /* Set the transaction information */
1531 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1532 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1533 hspi->TxXferSize = Size;
1534 hspi->TxXferCount = Size;
1535 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1536 hspi->RxXferSize = Size;
1537 hspi->RxXferCount = Size;
1538
1539 /* Set the function for IT treatment */
1540 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1541 {
1542 hspi->RxISR = SPI_2linesRxISR_16BIT;
1543 hspi->TxISR = SPI_2linesTxISR_16BIT;
1544 }
1545 else
1546 {
1547 hspi->RxISR = SPI_2linesRxISR_8BIT;
1548 hspi->TxISR = SPI_2linesTxISR_8BIT;
1549 }
1550
1551 #if (USE_SPI_CRC != 0U)
1552 /* Reset CRC Calculation */
1553 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1554 {
1555 SPI_RESET_CRC(hspi);
1556 }
1557 #endif /* USE_SPI_CRC */
1558
1559 /* Enable TXE, RXNE and ERR interrupt */
1560 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1561
1562 /* Check if the SPI is already enabled */
1563 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1564 {
1565 /* Enable SPI peripheral */
1566 __HAL_SPI_ENABLE(hspi);
1567 }
1568
1569 error :
1570 /* Process Unlocked */
1571 __HAL_UNLOCK(hspi);
1572 return errorcode;
1573 }
1574
1575 /**
1576 * @brief Transmit an amount of data in non-blocking mode with DMA.
1577 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1578 * the configuration information for SPI module.
1579 * @param pData pointer to data buffer
1580 * @param Size amount of data to be sent
1581 * @retval HAL status
1582 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1583 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1584 {
1585 HAL_StatusTypeDef errorcode = HAL_OK;
1586
1587 /* Check tx dma handle */
1588 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1589
1590 /* Check Direction parameter */
1591 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1592
1593 /* Process Locked */
1594 __HAL_LOCK(hspi);
1595
1596 if (hspi->State != HAL_SPI_STATE_READY)
1597 {
1598 errorcode = HAL_BUSY;
1599 goto error;
1600 }
1601
1602 if ((pData == NULL) || (Size == 0U))
1603 {
1604 errorcode = HAL_ERROR;
1605 goto error;
1606 }
1607
1608 /* Set the transaction information */
1609 hspi->State = HAL_SPI_STATE_BUSY_TX;
1610 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1611 hspi->pTxBuffPtr = (uint8_t *)pData;
1612 hspi->TxXferSize = Size;
1613 hspi->TxXferCount = Size;
1614
1615 /* Init field not used in handle to zero */
1616 hspi->pRxBuffPtr = (uint8_t *)NULL;
1617 hspi->TxISR = NULL;
1618 hspi->RxISR = NULL;
1619 hspi->RxXferSize = 0U;
1620 hspi->RxXferCount = 0U;
1621
1622 /* Configure communication direction : 1Line */
1623 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1624 {
1625 SPI_1LINE_TX(hspi);
1626 }
1627
1628 #if (USE_SPI_CRC != 0U)
1629 /* Reset CRC Calculation */
1630 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1631 {
1632 SPI_RESET_CRC(hspi);
1633 }
1634 #endif /* USE_SPI_CRC */
1635
1636 /* Set the SPI TxDMA Half transfer complete callback */
1637 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1638
1639 /* Set the SPI TxDMA transfer complete callback */
1640 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1641
1642 /* Set the DMA error callback */
1643 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1644
1645 /* Set the DMA AbortCpltCallback */
1646 hspi->hdmatx->XferAbortCallback = NULL;
1647
1648 /* Enable the Tx DMA Stream/Channel */
1649 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1650 hspi->TxXferCount))
1651 {
1652 /* Update SPI error code */
1653 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1654 errorcode = HAL_ERROR;
1655
1656 hspi->State = HAL_SPI_STATE_READY;
1657 goto error;
1658 }
1659
1660 /* Check if the SPI is already enabled */
1661 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1662 {
1663 /* Enable SPI peripheral */
1664 __HAL_SPI_ENABLE(hspi);
1665 }
1666
1667 /* Enable the SPI Error Interrupt Bit */
1668 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1669
1670 /* Enable Tx DMA Request */
1671 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1672
1673 error :
1674 /* Process Unlocked */
1675 __HAL_UNLOCK(hspi);
1676 return errorcode;
1677 }
1678
1679 /**
1680 * @brief Receive an amount of data in non-blocking mode with DMA.
1681 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1682 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1683 * the configuration information for SPI module.
1684 * @param pData pointer to data buffer
1685 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1686 * @param Size amount of data to be sent
1687 * @retval HAL status
1688 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1689 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1690 {
1691 HAL_StatusTypeDef errorcode = HAL_OK;
1692
1693 /* Check rx dma handle */
1694 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1695
1696 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1697 {
1698 hspi->State = HAL_SPI_STATE_BUSY_RX;
1699
1700 /* Check tx dma handle */
1701 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1702
1703 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1704 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1705 }
1706
1707 /* Process Locked */
1708 __HAL_LOCK(hspi);
1709
1710 if (hspi->State != HAL_SPI_STATE_READY)
1711 {
1712 errorcode = HAL_BUSY;
1713 goto error;
1714 }
1715
1716 if ((pData == NULL) || (Size == 0U))
1717 {
1718 errorcode = HAL_ERROR;
1719 goto error;
1720 }
1721
1722 /* Set the transaction information */
1723 hspi->State = HAL_SPI_STATE_BUSY_RX;
1724 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1725 hspi->pRxBuffPtr = (uint8_t *)pData;
1726 hspi->RxXferSize = Size;
1727 hspi->RxXferCount = Size;
1728
1729 /*Init field not used in handle to zero */
1730 hspi->RxISR = NULL;
1731 hspi->TxISR = NULL;
1732 hspi->TxXferSize = 0U;
1733 hspi->TxXferCount = 0U;
1734
1735 /* Configure communication direction : 1Line */
1736 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1737 {
1738 SPI_1LINE_RX(hspi);
1739 }
1740
1741 #if (USE_SPI_CRC != 0U)
1742 /* Reset CRC Calculation */
1743 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1744 {
1745 SPI_RESET_CRC(hspi);
1746 }
1747 #endif /* USE_SPI_CRC */
1748
1749 /* Set the SPI RxDMA Half transfer complete callback */
1750 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1751
1752 /* Set the SPI Rx DMA transfer complete callback */
1753 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1754
1755 /* Set the DMA error callback */
1756 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1757
1758 /* Set the DMA AbortCpltCallback */
1759 hspi->hdmarx->XferAbortCallback = NULL;
1760
1761 /* Enable the Rx DMA Stream/Channel */
1762 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
1763 hspi->RxXferCount))
1764 {
1765 /* Update SPI error code */
1766 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1767 errorcode = HAL_ERROR;
1768
1769 hspi->State = HAL_SPI_STATE_READY;
1770 goto error;
1771 }
1772
1773 /* Check if the SPI is already enabled */
1774 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1775 {
1776 /* Enable SPI peripheral */
1777 __HAL_SPI_ENABLE(hspi);
1778 }
1779
1780 /* Enable the SPI Error Interrupt Bit */
1781 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1782
1783 /* Enable Rx DMA Request */
1784 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1785
1786 error:
1787 /* Process Unlocked */
1788 __HAL_UNLOCK(hspi);
1789 return errorcode;
1790 }
1791
1792 /**
1793 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
1794 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1795 * the configuration information for SPI module.
1796 * @param pTxData pointer to transmission data buffer
1797 * @param pRxData pointer to reception data buffer
1798 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
1799 * @param Size amount of data to be sent
1800 * @retval HAL status
1801 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1802 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
1803 uint16_t Size)
1804 {
1805 uint32_t tmp_mode;
1806 HAL_SPI_StateTypeDef tmp_state;
1807 HAL_StatusTypeDef errorcode = HAL_OK;
1808
1809 /* Check rx & tx dma handles */
1810 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1811 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1812
1813 /* Check Direction parameter */
1814 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1815
1816 /* Process locked */
1817 __HAL_LOCK(hspi);
1818
1819 /* Init temporary variables */
1820 tmp_state = hspi->State;
1821 tmp_mode = hspi->Init.Mode;
1822
1823 if (!((tmp_state == HAL_SPI_STATE_READY) ||
1824 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1825 {
1826 errorcode = HAL_BUSY;
1827 goto error;
1828 }
1829
1830 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1831 {
1832 errorcode = HAL_ERROR;
1833 goto error;
1834 }
1835
1836 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1837 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1838 {
1839 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1840 }
1841
1842 /* Set the transaction information */
1843 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1844 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1845 hspi->TxXferSize = Size;
1846 hspi->TxXferCount = Size;
1847 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1848 hspi->RxXferSize = Size;
1849 hspi->RxXferCount = Size;
1850
1851 /* Init field not used in handle to zero */
1852 hspi->RxISR = NULL;
1853 hspi->TxISR = NULL;
1854
1855 #if (USE_SPI_CRC != 0U)
1856 /* Reset CRC Calculation */
1857 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1858 {
1859 SPI_RESET_CRC(hspi);
1860 }
1861 #endif /* USE_SPI_CRC */
1862
1863 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
1864 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
1865 {
1866 /* Set the SPI Rx DMA Half transfer complete callback */
1867 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1868 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1869 }
1870 else
1871 {
1872 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
1873 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1874 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
1875 }
1876
1877 /* Set the DMA error callback */
1878 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1879
1880 /* Set the DMA AbortCpltCallback */
1881 hspi->hdmarx->XferAbortCallback = NULL;
1882
1883 /* Enable the Rx DMA Stream/Channel */
1884 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
1885 hspi->RxXferCount))
1886 {
1887 /* Update SPI error code */
1888 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1889 errorcode = HAL_ERROR;
1890
1891 hspi->State = HAL_SPI_STATE_READY;
1892 goto error;
1893 }
1894
1895 /* Enable Rx DMA Request */
1896 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1897
1898 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1899 is performed in DMA reception complete callback */
1900 hspi->hdmatx->XferHalfCpltCallback = NULL;
1901 hspi->hdmatx->XferCpltCallback = NULL;
1902 hspi->hdmatx->XferErrorCallback = NULL;
1903 hspi->hdmatx->XferAbortCallback = NULL;
1904
1905 /* Enable the Tx DMA Stream/Channel */
1906 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1907 hspi->TxXferCount))
1908 {
1909 /* Update SPI error code */
1910 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1911 errorcode = HAL_ERROR;
1912
1913 hspi->State = HAL_SPI_STATE_READY;
1914 goto error;
1915 }
1916
1917 /* Check if the SPI is already enabled */
1918 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1919 {
1920 /* Enable SPI peripheral */
1921 __HAL_SPI_ENABLE(hspi);
1922 }
1923 /* Enable the SPI Error Interrupt Bit */
1924 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1925
1926 /* Enable Tx DMA Request */
1927 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1928
1929 error :
1930 /* Process Unlocked */
1931 __HAL_UNLOCK(hspi);
1932 return errorcode;
1933 }
1934
1935 /**
1936 * @brief Abort ongoing transfer (blocking mode).
1937 * @param hspi SPI handle.
1938 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
1939 * started in Interrupt or DMA mode.
1940 * This procedure performs following operations :
1941 * - Disable SPI Interrupts (depending of transfer direction)
1942 * - Disable the DMA transfer in the peripheral register (if enabled)
1943 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
1944 * - Set handle State to READY
1945 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
1946 * @retval HAL status
1947 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)1948 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
1949 {
1950 HAL_StatusTypeDef errorcode;
1951 __IO uint32_t count;
1952 __IO uint32_t resetcount;
1953
1954 /* Initialized local variable */
1955 errorcode = HAL_OK;
1956 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
1957 count = resetcount;
1958
1959 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
1960 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1961
1962 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
1963 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
1964 {
1965 hspi->TxISR = SPI_AbortTx_ISR;
1966 /* Wait HAL_SPI_STATE_ABORT state */
1967 do
1968 {
1969 if (count == 0U)
1970 {
1971 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
1972 break;
1973 }
1974 count--;
1975 } while (hspi->State != HAL_SPI_STATE_ABORT);
1976 /* Reset Timeout Counter */
1977 count = resetcount;
1978 }
1979
1980 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
1981 {
1982 hspi->RxISR = SPI_AbortRx_ISR;
1983 /* Wait HAL_SPI_STATE_ABORT state */
1984 do
1985 {
1986 if (count == 0U)
1987 {
1988 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
1989 break;
1990 }
1991 count--;
1992 } while (hspi->State != HAL_SPI_STATE_ABORT);
1993 /* Reset Timeout Counter */
1994 count = resetcount;
1995 }
1996
1997 /* Disable the SPI DMA Tx request if enabled */
1998 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
1999 {
2000 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2001 if (hspi->hdmatx != NULL)
2002 {
2003 /* Set the SPI DMA Abort callback :
2004 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2005 hspi->hdmatx->XferAbortCallback = NULL;
2006
2007 /* Abort DMA Tx Handle linked to SPI Peripheral */
2008 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2009 {
2010 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2011 }
2012
2013 /* Disable Tx DMA Request */
2014 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2015
2016 /* Wait until TXE flag is set */
2017 do
2018 {
2019 if (count == 0U)
2020 {
2021 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2022 break;
2023 }
2024 count--;
2025 } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2026 }
2027 }
2028
2029 /* Disable the SPI DMA Rx request if enabled */
2030 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2031 {
2032 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2033 if (hspi->hdmarx != NULL)
2034 {
2035 /* Set the SPI DMA Abort callback :
2036 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2037 hspi->hdmarx->XferAbortCallback = NULL;
2038
2039 /* Abort DMA Rx Handle linked to SPI Peripheral */
2040 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2041 {
2042 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2043 }
2044
2045 /* Disable peripheral */
2046 __HAL_SPI_DISABLE(hspi);
2047
2048 /* Disable Rx DMA Request */
2049 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2050 }
2051 }
2052 /* Reset Tx and Rx transfer counters */
2053 hspi->RxXferCount = 0U;
2054 hspi->TxXferCount = 0U;
2055
2056 /* Check error during Abort procedure */
2057 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2058 {
2059 /* return HAL_Error in case of error during Abort procedure */
2060 errorcode = HAL_ERROR;
2061 }
2062 else
2063 {
2064 /* Reset errorCode */
2065 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2066 }
2067
2068 /* Clear the Error flags in the SR register */
2069 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2070 __HAL_SPI_CLEAR_FREFLAG(hspi);
2071
2072 /* Restore hspi->state to ready */
2073 hspi->State = HAL_SPI_STATE_READY;
2074
2075 return errorcode;
2076 }
2077
2078 /**
2079 * @brief Abort ongoing transfer (Interrupt mode).
2080 * @param hspi SPI handle.
2081 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2082 * started in Interrupt or DMA mode.
2083 * This procedure performs following operations :
2084 * - Disable SPI Interrupts (depending of transfer direction)
2085 * - Disable the DMA transfer in the peripheral register (if enabled)
2086 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2087 * - Set handle State to READY
2088 * - At abort completion, call user abort complete callback
2089 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2090 * considered as completed only when user abort complete callback is executed (not when exiting function).
2091 * @retval HAL status
2092 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2093 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2094 {
2095 HAL_StatusTypeDef errorcode;
2096 uint32_t abortcplt ;
2097 __IO uint32_t count;
2098 __IO uint32_t resetcount;
2099
2100 /* Initialized local variable */
2101 errorcode = HAL_OK;
2102 abortcplt = 1U;
2103 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2104 count = resetcount;
2105
2106 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2107 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2108
2109 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2110 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2111 {
2112 hspi->TxISR = SPI_AbortTx_ISR;
2113 /* Wait HAL_SPI_STATE_ABORT state */
2114 do
2115 {
2116 if (count == 0U)
2117 {
2118 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2119 break;
2120 }
2121 count--;
2122 } while (hspi->State != HAL_SPI_STATE_ABORT);
2123 /* Reset Timeout Counter */
2124 count = resetcount;
2125 }
2126
2127 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2128 {
2129 hspi->RxISR = SPI_AbortRx_ISR;
2130 /* Wait HAL_SPI_STATE_ABORT state */
2131 do
2132 {
2133 if (count == 0U)
2134 {
2135 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2136 break;
2137 }
2138 count--;
2139 } while (hspi->State != HAL_SPI_STATE_ABORT);
2140 /* Reset Timeout Counter */
2141 count = resetcount;
2142 }
2143
2144 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2145 before any call to DMA Abort functions */
2146 /* DMA Tx Handle is valid */
2147 if (hspi->hdmatx != NULL)
2148 {
2149 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2150 Otherwise, set it to NULL */
2151 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2152 {
2153 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2154 }
2155 else
2156 {
2157 hspi->hdmatx->XferAbortCallback = NULL;
2158 }
2159 }
2160 /* DMA Rx Handle is valid */
2161 if (hspi->hdmarx != NULL)
2162 {
2163 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2164 Otherwise, set it to NULL */
2165 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2166 {
2167 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2168 }
2169 else
2170 {
2171 hspi->hdmarx->XferAbortCallback = NULL;
2172 }
2173 }
2174
2175 /* Disable the SPI DMA Tx request if enabled */
2176 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2177 {
2178 /* Abort the SPI DMA Tx Stream/Channel */
2179 if (hspi->hdmatx != NULL)
2180 {
2181 /* Abort DMA Tx Handle linked to SPI Peripheral */
2182 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2183 {
2184 hspi->hdmatx->XferAbortCallback = NULL;
2185 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2186 }
2187 else
2188 {
2189 abortcplt = 0U;
2190 }
2191 }
2192 }
2193 /* Disable the SPI DMA Rx request if enabled */
2194 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2195 {
2196 /* Abort the SPI DMA Rx Stream/Channel */
2197 if (hspi->hdmarx != NULL)
2198 {
2199 /* Abort DMA Rx Handle linked to SPI Peripheral */
2200 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2201 {
2202 hspi->hdmarx->XferAbortCallback = NULL;
2203 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2204 }
2205 else
2206 {
2207 abortcplt = 0U;
2208 }
2209 }
2210 }
2211
2212 if (abortcplt == 1U)
2213 {
2214 /* Reset Tx and Rx transfer counters */
2215 hspi->RxXferCount = 0U;
2216 hspi->TxXferCount = 0U;
2217
2218 /* Check error during Abort procedure */
2219 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2220 {
2221 /* return HAL_Error in case of error during Abort procedure */
2222 errorcode = HAL_ERROR;
2223 }
2224 else
2225 {
2226 /* Reset errorCode */
2227 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2228 }
2229
2230 /* Clear the Error flags in the SR register */
2231 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2232 __HAL_SPI_CLEAR_FREFLAG(hspi);
2233
2234 /* Restore hspi->State to Ready */
2235 hspi->State = HAL_SPI_STATE_READY;
2236
2237 /* As no DMA to be aborted, call directly user Abort complete callback */
2238 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2239 hspi->AbortCpltCallback(hspi);
2240 #else
2241 HAL_SPI_AbortCpltCallback(hspi);
2242 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2243 }
2244
2245 return errorcode;
2246 }
2247
2248 /**
2249 * @brief Pause the DMA Transfer.
2250 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2251 * the configuration information for the specified SPI module.
2252 * @retval HAL status
2253 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2254 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2255 {
2256 /* Process Locked */
2257 __HAL_LOCK(hspi);
2258
2259 /* Disable the SPI DMA Tx & Rx requests */
2260 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2261
2262 /* Process Unlocked */
2263 __HAL_UNLOCK(hspi);
2264
2265 return HAL_OK;
2266 }
2267
2268 /**
2269 * @brief Resume the DMA Transfer.
2270 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2271 * the configuration information for the specified SPI module.
2272 * @retval HAL status
2273 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2274 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2275 {
2276 /* Process Locked */
2277 __HAL_LOCK(hspi);
2278
2279 /* Enable the SPI DMA Tx & Rx requests */
2280 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2281
2282 /* Process Unlocked */
2283 __HAL_UNLOCK(hspi);
2284
2285 return HAL_OK;
2286 }
2287
2288 /**
2289 * @brief Stop the DMA Transfer.
2290 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2291 * the configuration information for the specified SPI module.
2292 * @retval HAL status
2293 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2294 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2295 {
2296 HAL_StatusTypeDef errorcode = HAL_OK;
2297 /* The Lock is not implemented on this API to allow the user application
2298 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2299 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2300 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2301 */
2302
2303 /* Abort the SPI DMA tx Stream/Channel */
2304 if (hspi->hdmatx != NULL)
2305 {
2306 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2307 {
2308 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2309 errorcode = HAL_ERROR;
2310 }
2311 }
2312 /* Abort the SPI DMA rx Stream/Channel */
2313 if (hspi->hdmarx != NULL)
2314 {
2315 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2316 {
2317 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2318 errorcode = HAL_ERROR;
2319 }
2320 }
2321
2322 /* Disable the SPI DMA Tx & Rx requests */
2323 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2324 hspi->State = HAL_SPI_STATE_READY;
2325 return errorcode;
2326 }
2327
2328 /**
2329 * @brief Handle SPI interrupt request.
2330 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2331 * the configuration information for the specified SPI module.
2332 * @retval None
2333 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2334 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2335 {
2336 uint32_t itsource = hspi->Instance->CR2;
2337 uint32_t itflag = hspi->Instance->SR;
2338
2339 /* SPI in mode Receiver ----------------------------------------------------*/
2340 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2341 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2342 {
2343 hspi->RxISR(hspi);
2344 return;
2345 }
2346
2347 /* SPI in mode Transmitter -------------------------------------------------*/
2348 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2349 {
2350 hspi->TxISR(hspi);
2351 return;
2352 }
2353
2354 /* SPI in Error Treatment --------------------------------------------------*/
2355 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2356 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2357 {
2358 /* SPI Overrun error interrupt occurred ----------------------------------*/
2359 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2360 {
2361 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2362 {
2363 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2364 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2365 }
2366 else
2367 {
2368 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2369 return;
2370 }
2371 }
2372
2373 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2374 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2375 {
2376 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2377 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2378 }
2379
2380 /* SPI Frame error interrupt occurred ------------------------------------*/
2381 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2382 {
2383 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2384 __HAL_SPI_CLEAR_FREFLAG(hspi);
2385 }
2386
2387 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2388 {
2389 /* Disable all interrupts */
2390 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2391
2392 hspi->State = HAL_SPI_STATE_READY;
2393 /* Disable the SPI DMA requests if enabled */
2394 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2395 {
2396 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2397
2398 /* Abort the SPI DMA Rx channel */
2399 if (hspi->hdmarx != NULL)
2400 {
2401 /* Set the SPI DMA Abort callback :
2402 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2403 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2404 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2405 {
2406 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2407 }
2408 }
2409 /* Abort the SPI DMA Tx channel */
2410 if (hspi->hdmatx != NULL)
2411 {
2412 /* Set the SPI DMA Abort callback :
2413 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2414 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2415 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2416 {
2417 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2418 }
2419 }
2420 }
2421 else
2422 {
2423 /* Call user error callback */
2424 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2425 hspi->ErrorCallback(hspi);
2426 #else
2427 HAL_SPI_ErrorCallback(hspi);
2428 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2429 }
2430 }
2431 return;
2432 }
2433 }
2434
2435 /**
2436 * @brief Tx Transfer completed callback.
2437 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2438 * the configuration information for SPI module.
2439 * @retval None
2440 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2441 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2442 {
2443 /* Prevent unused argument(s) compilation warning */
2444 UNUSED(hspi);
2445
2446 /* NOTE : This function should not be modified, when the callback is needed,
2447 the HAL_SPI_TxCpltCallback should be implemented in the user file
2448 */
2449 }
2450
2451 /**
2452 * @brief Rx Transfer completed callback.
2453 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2454 * the configuration information for SPI module.
2455 * @retval None
2456 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2457 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2458 {
2459 /* Prevent unused argument(s) compilation warning */
2460 UNUSED(hspi);
2461
2462 /* NOTE : This function should not be modified, when the callback is needed,
2463 the HAL_SPI_RxCpltCallback should be implemented in the user file
2464 */
2465 }
2466
2467 /**
2468 * @brief Tx and Rx Transfer completed callback.
2469 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2470 * the configuration information for SPI module.
2471 * @retval None
2472 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2473 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2474 {
2475 /* Prevent unused argument(s) compilation warning */
2476 UNUSED(hspi);
2477
2478 /* NOTE : This function should not be modified, when the callback is needed,
2479 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2480 */
2481 }
2482
2483 /**
2484 * @brief Tx Half Transfer completed callback.
2485 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2486 * the configuration information for SPI module.
2487 * @retval None
2488 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2489 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2490 {
2491 /* Prevent unused argument(s) compilation warning */
2492 UNUSED(hspi);
2493
2494 /* NOTE : This function should not be modified, when the callback is needed,
2495 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2496 */
2497 }
2498
2499 /**
2500 * @brief Rx Half Transfer completed callback.
2501 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2502 * the configuration information for SPI module.
2503 * @retval None
2504 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2505 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2506 {
2507 /* Prevent unused argument(s) compilation warning */
2508 UNUSED(hspi);
2509
2510 /* NOTE : This function should not be modified, when the callback is needed,
2511 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2512 */
2513 }
2514
2515 /**
2516 * @brief Tx and Rx Half Transfer callback.
2517 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2518 * the configuration information for SPI module.
2519 * @retval None
2520 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2521 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2522 {
2523 /* Prevent unused argument(s) compilation warning */
2524 UNUSED(hspi);
2525
2526 /* NOTE : This function should not be modified, when the callback is needed,
2527 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2528 */
2529 }
2530
2531 /**
2532 * @brief SPI error callback.
2533 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2534 * the configuration information for SPI module.
2535 * @retval None
2536 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2537 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2538 {
2539 /* Prevent unused argument(s) compilation warning */
2540 UNUSED(hspi);
2541
2542 /* NOTE : This function should not be modified, when the callback is needed,
2543 the HAL_SPI_ErrorCallback should be implemented in the user file
2544 */
2545 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2546 and user can use HAL_SPI_GetError() API to check the latest error occurred
2547 */
2548 }
2549
2550 /**
2551 * @brief SPI Abort Complete callback.
2552 * @param hspi SPI handle.
2553 * @retval None
2554 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2555 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2556 {
2557 /* Prevent unused argument(s) compilation warning */
2558 UNUSED(hspi);
2559
2560 /* NOTE : This function should not be modified, when the callback is needed,
2561 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2562 */
2563 }
2564
2565 /**
2566 * @}
2567 */
2568
2569 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2570 * @brief SPI control functions
2571 *
2572 @verbatim
2573 ===============================================================================
2574 ##### Peripheral State and Errors functions #####
2575 ===============================================================================
2576 [..]
2577 This subsection provides a set of functions allowing to control the SPI.
2578 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2579 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2580 @endverbatim
2581 * @{
2582 */
2583
2584 /**
2585 * @brief Return the SPI handle state.
2586 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2587 * the configuration information for SPI module.
2588 * @retval SPI state
2589 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2590 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2591 {
2592 /* Return SPI handle state */
2593 return hspi->State;
2594 }
2595
2596 /**
2597 * @brief Return the SPI error code.
2598 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2599 * the configuration information for SPI module.
2600 * @retval SPI error code in bitmap format
2601 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2602 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2603 {
2604 /* Return SPI ErrorCode */
2605 return hspi->ErrorCode;
2606 }
2607
2608 /**
2609 * @}
2610 */
2611
2612 /**
2613 * @}
2614 */
2615
2616 /** @addtogroup SPI_Private_Functions
2617 * @brief Private functions
2618 * @{
2619 */
2620
2621 /**
2622 * @brief DMA SPI transmit process complete callback.
2623 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2624 * the configuration information for the specified DMA module.
2625 * @retval None
2626 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2627 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2628 {
2629 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2630 uint32_t tickstart;
2631
2632 /* Init tickstart for timeout management*/
2633 tickstart = HAL_GetTick();
2634
2635 /* DMA Normal Mode */
2636 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
2637 {
2638 /* Disable ERR interrupt */
2639 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2640
2641 /* Disable Tx DMA Request */
2642 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2643
2644 /* Check the end of the transaction */
2645 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2646 {
2647 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2648 }
2649
2650 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2651 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2652 {
2653 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2654 }
2655
2656 hspi->TxXferCount = 0U;
2657 hspi->State = HAL_SPI_STATE_READY;
2658
2659 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2660 {
2661 /* Call user error callback */
2662 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2663 hspi->ErrorCallback(hspi);
2664 #else
2665 HAL_SPI_ErrorCallback(hspi);
2666 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2667 return;
2668 }
2669 }
2670 /* Call user Tx complete callback */
2671 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2672 hspi->TxCpltCallback(hspi);
2673 #else
2674 HAL_SPI_TxCpltCallback(hspi);
2675 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2676 }
2677
2678 /**
2679 * @brief DMA SPI receive process complete callback.
2680 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2681 * the configuration information for the specified DMA module.
2682 * @retval None
2683 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)2684 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2685 {
2686 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2687 uint32_t tickstart;
2688
2689 /* Init tickstart for timeout management*/
2690 tickstart = HAL_GetTick();
2691
2692 /* DMA Normal Mode */
2693 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
2694 {
2695 /* Disable ERR interrupt */
2696 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2697
2698 #if (USE_SPI_CRC != 0U)
2699 /* CRC handling */
2700 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2701 {
2702 /* Wait until RXNE flag */
2703 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2704 {
2705 /* Error on the CRC reception */
2706 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2707 }
2708 /* Read CRC */
2709 READ_REG(hspi->Instance->DR);
2710 }
2711 #endif /* USE_SPI_CRC */
2712
2713 /* Check if we are in Master RX 2 line mode */
2714 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
2715 {
2716 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
2717 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2718 }
2719 else
2720 {
2721 /* Normal case */
2722 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2723 }
2724
2725 /* Check the end of the transaction */
2726 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2727 {
2728 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
2729 }
2730
2731 hspi->RxXferCount = 0U;
2732 hspi->State = HAL_SPI_STATE_READY;
2733
2734 #if (USE_SPI_CRC != 0U)
2735 /* Check if CRC error occurred */
2736 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
2737 {
2738 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2739 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2740 }
2741 #endif /* USE_SPI_CRC */
2742
2743 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2744 {
2745 /* Call user error callback */
2746 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2747 hspi->ErrorCallback(hspi);
2748 #else
2749 HAL_SPI_ErrorCallback(hspi);
2750 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2751 return;
2752 }
2753 }
2754 /* Call user Rx complete callback */
2755 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2756 hspi->RxCpltCallback(hspi);
2757 #else
2758 HAL_SPI_RxCpltCallback(hspi);
2759 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2760 }
2761
2762 /**
2763 * @brief DMA SPI transmit receive process complete callback.
2764 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2765 * the configuration information for the specified DMA module.
2766 * @retval None
2767 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)2768 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2769 {
2770 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2771 uint32_t tickstart;
2772
2773 /* Init tickstart for timeout management*/
2774 tickstart = HAL_GetTick();
2775
2776 /* DMA Normal Mode */
2777 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
2778 {
2779 /* Disable ERR interrupt */
2780 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2781
2782 #if (USE_SPI_CRC != 0U)
2783 /* CRC handling */
2784 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2785 {
2786 /* Wait the CRC data */
2787 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2788 {
2789 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2790 }
2791 /* Read CRC to Flush DR and RXNE flag */
2792 READ_REG(hspi->Instance->DR);
2793 }
2794 #endif /* USE_SPI_CRC */
2795
2796 /* Check the end of the transaction */
2797 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2798 {
2799 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2800 }
2801
2802 /* Disable Rx/Tx DMA Request */
2803 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2804
2805 hspi->TxXferCount = 0U;
2806 hspi->RxXferCount = 0U;
2807 hspi->State = HAL_SPI_STATE_READY;
2808
2809 #if (USE_SPI_CRC != 0U)
2810 /* Check if CRC error occurred */
2811 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
2812 {
2813 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2814 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2815 }
2816 #endif /* USE_SPI_CRC */
2817
2818 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2819 {
2820 /* Call user error callback */
2821 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2822 hspi->ErrorCallback(hspi);
2823 #else
2824 HAL_SPI_ErrorCallback(hspi);
2825 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2826 return;
2827 }
2828 }
2829 /* Call user TxRx complete callback */
2830 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2831 hspi->TxRxCpltCallback(hspi);
2832 #else
2833 HAL_SPI_TxRxCpltCallback(hspi);
2834 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2835 }
2836
2837 /**
2838 * @brief DMA SPI half transmit process complete callback.
2839 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2840 * the configuration information for the specified DMA module.
2841 * @retval None
2842 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)2843 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2844 {
2845 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2846
2847 /* Call user Tx half complete callback */
2848 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2849 hspi->TxHalfCpltCallback(hspi);
2850 #else
2851 HAL_SPI_TxHalfCpltCallback(hspi);
2852 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2853 }
2854
2855 /**
2856 * @brief DMA SPI half receive process complete callback
2857 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2858 * the configuration information for the specified DMA module.
2859 * @retval None
2860 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)2861 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2862 {
2863 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2864
2865 /* Call user Rx half complete callback */
2866 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2867 hspi->RxHalfCpltCallback(hspi);
2868 #else
2869 HAL_SPI_RxHalfCpltCallback(hspi);
2870 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2871 }
2872
2873 /**
2874 * @brief DMA SPI half transmit receive process complete callback.
2875 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2876 * the configuration information for the specified DMA module.
2877 * @retval None
2878 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)2879 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2880 {
2881 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2882
2883 /* Call user TxRx half complete callback */
2884 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2885 hspi->TxRxHalfCpltCallback(hspi);
2886 #else
2887 HAL_SPI_TxRxHalfCpltCallback(hspi);
2888 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2889 }
2890
2891 /**
2892 * @brief DMA SPI communication error callback.
2893 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2894 * the configuration information for the specified DMA module.
2895 * @retval None
2896 */
SPI_DMAError(DMA_HandleTypeDef * hdma)2897 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2898 {
2899 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2900
2901 /* Stop the disable DMA transfer on SPI side */
2902 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2903
2904 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2905 hspi->State = HAL_SPI_STATE_READY;
2906 /* Call user error callback */
2907 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2908 hspi->ErrorCallback(hspi);
2909 #else
2910 HAL_SPI_ErrorCallback(hspi);
2911 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2912 }
2913
2914 /**
2915 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
2916 * (To be called at end of DMA Abort procedure following error occurrence).
2917 * @param hdma DMA handle.
2918 * @retval None
2919 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)2920 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
2921 {
2922 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2923 hspi->RxXferCount = 0U;
2924 hspi->TxXferCount = 0U;
2925
2926 /* Call user error callback */
2927 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2928 hspi->ErrorCallback(hspi);
2929 #else
2930 HAL_SPI_ErrorCallback(hspi);
2931 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2932 }
2933
2934 /**
2935 * @brief DMA SPI Tx communication abort callback, when initiated by user
2936 * (To be called at end of DMA Tx Abort procedure following user abort request).
2937 * @note When this callback is executed, User Abort complete call back is called only if no
2938 * Abort still ongoing for Rx DMA Handle.
2939 * @param hdma DMA handle.
2940 * @retval None
2941 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)2942 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
2943 {
2944 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2945 __IO uint32_t count;
2946
2947 hspi->hdmatx->XferAbortCallback = NULL;
2948 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2949
2950 /* Disable Tx DMA Request */
2951 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2952
2953 /* Wait until TXE flag is set */
2954 do
2955 {
2956 if (count == 0U)
2957 {
2958 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2959 break;
2960 }
2961 count--;
2962 } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2963
2964 /* Check if an Abort process is still ongoing */
2965 if (hspi->hdmarx != NULL)
2966 {
2967 if (hspi->hdmarx->XferAbortCallback != NULL)
2968 {
2969 return;
2970 }
2971 }
2972
2973 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
2974 hspi->RxXferCount = 0U;
2975 hspi->TxXferCount = 0U;
2976
2977 /* Check no error during Abort procedure */
2978 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
2979 {
2980 /* Reset errorCode */
2981 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2982 }
2983
2984 /* Clear the Error flags in the SR register */
2985 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2986 __HAL_SPI_CLEAR_FREFLAG(hspi);
2987
2988 /* Restore hspi->State to Ready */
2989 hspi->State = HAL_SPI_STATE_READY;
2990
2991 /* Call user Abort complete callback */
2992 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2993 hspi->AbortCpltCallback(hspi);
2994 #else
2995 HAL_SPI_AbortCpltCallback(hspi);
2996 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2997 }
2998
2999 /**
3000 * @brief DMA SPI Rx communication abort callback, when initiated by user
3001 * (To be called at end of DMA Rx Abort procedure following user abort request).
3002 * @note When this callback is executed, User Abort complete call back is called only if no
3003 * Abort still ongoing for Tx DMA Handle.
3004 * @param hdma DMA handle.
3005 * @retval None
3006 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3007 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3008 {
3009 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3010
3011 /* Disable SPI Peripheral */
3012 __HAL_SPI_DISABLE(hspi);
3013
3014 hspi->hdmarx->XferAbortCallback = NULL;
3015
3016 /* Disable Rx DMA Request */
3017 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3018
3019 /* Check Busy flag */
3020 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3021 {
3022 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3023 }
3024
3025 /* Check if an Abort process is still ongoing */
3026 if (hspi->hdmatx != NULL)
3027 {
3028 if (hspi->hdmatx->XferAbortCallback != NULL)
3029 {
3030 return;
3031 }
3032 }
3033
3034 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3035 hspi->RxXferCount = 0U;
3036 hspi->TxXferCount = 0U;
3037
3038 /* Check no error during Abort procedure */
3039 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3040 {
3041 /* Reset errorCode */
3042 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3043 }
3044
3045 /* Clear the Error flags in the SR register */
3046 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3047 __HAL_SPI_CLEAR_FREFLAG(hspi);
3048
3049 /* Restore hspi->State to Ready */
3050 hspi->State = HAL_SPI_STATE_READY;
3051
3052 /* Call user Abort complete callback */
3053 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3054 hspi->AbortCpltCallback(hspi);
3055 #else
3056 HAL_SPI_AbortCpltCallback(hspi);
3057 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3058 }
3059
3060 /**
3061 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3062 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3063 * the configuration information for SPI module.
3064 * @retval None
3065 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3066 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3067 {
3068 /* Receive data in 8bit mode */
3069 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3070 hspi->pRxBuffPtr++;
3071 hspi->RxXferCount--;
3072
3073 /* Check end of the reception */
3074 if (hspi->RxXferCount == 0U)
3075 {
3076 #if (USE_SPI_CRC != 0U)
3077 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3078 {
3079 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3080 return;
3081 }
3082 #endif /* USE_SPI_CRC */
3083
3084 /* Disable RXNE and ERR interrupt */
3085 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3086
3087 if (hspi->TxXferCount == 0U)
3088 {
3089 SPI_CloseRxTx_ISR(hspi);
3090 }
3091 }
3092 }
3093
3094 #if (USE_SPI_CRC != 0U)
3095 /**
3096 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3097 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3098 * the configuration information for SPI module.
3099 * @retval None
3100 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3101 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3102 {
3103 /* Read 8bit CRC to flush Data Regsiter */
3104 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3105
3106 /* Disable RXNE and ERR interrupt */
3107 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3108
3109 if (hspi->TxXferCount == 0U)
3110 {
3111 SPI_CloseRxTx_ISR(hspi);
3112 }
3113 }
3114 #endif /* USE_SPI_CRC */
3115
3116 /**
3117 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3118 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3119 * the configuration information for SPI module.
3120 * @retval None
3121 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3122 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3123 {
3124 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3125 hspi->pTxBuffPtr++;
3126 hspi->TxXferCount--;
3127
3128 /* Check the end of the transmission */
3129 if (hspi->TxXferCount == 0U)
3130 {
3131 #if (USE_SPI_CRC != 0U)
3132 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3133 {
3134 /* Set CRC Next Bit to send CRC */
3135 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3136 /* Disable TXE interrupt */
3137 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3138 return;
3139 }
3140 #endif /* USE_SPI_CRC */
3141
3142 /* Disable TXE interrupt */
3143 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3144
3145 if (hspi->RxXferCount == 0U)
3146 {
3147 SPI_CloseRxTx_ISR(hspi);
3148 }
3149 }
3150 }
3151
3152 /**
3153 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3154 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3155 * the configuration information for SPI module.
3156 * @retval None
3157 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3158 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3159 {
3160 /* Receive data in 16 Bit mode */
3161 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3162 hspi->pRxBuffPtr += sizeof(uint16_t);
3163 hspi->RxXferCount--;
3164
3165 if (hspi->RxXferCount == 0U)
3166 {
3167 #if (USE_SPI_CRC != 0U)
3168 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3169 {
3170 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3171 return;
3172 }
3173 #endif /* USE_SPI_CRC */
3174
3175 /* Disable RXNE interrupt */
3176 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3177
3178 if (hspi->TxXferCount == 0U)
3179 {
3180 SPI_CloseRxTx_ISR(hspi);
3181 }
3182 }
3183 }
3184
3185 #if (USE_SPI_CRC != 0U)
3186 /**
3187 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3188 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3189 * the configuration information for SPI module.
3190 * @retval None
3191 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3192 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3193 {
3194 /* Read 16bit CRC to flush Data Regsiter */
3195 READ_REG(hspi->Instance->DR);
3196
3197 /* Disable RXNE interrupt */
3198 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3199
3200 SPI_CloseRxTx_ISR(hspi);
3201 }
3202 #endif /* USE_SPI_CRC */
3203
3204 /**
3205 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3206 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3207 * the configuration information for SPI module.
3208 * @retval None
3209 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3210 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3211 {
3212 /* Transmit data in 16 Bit mode */
3213 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3214 hspi->pTxBuffPtr += sizeof(uint16_t);
3215 hspi->TxXferCount--;
3216
3217 /* Enable CRC Transmission */
3218 if (hspi->TxXferCount == 0U)
3219 {
3220 #if (USE_SPI_CRC != 0U)
3221 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3222 {
3223 /* Set CRC Next Bit to send CRC */
3224 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3225 /* Disable TXE interrupt */
3226 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3227 return;
3228 }
3229 #endif /* USE_SPI_CRC */
3230
3231 /* Disable TXE interrupt */
3232 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3233
3234 if (hspi->RxXferCount == 0U)
3235 {
3236 SPI_CloseRxTx_ISR(hspi);
3237 }
3238 }
3239 }
3240
3241 #if (USE_SPI_CRC != 0U)
3242 /**
3243 * @brief Manage the CRC 8-bit receive in Interrupt context.
3244 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3245 * the configuration information for SPI module.
3246 * @retval None
3247 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3248 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3249 {
3250 /* Read 8bit CRC to flush Data Register */
3251 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3252
3253 SPI_CloseRx_ISR(hspi);
3254 }
3255 #endif /* USE_SPI_CRC */
3256
3257 /**
3258 * @brief Manage the receive 8-bit in Interrupt context.
3259 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3260 * the configuration information for SPI module.
3261 * @retval None
3262 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3263 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3264 {
3265 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3266 hspi->pRxBuffPtr++;
3267 hspi->RxXferCount--;
3268
3269 #if (USE_SPI_CRC != 0U)
3270 /* Enable CRC Transmission */
3271 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3272 {
3273 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3274 }
3275 #endif /* USE_SPI_CRC */
3276
3277 if (hspi->RxXferCount == 0U)
3278 {
3279 #if (USE_SPI_CRC != 0U)
3280 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3281 {
3282 hspi->RxISR = SPI_RxISR_8BITCRC;
3283 return;
3284 }
3285 #endif /* USE_SPI_CRC */
3286 SPI_CloseRx_ISR(hspi);
3287 }
3288 }
3289
3290 #if (USE_SPI_CRC != 0U)
3291 /**
3292 * @brief Manage the CRC 16-bit receive in Interrupt context.
3293 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3294 * the configuration information for SPI module.
3295 * @retval None
3296 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3297 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3298 {
3299 /* Read 16bit CRC to flush Data Register */
3300 READ_REG(hspi->Instance->DR);
3301
3302 /* Disable RXNE and ERR interrupt */
3303 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3304
3305 SPI_CloseRx_ISR(hspi);
3306 }
3307 #endif /* USE_SPI_CRC */
3308
3309 /**
3310 * @brief Manage the 16-bit receive in Interrupt context.
3311 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3312 * the configuration information for SPI module.
3313 * @retval None
3314 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3315 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3316 {
3317 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3318 hspi->pRxBuffPtr += sizeof(uint16_t);
3319 hspi->RxXferCount--;
3320
3321 #if (USE_SPI_CRC != 0U)
3322 /* Enable CRC Transmission */
3323 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3324 {
3325 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3326 }
3327 #endif /* USE_SPI_CRC */
3328
3329 if (hspi->RxXferCount == 0U)
3330 {
3331 #if (USE_SPI_CRC != 0U)
3332 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3333 {
3334 hspi->RxISR = SPI_RxISR_16BITCRC;
3335 return;
3336 }
3337 #endif /* USE_SPI_CRC */
3338 SPI_CloseRx_ISR(hspi);
3339 }
3340 }
3341
3342 /**
3343 * @brief Handle the data 8-bit transmit in Interrupt mode.
3344 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3345 * the configuration information for SPI module.
3346 * @retval None
3347 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3348 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3349 {
3350 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3351 hspi->pTxBuffPtr++;
3352 hspi->TxXferCount--;
3353
3354 if (hspi->TxXferCount == 0U)
3355 {
3356 #if (USE_SPI_CRC != 0U)
3357 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3358 {
3359 /* Enable CRC Transmission */
3360 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3361 }
3362 #endif /* USE_SPI_CRC */
3363 SPI_CloseTx_ISR(hspi);
3364 }
3365 }
3366
3367 /**
3368 * @brief Handle the data 16-bit transmit in Interrupt mode.
3369 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3370 * the configuration information for SPI module.
3371 * @retval None
3372 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3373 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3374 {
3375 /* Transmit data in 16 Bit mode */
3376 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3377 hspi->pTxBuffPtr += sizeof(uint16_t);
3378 hspi->TxXferCount--;
3379
3380 if (hspi->TxXferCount == 0U)
3381 {
3382 #if (USE_SPI_CRC != 0U)
3383 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3384 {
3385 /* Enable CRC Transmission */
3386 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3387 }
3388 #endif /* USE_SPI_CRC */
3389 SPI_CloseTx_ISR(hspi);
3390 }
3391 }
3392
3393 /**
3394 * @brief Handle SPI Communication Timeout.
3395 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3396 * the configuration information for SPI module.
3397 * @param Flag SPI flag to check
3398 * @param State flag state to check
3399 * @param Timeout Timeout duration
3400 * @param Tickstart tick start value
3401 * @retval HAL status
3402 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3403 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3404 uint32_t Timeout, uint32_t Tickstart)
3405 {
3406 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3407 {
3408 if (Timeout != HAL_MAX_DELAY)
3409 {
3410 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3411 {
3412 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3413 on both master and slave sides in order to resynchronize the master
3414 and slave for their respective CRC calculation */
3415
3416 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3417 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3418
3419 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3420 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3421 {
3422 /* Disable SPI peripheral */
3423 __HAL_SPI_DISABLE(hspi);
3424 }
3425
3426 /* Reset CRC Calculation */
3427 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3428 {
3429 SPI_RESET_CRC(hspi);
3430 }
3431
3432 hspi->State = HAL_SPI_STATE_READY;
3433
3434 /* Process Unlocked */
3435 __HAL_UNLOCK(hspi);
3436
3437 return HAL_TIMEOUT;
3438 }
3439 }
3440 }
3441
3442 return HAL_OK;
3443 }
3444
3445 /**
3446 * @brief Handle the check of the RX transaction complete.
3447 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3448 * the configuration information for SPI module.
3449 * @param Timeout Timeout duration
3450 * @param Tickstart tick start value
3451 * @retval HAL status
3452 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3453 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3454 {
3455 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3456 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3457 {
3458 /* Disable SPI peripheral */
3459 __HAL_SPI_DISABLE(hspi);
3460 }
3461
3462 /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
3463 if (hspi->Init.Mode == SPI_MODE_MASTER)
3464 {
3465 if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
3466 {
3467 /* Control the BSY flag */
3468 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3469 {
3470 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3471 return HAL_TIMEOUT;
3472 }
3473 }
3474 else
3475 {
3476 /* Wait the RXNE reset */
3477 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
3478 {
3479 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3480 return HAL_TIMEOUT;
3481 }
3482 }
3483 }
3484 else
3485 {
3486 /* Wait the RXNE reset */
3487 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
3488 {
3489 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3490 return HAL_TIMEOUT;
3491 }
3492 }
3493 return HAL_OK;
3494 }
3495
3496 /**
3497 * @brief Handle the check of the RXTX or TX transaction complete.
3498 * @param hspi SPI handle
3499 * @param Timeout Timeout duration
3500 * @param Tickstart tick start value
3501 * @retval HAL status
3502 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3503 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3504 {
3505 /* Timeout in µs */
3506 __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
3507 /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
3508 if (hspi->Init.Mode == SPI_MODE_MASTER)
3509 {
3510 /* Control the BSY flag */
3511 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3512 {
3513 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3514 return HAL_TIMEOUT;
3515 }
3516 }
3517 else
3518 {
3519 /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
3520 * If Timeout is reached, the transfer is considered as finish.
3521 * User have to calculate the timeout value to fit with the time of 1 byte transfer.
3522 * This time is directly link with the SPI clock from Master device.
3523 */
3524 do
3525 {
3526 if (count == 0U)
3527 {
3528 break;
3529 }
3530 count--;
3531 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
3532 }
3533
3534 return HAL_OK;
3535 }
3536
3537 /**
3538 * @brief Handle the end of the RXTX transaction.
3539 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3540 * the configuration information for SPI module.
3541 * @retval None
3542 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)3543 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3544 {
3545 uint32_t tickstart;
3546 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3547
3548 /* Init tickstart for timeout managment*/
3549 tickstart = HAL_GetTick();
3550
3551 /* Disable ERR interrupt */
3552 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3553
3554 /* Wait until TXE flag is set */
3555 do
3556 {
3557 if (count == 0U)
3558 {
3559 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3560 break;
3561 }
3562 count--;
3563 } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3564
3565 /* Check the end of the transaction */
3566 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3567 {
3568 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3569 }
3570
3571 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3572 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3573 {
3574 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3575 }
3576
3577 #if (USE_SPI_CRC != 0U)
3578 /* Check if CRC error occurred */
3579 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3580 {
3581 hspi->State = HAL_SPI_STATE_READY;
3582 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3583 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3584 /* Call user error callback */
3585 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3586 hspi->ErrorCallback(hspi);
3587 #else
3588 HAL_SPI_ErrorCallback(hspi);
3589 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3590 }
3591 else
3592 {
3593 #endif /* USE_SPI_CRC */
3594 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3595 {
3596 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
3597 {
3598 hspi->State = HAL_SPI_STATE_READY;
3599 /* Call user Rx complete callback */
3600 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3601 hspi->RxCpltCallback(hspi);
3602 #else
3603 HAL_SPI_RxCpltCallback(hspi);
3604 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3605 }
3606 else
3607 {
3608 hspi->State = HAL_SPI_STATE_READY;
3609 /* Call user TxRx complete callback */
3610 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3611 hspi->TxRxCpltCallback(hspi);
3612 #else
3613 HAL_SPI_TxRxCpltCallback(hspi);
3614 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3615 }
3616 }
3617 else
3618 {
3619 hspi->State = HAL_SPI_STATE_READY;
3620 /* Call user error callback */
3621 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3622 hspi->ErrorCallback(hspi);
3623 #else
3624 HAL_SPI_ErrorCallback(hspi);
3625 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3626 }
3627 #if (USE_SPI_CRC != 0U)
3628 }
3629 #endif /* USE_SPI_CRC */
3630 }
3631
3632 /**
3633 * @brief Handle the end of the RX transaction.
3634 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3635 * the configuration information for SPI module.
3636 * @retval None
3637 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)3638 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
3639 {
3640 /* Disable RXNE and ERR interrupt */
3641 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3642
3643 /* Check the end of the transaction */
3644 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3645 {
3646 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3647 }
3648
3649 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3650 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3651 {
3652 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3653 }
3654 hspi->State = HAL_SPI_STATE_READY;
3655
3656 #if (USE_SPI_CRC != 0U)
3657 /* Check if CRC error occurred */
3658 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3659 {
3660 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3661 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3662 /* Call user error callback */
3663 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3664 hspi->ErrorCallback(hspi);
3665 #else
3666 HAL_SPI_ErrorCallback(hspi);
3667 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3668 }
3669 else
3670 {
3671 #endif /* USE_SPI_CRC */
3672 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3673 {
3674 /* Call user Rx complete callback */
3675 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3676 hspi->RxCpltCallback(hspi);
3677 #else
3678 HAL_SPI_RxCpltCallback(hspi);
3679 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3680 }
3681 else
3682 {
3683 /* Call user error callback */
3684 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3685 hspi->ErrorCallback(hspi);
3686 #else
3687 HAL_SPI_ErrorCallback(hspi);
3688 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3689 }
3690 #if (USE_SPI_CRC != 0U)
3691 }
3692 #endif /* USE_SPI_CRC */
3693 }
3694
3695 /**
3696 * @brief Handle the end of the TX transaction.
3697 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3698 * the configuration information for SPI module.
3699 * @retval None
3700 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)3701 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
3702 {
3703 uint32_t tickstart;
3704 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3705
3706 /* Init tickstart for timeout management*/
3707 tickstart = HAL_GetTick();
3708
3709 /* Wait until TXE flag is set */
3710 do
3711 {
3712 if (count == 0U)
3713 {
3714 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3715 break;
3716 }
3717 count--;
3718 } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3719
3720 /* Disable TXE and ERR interrupt */
3721 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
3722
3723 /* Check the end of the transaction */
3724 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3725 {
3726 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3727 }
3728
3729 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3730 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3731 {
3732 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3733 }
3734
3735 hspi->State = HAL_SPI_STATE_READY;
3736 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3737 {
3738 /* Call user error callback */
3739 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3740 hspi->ErrorCallback(hspi);
3741 #else
3742 HAL_SPI_ErrorCallback(hspi);
3743 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3744 }
3745 else
3746 {
3747 /* Call user Rx complete callback */
3748 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3749 hspi->TxCpltCallback(hspi);
3750 #else
3751 HAL_SPI_TxCpltCallback(hspi);
3752 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3753 }
3754 }
3755
3756 /**
3757 * @brief Handle abort a Rx transaction.
3758 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3759 * the configuration information for SPI module.
3760 * @retval None
3761 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)3762 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
3763 {
3764 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3765
3766 /* Wait until TXE flag is set */
3767 do
3768 {
3769 if (count == 0U)
3770 {
3771 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3772 break;
3773 }
3774 count--;
3775 } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3776
3777 /* Disable SPI Peripheral */
3778 __HAL_SPI_DISABLE(hspi);
3779
3780 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3781 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3782
3783 /* Read CRC to flush Data Register */
3784 READ_REG(hspi->Instance->DR);
3785
3786 hspi->State = HAL_SPI_STATE_ABORT;
3787 }
3788
3789 /**
3790 * @brief Handle abort a Tx or Rx/Tx transaction.
3791 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3792 * the configuration information for SPI module.
3793 * @retval None
3794 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)3795 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
3796 {
3797 /* Disable TXEIE interrupt */
3798 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
3799
3800 /* Disable SPI Peripheral */
3801 __HAL_SPI_DISABLE(hspi);
3802
3803 hspi->State = HAL_SPI_STATE_ABORT;
3804 }
3805
3806 /**
3807 * @}
3808 */
3809
3810 #endif /* HAL_SPI_MODULE_ENABLED */
3811
3812 /**
3813 * @}
3814 */
3815
3816 /**
3817 * @}
3818 */
3819
3820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3821