1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.</center></h2>
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32f4xx_hal.h"
27
28 /** @addtogroup STM32F4xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup PWR PWR
33 * @brief PWR HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_PWR_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private define ------------------------------------------------------------*/
41 /** @addtogroup PWR_Private_Constants
42 * @{
43 */
44
45 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
46 * @{
47 */
48 #define PVD_MODE_IT 0x00010000U
49 #define PVD_MODE_EVT 0x00020000U
50 #define PVD_RISING_EDGE 0x00000001U
51 #define PVD_FALLING_EDGE 0x00000002U
52 /**
53 * @}
54 */
55
56 /**
57 * @}
58 */
59 /* Private macro -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private function prototypes -----------------------------------------------*/
62 /* Private functions ---------------------------------------------------------*/
63
64 /** @defgroup PWR_Exported_Functions PWR Exported Functions
65 * @{
66 */
67
68 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
69 * @brief Initialization and de-initialization functions
70 *
71 @verbatim
72 ===============================================================================
73 ##### Initialization and de-initialization functions #####
74 ===============================================================================
75 [..]
76 After reset, the backup domain (RTC registers, RTC backup data
77 registers and backup SRAM) is protected against possible unwanted
78 write accesses.
79 To enable access to the RTC Domain and RTC registers, proceed as follows:
80 (+) Enable the Power Controller (PWR) APB1 interface clock using the
81 __HAL_RCC_PWR_CLK_ENABLE() macro.
82 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
83
84 @endverbatim
85 * @{
86 */
87
88 /**
89 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
90 * @retval None
91 */
HAL_PWR_DeInit(void)92 void HAL_PWR_DeInit(void)
93 {
94 __HAL_RCC_PWR_FORCE_RESET();
95 __HAL_RCC_PWR_RELEASE_RESET();
96 }
97
98 /**
99 * @brief Enables access to the backup domain (RTC registers, RTC
100 * backup data registers and backup SRAM).
101 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
102 * Backup Domain Access should be kept enabled.
103 * @retval None
104 */
HAL_PWR_EnableBkUpAccess(void)105 void HAL_PWR_EnableBkUpAccess(void)
106 {
107 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
108 }
109
110 /**
111 * @brief Disables access to the backup domain (RTC registers, RTC
112 * backup data registers and backup SRAM).
113 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
114 * Backup Domain Access should be kept enabled.
115 * @retval None
116 */
HAL_PWR_DisableBkUpAccess(void)117 void HAL_PWR_DisableBkUpAccess(void)
118 {
119 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
120 }
121
122 /**
123 * @}
124 */
125
126 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
127 * @brief Low Power modes configuration functions
128 *
129 @verbatim
130
131 ===============================================================================
132 ##### Peripheral Control functions #####
133 ===============================================================================
134
135 *** PVD configuration ***
136 =========================
137 [..]
138 (+) The PVD is used to monitor the VDD power supply by comparing it to a
139 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
140 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
141 than the PVD threshold. This event is internally connected to the EXTI
142 line16 and can generate an interrupt if enabled. This is done through
143 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
144 (+) The PVD is stopped in Standby mode.
145
146 *** Wake-up pin configuration ***
147 ================================
148 [..]
149 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
150 forced in input pull-down configuration and is active on rising edges.
151 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
152 (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
153 (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
154
155 *** Low Power modes configuration ***
156 =====================================
157 [..]
158 The devices feature 3 low-power modes:
159 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
160 (+) Stop mode: all clocks are stopped, regulator running, regulator
161 in low power mode
162 (+) Standby mode: 1.2V domain powered off.
163
164 *** Sleep mode ***
165 ==================
166 [..]
167 (+) Entry:
168 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
169 functions with
170 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
171 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
172
173 -@@- The Regulator parameter is not used for the STM32F4 family
174 and is kept as parameter just to maintain compatibility with the
175 lower power families (STM32L).
176 (+) Exit:
177 Any peripheral interrupt acknowledged by the nested vectored interrupt
178 controller (NVIC) can wake up the device from Sleep mode.
179
180 *** Stop mode ***
181 =================
182 [..]
183 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
184 and the HSE RC oscillators are disabled. Internal SRAM and register contents
185 are preserved.
186 The voltage regulator can be configured either in normal or low-power mode.
187 To minimize the consumption In Stop mode, FLASH can be powered off before
188 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
189 It can be switched on again by software after exiting the Stop mode using
190 the HAL_PWREx_DisableFlashPowerDown() function.
191
192 (+) Entry:
193 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
194 function with:
195 (++) Main regulator ON.
196 (++) Low Power regulator ON.
197 (+) Exit:
198 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
199
200 *** Standby mode ***
201 ====================
202 [..]
203 (+)
204 The Standby mode allows to achieve the lowest power consumption. It is based
205 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
206 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
207 the HSE oscillator are also switched off. SRAM and register contents are lost
208 except for the RTC registers, RTC backup registers, backup SRAM and Standby
209 circuitry.
210
211 The voltage regulator is OFF.
212
213 (++) Entry:
214 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
215 (++) Exit:
216 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
217 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
218
219 *** Auto-wake-up (AWU) from low-power mode ***
220 =============================================
221 [..]
222
223 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
224 Wake-up event, a tamper event or a time-stamp event, without depending on
225 an external interrupt (Auto-wake-up mode).
226
227 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
228
229 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
230 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
231
232 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
233 is necessary to configure the RTC to detect the tamper or time stamp event using the
234 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
235
236 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
237 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
238
239 @endverbatim
240 * @{
241 */
242
243 /**
244 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
245 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
246 * information for the PVD.
247 * @note Refer to the electrical characteristics of your device datasheet for
248 * more details about the voltage threshold corresponding to each
249 * detection level.
250 * @retval None
251 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)252 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
253 {
254 /* Check the parameters */
255 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
256 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
257
258 /* Set PLS[7:5] bits according to PVDLevel value */
259 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
260
261 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
262 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
263 __HAL_PWR_PVD_EXTI_DISABLE_IT();
264 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
265 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
266
267 /* Configure interrupt mode */
268 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
269 {
270 __HAL_PWR_PVD_EXTI_ENABLE_IT();
271 }
272
273 /* Configure event mode */
274 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
275 {
276 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
277 }
278
279 /* Configure the edge */
280 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
281 {
282 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
283 }
284
285 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
286 {
287 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
288 }
289 }
290
291 /**
292 * @brief Enables the Power Voltage Detector(PVD).
293 * @retval None
294 */
HAL_PWR_EnablePVD(void)295 void HAL_PWR_EnablePVD(void)
296 {
297 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
298 }
299
300 /**
301 * @brief Disables the Power Voltage Detector(PVD).
302 * @retval None
303 */
HAL_PWR_DisablePVD(void)304 void HAL_PWR_DisablePVD(void)
305 {
306 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
307 }
308
309 /**
310 * @brief Enables the Wake-up PINx functionality.
311 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
312 * This parameter can be one of the following values:
313 * @arg PWR_WAKEUP_PIN1
314 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
315 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
316 * @retval None
317 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)318 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
319 {
320 /* Check the parameter */
321 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
322
323 /* Enable the wake up pin */
324 SET_BIT(PWR->CSR, WakeUpPinx);
325 }
326
327 /**
328 * @brief Disables the Wake-up PINx functionality.
329 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
330 * This parameter can be one of the following values:
331 * @arg PWR_WAKEUP_PIN1
332 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
333 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
334 * @retval None
335 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)336 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
337 {
338 /* Check the parameter */
339 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
340
341 /* Disable the wake up pin */
342 CLEAR_BIT(PWR->CSR, WakeUpPinx);
343 }
344
345 /**
346 * @brief Enters Sleep mode.
347 *
348 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
349 *
350 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
351 * systick interrupt when used as time base for Timeout
352 *
353 * @param Regulator Specifies the regulator state in SLEEP mode.
354 * This parameter can be one of the following values:
355 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
356 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
357 * @note This parameter is not used for the STM32F4 family and is kept as parameter
358 * just to maintain compatibility with the lower power families.
359 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
360 * This parameter can be one of the following values:
361 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
362 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
363 * @retval None
364 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)365 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
366 {
367 /* Check the parameters */
368 assert_param(IS_PWR_REGULATOR(Regulator));
369 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
370
371 /* Clear SLEEPDEEP bit of Cortex System Control Register */
372 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
373
374 /* Select SLEEP mode entry -------------------------------------------------*/
375 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
376 {
377 /* Request Wait For Interrupt */
378 __WFI();
379 }
380 else
381 {
382 /* Request Wait For Event */
383 __SEV();
384 __WFE();
385 __WFE();
386 }
387 }
388
389 /**
390 * @brief Enters Stop mode.
391 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
392 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
393 * the HSI RC oscillator is selected as system clock.
394 * @note When the voltage regulator operates in low power mode, an additional
395 * startup delay is incurred when waking up from Stop mode.
396 * By keeping the internal regulator ON during Stop mode, the consumption
397 * is higher although the startup time is reduced.
398 * @param Regulator Specifies the regulator state in Stop mode.
399 * This parameter can be one of the following values:
400 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
401 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
402 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
403 * This parameter can be one of the following values:
404 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
405 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
406 * @retval None
407 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)408 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
409 {
410 /* Check the parameters */
411 assert_param(IS_PWR_REGULATOR(Regulator));
412 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
413
414 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
415 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
416
417 /* Set SLEEPDEEP bit of Cortex System Control Register */
418 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
419
420 /* Select Stop mode entry --------------------------------------------------*/
421 if(STOPEntry == PWR_STOPENTRY_WFI)
422 {
423 /* Request Wait For Interrupt */
424 __WFI();
425 }
426 else
427 {
428 /* Request Wait For Event */
429 __SEV();
430 __WFE();
431 __WFE();
432 }
433 /* Reset SLEEPDEEP bit of Cortex System Control Register */
434 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
435 }
436
437 /**
438 * @brief Enters Standby mode.
439 * @note In Standby mode, all I/O pins are high impedance except for:
440 * - Reset pad (still available)
441 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
442 * Alarm out, or RTC clock calibration out.
443 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
444 * - WKUP pin 1 (PA0) if enabled.
445 * @retval None
446 */
HAL_PWR_EnterSTANDBYMode(void)447 void HAL_PWR_EnterSTANDBYMode(void)
448 {
449 /* Select Standby mode */
450 SET_BIT(PWR->CR, PWR_CR_PDDS);
451
452 /* Set SLEEPDEEP bit of Cortex System Control Register */
453 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
454
455 /* This option is used to ensure that store operations are completed */
456 #if defined ( __CC_ARM)
457 __force_stores();
458 #endif
459 /* Request Wait For Interrupt */
460 __WFI();
461 }
462
463 /**
464 * @brief This function handles the PWR PVD interrupt request.
465 * @note This API should be called under the PVD_IRQHandler().
466 * @retval None
467 */
HAL_PWR_PVD_IRQHandler(void)468 void HAL_PWR_PVD_IRQHandler(void)
469 {
470 /* Check PWR Exti flag */
471 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
472 {
473 /* PWR PVD interrupt user callback */
474 HAL_PWR_PVDCallback();
475
476 /* Clear PWR Exti pending bit */
477 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
478 }
479 }
480
481 /**
482 * @brief PWR PVD interrupt callback
483 * @retval None
484 */
HAL_PWR_PVDCallback(void)485 __weak void HAL_PWR_PVDCallback(void)
486 {
487 /* NOTE : This function Should not be modified, when the callback is needed,
488 the HAL_PWR_PVDCallback could be implemented in the user file
489 */
490 }
491
492 /**
493 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
494 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
495 * re-enters SLEEP mode when an interruption handling is over.
496 * Setting this bit is useful when the processor is expected to run only on
497 * interruptions handling.
498 * @retval None
499 */
HAL_PWR_EnableSleepOnExit(void)500 void HAL_PWR_EnableSleepOnExit(void)
501 {
502 /* Set SLEEPONEXIT bit of Cortex System Control Register */
503 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
504 }
505
506 /**
507 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
508 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
509 * re-enters SLEEP mode when an interruption handling is over.
510 * @retval None
511 */
HAL_PWR_DisableSleepOnExit(void)512 void HAL_PWR_DisableSleepOnExit(void)
513 {
514 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
515 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
516 }
517
518 /**
519 * @brief Enables CORTEX M4 SEVONPEND bit.
520 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
521 * WFE to wake up when an interrupt moves from inactive to pended.
522 * @retval None
523 */
HAL_PWR_EnableSEVOnPend(void)524 void HAL_PWR_EnableSEVOnPend(void)
525 {
526 /* Set SEVONPEND bit of Cortex System Control Register */
527 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
528 }
529
530 /**
531 * @brief Disables CORTEX M4 SEVONPEND bit.
532 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
533 * WFE to wake up when an interrupt moves from inactive to pended.
534 * @retval None
535 */
HAL_PWR_DisableSEVOnPend(void)536 void HAL_PWR_DisableSEVOnPend(void)
537 {
538 /* Clear SEVONPEND bit of Cortex System Control Register */
539 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
540 }
541
542 /**
543 * @}
544 */
545
546 /**
547 * @}
548 */
549
550 #endif /* HAL_PWR_MODULE_ENABLED */
551 /**
552 * @}
553 */
554
555 /**
556 * @}
557 */
558
559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
560