1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16 [..]
17 The I2C HAL driver can be used as follows:
18
19 (#) Declare a I2C_HandleTypeDef handle structure, for example:
20 I2C_HandleTypeDef hi2c;
21
22 (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
23 (##) Enable the I2Cx interface clock
24 (##) I2C pins configuration
25 (+++) Enable the clock for the I2C GPIOs
26 (+++) Configure I2C pins as alternate function open-drain
27 (##) NVIC configuration if you need to use interrupt process
28 (+++) Configure the I2Cx interrupt priority
29 (+++) Enable the NVIC I2C IRQ Channel
30 (##) DMA Configuration if you need to use DMA process
31 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
32 (+++) Enable the DMAx interface clock using
33 (+++) Configure the DMA handle parameters
34 (+++) Configure the DMA Tx or Rx stream
35 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
36 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
37 the DMA Tx or Rx stream
38
39 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
40 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
41
42 (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
43 (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API.
44
45 (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
46
47 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
48
49 *** Polling mode IO operation ***
50 =================================
51 [..]
52 (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
53 (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
54 (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
55 (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
56
57 *** Polling mode IO MEM operation ***
58 =====================================
59 [..]
60 (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
61 (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
62
63
64 *** Interrupt mode IO operation ***
65 ===================================
66 [..]
67 (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
68 (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
69 add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
70 (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
71 (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
72 add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
73 (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
74 (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
75 add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
76 (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
77 (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
78 add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
79 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
80 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
81 (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
82 (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
83 add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
84
85 *** Interrupt mode or DMA mode IO sequential operation ***
86 ==========================================================
87 [..]
88 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
89 when a direction change during transfer
90 [..]
91 (+) A specific option field manage the different steps of a sequential transfer
92 (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
93 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
94 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
95 and data to transfer without a final stop condition
96 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
97 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
98 several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
99 or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
100 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
101 and with new data to transfer if the direction change or manage only the new data to transfer
102 if no direction change and without a final stop condition in both cases
103 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
104 and with new data to transfer if the direction change or manage only the new data to transfer
105 if no direction change and with a final stop condition in both cases
106 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
107 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
108 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
109 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
110 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
111 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
112 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
113 without stopping the communication and so generate a restart condition.
114 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
115 interface.
116 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
117 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
118 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
119 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
120 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
121
122 (+) Differents sequential I2C interfaces are listed below:
123 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
124 or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
125 (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
126 add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
127 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
128 or using @ref HAL_I2C_Master_Seq_Receive_DMA()
129 (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
130 add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
131 (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
132 (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
133 add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
134 (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
135 (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
136 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
137 (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
138 add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
139 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
140 or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
141 (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
142 add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
143 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
144 or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
145 (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
146 add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
147 (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
148 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
149
150 *** Interrupt mode IO MEM operation ***
151 =======================================
152 [..]
153 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
154 @ref HAL_I2C_Mem_Write_IT()
155 (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
156 add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
157 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
158 @ref HAL_I2C_Mem_Read_IT()
159 (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
160 add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
161 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
162 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
163
164 *** DMA mode IO operation ***
165 ==============================
166 [..]
167 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
168 @ref HAL_I2C_Master_Transmit_DMA()
169 (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
170 add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
171 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
172 @ref HAL_I2C_Master_Receive_DMA()
173 (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
174 add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
175 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
176 @ref HAL_I2C_Slave_Transmit_DMA()
177 (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
178 add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
179 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
180 @ref HAL_I2C_Slave_Receive_DMA()
181 (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
182 add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
183 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
184 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
185 (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
186 (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
187 add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
188
189 *** DMA mode IO MEM operation ***
190 =================================
191 [..]
192 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
193 @ref HAL_I2C_Mem_Write_DMA()
194 (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
195 add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
196 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
197 @ref HAL_I2C_Mem_Read_DMA()
198 (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
199 add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
200 (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
201 add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
202
203
204 *** I2C HAL driver macros list ***
205 ==================================
206 [..]
207 Below the list of most used macros in I2C HAL driver.
208
209 (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
210 (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
211 (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
212 (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
213 (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
214 (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
215
216 *** Callback registration ***
217 =============================================
218 [..]
219 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
220 allows the user to configure dynamically the driver callbacks.
221 Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
222 to register an interrupt callback.
223 [..]
224 Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
225 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
226 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
227 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
228 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
229 (+) ListenCpltCallback : callback for end of listen mode.
230 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
231 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
232 (+) ErrorCallback : callback for error detection.
233 (+) AbortCpltCallback : callback for abort completion process.
234 (+) MspInitCallback : callback for Msp Init.
235 (+) MspDeInitCallback : callback for Msp DeInit.
236 This function takes as parameters the HAL peripheral handle, the Callback ID
237 and a pointer to the user callback function.
238 [..]
239 For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
240 [..]
241 Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
242 weak function.
243 @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
244 and the Callback ID.
245 This function allows to reset following callbacks:
246 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
247 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
248 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
249 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
250 (+) ListenCpltCallback : callback for end of listen mode.
251 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
252 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
253 (+) ErrorCallback : callback for error detection.
254 (+) AbortCpltCallback : callback for abort completion process.
255 (+) MspInitCallback : callback for Msp Init.
256 (+) MspDeInitCallback : callback for Msp DeInit.
257 [..]
258 For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
259 [..]
260 By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
261 all callbacks are set to the corresponding weak functions:
262 examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
263 Exception done for MspInit and MspDeInit functions that are
264 reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
265 these callbacks are null (not registered beforehand).
266 If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
267 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
268 [..]
269 Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
270 Exception done MspInit/MspDeInit functions that can be registered/unregistered
271 in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
272 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
273 Then, the user first registers the MspInit/MspDeInit user callbacks
274 using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
275 or @ref HAL_I2C_Init() function.
276 [..]
277 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
278 not defined, the callback registration feature is not available and all callbacks
279 are set to the corresponding weak functions.
280
281
282
283 [..]
284 (@) You can refer to the I2C HAL driver header file for more useful macros
285
286 @endverbatim
287 ******************************************************************************
288 * @attention
289 *
290 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
291 * All rights reserved.</center></h2>
292 *
293 * This software component is licensed by ST under BSD 3-Clause license,
294 * the "License"; You may not use this file except in compliance with the
295 * License. You may obtain a copy of the License at:
296 * opensource.org/licenses/BSD-3-Clause
297 *
298 ******************************************************************************
299 */
300
301 /* Includes ------------------------------------------------------------------*/
302 #include "stm32f4xx_hal.h"
303
304 /** @addtogroup STM32F4xx_HAL_Driver
305 * @{
306 */
307
308 /** @defgroup I2C I2C
309 * @brief I2C HAL module driver
310 * @{
311 */
312
313 #ifdef HAL_I2C_MODULE_ENABLED
314
315 /* Private typedef -----------------------------------------------------------*/
316 /* Private define ------------------------------------------------------------*/
317 /** @addtogroup I2C_Private_Define
318 * @{
319 */
320 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
321 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
322 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
323 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
324
325 /* Private define for @ref PreviousState usage */
326 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
327 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
328 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
329 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
330 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
331 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
332
333 /**
334 * @}
335 */
336
337 /* Private macro -------------------------------------------------------------*/
338 /* Private variables ---------------------------------------------------------*/
339 /* Private function prototypes -----------------------------------------------*/
340
341 /** @defgroup I2C_Private_Functions I2C Private Functions
342 * @{
343 */
344 /* Private functions to handle DMA transfer */
345 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
346 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
347 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
348
349 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
350
351 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
352 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
353 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
354 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
355
356 /* Private functions to handle flags during polling transfer */
357 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
358 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
362 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
363 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
364 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
365
366 /* Private functions for I2C transfer IRQ handler */
367 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
368 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
369 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
370 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
371 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
372 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
373 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
374
375 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
376 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
377 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
378 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
379 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
380 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
381 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
382
383 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
384
385 /* Private function to Convert Specific options */
386 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
387 /**
388 * @}
389 */
390
391 /* Exported functions --------------------------------------------------------*/
392
393 /** @defgroup I2C_Exported_Functions I2C Exported Functions
394 * @{
395 */
396
397 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
398 * @brief Initialization and Configuration functions
399 *
400 @verbatim
401 ===============================================================================
402 ##### Initialization and de-initialization functions #####
403 ===============================================================================
404 [..] This subsection provides a set of functions allowing to initialize and
405 deinitialize the I2Cx peripheral:
406
407 (+) User must Implement HAL_I2C_MspInit() function in which he configures
408 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
409
410 (+) Call the function HAL_I2C_Init() to configure the selected device with
411 the selected configuration:
412 (++) Communication Speed
413 (++) Duty cycle
414 (++) Addressing mode
415 (++) Own Address 1
416 (++) Dual Addressing mode
417 (++) Own Address 2
418 (++) General call mode
419 (++) Nostretch mode
420
421 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
422 of the selected I2Cx peripheral.
423
424 @endverbatim
425 * @{
426 */
427
428 /**
429 * @brief Initializes the I2C according to the specified parameters
430 * in the I2C_InitTypeDef and initialize the associated handle.
431 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
432 * the configuration information for the specified I2C.
433 * @retval HAL status
434 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)435 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
436 {
437 uint32_t freqrange;
438 uint32_t pclk1;
439
440 /* Check the I2C handle allocation */
441 if (hi2c == NULL)
442 {
443 return HAL_ERROR;
444 }
445
446 /* Check the parameters */
447 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
448 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
449 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
450 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
451 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
452 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
453 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
454 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
455 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
456
457 if (hi2c->State == HAL_I2C_STATE_RESET)
458 {
459 /* Allocate lock resource and initialize it */
460 hi2c->Lock = HAL_UNLOCKED;
461
462 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
463 /* Init the I2C Callback settings */
464 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
465 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
466 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
467 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
468 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
469 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
470 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
471 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
472 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
473 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
474
475 if (hi2c->MspInitCallback == NULL)
476 {
477 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
478 }
479
480 /* Init the low level hardware : GPIO, CLOCK, NVIC */
481 hi2c->MspInitCallback(hi2c);
482 #else
483 /* Init the low level hardware : GPIO, CLOCK, NVIC */
484 HAL_I2C_MspInit(hi2c);
485 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
486 }
487
488 hi2c->State = HAL_I2C_STATE_BUSY;
489
490 /* Disable the selected I2C peripheral */
491 __HAL_I2C_DISABLE(hi2c);
492
493 /*Reset I2C*/
494 hi2c->Instance->CR1 |= I2C_CR1_SWRST;
495 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
496
497 /* Get PCLK1 frequency */
498 pclk1 = HAL_RCC_GetPCLK1Freq();
499
500 /* Check the minimum allowed PCLK1 frequency */
501 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
502 {
503 return HAL_ERROR;
504 }
505
506 /* Calculate frequency range */
507 freqrange = I2C_FREQRANGE(pclk1);
508
509 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
510 /* Configure I2Cx: Frequency range */
511 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
512
513 /*---------------------------- I2Cx TRISE Configuration --------------------*/
514 /* Configure I2Cx: Rise Time */
515 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
516
517 /*---------------------------- I2Cx CCR Configuration ----------------------*/
518 /* Configure I2Cx: Speed */
519 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
520
521 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
522 /* Configure I2Cx: Generalcall and NoStretch mode */
523 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
524
525 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
526 /* Configure I2Cx: Own Address1 and addressing mode */
527 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
528
529 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
530 /* Configure I2Cx: Dual mode and Own Address2 */
531 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
532
533 /* Enable the selected I2C peripheral */
534 __HAL_I2C_ENABLE(hi2c);
535
536 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
537 hi2c->State = HAL_I2C_STATE_READY;
538 hi2c->PreviousState = I2C_STATE_NONE;
539 hi2c->Mode = HAL_I2C_MODE_NONE;
540
541 return HAL_OK;
542 }
543
544 /**
545 * @brief DeInitialize the I2C peripheral.
546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
547 * the configuration information for the specified I2C.
548 * @retval HAL status
549 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)550 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
551 {
552 /* Check the I2C handle allocation */
553 if (hi2c == NULL)
554 {
555 return HAL_ERROR;
556 }
557
558 /* Check the parameters */
559 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
560
561 hi2c->State = HAL_I2C_STATE_BUSY;
562
563 /* Disable the I2C Peripheral Clock */
564 __HAL_I2C_DISABLE(hi2c);
565
566 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
567 if (hi2c->MspDeInitCallback == NULL)
568 {
569 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
570 }
571
572 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
573 hi2c->MspDeInitCallback(hi2c);
574 #else
575 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
576 HAL_I2C_MspDeInit(hi2c);
577 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
578
579 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
580 hi2c->State = HAL_I2C_STATE_RESET;
581 hi2c->PreviousState = I2C_STATE_NONE;
582 hi2c->Mode = HAL_I2C_MODE_NONE;
583
584 /* Release Lock */
585 __HAL_UNLOCK(hi2c);
586
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Initialize the I2C MSP.
592 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
593 * the configuration information for the specified I2C.
594 * @retval None
595 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)596 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
597 {
598 /* Prevent unused argument(s) compilation warning */
599 UNUSED(hi2c);
600
601 /* NOTE : This function should not be modified, when the callback is needed,
602 the HAL_I2C_MspInit could be implemented in the user file
603 */
604 }
605
606 /**
607 * @brief DeInitialize the I2C MSP.
608 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
609 * the configuration information for the specified I2C.
610 * @retval None
611 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)612 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
613 {
614 /* Prevent unused argument(s) compilation warning */
615 UNUSED(hi2c);
616
617 /* NOTE : This function should not be modified, when the callback is needed,
618 the HAL_I2C_MspDeInit could be implemented in the user file
619 */
620 }
621
622 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
623 /**
624 * @brief Register a User I2C Callback
625 * To be used instead of the weak predefined callback
626 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
627 * the configuration information for the specified I2C.
628 * @param CallbackID ID of the callback to be registered
629 * This parameter can be one of the following values:
630 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
631 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
632 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
633 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
634 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
635 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
636 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
637 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
638 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
639 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
640 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
641 * @param pCallback pointer to the Callback function
642 * @retval HAL status
643 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)644 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
645 {
646 HAL_StatusTypeDef status = HAL_OK;
647
648 if (pCallback == NULL)
649 {
650 /* Update the error code */
651 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
652
653 return HAL_ERROR;
654 }
655 /* Process locked */
656 __HAL_LOCK(hi2c);
657
658 if (HAL_I2C_STATE_READY == hi2c->State)
659 {
660 switch (CallbackID)
661 {
662 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
663 hi2c->MasterTxCpltCallback = pCallback;
664 break;
665
666 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
667 hi2c->MasterRxCpltCallback = pCallback;
668 break;
669
670 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
671 hi2c->SlaveTxCpltCallback = pCallback;
672 break;
673
674 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
675 hi2c->SlaveRxCpltCallback = pCallback;
676 break;
677
678 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
679 hi2c->ListenCpltCallback = pCallback;
680 break;
681
682 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
683 hi2c->MemTxCpltCallback = pCallback;
684 break;
685
686 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
687 hi2c->MemRxCpltCallback = pCallback;
688 break;
689
690 case HAL_I2C_ERROR_CB_ID :
691 hi2c->ErrorCallback = pCallback;
692 break;
693
694 case HAL_I2C_ABORT_CB_ID :
695 hi2c->AbortCpltCallback = pCallback;
696 break;
697
698 case HAL_I2C_MSPINIT_CB_ID :
699 hi2c->MspInitCallback = pCallback;
700 break;
701
702 case HAL_I2C_MSPDEINIT_CB_ID :
703 hi2c->MspDeInitCallback = pCallback;
704 break;
705
706 default :
707 /* Update the error code */
708 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
709
710 /* Return error status */
711 status = HAL_ERROR;
712 break;
713 }
714 }
715 else if (HAL_I2C_STATE_RESET == hi2c->State)
716 {
717 switch (CallbackID)
718 {
719 case HAL_I2C_MSPINIT_CB_ID :
720 hi2c->MspInitCallback = pCallback;
721 break;
722
723 case HAL_I2C_MSPDEINIT_CB_ID :
724 hi2c->MspDeInitCallback = pCallback;
725 break;
726
727 default :
728 /* Update the error code */
729 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
730
731 /* Return error status */
732 status = HAL_ERROR;
733 break;
734 }
735 }
736 else
737 {
738 /* Update the error code */
739 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
740
741 /* Return error status */
742 status = HAL_ERROR;
743 }
744
745 /* Release Lock */
746 __HAL_UNLOCK(hi2c);
747 return status;
748 }
749
750 /**
751 * @brief Unregister an I2C Callback
752 * I2C callback is redirected to the weak predefined callback
753 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
754 * the configuration information for the specified I2C.
755 * @param CallbackID ID of the callback to be unregistered
756 * This parameter can be one of the following values:
757 * This parameter can be one of the following values:
758 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
759 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
760 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
761 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
762 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
763 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
764 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
765 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
766 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
767 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
768 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
769 * @retval HAL status
770 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)771 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
772 {
773 HAL_StatusTypeDef status = HAL_OK;
774
775 /* Process locked */
776 __HAL_LOCK(hi2c);
777
778 if (HAL_I2C_STATE_READY == hi2c->State)
779 {
780 switch (CallbackID)
781 {
782 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
783 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
784 break;
785
786 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
787 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
788 break;
789
790 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
791 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
792 break;
793
794 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
795 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
796 break;
797
798 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
799 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
800 break;
801
802 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
803 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
804 break;
805
806 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
807 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
808 break;
809
810 case HAL_I2C_ERROR_CB_ID :
811 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
812 break;
813
814 case HAL_I2C_ABORT_CB_ID :
815 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
816 break;
817
818 case HAL_I2C_MSPINIT_CB_ID :
819 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
820 break;
821
822 case HAL_I2C_MSPDEINIT_CB_ID :
823 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
824 break;
825
826 default :
827 /* Update the error code */
828 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
829
830 /* Return error status */
831 status = HAL_ERROR;
832 break;
833 }
834 }
835 else if (HAL_I2C_STATE_RESET == hi2c->State)
836 {
837 switch (CallbackID)
838 {
839 case HAL_I2C_MSPINIT_CB_ID :
840 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
841 break;
842
843 case HAL_I2C_MSPDEINIT_CB_ID :
844 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
845 break;
846
847 default :
848 /* Update the error code */
849 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
850
851 /* Return error status */
852 status = HAL_ERROR;
853 break;
854 }
855 }
856 else
857 {
858 /* Update the error code */
859 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
860
861 /* Return error status */
862 status = HAL_ERROR;
863 }
864
865 /* Release Lock */
866 __HAL_UNLOCK(hi2c);
867 return status;
868 }
869
870 /**
871 * @brief Register the Slave Address Match I2C Callback
872 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
873 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
874 * the configuration information for the specified I2C.
875 * @param pCallback pointer to the Address Match Callback function
876 * @retval HAL status
877 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)878 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881
882 if (pCallback == NULL)
883 {
884 /* Update the error code */
885 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
886
887 return HAL_ERROR;
888 }
889 /* Process locked */
890 __HAL_LOCK(hi2c);
891
892 if (HAL_I2C_STATE_READY == hi2c->State)
893 {
894 hi2c->AddrCallback = pCallback;
895 }
896 else
897 {
898 /* Update the error code */
899 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
900
901 /* Return error status */
902 status = HAL_ERROR;
903 }
904
905 /* Release Lock */
906 __HAL_UNLOCK(hi2c);
907 return status;
908 }
909
910 /**
911 * @brief UnRegister the Slave Address Match I2C Callback
912 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
913 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
914 * the configuration information for the specified I2C.
915 * @retval HAL status
916 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)917 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
918 {
919 HAL_StatusTypeDef status = HAL_OK;
920
921 /* Process locked */
922 __HAL_LOCK(hi2c);
923
924 if (HAL_I2C_STATE_READY == hi2c->State)
925 {
926 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
927 }
928 else
929 {
930 /* Update the error code */
931 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
932
933 /* Return error status */
934 status = HAL_ERROR;
935 }
936
937 /* Release Lock */
938 __HAL_UNLOCK(hi2c);
939 return status;
940 }
941
942 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
943
944 /**
945 * @}
946 */
947
948 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
949 * @brief Data transfers functions
950 *
951 @verbatim
952 ===============================================================================
953 ##### IO operation functions #####
954 ===============================================================================
955 [..]
956 This subsection provides a set of functions allowing to manage the I2C data
957 transfers.
958
959 (#) There are two modes of transfer:
960 (++) Blocking mode : The communication is performed in the polling mode.
961 The status of all data processing is returned by the same function
962 after finishing transfer.
963 (++) No-Blocking mode : The communication is performed using Interrupts
964 or DMA. These functions return the status of the transfer startup.
965 The end of the data processing will be indicated through the
966 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
967 using DMA mode.
968
969 (#) Blocking mode functions are :
970 (++) HAL_I2C_Master_Transmit()
971 (++) HAL_I2C_Master_Receive()
972 (++) HAL_I2C_Slave_Transmit()
973 (++) HAL_I2C_Slave_Receive()
974 (++) HAL_I2C_Mem_Write()
975 (++) HAL_I2C_Mem_Read()
976 (++) HAL_I2C_IsDeviceReady()
977
978 (#) No-Blocking mode functions with Interrupt are :
979 (++) HAL_I2C_Master_Transmit_IT()
980 (++) HAL_I2C_Master_Receive_IT()
981 (++) HAL_I2C_Slave_Transmit_IT()
982 (++) HAL_I2C_Slave_Receive_IT()
983 (++) HAL_I2C_Mem_Write_IT()
984 (++) HAL_I2C_Mem_Read_IT()
985 (++) HAL_I2C_Master_Seq_Transmit_IT()
986 (++) HAL_I2C_Master_Seq_Receive_IT()
987 (++) HAL_I2C_Slave_Seq_Transmit_IT()
988 (++) HAL_I2C_Slave_Seq_Receive_IT()
989 (++) HAL_I2C_EnableListen_IT()
990 (++) HAL_I2C_DisableListen_IT()
991 (++) HAL_I2C_Master_Abort_IT()
992
993 (#) No-Blocking mode functions with DMA are :
994 (++) HAL_I2C_Master_Transmit_DMA()
995 (++) HAL_I2C_Master_Receive_DMA()
996 (++) HAL_I2C_Slave_Transmit_DMA()
997 (++) HAL_I2C_Slave_Receive_DMA()
998 (++) HAL_I2C_Mem_Write_DMA()
999 (++) HAL_I2C_Mem_Read_DMA()
1000 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1001 (++) HAL_I2C_Master_Seq_Receive_DMA()
1002 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1003 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1004
1005 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1006 (++) HAL_I2C_MasterTxCpltCallback()
1007 (++) HAL_I2C_MasterRxCpltCallback()
1008 (++) HAL_I2C_SlaveTxCpltCallback()
1009 (++) HAL_I2C_SlaveRxCpltCallback()
1010 (++) HAL_I2C_MemTxCpltCallback()
1011 (++) HAL_I2C_MemRxCpltCallback()
1012 (++) HAL_I2C_AddrCallback()
1013 (++) HAL_I2C_ListenCpltCallback()
1014 (++) HAL_I2C_ErrorCallback()
1015 (++) HAL_I2C_AbortCpltCallback()
1016
1017 @endverbatim
1018 * @{
1019 */
1020
1021 /**
1022 * @brief Transmits in master mode an amount of data in blocking mode.
1023 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1024 * the configuration information for the specified I2C.
1025 * @param DevAddress Target device address: The device 7 bits address value
1026 * in datasheet must be shifted to the left before calling the interface
1027 * @param pData Pointer to data buffer
1028 * @param Size Amount of data to be sent
1029 * @param Timeout Timeout duration
1030 * @retval HAL status
1031 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1032 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1033 {
1034 /* Init tickstart for timeout management*/
1035 uint32_t tickstart = HAL_GetTick();
1036
1037 if (hi2c->State == HAL_I2C_STATE_READY)
1038 {
1039 /* Wait until BUSY flag is reset */
1040 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1041 {
1042 return HAL_BUSY;
1043 }
1044
1045 /* Process Locked */
1046 __HAL_LOCK(hi2c);
1047
1048 /* Check if the I2C is already enabled */
1049 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1050 {
1051 /* Enable I2C peripheral */
1052 __HAL_I2C_ENABLE(hi2c);
1053 }
1054
1055 /* Disable Pos */
1056 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1057
1058 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1059 hi2c->Mode = HAL_I2C_MODE_MASTER;
1060 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1061
1062 /* Prepare transfer parameters */
1063 hi2c->pBuffPtr = pData;
1064 hi2c->XferCount = Size;
1065 hi2c->XferSize = hi2c->XferCount;
1066 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1067
1068 /* Send Slave Address */
1069 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1070 {
1071 return HAL_ERROR;
1072 }
1073
1074 /* Clear ADDR flag */
1075 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1076
1077 while (hi2c->XferSize > 0U)
1078 {
1079 /* Wait until TXE flag is set */
1080 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1081 {
1082 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1083 {
1084 /* Generate Stop */
1085 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1086 }
1087 return HAL_ERROR;
1088 }
1089
1090 /* Write data to DR */
1091 hi2c->Instance->DR = *hi2c->pBuffPtr;
1092
1093 /* Increment Buffer pointer */
1094 hi2c->pBuffPtr++;
1095
1096 /* Update counter */
1097 hi2c->XferCount--;
1098 hi2c->XferSize--;
1099
1100 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1101 {
1102 /* Write data to DR */
1103 hi2c->Instance->DR = *hi2c->pBuffPtr;
1104
1105 /* Increment Buffer pointer */
1106 hi2c->pBuffPtr++;
1107
1108 /* Update counter */
1109 hi2c->XferCount--;
1110 hi2c->XferSize--;
1111 }
1112
1113 /* Wait until BTF flag is set */
1114 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1115 {
1116 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1117 {
1118 /* Generate Stop */
1119 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1120 }
1121 return HAL_ERROR;
1122 }
1123 }
1124
1125 /* Generate Stop */
1126 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1127
1128 hi2c->State = HAL_I2C_STATE_READY;
1129 hi2c->Mode = HAL_I2C_MODE_NONE;
1130
1131 /* Process Unlocked */
1132 __HAL_UNLOCK(hi2c);
1133
1134 return HAL_OK;
1135 }
1136 else
1137 {
1138 return HAL_BUSY;
1139 }
1140 }
1141
1142 /**
1143 * @brief Receives in master mode an amount of data in blocking mode.
1144 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1145 * the configuration information for the specified I2C.
1146 * @param DevAddress Target device address: The device 7 bits address value
1147 * in datasheet must be shifted to the left before calling the interface
1148 * @param pData Pointer to data buffer
1149 * @param Size Amount of data to be sent
1150 * @param Timeout Timeout duration
1151 * @retval HAL status
1152 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1153 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1154 {
1155 /* Init tickstart for timeout management*/
1156 uint32_t tickstart = HAL_GetTick();
1157
1158 if (hi2c->State == HAL_I2C_STATE_READY)
1159 {
1160 /* Wait until BUSY flag is reset */
1161 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1162 {
1163 return HAL_BUSY;
1164 }
1165
1166 /* Process Locked */
1167 __HAL_LOCK(hi2c);
1168
1169 /* Check if the I2C is already enabled */
1170 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1171 {
1172 /* Enable I2C peripheral */
1173 __HAL_I2C_ENABLE(hi2c);
1174 }
1175
1176 /* Disable Pos */
1177 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1178
1179 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1180 hi2c->Mode = HAL_I2C_MODE_MASTER;
1181 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1182
1183 /* Prepare transfer parameters */
1184 hi2c->pBuffPtr = pData;
1185 hi2c->XferCount = Size;
1186 hi2c->XferSize = hi2c->XferCount;
1187 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1188
1189 /* Send Slave Address */
1190 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1191 {
1192 return HAL_ERROR;
1193 }
1194
1195 if (hi2c->XferSize == 0U)
1196 {
1197 /* Clear ADDR flag */
1198 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1199
1200 /* Generate Stop */
1201 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1202 }
1203 else if (hi2c->XferSize == 1U)
1204 {
1205 /* Disable Acknowledge */
1206 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1207
1208 /* Clear ADDR flag */
1209 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1210
1211 /* Generate Stop */
1212 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1213 }
1214 else if (hi2c->XferSize == 2U)
1215 {
1216 /* Disable Acknowledge */
1217 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1218
1219 /* Enable Pos */
1220 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1221
1222 /* Clear ADDR flag */
1223 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1224 }
1225 else
1226 {
1227 /* Enable Acknowledge */
1228 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1229
1230 /* Clear ADDR flag */
1231 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1232 }
1233
1234 while (hi2c->XferSize > 0U)
1235 {
1236 if (hi2c->XferSize <= 3U)
1237 {
1238 /* One byte */
1239 if (hi2c->XferSize == 1U)
1240 {
1241 /* Wait until RXNE flag is set */
1242 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1243 {
1244 return HAL_ERROR;
1245 }
1246
1247 /* Read data from DR */
1248 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1249
1250 /* Increment Buffer pointer */
1251 hi2c->pBuffPtr++;
1252
1253 /* Update counter */
1254 hi2c->XferSize--;
1255 hi2c->XferCount--;
1256 }
1257 /* Two bytes */
1258 else if (hi2c->XferSize == 2U)
1259 {
1260 /* Wait until BTF flag is set */
1261 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1262 {
1263 return HAL_ERROR;
1264 }
1265
1266 /* Generate Stop */
1267 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1268
1269 /* Read data from DR */
1270 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1271
1272 /* Increment Buffer pointer */
1273 hi2c->pBuffPtr++;
1274
1275 /* Update counter */
1276 hi2c->XferSize--;
1277 hi2c->XferCount--;
1278
1279 /* Read data from DR */
1280 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1281
1282 /* Increment Buffer pointer */
1283 hi2c->pBuffPtr++;
1284
1285 /* Update counter */
1286 hi2c->XferSize--;
1287 hi2c->XferCount--;
1288 }
1289 /* 3 Last bytes */
1290 else
1291 {
1292 /* Wait until BTF flag is set */
1293 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1294 {
1295 return HAL_ERROR;
1296 }
1297
1298 /* Disable Acknowledge */
1299 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1300
1301 /* Read data from DR */
1302 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1303
1304 /* Increment Buffer pointer */
1305 hi2c->pBuffPtr++;
1306
1307 /* Update counter */
1308 hi2c->XferSize--;
1309 hi2c->XferCount--;
1310
1311 /* Wait until BTF flag is set */
1312 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1313 {
1314 return HAL_ERROR;
1315 }
1316
1317 /* Generate Stop */
1318 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1319
1320 /* Read data from DR */
1321 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1322
1323 /* Increment Buffer pointer */
1324 hi2c->pBuffPtr++;
1325
1326 /* Update counter */
1327 hi2c->XferSize--;
1328 hi2c->XferCount--;
1329
1330 /* Read data from DR */
1331 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1332
1333 /* Increment Buffer pointer */
1334 hi2c->pBuffPtr++;
1335
1336 /* Update counter */
1337 hi2c->XferSize--;
1338 hi2c->XferCount--;
1339 }
1340 }
1341 else
1342 {
1343 /* Wait until RXNE flag is set */
1344 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1345 {
1346 return HAL_ERROR;
1347 }
1348
1349 /* Read data from DR */
1350 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1351
1352 /* Increment Buffer pointer */
1353 hi2c->pBuffPtr++;
1354
1355 /* Update counter */
1356 hi2c->XferSize--;
1357 hi2c->XferCount--;
1358
1359 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1360 {
1361 /* Read data from DR */
1362 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1363
1364 /* Increment Buffer pointer */
1365 hi2c->pBuffPtr++;
1366
1367 /* Update counter */
1368 hi2c->XferSize--;
1369 hi2c->XferCount--;
1370 }
1371 }
1372 }
1373
1374 hi2c->State = HAL_I2C_STATE_READY;
1375 hi2c->Mode = HAL_I2C_MODE_NONE;
1376
1377 /* Process Unlocked */
1378 __HAL_UNLOCK(hi2c);
1379
1380 return HAL_OK;
1381 }
1382 else
1383 {
1384 return HAL_BUSY;
1385 }
1386 }
1387
1388 /**
1389 * @brief Transmits in slave mode an amount of data in blocking mode.
1390 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1391 * the configuration information for the specified I2C.
1392 * @param pData Pointer to data buffer
1393 * @param Size Amount of data to be sent
1394 * @param Timeout Timeout duration
1395 * @retval HAL status
1396 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1397 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1398 {
1399 /* Init tickstart for timeout management*/
1400 uint32_t tickstart = HAL_GetTick();
1401
1402 if (hi2c->State == HAL_I2C_STATE_READY)
1403 {
1404 if ((pData == NULL) || (Size == 0U))
1405 {
1406 return HAL_ERROR;
1407 }
1408
1409 /* Process Locked */
1410 __HAL_LOCK(hi2c);
1411
1412 /* Check if the I2C is already enabled */
1413 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1414 {
1415 /* Enable I2C peripheral */
1416 __HAL_I2C_ENABLE(hi2c);
1417 }
1418
1419 /* Disable Pos */
1420 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1421
1422 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1423 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1424 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1425
1426 /* Prepare transfer parameters */
1427 hi2c->pBuffPtr = pData;
1428 hi2c->XferCount = Size;
1429 hi2c->XferSize = hi2c->XferCount;
1430 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1431
1432 /* Enable Address Acknowledge */
1433 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1434
1435 /* Wait until ADDR flag is set */
1436 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1437 {
1438 return HAL_ERROR;
1439 }
1440
1441 /* Clear ADDR flag */
1442 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1443
1444 /* If 10bit addressing mode is selected */
1445 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1446 {
1447 /* Wait until ADDR flag is set */
1448 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1449 {
1450 return HAL_ERROR;
1451 }
1452
1453 /* Clear ADDR flag */
1454 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1455 }
1456
1457 while (hi2c->XferSize > 0U)
1458 {
1459 /* Wait until TXE flag is set */
1460 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1461 {
1462 /* Disable Address Acknowledge */
1463 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1464
1465 return HAL_ERROR;
1466 }
1467
1468 /* Write data to DR */
1469 hi2c->Instance->DR = *hi2c->pBuffPtr;
1470
1471 /* Increment Buffer pointer */
1472 hi2c->pBuffPtr++;
1473
1474 /* Update counter */
1475 hi2c->XferCount--;
1476 hi2c->XferSize--;
1477
1478 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1479 {
1480 /* Write data to DR */
1481 hi2c->Instance->DR = *hi2c->pBuffPtr;
1482
1483 /* Increment Buffer pointer */
1484 hi2c->pBuffPtr++;
1485
1486 /* Update counter */
1487 hi2c->XferCount--;
1488 hi2c->XferSize--;
1489 }
1490 }
1491
1492 /* Wait until AF flag is set */
1493 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1494 {
1495 return HAL_ERROR;
1496 }
1497
1498 /* Clear AF flag */
1499 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1500
1501 /* Disable Address Acknowledge */
1502 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1503
1504 hi2c->State = HAL_I2C_STATE_READY;
1505 hi2c->Mode = HAL_I2C_MODE_NONE;
1506
1507 /* Process Unlocked */
1508 __HAL_UNLOCK(hi2c);
1509
1510 return HAL_OK;
1511 }
1512 else
1513 {
1514 return HAL_BUSY;
1515 }
1516 }
1517
1518 /**
1519 * @brief Receive in slave mode an amount of data in blocking mode
1520 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1521 * the configuration information for the specified I2C.
1522 * @param pData Pointer to data buffer
1523 * @param Size Amount of data to be sent
1524 * @param Timeout Timeout duration
1525 * @retval HAL status
1526 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1527 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1528 {
1529 /* Init tickstart for timeout management*/
1530 uint32_t tickstart = HAL_GetTick();
1531
1532 if (hi2c->State == HAL_I2C_STATE_READY)
1533 {
1534 if ((pData == NULL) || (Size == (uint16_t)0))
1535 {
1536 return HAL_ERROR;
1537 }
1538
1539 /* Process Locked */
1540 __HAL_LOCK(hi2c);
1541
1542 /* Check if the I2C is already enabled */
1543 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1544 {
1545 /* Enable I2C peripheral */
1546 __HAL_I2C_ENABLE(hi2c);
1547 }
1548
1549 /* Disable Pos */
1550 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1551
1552 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1553 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1554 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1555
1556 /* Prepare transfer parameters */
1557 hi2c->pBuffPtr = pData;
1558 hi2c->XferCount = Size;
1559 hi2c->XferSize = hi2c->XferCount;
1560 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1561
1562 /* Enable Address Acknowledge */
1563 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1564
1565 /* Wait until ADDR flag is set */
1566 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1567 {
1568 return HAL_ERROR;
1569 }
1570
1571 /* Clear ADDR flag */
1572 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1573
1574 while (hi2c->XferSize > 0U)
1575 {
1576 /* Wait until RXNE flag is set */
1577 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1578 {
1579 /* Disable Address Acknowledge */
1580 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1581
1582 return HAL_ERROR;
1583 }
1584
1585 /* Read data from DR */
1586 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1587
1588 /* Increment Buffer pointer */
1589 hi2c->pBuffPtr++;
1590
1591 /* Update counter */
1592 hi2c->XferSize--;
1593 hi2c->XferCount--;
1594
1595 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1596 {
1597 /* Read data from DR */
1598 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1599
1600 /* Increment Buffer pointer */
1601 hi2c->pBuffPtr++;
1602
1603 /* Update counter */
1604 hi2c->XferSize--;
1605 hi2c->XferCount--;
1606 }
1607 }
1608
1609 /* Wait until STOP flag is set */
1610 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1611 {
1612 /* Disable Address Acknowledge */
1613 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1614
1615 return HAL_ERROR;
1616 }
1617
1618 /* Clear STOP flag */
1619 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1620
1621 /* Disable Address Acknowledge */
1622 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1623
1624 hi2c->State = HAL_I2C_STATE_READY;
1625 hi2c->Mode = HAL_I2C_MODE_NONE;
1626
1627 /* Process Unlocked */
1628 __HAL_UNLOCK(hi2c);
1629
1630 return HAL_OK;
1631 }
1632 else
1633 {
1634 return HAL_BUSY;
1635 }
1636 }
1637
1638 /**
1639 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1640 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1641 * the configuration information for the specified I2C.
1642 * @param DevAddress Target device address: The device 7 bits address value
1643 * in datasheet must be shifted to the left before calling the interface
1644 * @param pData Pointer to data buffer
1645 * @param Size Amount of data to be sent
1646 * @retval HAL status
1647 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1648 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1649 {
1650 __IO uint32_t count = 0U;
1651
1652 if (hi2c->State == HAL_I2C_STATE_READY)
1653 {
1654 /* Wait until BUSY flag is reset */
1655 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1656 do
1657 {
1658 count--;
1659 if (count == 0U)
1660 {
1661 hi2c->PreviousState = I2C_STATE_NONE;
1662 hi2c->State = HAL_I2C_STATE_READY;
1663 hi2c->Mode = HAL_I2C_MODE_NONE;
1664 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1665
1666 /* Process Unlocked */
1667 __HAL_UNLOCK(hi2c);
1668
1669 return HAL_ERROR;
1670 }
1671 }
1672 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1673
1674 /* Process Locked */
1675 __HAL_LOCK(hi2c);
1676
1677 /* Check if the I2C is already enabled */
1678 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1679 {
1680 /* Enable I2C peripheral */
1681 __HAL_I2C_ENABLE(hi2c);
1682 }
1683
1684 /* Disable Pos */
1685 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1686
1687 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1688 hi2c->Mode = HAL_I2C_MODE_MASTER;
1689 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1690
1691 /* Prepare transfer parameters */
1692 hi2c->pBuffPtr = pData;
1693 hi2c->XferCount = Size;
1694 hi2c->XferSize = hi2c->XferCount;
1695 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1696 hi2c->Devaddress = DevAddress;
1697
1698 /* Generate Start */
1699 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1700
1701 /* Process Unlocked */
1702 __HAL_UNLOCK(hi2c);
1703
1704 /* Note : The I2C interrupts must be enabled after unlocking current process
1705 to avoid the risk of I2C interrupt handle execution before current
1706 process unlock */
1707 /* Enable EVT, BUF and ERR interrupt */
1708 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1709
1710 return HAL_OK;
1711 }
1712 else
1713 {
1714 return HAL_BUSY;
1715 }
1716 }
1717
1718 /**
1719 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1720 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1721 * the configuration information for the specified I2C.
1722 * @param DevAddress Target device address: The device 7 bits address value
1723 * in datasheet must be shifted to the left before calling the interface
1724 * @param pData Pointer to data buffer
1725 * @param Size Amount of data to be sent
1726 * @retval HAL status
1727 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1728 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1729 {
1730 __IO uint32_t count = 0U;
1731
1732 if (hi2c->State == HAL_I2C_STATE_READY)
1733 {
1734 /* Wait until BUSY flag is reset */
1735 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1736 do
1737 {
1738 count--;
1739 if (count == 0U)
1740 {
1741 hi2c->PreviousState = I2C_STATE_NONE;
1742 hi2c->State = HAL_I2C_STATE_READY;
1743 hi2c->Mode = HAL_I2C_MODE_NONE;
1744 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1745
1746 /* Process Unlocked */
1747 __HAL_UNLOCK(hi2c);
1748
1749 return HAL_ERROR;
1750 }
1751 }
1752 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1753
1754 /* Process Locked */
1755 __HAL_LOCK(hi2c);
1756
1757 /* Check if the I2C is already enabled */
1758 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1759 {
1760 /* Enable I2C peripheral */
1761 __HAL_I2C_ENABLE(hi2c);
1762 }
1763
1764 /* Disable Pos */
1765 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1766
1767 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1768 hi2c->Mode = HAL_I2C_MODE_MASTER;
1769 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1770
1771 /* Prepare transfer parameters */
1772 hi2c->pBuffPtr = pData;
1773 hi2c->XferCount = Size;
1774 hi2c->XferSize = hi2c->XferCount;
1775 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1776 hi2c->Devaddress = DevAddress;
1777
1778 /* Enable Acknowledge */
1779 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1780
1781 /* Generate Start */
1782 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1783
1784 /* Process Unlocked */
1785 __HAL_UNLOCK(hi2c);
1786
1787 /* Note : The I2C interrupts must be enabled after unlocking current process
1788 to avoid the risk of I2C interrupt handle execution before current
1789 process unlock */
1790
1791 /* Enable EVT, BUF and ERR interrupt */
1792 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1793
1794 return HAL_OK;
1795 }
1796 else
1797 {
1798 return HAL_BUSY;
1799 }
1800 }
1801
1802 /**
1803 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1804 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1805 * the configuration information for the specified I2C.
1806 * @param pData Pointer to data buffer
1807 * @param Size Amount of data to be sent
1808 * @retval HAL status
1809 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1810 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1811 {
1812
1813 if (hi2c->State == HAL_I2C_STATE_READY)
1814 {
1815 if ((pData == NULL) || (Size == 0U))
1816 {
1817 return HAL_ERROR;
1818 }
1819
1820 /* Process Locked */
1821 __HAL_LOCK(hi2c);
1822
1823 /* Check if the I2C is already enabled */
1824 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1825 {
1826 /* Enable I2C peripheral */
1827 __HAL_I2C_ENABLE(hi2c);
1828 }
1829
1830 /* Disable Pos */
1831 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1832
1833 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1834 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1835 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1836
1837 /* Prepare transfer parameters */
1838 hi2c->pBuffPtr = pData;
1839 hi2c->XferCount = Size;
1840 hi2c->XferSize = hi2c->XferCount;
1841 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1842
1843 /* Enable Address Acknowledge */
1844 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1845
1846 /* Process Unlocked */
1847 __HAL_UNLOCK(hi2c);
1848
1849 /* Note : The I2C interrupts must be enabled after unlocking current process
1850 to avoid the risk of I2C interrupt handle execution before current
1851 process unlock */
1852
1853 /* Enable EVT, BUF and ERR interrupt */
1854 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1855
1856 return HAL_OK;
1857 }
1858 else
1859 {
1860 return HAL_BUSY;
1861 }
1862 }
1863
1864 /**
1865 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1866 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1867 * the configuration information for the specified I2C.
1868 * @param pData Pointer to data buffer
1869 * @param Size Amount of data to be sent
1870 * @retval HAL status
1871 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1872 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1873 {
1874
1875 if (hi2c->State == HAL_I2C_STATE_READY)
1876 {
1877 if ((pData == NULL) || (Size == 0U))
1878 {
1879 return HAL_ERROR;
1880 }
1881
1882 /* Process Locked */
1883 __HAL_LOCK(hi2c);
1884
1885 /* Check if the I2C is already enabled */
1886 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1887 {
1888 /* Enable I2C peripheral */
1889 __HAL_I2C_ENABLE(hi2c);
1890 }
1891
1892 /* Disable Pos */
1893 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1894
1895 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1896 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1897 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1898
1899 /* Prepare transfer parameters */
1900 hi2c->pBuffPtr = pData;
1901 hi2c->XferCount = Size;
1902 hi2c->XferSize = hi2c->XferCount;
1903 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1904
1905 /* Enable Address Acknowledge */
1906 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1907
1908 /* Process Unlocked */
1909 __HAL_UNLOCK(hi2c);
1910
1911 /* Note : The I2C interrupts must be enabled after unlocking current process
1912 to avoid the risk of I2C interrupt handle execution before current
1913 process unlock */
1914
1915 /* Enable EVT, BUF and ERR interrupt */
1916 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1917
1918 return HAL_OK;
1919 }
1920 else
1921 {
1922 return HAL_BUSY;
1923 }
1924 }
1925
1926 /**
1927 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1928 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1929 * the configuration information for the specified I2C.
1930 * @param DevAddress Target device address: The device 7 bits address value
1931 * in datasheet must be shifted to the left before calling the interface
1932 * @param pData Pointer to data buffer
1933 * @param Size Amount of data to be sent
1934 * @retval HAL status
1935 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1936 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1937 {
1938 __IO uint32_t count = 0U;
1939 HAL_StatusTypeDef dmaxferstatus;
1940
1941 if (hi2c->State == HAL_I2C_STATE_READY)
1942 {
1943 /* Wait until BUSY flag is reset */
1944 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1945 do
1946 {
1947 count--;
1948 if (count == 0U)
1949 {
1950 hi2c->PreviousState = I2C_STATE_NONE;
1951 hi2c->State = HAL_I2C_STATE_READY;
1952 hi2c->Mode = HAL_I2C_MODE_NONE;
1953 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1954
1955 /* Process Unlocked */
1956 __HAL_UNLOCK(hi2c);
1957
1958 return HAL_ERROR;
1959 }
1960 }
1961 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1962
1963 /* Process Locked */
1964 __HAL_LOCK(hi2c);
1965
1966 /* Check if the I2C is already enabled */
1967 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1968 {
1969 /* Enable I2C peripheral */
1970 __HAL_I2C_ENABLE(hi2c);
1971 }
1972
1973 /* Disable Pos */
1974 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1975
1976 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1977 hi2c->Mode = HAL_I2C_MODE_MASTER;
1978 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1979
1980 /* Prepare transfer parameters */
1981 hi2c->pBuffPtr = pData;
1982 hi2c->XferCount = Size;
1983 hi2c->XferSize = hi2c->XferCount;
1984 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1985 hi2c->Devaddress = DevAddress;
1986
1987 if (hi2c->XferSize > 0U)
1988 {
1989 /* Set the I2C DMA transfer complete callback */
1990 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
1991
1992 /* Set the DMA error callback */
1993 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1994
1995 /* Set the unused DMA callbacks to NULL */
1996 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1997 hi2c->hdmatx->XferM1CpltCallback = NULL;
1998 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
1999 hi2c->hdmatx->XferAbortCallback = NULL;
2000
2001 /* Enable the DMA stream */
2002 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2003
2004 if (dmaxferstatus == HAL_OK)
2005 {
2006 /* Enable Acknowledge */
2007 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2008
2009 /* Generate Start */
2010 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2011
2012 /* Process Unlocked */
2013 __HAL_UNLOCK(hi2c);
2014
2015 /* Note : The I2C interrupts must be enabled after unlocking current process
2016 to avoid the risk of I2C interrupt handle execution before current
2017 process unlock */
2018
2019 /* Enable EVT and ERR interrupt */
2020 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2021
2022 /* Enable DMA Request */
2023 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2024 }
2025 else
2026 {
2027 /* Update I2C state */
2028 hi2c->State = HAL_I2C_STATE_READY;
2029 hi2c->Mode = HAL_I2C_MODE_NONE;
2030
2031 /* Update I2C error code */
2032 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2033
2034 /* Process Unlocked */
2035 __HAL_UNLOCK(hi2c);
2036
2037 return HAL_ERROR;
2038 }
2039 }
2040 else
2041 {
2042 /* Enable Acknowledge */
2043 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2044
2045 /* Generate Start */
2046 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2047
2048 /* Process Unlocked */
2049 __HAL_UNLOCK(hi2c);
2050
2051 /* Note : The I2C interrupts must be enabled after unlocking current process
2052 to avoid the risk of I2C interrupt handle execution before current
2053 process unlock */
2054
2055 /* Enable EVT, BUF and ERR interrupt */
2056 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2057 }
2058
2059 return HAL_OK;
2060 }
2061 else
2062 {
2063 return HAL_BUSY;
2064 }
2065 }
2066
2067 /**
2068 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2069 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2070 * the configuration information for the specified I2C.
2071 * @param DevAddress Target device address: The device 7 bits address value
2072 * in datasheet must be shifted to the left before calling the interface
2073 * @param pData Pointer to data buffer
2074 * @param Size Amount of data to be sent
2075 * @retval HAL status
2076 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2077 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2078 {
2079 __IO uint32_t count = 0U;
2080 HAL_StatusTypeDef dmaxferstatus;
2081
2082 if (hi2c->State == HAL_I2C_STATE_READY)
2083 {
2084 /* Wait until BUSY flag is reset */
2085 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2086 do
2087 {
2088 count--;
2089 if (count == 0U)
2090 {
2091 hi2c->PreviousState = I2C_STATE_NONE;
2092 hi2c->State = HAL_I2C_STATE_READY;
2093 hi2c->Mode = HAL_I2C_MODE_NONE;
2094 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2095
2096 /* Process Unlocked */
2097 __HAL_UNLOCK(hi2c);
2098
2099 return HAL_ERROR;
2100 }
2101 }
2102 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2103
2104 /* Process Locked */
2105 __HAL_LOCK(hi2c);
2106
2107 /* Check if the I2C is already enabled */
2108 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2109 {
2110 /* Enable I2C peripheral */
2111 __HAL_I2C_ENABLE(hi2c);
2112 }
2113
2114 /* Disable Pos */
2115 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2116
2117 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2118 hi2c->Mode = HAL_I2C_MODE_MASTER;
2119 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2120
2121 /* Prepare transfer parameters */
2122 hi2c->pBuffPtr = pData;
2123 hi2c->XferCount = Size;
2124 hi2c->XferSize = hi2c->XferCount;
2125 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2126 hi2c->Devaddress = DevAddress;
2127
2128 if (hi2c->XferSize > 0U)
2129 {
2130 /* Set the I2C DMA transfer complete callback */
2131 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2132
2133 /* Set the DMA error callback */
2134 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2135
2136 /* Set the unused DMA callbacks to NULL */
2137 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2138 hi2c->hdmarx->XferM1CpltCallback = NULL;
2139 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2140 hi2c->hdmarx->XferAbortCallback = NULL;
2141
2142 /* Enable the DMA stream */
2143 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2144
2145 if (dmaxferstatus == HAL_OK)
2146 {
2147 /* Enable Acknowledge */
2148 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2149
2150 /* Generate Start */
2151 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2152
2153 /* Process Unlocked */
2154 __HAL_UNLOCK(hi2c);
2155
2156 /* Note : The I2C interrupts must be enabled after unlocking current process
2157 to avoid the risk of I2C interrupt handle execution before current
2158 process unlock */
2159
2160 /* Enable EVT and ERR interrupt */
2161 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2162
2163 /* Enable DMA Request */
2164 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2165 }
2166 else
2167 {
2168 /* Update I2C state */
2169 hi2c->State = HAL_I2C_STATE_READY;
2170 hi2c->Mode = HAL_I2C_MODE_NONE;
2171
2172 /* Update I2C error code */
2173 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2174
2175 /* Process Unlocked */
2176 __HAL_UNLOCK(hi2c);
2177
2178 return HAL_ERROR;
2179 }
2180 }
2181 else
2182 {
2183 /* Enable Acknowledge */
2184 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2185
2186 /* Generate Start */
2187 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2188
2189 /* Process Unlocked */
2190 __HAL_UNLOCK(hi2c);
2191
2192 /* Note : The I2C interrupts must be enabled after unlocking current process
2193 to avoid the risk of I2C interrupt handle execution before current
2194 process unlock */
2195
2196 /* Enable EVT, BUF and ERR interrupt */
2197 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2198 }
2199
2200 return HAL_OK;
2201 }
2202 else
2203 {
2204 return HAL_BUSY;
2205 }
2206 }
2207
2208 /**
2209 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2210 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2211 * the configuration information for the specified I2C.
2212 * @param pData Pointer to data buffer
2213 * @param Size Amount of data to be sent
2214 * @retval HAL status
2215 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2216 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2217 {
2218 HAL_StatusTypeDef dmaxferstatus;
2219
2220 if (hi2c->State == HAL_I2C_STATE_READY)
2221 {
2222 if ((pData == NULL) || (Size == 0U))
2223 {
2224 return HAL_ERROR;
2225 }
2226
2227 /* Process Locked */
2228 __HAL_LOCK(hi2c);
2229
2230 /* Check if the I2C is already enabled */
2231 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2232 {
2233 /* Enable I2C peripheral */
2234 __HAL_I2C_ENABLE(hi2c);
2235 }
2236
2237 /* Disable Pos */
2238 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2239
2240 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2241 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2242 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2243
2244 /* Prepare transfer parameters */
2245 hi2c->pBuffPtr = pData;
2246 hi2c->XferCount = Size;
2247 hi2c->XferSize = hi2c->XferCount;
2248 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2249
2250 /* Set the I2C DMA transfer complete callback */
2251 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2252
2253 /* Set the DMA error callback */
2254 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2255
2256 /* Set the unused DMA callbacks to NULL */
2257 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2258 hi2c->hdmatx->XferM1CpltCallback = NULL;
2259 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2260 hi2c->hdmatx->XferAbortCallback = NULL;
2261
2262 /* Enable the DMA stream */
2263 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2264
2265 if (dmaxferstatus == HAL_OK)
2266 {
2267 /* Enable Address Acknowledge */
2268 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2269
2270 /* Process Unlocked */
2271 __HAL_UNLOCK(hi2c);
2272
2273 /* Note : The I2C interrupts must be enabled after unlocking current process
2274 to avoid the risk of I2C interrupt handle execution before current
2275 process unlock */
2276 /* Enable EVT and ERR interrupt */
2277 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2278
2279 /* Enable DMA Request */
2280 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2281
2282 return HAL_OK;
2283 }
2284 else
2285 {
2286 /* Update I2C state */
2287 hi2c->State = HAL_I2C_STATE_READY;
2288 hi2c->Mode = HAL_I2C_MODE_NONE;
2289
2290 /* Update I2C error code */
2291 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2292
2293 /* Process Unlocked */
2294 __HAL_UNLOCK(hi2c);
2295
2296 return HAL_ERROR;
2297 }
2298 }
2299 else
2300 {
2301 return HAL_BUSY;
2302 }
2303 }
2304
2305 /**
2306 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2307 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2308 * the configuration information for the specified I2C.
2309 * @param pData Pointer to data buffer
2310 * @param Size Amount of data to be sent
2311 * @retval HAL status
2312 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2313 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2314 {
2315 HAL_StatusTypeDef dmaxferstatus;
2316
2317 if (hi2c->State == HAL_I2C_STATE_READY)
2318 {
2319 if ((pData == NULL) || (Size == 0U))
2320 {
2321 return HAL_ERROR;
2322 }
2323
2324 /* Process Locked */
2325 __HAL_LOCK(hi2c);
2326
2327 /* Check if the I2C is already enabled */
2328 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2329 {
2330 /* Enable I2C peripheral */
2331 __HAL_I2C_ENABLE(hi2c);
2332 }
2333
2334 /* Disable Pos */
2335 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2336
2337 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2338 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2339 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2340
2341 /* Prepare transfer parameters */
2342 hi2c->pBuffPtr = pData;
2343 hi2c->XferCount = Size;
2344 hi2c->XferSize = hi2c->XferCount;
2345 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2346
2347 /* Set the I2C DMA transfer complete callback */
2348 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2349
2350 /* Set the DMA error callback */
2351 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2352
2353 /* Set the unused DMA callbacks to NULL */
2354 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2355 hi2c->hdmarx->XferM1CpltCallback = NULL;
2356 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2357 hi2c->hdmarx->XferAbortCallback = NULL;
2358
2359 /* Enable the DMA stream */
2360 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2361
2362 if (dmaxferstatus == HAL_OK)
2363 {
2364 /* Enable Address Acknowledge */
2365 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2366
2367 /* Process Unlocked */
2368 __HAL_UNLOCK(hi2c);
2369
2370 /* Note : The I2C interrupts must be enabled after unlocking current process
2371 to avoid the risk of I2C interrupt handle execution before current
2372 process unlock */
2373 /* Enable EVT and ERR interrupt */
2374 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2375
2376 /* Enable DMA Request */
2377 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2378
2379 return HAL_OK;
2380 }
2381 else
2382 {
2383 /* Update I2C state */
2384 hi2c->State = HAL_I2C_STATE_READY;
2385 hi2c->Mode = HAL_I2C_MODE_NONE;
2386
2387 /* Update I2C error code */
2388 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2389
2390 /* Process Unlocked */
2391 __HAL_UNLOCK(hi2c);
2392
2393 return HAL_ERROR;
2394 }
2395 }
2396 else
2397 {
2398 return HAL_BUSY;
2399 }
2400 }
2401
2402 /**
2403 * @brief Write an amount of data in blocking mode to a specific memory address
2404 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2405 * the configuration information for the specified I2C.
2406 * @param DevAddress Target device address: The device 7 bits address value
2407 * in datasheet must be shifted to the left before calling the interface
2408 * @param MemAddress Internal memory address
2409 * @param MemAddSize Size of internal memory address
2410 * @param pData Pointer to data buffer
2411 * @param Size Amount of data to be sent
2412 * @param Timeout Timeout duration
2413 * @retval HAL status
2414 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2415 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2416 {
2417 /* Init tickstart for timeout management*/
2418 uint32_t tickstart = HAL_GetTick();
2419
2420 /* Check the parameters */
2421 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2422
2423 if (hi2c->State == HAL_I2C_STATE_READY)
2424 {
2425 /* Wait until BUSY flag is reset */
2426 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2427 {
2428 return HAL_BUSY;
2429 }
2430
2431 /* Process Locked */
2432 __HAL_LOCK(hi2c);
2433
2434 /* Check if the I2C is already enabled */
2435 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2436 {
2437 /* Enable I2C peripheral */
2438 __HAL_I2C_ENABLE(hi2c);
2439 }
2440
2441 /* Disable Pos */
2442 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2443
2444 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2445 hi2c->Mode = HAL_I2C_MODE_MEM;
2446 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2447
2448 /* Prepare transfer parameters */
2449 hi2c->pBuffPtr = pData;
2450 hi2c->XferCount = Size;
2451 hi2c->XferSize = hi2c->XferCount;
2452 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2453
2454 /* Send Slave Address and Memory Address */
2455 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2456 {
2457 return HAL_ERROR;
2458 }
2459
2460 while (hi2c->XferSize > 0U)
2461 {
2462 /* Wait until TXE flag is set */
2463 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2464 {
2465 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2466 {
2467 /* Generate Stop */
2468 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2469 }
2470 return HAL_ERROR;
2471 }
2472
2473 /* Write data to DR */
2474 hi2c->Instance->DR = *hi2c->pBuffPtr;
2475
2476 /* Increment Buffer pointer */
2477 hi2c->pBuffPtr++;
2478
2479 /* Update counter */
2480 hi2c->XferSize--;
2481 hi2c->XferCount--;
2482
2483 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2484 {
2485 /* Write data to DR */
2486 hi2c->Instance->DR = *hi2c->pBuffPtr;
2487
2488 /* Increment Buffer pointer */
2489 hi2c->pBuffPtr++;
2490
2491 /* Update counter */
2492 hi2c->XferSize--;
2493 hi2c->XferCount--;
2494 }
2495 }
2496
2497 /* Wait until BTF flag is set */
2498 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2499 {
2500 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2501 {
2502 /* Generate Stop */
2503 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2504 }
2505 return HAL_ERROR;
2506 }
2507
2508 /* Generate Stop */
2509 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2510
2511 hi2c->State = HAL_I2C_STATE_READY;
2512 hi2c->Mode = HAL_I2C_MODE_NONE;
2513
2514 /* Process Unlocked */
2515 __HAL_UNLOCK(hi2c);
2516
2517 return HAL_OK;
2518 }
2519 else
2520 {
2521 return HAL_BUSY;
2522 }
2523 }
2524
2525 /**
2526 * @brief Read an amount of data in blocking mode from a specific memory address
2527 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2528 * the configuration information for the specified I2C.
2529 * @param DevAddress Target device address: The device 7 bits address value
2530 * in datasheet must be shifted to the left before calling the interface
2531 * @param MemAddress Internal memory address
2532 * @param MemAddSize Size of internal memory address
2533 * @param pData Pointer to data buffer
2534 * @param Size Amount of data to be sent
2535 * @param Timeout Timeout duration
2536 * @retval HAL status
2537 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2538 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2539 {
2540 /* Init tickstart for timeout management*/
2541 uint32_t tickstart = HAL_GetTick();
2542
2543 /* Check the parameters */
2544 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2545
2546 if (hi2c->State == HAL_I2C_STATE_READY)
2547 {
2548 /* Wait until BUSY flag is reset */
2549 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2550 {
2551 return HAL_BUSY;
2552 }
2553
2554 /* Process Locked */
2555 __HAL_LOCK(hi2c);
2556
2557 /* Check if the I2C is already enabled */
2558 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2559 {
2560 /* Enable I2C peripheral */
2561 __HAL_I2C_ENABLE(hi2c);
2562 }
2563
2564 /* Disable Pos */
2565 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2566
2567 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2568 hi2c->Mode = HAL_I2C_MODE_MEM;
2569 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2570
2571 /* Prepare transfer parameters */
2572 hi2c->pBuffPtr = pData;
2573 hi2c->XferCount = Size;
2574 hi2c->XferSize = hi2c->XferCount;
2575 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2576
2577 /* Send Slave Address and Memory Address */
2578 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2579 {
2580 return HAL_ERROR;
2581 }
2582
2583 if (hi2c->XferSize == 0U)
2584 {
2585 /* Clear ADDR flag */
2586 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2587
2588 /* Generate Stop */
2589 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2590 }
2591 else if (hi2c->XferSize == 1U)
2592 {
2593 /* Disable Acknowledge */
2594 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2595
2596 /* Clear ADDR flag */
2597 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2598
2599 /* Generate Stop */
2600 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2601 }
2602 else if (hi2c->XferSize == 2U)
2603 {
2604 /* Disable Acknowledge */
2605 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2606
2607 /* Enable Pos */
2608 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2609
2610 /* Clear ADDR flag */
2611 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2612 }
2613 else
2614 {
2615 /* Clear ADDR flag */
2616 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2617 }
2618
2619 while (hi2c->XferSize > 0U)
2620 {
2621 if (hi2c->XferSize <= 3U)
2622 {
2623 /* One byte */
2624 if (hi2c->XferSize == 1U)
2625 {
2626 /* Wait until RXNE flag is set */
2627 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2628 {
2629 return HAL_ERROR;
2630 }
2631
2632 /* Read data from DR */
2633 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2634
2635 /* Increment Buffer pointer */
2636 hi2c->pBuffPtr++;
2637
2638 /* Update counter */
2639 hi2c->XferSize--;
2640 hi2c->XferCount--;
2641 }
2642 /* Two bytes */
2643 else if (hi2c->XferSize == 2U)
2644 {
2645 /* Wait until BTF flag is set */
2646 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2647 {
2648 return HAL_ERROR;
2649 }
2650
2651 /* Generate Stop */
2652 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2653
2654 /* Read data from DR */
2655 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2656
2657 /* Increment Buffer pointer */
2658 hi2c->pBuffPtr++;
2659
2660 /* Update counter */
2661 hi2c->XferSize--;
2662 hi2c->XferCount--;
2663
2664 /* Read data from DR */
2665 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2666
2667 /* Increment Buffer pointer */
2668 hi2c->pBuffPtr++;
2669
2670 /* Update counter */
2671 hi2c->XferSize--;
2672 hi2c->XferCount--;
2673 }
2674 /* 3 Last bytes */
2675 else
2676 {
2677 /* Wait until BTF flag is set */
2678 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2679 {
2680 return HAL_ERROR;
2681 }
2682
2683 /* Disable Acknowledge */
2684 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2685
2686 /* Read data from DR */
2687 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2688
2689 /* Increment Buffer pointer */
2690 hi2c->pBuffPtr++;
2691
2692 /* Update counter */
2693 hi2c->XferSize--;
2694 hi2c->XferCount--;
2695
2696 /* Wait until BTF flag is set */
2697 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2698 {
2699 return HAL_ERROR;
2700 }
2701
2702 /* Generate Stop */
2703 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2704
2705 /* Read data from DR */
2706 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2707
2708 /* Increment Buffer pointer */
2709 hi2c->pBuffPtr++;
2710
2711 /* Update counter */
2712 hi2c->XferSize--;
2713 hi2c->XferCount--;
2714
2715 /* Read data from DR */
2716 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2717
2718 /* Increment Buffer pointer */
2719 hi2c->pBuffPtr++;
2720
2721 /* Update counter */
2722 hi2c->XferSize--;
2723 hi2c->XferCount--;
2724 }
2725 }
2726 else
2727 {
2728 /* Wait until RXNE flag is set */
2729 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2730 {
2731 return HAL_ERROR;
2732 }
2733
2734 /* Read data from DR */
2735 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2736
2737 /* Increment Buffer pointer */
2738 hi2c->pBuffPtr++;
2739
2740 /* Update counter */
2741 hi2c->XferSize--;
2742 hi2c->XferCount--;
2743
2744 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2745 {
2746 /* Read data from DR */
2747 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2748
2749 /* Increment Buffer pointer */
2750 hi2c->pBuffPtr++;
2751
2752 /* Update counter */
2753 hi2c->XferSize--;
2754 hi2c->XferCount--;
2755 }
2756 }
2757 }
2758
2759 hi2c->State = HAL_I2C_STATE_READY;
2760 hi2c->Mode = HAL_I2C_MODE_NONE;
2761
2762 /* Process Unlocked */
2763 __HAL_UNLOCK(hi2c);
2764
2765 return HAL_OK;
2766 }
2767 else
2768 {
2769 return HAL_BUSY;
2770 }
2771 }
2772
2773 /**
2774 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2775 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2776 * the configuration information for the specified I2C.
2777 * @param DevAddress Target device address: The device 7 bits address value
2778 * in datasheet must be shifted to the left before calling the interface
2779 * @param MemAddress Internal memory address
2780 * @param MemAddSize Size of internal memory address
2781 * @param pData Pointer to data buffer
2782 * @param Size Amount of data to be sent
2783 * @retval HAL status
2784 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2785 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2786 {
2787 __IO uint32_t count = 0U;
2788
2789 /* Check the parameters */
2790 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2791
2792 if (hi2c->State == HAL_I2C_STATE_READY)
2793 {
2794 /* Wait until BUSY flag is reset */
2795 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2796 do
2797 {
2798 count--;
2799 if (count == 0U)
2800 {
2801 hi2c->PreviousState = I2C_STATE_NONE;
2802 hi2c->State = HAL_I2C_STATE_READY;
2803 hi2c->Mode = HAL_I2C_MODE_NONE;
2804 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2805
2806 /* Process Unlocked */
2807 __HAL_UNLOCK(hi2c);
2808
2809 return HAL_ERROR;
2810 }
2811 }
2812 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2813
2814 /* Process Locked */
2815 __HAL_LOCK(hi2c);
2816
2817 /* Check if the I2C is already enabled */
2818 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2819 {
2820 /* Enable I2C peripheral */
2821 __HAL_I2C_ENABLE(hi2c);
2822 }
2823
2824 /* Disable Pos */
2825 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2826
2827 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2828 hi2c->Mode = HAL_I2C_MODE_MEM;
2829 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2830
2831 /* Prepare transfer parameters */
2832 hi2c->pBuffPtr = pData;
2833 hi2c->XferCount = Size;
2834 hi2c->XferSize = hi2c->XferCount;
2835 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2836 hi2c->Devaddress = DevAddress;
2837 hi2c->Memaddress = MemAddress;
2838 hi2c->MemaddSize = MemAddSize;
2839 hi2c->EventCount = 0U;
2840
2841 /* Generate Start */
2842 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2843
2844 /* Process Unlocked */
2845 __HAL_UNLOCK(hi2c);
2846
2847 /* Note : The I2C interrupts must be enabled after unlocking current process
2848 to avoid the risk of I2C interrupt handle execution before current
2849 process unlock */
2850
2851 /* Enable EVT, BUF and ERR interrupt */
2852 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2853
2854 return HAL_OK;
2855 }
2856 else
2857 {
2858 return HAL_BUSY;
2859 }
2860 }
2861
2862 /**
2863 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2864 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2865 * the configuration information for the specified I2C.
2866 * @param DevAddress Target device address
2867 * @param MemAddress Internal memory address
2868 * @param MemAddSize Size of internal memory address
2869 * @param pData Pointer to data buffer
2870 * @param Size Amount of data to be sent
2871 * @retval HAL status
2872 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2873 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2874 {
2875 __IO uint32_t count = 0U;
2876
2877 /* Check the parameters */
2878 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2879
2880 if (hi2c->State == HAL_I2C_STATE_READY)
2881 {
2882 /* Wait until BUSY flag is reset */
2883 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2884 do
2885 {
2886 count--;
2887 if (count == 0U)
2888 {
2889 hi2c->PreviousState = I2C_STATE_NONE;
2890 hi2c->State = HAL_I2C_STATE_READY;
2891 hi2c->Mode = HAL_I2C_MODE_NONE;
2892 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2893
2894 /* Process Unlocked */
2895 __HAL_UNLOCK(hi2c);
2896
2897 return HAL_ERROR;
2898 }
2899 }
2900 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2901
2902 /* Process Locked */
2903 __HAL_LOCK(hi2c);
2904
2905 /* Check if the I2C is already enabled */
2906 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2907 {
2908 /* Enable I2C peripheral */
2909 __HAL_I2C_ENABLE(hi2c);
2910 }
2911
2912 /* Disable Pos */
2913 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2914
2915 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2916 hi2c->Mode = HAL_I2C_MODE_MEM;
2917 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2918
2919 /* Prepare transfer parameters */
2920 hi2c->pBuffPtr = pData;
2921 hi2c->XferCount = Size;
2922 hi2c->XferSize = hi2c->XferCount;
2923 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2924 hi2c->Devaddress = DevAddress;
2925 hi2c->Memaddress = MemAddress;
2926 hi2c->MemaddSize = MemAddSize;
2927 hi2c->EventCount = 0U;
2928
2929 /* Enable Acknowledge */
2930 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2931
2932 /* Generate Start */
2933 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2934
2935 /* Process Unlocked */
2936 __HAL_UNLOCK(hi2c);
2937
2938 if (hi2c->XferSize > 0U)
2939 {
2940 /* Note : The I2C interrupts must be enabled after unlocking current process
2941 to avoid the risk of I2C interrupt handle execution before current
2942 process unlock */
2943
2944 /* Enable EVT, BUF and ERR interrupt */
2945 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2946 }
2947 return HAL_OK;
2948 }
2949 else
2950 {
2951 return HAL_BUSY;
2952 }
2953 }
2954
2955 /**
2956 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2958 * the configuration information for the specified I2C.
2959 * @param DevAddress Target device address: The device 7 bits address value
2960 * in datasheet must be shifted to the left before calling the interface
2961 * @param MemAddress Internal memory address
2962 * @param MemAddSize Size of internal memory address
2963 * @param pData Pointer to data buffer
2964 * @param Size Amount of data to be sent
2965 * @retval HAL status
2966 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2967 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2968 {
2969 __IO uint32_t count = 0U;
2970 HAL_StatusTypeDef dmaxferstatus;
2971
2972 /* Init tickstart for timeout management*/
2973 uint32_t tickstart = HAL_GetTick();
2974
2975 /* Check the parameters */
2976 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2977
2978 if (hi2c->State == HAL_I2C_STATE_READY)
2979 {
2980 /* Wait until BUSY flag is reset */
2981 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2982 do
2983 {
2984 count--;
2985 if (count == 0U)
2986 {
2987 hi2c->PreviousState = I2C_STATE_NONE;
2988 hi2c->State = HAL_I2C_STATE_READY;
2989 hi2c->Mode = HAL_I2C_MODE_NONE;
2990 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2991
2992 /* Process Unlocked */
2993 __HAL_UNLOCK(hi2c);
2994
2995 return HAL_ERROR;
2996 }
2997 }
2998 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2999
3000 /* Process Locked */
3001 __HAL_LOCK(hi2c);
3002
3003 /* Check if the I2C is already enabled */
3004 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3005 {
3006 /* Enable I2C peripheral */
3007 __HAL_I2C_ENABLE(hi2c);
3008 }
3009
3010 /* Disable Pos */
3011 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3012
3013 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3014 hi2c->Mode = HAL_I2C_MODE_MEM;
3015 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3016
3017 /* Prepare transfer parameters */
3018 hi2c->pBuffPtr = pData;
3019 hi2c->XferCount = Size;
3020 hi2c->XferSize = hi2c->XferCount;
3021 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3022
3023 if (hi2c->XferSize > 0U)
3024 {
3025 /* Set the I2C DMA transfer complete callback */
3026 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3027
3028 /* Set the DMA error callback */
3029 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3030
3031 /* Set the unused DMA callbacks to NULL */
3032 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3033 hi2c->hdmatx->XferM1CpltCallback = NULL;
3034 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3035 hi2c->hdmatx->XferAbortCallback = NULL;
3036
3037 /* Enable the DMA stream */
3038 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3039
3040 if (dmaxferstatus == HAL_OK)
3041 {
3042 /* Send Slave Address and Memory Address */
3043 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3044 {
3045 /* Abort the ongoing DMA */
3046 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3047
3048 /* Prevent unused argument(s) compilation and MISRA warning */
3049 UNUSED(dmaxferstatus);
3050
3051 /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
3052 if (hi2c->hdmatx != NULL)
3053 {
3054 hi2c->hdmatx->XferCpltCallback = NULL;
3055 }
3056
3057 /* Disable Acknowledge */
3058 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3059
3060 hi2c->XferSize = 0U;
3061 hi2c->XferCount = 0U;
3062
3063 /* Disable I2C peripheral to prevent dummy data in buffer */
3064 __HAL_I2C_DISABLE(hi2c);
3065
3066 return HAL_ERROR;
3067 }
3068
3069 /* Clear ADDR flag */
3070 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3071
3072 /* Process Unlocked */
3073 __HAL_UNLOCK(hi2c);
3074
3075 /* Note : The I2C interrupts must be enabled after unlocking current process
3076 to avoid the risk of I2C interrupt handle execution before current
3077 process unlock */
3078 /* Enable ERR interrupt */
3079 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3080
3081 /* Enable DMA Request */
3082 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3083
3084 return HAL_OK;
3085 }
3086 else
3087 {
3088 /* Update I2C state */
3089 hi2c->State = HAL_I2C_STATE_READY;
3090 hi2c->Mode = HAL_I2C_MODE_NONE;
3091
3092 /* Update I2C error code */
3093 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3094
3095 /* Process Unlocked */
3096 __HAL_UNLOCK(hi2c);
3097
3098 return HAL_ERROR;
3099 }
3100 }
3101 else
3102 {
3103 /* Update I2C state */
3104 hi2c->State = HAL_I2C_STATE_READY;
3105 hi2c->Mode = HAL_I2C_MODE_NONE;
3106
3107 /* Update I2C error code */
3108 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3109
3110 /* Process Unlocked */
3111 __HAL_UNLOCK(hi2c);
3112
3113 return HAL_ERROR;
3114 }
3115 }
3116 else
3117 {
3118 return HAL_BUSY;
3119 }
3120 }
3121
3122 /**
3123 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3124 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3125 * the configuration information for the specified I2C.
3126 * @param DevAddress Target device address: The device 7 bits address value
3127 * in datasheet must be shifted to the left before calling the interface
3128 * @param MemAddress Internal memory address
3129 * @param MemAddSize Size of internal memory address
3130 * @param pData Pointer to data buffer
3131 * @param Size Amount of data to be read
3132 * @retval HAL status
3133 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3134 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3135 {
3136 /* Init tickstart for timeout management*/
3137 uint32_t tickstart = HAL_GetTick();
3138 __IO uint32_t count = 0U;
3139 HAL_StatusTypeDef dmaxferstatus;
3140
3141 /* Check the parameters */
3142 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3143
3144 if (hi2c->State == HAL_I2C_STATE_READY)
3145 {
3146 /* Wait until BUSY flag is reset */
3147 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3148 do
3149 {
3150 count--;
3151 if (count == 0U)
3152 {
3153 hi2c->PreviousState = I2C_STATE_NONE;
3154 hi2c->State = HAL_I2C_STATE_READY;
3155 hi2c->Mode = HAL_I2C_MODE_NONE;
3156 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3157
3158 /* Process Unlocked */
3159 __HAL_UNLOCK(hi2c);
3160
3161 return HAL_ERROR;
3162 }
3163 }
3164 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3165
3166 /* Process Locked */
3167 __HAL_LOCK(hi2c);
3168
3169 /* Check if the I2C is already enabled */
3170 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3171 {
3172 /* Enable I2C peripheral */
3173 __HAL_I2C_ENABLE(hi2c);
3174 }
3175
3176 /* Disable Pos */
3177 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3178
3179 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3180 hi2c->Mode = HAL_I2C_MODE_MEM;
3181 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3182
3183 /* Prepare transfer parameters */
3184 hi2c->pBuffPtr = pData;
3185 hi2c->XferCount = Size;
3186 hi2c->XferSize = hi2c->XferCount;
3187 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3188
3189 if (hi2c->XferSize > 0U)
3190 {
3191 /* Set the I2C DMA transfer complete callback */
3192 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3193
3194 /* Set the DMA error callback */
3195 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3196
3197 /* Set the unused DMA callbacks to NULL */
3198 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3199 hi2c->hdmarx->XferM1CpltCallback = NULL;
3200 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3201 hi2c->hdmarx->XferAbortCallback = NULL;
3202
3203 /* Enable the DMA stream */
3204 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3205
3206 if (dmaxferstatus == HAL_OK)
3207 {
3208 /* Send Slave Address and Memory Address */
3209 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3210 {
3211 /* Abort the ongoing DMA */
3212 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3213
3214 /* Prevent unused argument(s) compilation and MISRA warning */
3215 UNUSED(dmaxferstatus);
3216
3217 /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
3218 if (hi2c->hdmarx != NULL)
3219 {
3220 hi2c->hdmarx->XferCpltCallback = NULL;
3221 }
3222
3223 /* Disable Acknowledge */
3224 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3225
3226 hi2c->XferSize = 0U;
3227 hi2c->XferCount = 0U;
3228
3229 /* Disable I2C peripheral to prevent dummy data in buffer */
3230 __HAL_I2C_DISABLE(hi2c);
3231
3232 return HAL_ERROR;
3233 }
3234
3235 if (hi2c->XferSize == 1U)
3236 {
3237 /* Disable Acknowledge */
3238 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3239 }
3240 else
3241 {
3242 /* Enable Last DMA bit */
3243 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3244 }
3245
3246 /* Clear ADDR flag */
3247 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3248
3249 /* Process Unlocked */
3250 __HAL_UNLOCK(hi2c);
3251
3252 /* Note : The I2C interrupts must be enabled after unlocking current process
3253 to avoid the risk of I2C interrupt handle execution before current
3254 process unlock */
3255 /* Enable ERR interrupt */
3256 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3257
3258 /* Enable DMA Request */
3259 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3260 }
3261 else
3262 {
3263 /* Update I2C state */
3264 hi2c->State = HAL_I2C_STATE_READY;
3265 hi2c->Mode = HAL_I2C_MODE_NONE;
3266
3267 /* Update I2C error code */
3268 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3269
3270 /* Process Unlocked */
3271 __HAL_UNLOCK(hi2c);
3272
3273 return HAL_ERROR;
3274 }
3275 }
3276 else
3277 {
3278 /* Send Slave Address and Memory Address */
3279 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3280 {
3281 return HAL_ERROR;
3282 }
3283
3284 /* Clear ADDR flag */
3285 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3286
3287 /* Generate Stop */
3288 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3289
3290 hi2c->State = HAL_I2C_STATE_READY;
3291
3292 /* Process Unlocked */
3293 __HAL_UNLOCK(hi2c);
3294 }
3295
3296 return HAL_OK;
3297 }
3298 else
3299 {
3300 return HAL_BUSY;
3301 }
3302 }
3303
3304 /**
3305 * @brief Checks if target device is ready for communication.
3306 * @note This function is used with Memory devices
3307 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3308 * the configuration information for the specified I2C.
3309 * @param DevAddress Target device address: The device 7 bits address value
3310 * in datasheet must be shifted to the left before calling the interface
3311 * @param Trials Number of trials
3312 * @param Timeout Timeout duration
3313 * @retval HAL status
3314 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3315 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3316 {
3317 /* Get tick */
3318 uint32_t tickstart = HAL_GetTick();
3319 uint32_t I2C_Trials = 1U;
3320 FlagStatus tmp1;
3321 FlagStatus tmp2;
3322
3323 if (hi2c->State == HAL_I2C_STATE_READY)
3324 {
3325 /* Wait until BUSY flag is reset */
3326 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3327 {
3328 return HAL_BUSY;
3329 }
3330
3331 /* Process Locked */
3332 __HAL_LOCK(hi2c);
3333
3334 /* Check if the I2C is already enabled */
3335 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3336 {
3337 /* Enable I2C peripheral */
3338 __HAL_I2C_ENABLE(hi2c);
3339 }
3340
3341 /* Disable Pos */
3342 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3343
3344 hi2c->State = HAL_I2C_STATE_BUSY;
3345 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3346 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3347
3348 do
3349 {
3350 /* Generate Start */
3351 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3352
3353 /* Wait until SB flag is set */
3354 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3355 {
3356 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3357 {
3358 hi2c->ErrorCode = HAL_I2C_WRONG_START;
3359 }
3360 return HAL_TIMEOUT;
3361 }
3362
3363 /* Send slave address */
3364 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3365
3366 /* Wait until ADDR or AF flag are set */
3367 /* Get tick */
3368 tickstart = HAL_GetTick();
3369
3370 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3371 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3372 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3373 {
3374 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3375 {
3376 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3377 }
3378 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3379 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3380 }
3381
3382 hi2c->State = HAL_I2C_STATE_READY;
3383
3384 /* Check if the ADDR flag has been set */
3385 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3386 {
3387 /* Generate Stop */
3388 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3389
3390 /* Clear ADDR Flag */
3391 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3392
3393 /* Wait until BUSY flag is reset */
3394 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3395 {
3396 return HAL_ERROR;
3397 }
3398
3399 hi2c->State = HAL_I2C_STATE_READY;
3400
3401 /* Process Unlocked */
3402 __HAL_UNLOCK(hi2c);
3403
3404 return HAL_OK;
3405 }
3406 else
3407 {
3408 /* Generate Stop */
3409 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3410
3411 /* Clear AF Flag */
3412 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3413
3414 /* Wait until BUSY flag is reset */
3415 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3416 {
3417 return HAL_ERROR;
3418 }
3419 }
3420
3421 /* Increment Trials */
3422 I2C_Trials++;
3423 }
3424 while (I2C_Trials < Trials);
3425
3426 hi2c->State = HAL_I2C_STATE_READY;
3427
3428 /* Process Unlocked */
3429 __HAL_UNLOCK(hi2c);
3430
3431 return HAL_ERROR;
3432 }
3433 else
3434 {
3435 return HAL_BUSY;
3436 }
3437 }
3438
3439 /**
3440 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3441 * @note This interface allow to manage repeated start condition when a direction change during transfer
3442 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3443 * the configuration information for the specified I2C.
3444 * @param DevAddress Target device address: The device 7 bits address value
3445 * in datasheet must be shifted to the left before calling the interface
3446 * @param pData Pointer to data buffer
3447 * @param Size Amount of data to be sent
3448 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3449 * @retval HAL status
3450 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3451 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3452 {
3453 __IO uint32_t Prev_State = 0x00U;
3454 __IO uint32_t count = 0x00U;
3455
3456 /* Check the parameters */
3457 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3458
3459 if (hi2c->State == HAL_I2C_STATE_READY)
3460 {
3461 /* Check Busy Flag only if FIRST call of Master interface */
3462 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3463 {
3464 /* Wait until BUSY flag is reset */
3465 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3466 do
3467 {
3468 count--;
3469 if (count == 0U)
3470 {
3471 hi2c->PreviousState = I2C_STATE_NONE;
3472 hi2c->State = HAL_I2C_STATE_READY;
3473 hi2c->Mode = HAL_I2C_MODE_NONE;
3474 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3475
3476 /* Process Unlocked */
3477 __HAL_UNLOCK(hi2c);
3478
3479 return HAL_ERROR;
3480 }
3481 }
3482 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3483 }
3484
3485 /* Process Locked */
3486 __HAL_LOCK(hi2c);
3487
3488 /* Check if the I2C is already enabled */
3489 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3490 {
3491 /* Enable I2C peripheral */
3492 __HAL_I2C_ENABLE(hi2c);
3493 }
3494
3495 /* Disable Pos */
3496 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3497
3498 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3499 hi2c->Mode = HAL_I2C_MODE_MASTER;
3500 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3501
3502 /* Prepare transfer parameters */
3503 hi2c->pBuffPtr = pData;
3504 hi2c->XferCount = Size;
3505 hi2c->XferSize = hi2c->XferCount;
3506 hi2c->XferOptions = XferOptions;
3507 hi2c->Devaddress = DevAddress;
3508
3509 Prev_State = hi2c->PreviousState;
3510
3511 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3512 /* Mean Previous state is same as current state */
3513 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3514 {
3515 /* Generate Start */
3516 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3517 }
3518
3519 /* Process Unlocked */
3520 __HAL_UNLOCK(hi2c);
3521
3522 /* Note : The I2C interrupts must be enabled after unlocking current process
3523 to avoid the risk of I2C interrupt handle execution before current
3524 process unlock */
3525
3526 /* Enable EVT, BUF and ERR interrupt */
3527 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3528
3529 return HAL_OK;
3530 }
3531 else
3532 {
3533 return HAL_BUSY;
3534 }
3535 }
3536
3537 /**
3538 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3539 * @note This interface allow to manage repeated start condition when a direction change during transfer
3540 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3541 * the configuration information for the specified I2C.
3542 * @param DevAddress Target device address: The device 7 bits address value
3543 * in datasheet must be shifted to the left before calling the interface
3544 * @param pData Pointer to data buffer
3545 * @param Size Amount of data to be sent
3546 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3547 * @retval HAL status
3548 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3549 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3550 {
3551 __IO uint32_t Prev_State = 0x00U;
3552 __IO uint32_t count = 0x00U;
3553 HAL_StatusTypeDef dmaxferstatus;
3554
3555 /* Check the parameters */
3556 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3557
3558 if (hi2c->State == HAL_I2C_STATE_READY)
3559 {
3560 /* Check Busy Flag only if FIRST call of Master interface */
3561 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3562 {
3563 /* Wait until BUSY flag is reset */
3564 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3565 do
3566 {
3567 count--;
3568 if (count == 0U)
3569 {
3570 hi2c->PreviousState = I2C_STATE_NONE;
3571 hi2c->State = HAL_I2C_STATE_READY;
3572 hi2c->Mode = HAL_I2C_MODE_NONE;
3573 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3574
3575 /* Process Unlocked */
3576 __HAL_UNLOCK(hi2c);
3577
3578 return HAL_ERROR;
3579 }
3580 }
3581 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3582 }
3583
3584 /* Process Locked */
3585 __HAL_LOCK(hi2c);
3586
3587 /* Check if the I2C is already enabled */
3588 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3589 {
3590 /* Enable I2C peripheral */
3591 __HAL_I2C_ENABLE(hi2c);
3592 }
3593
3594 /* Disable Pos */
3595 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3596
3597 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3598 hi2c->Mode = HAL_I2C_MODE_MASTER;
3599 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3600
3601 /* Prepare transfer parameters */
3602 hi2c->pBuffPtr = pData;
3603 hi2c->XferCount = Size;
3604 hi2c->XferSize = hi2c->XferCount;
3605 hi2c->XferOptions = XferOptions;
3606 hi2c->Devaddress = DevAddress;
3607
3608 Prev_State = hi2c->PreviousState;
3609
3610 if (hi2c->XferSize > 0U)
3611 {
3612 /* Set the I2C DMA transfer complete callback */
3613 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3614
3615 /* Set the DMA error callback */
3616 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3617
3618 /* Set the unused DMA callbacks to NULL */
3619 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3620 hi2c->hdmatx->XferAbortCallback = NULL;
3621
3622 /* Enable the DMA stream */
3623 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3624
3625 if (dmaxferstatus == HAL_OK)
3626 {
3627 /* Enable Acknowledge */
3628 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3629
3630 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3631 /* Mean Previous state is same as current state */
3632 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3633 {
3634 /* Generate Start */
3635 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3636 }
3637
3638 /* Process Unlocked */
3639 __HAL_UNLOCK(hi2c);
3640
3641 /* Note : The I2C interrupts must be enabled after unlocking current process
3642 to avoid the risk of I2C interrupt handle execution before current
3643 process unlock */
3644
3645 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3646 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3647 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3648 {
3649 /* Enable DMA Request */
3650 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3651 }
3652
3653 /* Enable EVT and ERR interrupt */
3654 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3655 }
3656 else
3657 {
3658 /* Update I2C state */
3659 hi2c->State = HAL_I2C_STATE_READY;
3660 hi2c->Mode = HAL_I2C_MODE_NONE;
3661
3662 /* Update I2C error code */
3663 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3664
3665 /* Process Unlocked */
3666 __HAL_UNLOCK(hi2c);
3667
3668 return HAL_ERROR;
3669 }
3670 }
3671 else
3672 {
3673 /* Enable Acknowledge */
3674 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3675
3676 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3677 /* Mean Previous state is same as current state */
3678 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3679 {
3680 /* Generate Start */
3681 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3682 }
3683
3684 /* Process Unlocked */
3685 __HAL_UNLOCK(hi2c);
3686
3687 /* Note : The I2C interrupts must be enabled after unlocking current process
3688 to avoid the risk of I2C interrupt handle execution before current
3689 process unlock */
3690
3691 /* Enable EVT, BUF and ERR interrupt */
3692 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3693 }
3694
3695 return HAL_OK;
3696 }
3697 else
3698 {
3699 return HAL_BUSY;
3700 }
3701 }
3702
3703 /**
3704 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3705 * @note This interface allow to manage repeated start condition when a direction change during transfer
3706 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3707 * the configuration information for the specified I2C.
3708 * @param DevAddress Target device address: The device 7 bits address value
3709 * in datasheet must be shifted to the left before calling the interface
3710 * @param pData Pointer to data buffer
3711 * @param Size Amount of data to be sent
3712 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3713 * @retval HAL status
3714 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3715 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3716 {
3717 __IO uint32_t Prev_State = 0x00U;
3718 __IO uint32_t count = 0U;
3719 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3720
3721 /* Check the parameters */
3722 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3723
3724 if (hi2c->State == HAL_I2C_STATE_READY)
3725 {
3726 /* Check Busy Flag only if FIRST call of Master interface */
3727 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3728 {
3729 /* Wait until BUSY flag is reset */
3730 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3731 do
3732 {
3733 count--;
3734 if (count == 0U)
3735 {
3736 hi2c->PreviousState = I2C_STATE_NONE;
3737 hi2c->State = HAL_I2C_STATE_READY;
3738 hi2c->Mode = HAL_I2C_MODE_NONE;
3739 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3740
3741 /* Process Unlocked */
3742 __HAL_UNLOCK(hi2c);
3743
3744 return HAL_ERROR;
3745 }
3746 }
3747 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3748 }
3749
3750 /* Process Locked */
3751 __HAL_LOCK(hi2c);
3752
3753 /* Check if the I2C is already enabled */
3754 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3755 {
3756 /* Enable I2C peripheral */
3757 __HAL_I2C_ENABLE(hi2c);
3758 }
3759
3760 /* Disable Pos */
3761 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3762
3763 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3764 hi2c->Mode = HAL_I2C_MODE_MASTER;
3765 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3766
3767 /* Prepare transfer parameters */
3768 hi2c->pBuffPtr = pData;
3769 hi2c->XferCount = Size;
3770 hi2c->XferSize = hi2c->XferCount;
3771 hi2c->XferOptions = XferOptions;
3772 hi2c->Devaddress = DevAddress;
3773
3774 Prev_State = hi2c->PreviousState;
3775
3776 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3777 {
3778 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3779 {
3780 /* Disable Acknowledge */
3781 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3782
3783 /* Enable Pos */
3784 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3785
3786 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3787 enableIT &= ~I2C_IT_BUF;
3788 }
3789 else
3790 {
3791 /* Enable Acknowledge */
3792 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3793 }
3794 }
3795 else
3796 {
3797 /* Enable Acknowledge */
3798 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3799 }
3800
3801 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3802 /* Mean Previous state is same as current state */
3803 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3804 {
3805 /* Generate Start */
3806 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3807 }
3808
3809 /* Process Unlocked */
3810 __HAL_UNLOCK(hi2c);
3811
3812 /* Note : The I2C interrupts must be enabled after unlocking current process
3813 to avoid the risk of I2C interrupt handle execution before current
3814 process unlock */
3815
3816 /* Enable interrupts */
3817 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3818
3819 return HAL_OK;
3820 }
3821 else
3822 {
3823 return HAL_BUSY;
3824 }
3825 }
3826
3827 /**
3828 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
3829 * @note This interface allow to manage repeated start condition when a direction change during transfer
3830 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3831 * the configuration information for the specified I2C.
3832 * @param DevAddress Target device address: The device 7 bits address value
3833 * in datasheet must be shifted to the left before calling the interface
3834 * @param pData Pointer to data buffer
3835 * @param Size Amount of data to be sent
3836 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3837 * @retval HAL status
3838 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3839 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3840 {
3841 __IO uint32_t Prev_State = 0x00U;
3842 __IO uint32_t count = 0U;
3843 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3844 HAL_StatusTypeDef dmaxferstatus;
3845
3846 /* Check the parameters */
3847 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3848
3849 if (hi2c->State == HAL_I2C_STATE_READY)
3850 {
3851 /* Check Busy Flag only if FIRST call of Master interface */
3852 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3853 {
3854 /* Wait until BUSY flag is reset */
3855 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3856 do
3857 {
3858 count--;
3859 if (count == 0U)
3860 {
3861 hi2c->PreviousState = I2C_STATE_NONE;
3862 hi2c->State = HAL_I2C_STATE_READY;
3863 hi2c->Mode = HAL_I2C_MODE_NONE;
3864 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3865
3866 /* Process Unlocked */
3867 __HAL_UNLOCK(hi2c);
3868
3869 return HAL_ERROR;
3870 }
3871 }
3872 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3873 }
3874
3875 /* Process Locked */
3876 __HAL_LOCK(hi2c);
3877
3878 /* Check if the I2C is already enabled */
3879 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3880 {
3881 /* Enable I2C peripheral */
3882 __HAL_I2C_ENABLE(hi2c);
3883 }
3884
3885 /* Disable Pos */
3886 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3887
3888 /* Clear Last DMA bit */
3889 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3890
3891 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3892 hi2c->Mode = HAL_I2C_MODE_MASTER;
3893 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3894
3895 /* Prepare transfer parameters */
3896 hi2c->pBuffPtr = pData;
3897 hi2c->XferCount = Size;
3898 hi2c->XferSize = hi2c->XferCount;
3899 hi2c->XferOptions = XferOptions;
3900 hi2c->Devaddress = DevAddress;
3901
3902 Prev_State = hi2c->PreviousState;
3903
3904 if (hi2c->XferSize > 0U)
3905 {
3906 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3907 {
3908 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3909 {
3910 /* Disable Acknowledge */
3911 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3912
3913 /* Enable Pos */
3914 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3915
3916 /* Enable Last DMA bit */
3917 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3918 }
3919 else
3920 {
3921 /* Enable Acknowledge */
3922 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3923 }
3924 }
3925 else
3926 {
3927 /* Enable Acknowledge */
3928 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3929
3930 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3931 {
3932 /* Enable Last DMA bit */
3933 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3934 }
3935 }
3936
3937 /* Set the I2C DMA transfer complete callback */
3938 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3939
3940 /* Set the DMA error callback */
3941 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3942
3943 /* Set the unused DMA callbacks to NULL */
3944 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3945 hi2c->hdmarx->XferAbortCallback = NULL;
3946
3947 /* Enable the DMA stream */
3948 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3949
3950 if (dmaxferstatus == HAL_OK)
3951 {
3952 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3953 /* Mean Previous state is same as current state */
3954 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3955 {
3956 /* Generate Start */
3957 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3958
3959 /* Update interrupt for only EVT and ERR */
3960 enableIT = (I2C_IT_EVT | I2C_IT_ERR);
3961 }
3962 else
3963 {
3964 /* Update interrupt for only ERR */
3965 enableIT = I2C_IT_ERR;
3966 }
3967
3968 /* Process Unlocked */
3969 __HAL_UNLOCK(hi2c);
3970
3971 /* Note : The I2C interrupts must be enabled after unlocking current process
3972 to avoid the risk of I2C interrupt handle execution before current
3973 process unlock */
3974
3975 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3976 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3977 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3978 {
3979 /* Enable DMA Request */
3980 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3981 }
3982
3983 /* Enable EVT and ERR interrupt */
3984 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3985 }
3986 else
3987 {
3988 /* Update I2C state */
3989 hi2c->State = HAL_I2C_STATE_READY;
3990 hi2c->Mode = HAL_I2C_MODE_NONE;
3991
3992 /* Update I2C error code */
3993 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3994
3995 /* Process Unlocked */
3996 __HAL_UNLOCK(hi2c);
3997
3998 return HAL_ERROR;
3999 }
4000 }
4001 else
4002 {
4003 /* Enable Acknowledge */
4004 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4005
4006 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4007 /* Mean Previous state is same as current state */
4008 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4009 {
4010 /* Generate Start */
4011 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4012 }
4013
4014 /* Process Unlocked */
4015 __HAL_UNLOCK(hi2c);
4016
4017 /* Note : The I2C interrupts must be enabled after unlocking current process
4018 to avoid the risk of I2C interrupt handle execution before current
4019 process unlock */
4020
4021 /* Enable interrupts */
4022 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4023 }
4024 return HAL_OK;
4025 }
4026 else
4027 {
4028 return HAL_BUSY;
4029 }
4030 }
4031
4032 /**
4033 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
4034 * @note This interface allow to manage repeated start condition when a direction change during transfer
4035 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4036 * the configuration information for the specified I2C.
4037 * @param pData Pointer to data buffer
4038 * @param Size Amount of data to be sent
4039 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4040 * @retval HAL status
4041 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4042 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4043 {
4044 /* Check the parameters */
4045 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4046
4047 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4048 {
4049 if ((pData == NULL) || (Size == 0U))
4050 {
4051 return HAL_ERROR;
4052 }
4053
4054 /* Process Locked */
4055 __HAL_LOCK(hi2c);
4056
4057 /* Check if the I2C is already enabled */
4058 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4059 {
4060 /* Enable I2C peripheral */
4061 __HAL_I2C_ENABLE(hi2c);
4062 }
4063
4064 /* Disable Pos */
4065 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4066
4067 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4068 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4069 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4070
4071 /* Prepare transfer parameters */
4072 hi2c->pBuffPtr = pData;
4073 hi2c->XferCount = Size;
4074 hi2c->XferSize = hi2c->XferCount;
4075 hi2c->XferOptions = XferOptions;
4076
4077 /* Clear ADDR flag */
4078 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4079
4080 /* Process Unlocked */
4081 __HAL_UNLOCK(hi2c);
4082
4083 /* Note : The I2C interrupts must be enabled after unlocking current process
4084 to avoid the risk of I2C interrupt handle execution before current
4085 process unlock */
4086
4087 /* Enable EVT, BUF and ERR interrupt */
4088 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4089
4090 return HAL_OK;
4091 }
4092 else
4093 {
4094 return HAL_BUSY;
4095 }
4096 }
4097
4098 /**
4099 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4100 * @note This interface allow to manage repeated start condition when a direction change during transfer
4101 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4102 * the configuration information for the specified I2C.
4103 * @param pData Pointer to data buffer
4104 * @param Size Amount of data to be sent
4105 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4106 * @retval HAL status
4107 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4108 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4109 {
4110 HAL_StatusTypeDef dmaxferstatus;
4111
4112 /* Check the parameters */
4113 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4114
4115 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4116 {
4117 if ((pData == NULL) || (Size == 0U))
4118 {
4119 return HAL_ERROR;
4120 }
4121
4122 /* Process Locked */
4123 __HAL_LOCK(hi2c);
4124
4125 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4126 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4127
4128 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4129 /* and then toggle the HAL slave RX state to TX state */
4130 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4131 {
4132 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4133 {
4134 /* Abort DMA Xfer if any */
4135 if (hi2c->hdmarx != NULL)
4136 {
4137 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4138
4139 /* Set the I2C DMA Abort callback :
4140 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4141 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4142
4143 /* Abort DMA RX */
4144 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4145 {
4146 /* Call Directly XferAbortCallback function in case of error */
4147 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4148 }
4149 }
4150 }
4151 }
4152 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4153 {
4154 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4155 {
4156 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4157
4158 /* Abort DMA Xfer if any */
4159 if (hi2c->hdmatx != NULL)
4160 {
4161 /* Set the I2C DMA Abort callback :
4162 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4163 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4164
4165 /* Abort DMA TX */
4166 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4167 {
4168 /* Call Directly XferAbortCallback function in case of error */
4169 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4170 }
4171 }
4172 }
4173 }
4174 else
4175 {
4176 /* Nothing to do */
4177 }
4178
4179 /* Check if the I2C is already enabled */
4180 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4181 {
4182 /* Enable I2C peripheral */
4183 __HAL_I2C_ENABLE(hi2c);
4184 }
4185
4186 /* Disable Pos */
4187 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4188
4189 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4190 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4191 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4192
4193 /* Prepare transfer parameters */
4194 hi2c->pBuffPtr = pData;
4195 hi2c->XferCount = Size;
4196 hi2c->XferSize = hi2c->XferCount;
4197 hi2c->XferOptions = XferOptions;
4198
4199 /* Set the I2C DMA transfer complete callback */
4200 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4201
4202 /* Set the DMA error callback */
4203 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4204
4205 /* Set the unused DMA callbacks to NULL */
4206 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4207 hi2c->hdmatx->XferAbortCallback = NULL;
4208
4209 /* Enable the DMA stream */
4210 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4211
4212 if (dmaxferstatus == HAL_OK)
4213 {
4214 /* Enable Address Acknowledge */
4215 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4216
4217 /* Clear ADDR flag */
4218 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4219
4220 /* Process Unlocked */
4221 __HAL_UNLOCK(hi2c);
4222
4223 /* Note : The I2C interrupts must be enabled after unlocking current process
4224 to avoid the risk of I2C interrupt handle execution before current
4225 process unlock */
4226 /* Enable EVT and ERR interrupt */
4227 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4228
4229 /* Enable DMA Request */
4230 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4231
4232 return HAL_OK;
4233 }
4234 else
4235 {
4236 /* Update I2C state */
4237 hi2c->State = HAL_I2C_STATE_READY;
4238 hi2c->Mode = HAL_I2C_MODE_NONE;
4239
4240 /* Update I2C error code */
4241 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4242
4243 /* Process Unlocked */
4244 __HAL_UNLOCK(hi2c);
4245
4246 return HAL_ERROR;
4247 }
4248 }
4249 else
4250 {
4251 return HAL_BUSY;
4252 }
4253 }
4254
4255 /**
4256 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4257 * @note This interface allow to manage repeated start condition when a direction change during transfer
4258 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4259 * the configuration information for the specified I2C.
4260 * @param pData Pointer to data buffer
4261 * @param Size Amount of data to be sent
4262 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4263 * @retval HAL status
4264 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4265 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4266 {
4267 /* Check the parameters */
4268 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4269
4270 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4271 {
4272 if ((pData == NULL) || (Size == 0U))
4273 {
4274 return HAL_ERROR;
4275 }
4276
4277 /* Process Locked */
4278 __HAL_LOCK(hi2c);
4279
4280 /* Check if the I2C is already enabled */
4281 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4282 {
4283 /* Enable I2C peripheral */
4284 __HAL_I2C_ENABLE(hi2c);
4285 }
4286
4287 /* Disable Pos */
4288 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4289
4290 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4291 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4292 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4293
4294 /* Prepare transfer parameters */
4295 hi2c->pBuffPtr = pData;
4296 hi2c->XferCount = Size;
4297 hi2c->XferSize = hi2c->XferCount;
4298 hi2c->XferOptions = XferOptions;
4299
4300 /* Clear ADDR flag */
4301 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4302
4303 /* Process Unlocked */
4304 __HAL_UNLOCK(hi2c);
4305
4306 /* Note : The I2C interrupts must be enabled after unlocking current process
4307 to avoid the risk of I2C interrupt handle execution before current
4308 process unlock */
4309
4310 /* Enable EVT, BUF and ERR interrupt */
4311 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4312
4313 return HAL_OK;
4314 }
4315 else
4316 {
4317 return HAL_BUSY;
4318 }
4319 }
4320
4321 /**
4322 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4323 * @note This interface allow to manage repeated start condition when a direction change during transfer
4324 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4325 * the configuration information for the specified I2C.
4326 * @param pData Pointer to data buffer
4327 * @param Size Amount of data to be sent
4328 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4329 * @retval HAL status
4330 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4331 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4332 {
4333 HAL_StatusTypeDef dmaxferstatus;
4334
4335 /* Check the parameters */
4336 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4337
4338 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4339 {
4340 if ((pData == NULL) || (Size == 0U))
4341 {
4342 return HAL_ERROR;
4343 }
4344
4345 /* Process Locked */
4346 __HAL_LOCK(hi2c);
4347
4348 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4349 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4350
4351 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4352 /* and then toggle the HAL slave RX state to TX state */
4353 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4354 {
4355 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4356 {
4357 /* Abort DMA Xfer if any */
4358 if (hi2c->hdmarx != NULL)
4359 {
4360 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4361
4362 /* Set the I2C DMA Abort callback :
4363 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4364 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4365
4366 /* Abort DMA RX */
4367 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4368 {
4369 /* Call Directly XferAbortCallback function in case of error */
4370 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4371 }
4372 }
4373 }
4374 }
4375 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4376 {
4377 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4378 {
4379 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4380
4381 /* Abort DMA Xfer if any */
4382 if (hi2c->hdmatx != NULL)
4383 {
4384 /* Set the I2C DMA Abort callback :
4385 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4386 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4387
4388 /* Abort DMA TX */
4389 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4390 {
4391 /* Call Directly XferAbortCallback function in case of error */
4392 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4393 }
4394 }
4395 }
4396 }
4397 else
4398 {
4399 /* Nothing to do */
4400 }
4401
4402 /* Check if the I2C is already enabled */
4403 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4404 {
4405 /* Enable I2C peripheral */
4406 __HAL_I2C_ENABLE(hi2c);
4407 }
4408
4409 /* Disable Pos */
4410 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4411
4412 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4413 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4414 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4415
4416 /* Prepare transfer parameters */
4417 hi2c->pBuffPtr = pData;
4418 hi2c->XferCount = Size;
4419 hi2c->XferSize = hi2c->XferCount;
4420 hi2c->XferOptions = XferOptions;
4421
4422 /* Set the I2C DMA transfer complete callback */
4423 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4424
4425 /* Set the DMA error callback */
4426 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4427
4428 /* Set the unused DMA callbacks to NULL */
4429 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4430 hi2c->hdmarx->XferAbortCallback = NULL;
4431
4432 /* Enable the DMA stream */
4433 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4434
4435 if (dmaxferstatus == HAL_OK)
4436 {
4437 /* Enable Address Acknowledge */
4438 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4439
4440 /* Clear ADDR flag */
4441 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4442
4443 /* Process Unlocked */
4444 __HAL_UNLOCK(hi2c);
4445
4446 /* Enable DMA Request */
4447 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4448
4449 /* Note : The I2C interrupts must be enabled after unlocking current process
4450 to avoid the risk of I2C interrupt handle execution before current
4451 process unlock */
4452 /* Enable EVT and ERR interrupt */
4453 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4454
4455 return HAL_OK;
4456 }
4457 else
4458 {
4459 /* Update I2C state */
4460 hi2c->State = HAL_I2C_STATE_READY;
4461 hi2c->Mode = HAL_I2C_MODE_NONE;
4462
4463 /* Update I2C error code */
4464 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4465
4466 /* Process Unlocked */
4467 __HAL_UNLOCK(hi2c);
4468
4469 return HAL_ERROR;
4470 }
4471 }
4472 else
4473 {
4474 return HAL_BUSY;
4475 }
4476 }
4477
4478 /**
4479 * @brief Enable the Address listen mode with Interrupt.
4480 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4481 * the configuration information for the specified I2C.
4482 * @retval HAL status
4483 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4484 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4485 {
4486 if (hi2c->State == HAL_I2C_STATE_READY)
4487 {
4488 hi2c->State = HAL_I2C_STATE_LISTEN;
4489
4490 /* Check if the I2C is already enabled */
4491 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4492 {
4493 /* Enable I2C peripheral */
4494 __HAL_I2C_ENABLE(hi2c);
4495 }
4496
4497 /* Enable Address Acknowledge */
4498 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4499
4500 /* Enable EVT and ERR interrupt */
4501 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4502
4503 return HAL_OK;
4504 }
4505 else
4506 {
4507 return HAL_BUSY;
4508 }
4509 }
4510
4511 /**
4512 * @brief Disable the Address listen mode with Interrupt.
4513 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4514 * the configuration information for the specified I2C.
4515 * @retval HAL status
4516 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4517 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4518 {
4519 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4520 uint32_t tmp;
4521
4522 /* Disable Address listen mode only if a transfer is not ongoing */
4523 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4524 {
4525 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4526 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4527 hi2c->State = HAL_I2C_STATE_READY;
4528 hi2c->Mode = HAL_I2C_MODE_NONE;
4529
4530 /* Disable Address Acknowledge */
4531 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4532
4533 /* Disable EVT and ERR interrupt */
4534 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4535
4536 return HAL_OK;
4537 }
4538 else
4539 {
4540 return HAL_BUSY;
4541 }
4542 }
4543
4544 /**
4545 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4547 * the configuration information for the specified I2C.
4548 * @param DevAddress Target device address: The device 7 bits address value
4549 * in datasheet must be shifted to the left before calling the interface
4550 * @retval HAL status
4551 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4552 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4553 {
4554 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4555 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4556
4557 /* Prevent unused argument(s) compilation warning */
4558 UNUSED(DevAddress);
4559
4560 /* Abort Master transfer during Receive or Transmit process */
4561 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
4562 {
4563 /* Process Locked */
4564 __HAL_LOCK(hi2c);
4565
4566 hi2c->PreviousState = I2C_STATE_NONE;
4567 hi2c->State = HAL_I2C_STATE_ABORT;
4568
4569 /* Disable Acknowledge */
4570 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4571
4572 /* Generate Stop */
4573 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4574
4575 hi2c->XferCount = 0U;
4576
4577 /* Disable EVT, BUF and ERR interrupt */
4578 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4579
4580 /* Process Unlocked */
4581 __HAL_UNLOCK(hi2c);
4582
4583 /* Call the corresponding callback to inform upper layer of End of Transfer */
4584 I2C_ITError(hi2c);
4585
4586 return HAL_OK;
4587 }
4588 else
4589 {
4590 /* Wrong usage of abort function */
4591 /* This function should be used only in case of abort monitored by master device */
4592 /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4593 return HAL_ERROR;
4594 }
4595 }
4596
4597 /**
4598 * @}
4599 */
4600
4601 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4602 * @{
4603 */
4604
4605 /**
4606 * @brief This function handles I2C event interrupt request.
4607 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4608 * the configuration information for the specified I2C.
4609 * @retval None
4610 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4611 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4612 {
4613 uint32_t sr1itflags;
4614 uint32_t sr2itflags = 0U;
4615 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4616 uint32_t CurrentXferOptions = hi2c->XferOptions;
4617 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4618 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4619
4620 /* Master or Memory mode selected */
4621 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4622 {
4623 sr2itflags = READ_REG(hi2c->Instance->SR2);
4624 sr1itflags = READ_REG(hi2c->Instance->SR1);
4625
4626 /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4627 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4628 {
4629 return;
4630 }
4631
4632 /* SB Set ----------------------------------------------------------------*/
4633 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4634 {
4635 /* Convert OTHER_xxx XferOptions if any */
4636 I2C_ConvertOtherXferOptions(hi2c);
4637
4638 I2C_Master_SB(hi2c);
4639 }
4640 /* ADD10 Set -------------------------------------------------------------*/
4641 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4642 {
4643 I2C_Master_ADD10(hi2c);
4644 }
4645 /* ADDR Set --------------------------------------------------------------*/
4646 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4647 {
4648 I2C_Master_ADDR(hi2c);
4649 }
4650 /* I2C in mode Transmitter -----------------------------------------------*/
4651 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4652 {
4653 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4654 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4655 {
4656 /* TXE set and BTF reset -----------------------------------------------*/
4657 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4658 {
4659 I2C_MasterTransmit_TXE(hi2c);
4660 }
4661 /* BTF set -------------------------------------------------------------*/
4662 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4663 {
4664 if (CurrentMode == HAL_I2C_MODE_MASTER)
4665 {
4666 I2C_MasterTransmit_BTF(hi2c);
4667 }
4668 else /* HAL_I2C_MODE_MEM */
4669 {
4670 I2C_MemoryTransmit_TXE_BTF(hi2c);
4671 }
4672 }
4673 else
4674 {
4675 /* Do nothing */
4676 }
4677 }
4678 }
4679 /* I2C in mode Receiver --------------------------------------------------*/
4680 else
4681 {
4682 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4683 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4684 {
4685 /* RXNE set and BTF reset -----------------------------------------------*/
4686 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4687 {
4688 I2C_MasterReceive_RXNE(hi2c);
4689 }
4690 /* BTF set -------------------------------------------------------------*/
4691 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4692 {
4693 I2C_MasterReceive_BTF(hi2c);
4694 }
4695 else
4696 {
4697 /* Do nothing */
4698 }
4699 }
4700 }
4701 }
4702 /* Slave mode selected */
4703 else
4704 {
4705 /* If an error is detected, read only SR1 register to prevent */
4706 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4707 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4708 {
4709 sr1itflags = READ_REG(hi2c->Instance->SR1);
4710 }
4711 else
4712 {
4713 sr2itflags = READ_REG(hi2c->Instance->SR2);
4714 sr1itflags = READ_REG(hi2c->Instance->SR1);
4715 }
4716
4717 /* ADDR set --------------------------------------------------------------*/
4718 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4719 {
4720 /* Now time to read SR2, this will clear ADDR flag automatically */
4721 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4722 {
4723 sr2itflags = READ_REG(hi2c->Instance->SR2);
4724 }
4725 I2C_Slave_ADDR(hi2c, sr2itflags);
4726 }
4727 /* STOPF set --------------------------------------------------------------*/
4728 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4729 {
4730 I2C_Slave_STOPF(hi2c);
4731 }
4732 /* I2C in mode Transmitter -----------------------------------------------*/
4733 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4734 {
4735 /* TXE set and BTF reset -----------------------------------------------*/
4736 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4737 {
4738 I2C_SlaveTransmit_TXE(hi2c);
4739 }
4740 /* BTF set -------------------------------------------------------------*/
4741 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4742 {
4743 I2C_SlaveTransmit_BTF(hi2c);
4744 }
4745 else
4746 {
4747 /* Do nothing */
4748 }
4749 }
4750 /* I2C in mode Receiver --------------------------------------------------*/
4751 else
4752 {
4753 /* RXNE set and BTF reset ----------------------------------------------*/
4754 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4755 {
4756 I2C_SlaveReceive_RXNE(hi2c);
4757 }
4758 /* BTF set -------------------------------------------------------------*/
4759 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4760 {
4761 I2C_SlaveReceive_BTF(hi2c);
4762 }
4763 else
4764 {
4765 /* Do nothing */
4766 }
4767 }
4768 }
4769 }
4770
4771 /**
4772 * @brief This function handles I2C error interrupt request.
4773 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4774 * the configuration information for the specified I2C.
4775 * @retval None
4776 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4777 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4778 {
4779 HAL_I2C_ModeTypeDef tmp1;
4780 uint32_t tmp2;
4781 HAL_I2C_StateTypeDef tmp3;
4782 uint32_t tmp4;
4783 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4784 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4785 uint32_t error = HAL_I2C_ERROR_NONE;
4786 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4787
4788 /* I2C Bus error interrupt occurred ----------------------------------------*/
4789 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4790 {
4791 error |= HAL_I2C_ERROR_BERR;
4792
4793 /* Clear BERR flag */
4794 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4795 }
4796
4797 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4798 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4799 {
4800 error |= HAL_I2C_ERROR_ARLO;
4801
4802 /* Clear ARLO flag */
4803 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4804 }
4805
4806 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4807 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4808 {
4809 tmp1 = CurrentMode;
4810 tmp2 = hi2c->XferCount;
4811 tmp3 = hi2c->State;
4812 tmp4 = hi2c->PreviousState;
4813 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4814 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4815 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4816 {
4817 I2C_Slave_AF(hi2c);
4818 }
4819 else
4820 {
4821 /* Clear AF flag */
4822 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4823
4824 error |= HAL_I2C_ERROR_AF;
4825
4826 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
4827 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4828 {
4829 /* Generate Stop */
4830 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4831 }
4832 }
4833 }
4834
4835 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
4836 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4837 {
4838 error |= HAL_I2C_ERROR_OVR;
4839 /* Clear OVR flag */
4840 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4841 }
4842
4843 /* Call the Error Callback in case of Error detected -----------------------*/
4844 if (error != HAL_I2C_ERROR_NONE)
4845 {
4846 hi2c->ErrorCode |= error;
4847 I2C_ITError(hi2c);
4848 }
4849 }
4850
4851 /**
4852 * @brief Master Tx Transfer completed callback.
4853 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4854 * the configuration information for the specified I2C.
4855 * @retval None
4856 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4857 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4858 {
4859 /* Prevent unused argument(s) compilation warning */
4860 UNUSED(hi2c);
4861
4862 /* NOTE : This function should not be modified, when the callback is needed,
4863 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4864 */
4865 }
4866
4867 /**
4868 * @brief Master Rx Transfer completed callback.
4869 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4870 * the configuration information for the specified I2C.
4871 * @retval None
4872 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4873 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4874 {
4875 /* Prevent unused argument(s) compilation warning */
4876 UNUSED(hi2c);
4877
4878 /* NOTE : This function should not be modified, when the callback is needed,
4879 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4880 */
4881 }
4882
4883 /** @brief Slave Tx Transfer completed callback.
4884 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4885 * the configuration information for the specified I2C.
4886 * @retval None
4887 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4888 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4889 {
4890 /* Prevent unused argument(s) compilation warning */
4891 UNUSED(hi2c);
4892
4893 /* NOTE : This function should not be modified, when the callback is needed,
4894 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4895 */
4896 }
4897
4898 /**
4899 * @brief Slave Rx Transfer completed callback.
4900 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4901 * the configuration information for the specified I2C.
4902 * @retval None
4903 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4904 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4905 {
4906 /* Prevent unused argument(s) compilation warning */
4907 UNUSED(hi2c);
4908
4909 /* NOTE : This function should not be modified, when the callback is needed,
4910 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4911 */
4912 }
4913
4914 /**
4915 * @brief Slave Address Match callback.
4916 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4917 * the configuration information for the specified I2C.
4918 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
4919 * @param AddrMatchCode Address Match Code
4920 * @retval None
4921 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4922 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4923 {
4924 /* Prevent unused argument(s) compilation warning */
4925 UNUSED(hi2c);
4926 UNUSED(TransferDirection);
4927 UNUSED(AddrMatchCode);
4928
4929 /* NOTE : This function should not be modified, when the callback is needed,
4930 the HAL_I2C_AddrCallback() could be implemented in the user file
4931 */
4932 }
4933
4934 /**
4935 * @brief Listen Complete callback.
4936 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4937 * the configuration information for the specified I2C.
4938 * @retval None
4939 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4940 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4941 {
4942 /* Prevent unused argument(s) compilation warning */
4943 UNUSED(hi2c);
4944
4945 /* NOTE : This function should not be modified, when the callback is needed,
4946 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4947 */
4948 }
4949
4950 /**
4951 * @brief Memory Tx Transfer completed callback.
4952 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4953 * the configuration information for the specified I2C.
4954 * @retval None
4955 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4956 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4957 {
4958 /* Prevent unused argument(s) compilation warning */
4959 UNUSED(hi2c);
4960
4961 /* NOTE : This function should not be modified, when the callback is needed,
4962 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4963 */
4964 }
4965
4966 /**
4967 * @brief Memory Rx Transfer completed callback.
4968 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4969 * the configuration information for the specified I2C.
4970 * @retval None
4971 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4972 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4973 {
4974 /* Prevent unused argument(s) compilation warning */
4975 UNUSED(hi2c);
4976
4977 /* NOTE : This function should not be modified, when the callback is needed,
4978 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4979 */
4980 }
4981
4982 /**
4983 * @brief I2C error callback.
4984 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4985 * the configuration information for the specified I2C.
4986 * @retval None
4987 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4988 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4989 {
4990 /* Prevent unused argument(s) compilation warning */
4991 UNUSED(hi2c);
4992
4993 /* NOTE : This function should not be modified, when the callback is needed,
4994 the HAL_I2C_ErrorCallback could be implemented in the user file
4995 */
4996 }
4997
4998 /**
4999 * @brief I2C abort callback.
5000 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5001 * the configuration information for the specified I2C.
5002 * @retval None
5003 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5004 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5005 {
5006 /* Prevent unused argument(s) compilation warning */
5007 UNUSED(hi2c);
5008
5009 /* NOTE : This function should not be modified, when the callback is needed,
5010 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5011 */
5012 }
5013
5014 /**
5015 * @}
5016 */
5017
5018 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5019 * @brief Peripheral State, Mode and Error functions
5020 *
5021 @verbatim
5022 ===============================================================================
5023 ##### Peripheral State, Mode and Error functions #####
5024 ===============================================================================
5025 [..]
5026 This subsection permit to get in run-time the status of the peripheral
5027 and the data flow.
5028
5029 @endverbatim
5030 * @{
5031 */
5032
5033 /**
5034 * @brief Return the I2C handle state.
5035 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5036 * the configuration information for the specified I2C.
5037 * @retval HAL state
5038 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5039 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5040 {
5041 /* Return I2C handle state */
5042 return hi2c->State;
5043 }
5044
5045 /**
5046 * @brief Returns the I2C Master, Slave, Memory or no mode.
5047 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5048 * the configuration information for I2C module
5049 * @retval HAL mode
5050 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5051 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5052 {
5053 return hi2c->Mode;
5054 }
5055
5056 /**
5057 * @brief Return the I2C error code.
5058 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5059 * the configuration information for the specified I2C.
5060 * @retval I2C Error Code
5061 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5062 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5063 {
5064 return hi2c->ErrorCode;
5065 }
5066
5067 /**
5068 * @}
5069 */
5070
5071 /**
5072 * @}
5073 */
5074
5075 /** @addtogroup I2C_Private_Functions
5076 * @{
5077 */
5078
5079 /**
5080 * @brief Handle TXE flag for Master
5081 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5082 * the configuration information for I2C module
5083 * @retval None
5084 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)5085 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5086 {
5087 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5088 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5089 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5090 uint32_t CurrentXferOptions = hi2c->XferOptions;
5091
5092 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5093 {
5094 /* Call TxCpltCallback() directly if no stop mode is set */
5095 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5096 {
5097 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5098
5099 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5100 hi2c->Mode = HAL_I2C_MODE_NONE;
5101 hi2c->State = HAL_I2C_STATE_READY;
5102
5103 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5104 hi2c->MasterTxCpltCallback(hi2c);
5105 #else
5106 HAL_I2C_MasterTxCpltCallback(hi2c);
5107 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5108 }
5109 else /* Generate Stop condition then Call TxCpltCallback() */
5110 {
5111 /* Disable EVT, BUF and ERR interrupt */
5112 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5113
5114 /* Generate Stop */
5115 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5116
5117 hi2c->PreviousState = I2C_STATE_NONE;
5118 hi2c->State = HAL_I2C_STATE_READY;
5119
5120 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5121 {
5122 hi2c->Mode = HAL_I2C_MODE_NONE;
5123 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5124 hi2c->MemTxCpltCallback(hi2c);
5125 #else
5126 HAL_I2C_MemTxCpltCallback(hi2c);
5127 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5128 }
5129 else
5130 {
5131 hi2c->Mode = HAL_I2C_MODE_NONE;
5132 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5133 hi2c->MasterTxCpltCallback(hi2c);
5134 #else
5135 HAL_I2C_MasterTxCpltCallback(hi2c);
5136 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5137 }
5138 }
5139 }
5140 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5141 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5142 {
5143 if (hi2c->XferCount == 0U)
5144 {
5145 /* Disable BUF interrupt */
5146 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5147 }
5148 else
5149 {
5150 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5151 {
5152 I2C_MemoryTransmit_TXE_BTF(hi2c);
5153 }
5154 else
5155 {
5156 /* Write data to DR */
5157 hi2c->Instance->DR = *hi2c->pBuffPtr;
5158
5159 /* Increment Buffer pointer */
5160 hi2c->pBuffPtr++;
5161
5162 /* Update counter */
5163 hi2c->XferCount--;
5164 }
5165 }
5166 }
5167 else
5168 {
5169 /* Do nothing */
5170 }
5171 }
5172
5173 /**
5174 * @brief Handle BTF flag for Master transmitter
5175 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5176 * the configuration information for I2C module
5177 * @retval None
5178 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)5179 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5180 {
5181 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5182 uint32_t CurrentXferOptions = hi2c->XferOptions;
5183
5184 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5185 {
5186 if (hi2c->XferCount != 0U)
5187 {
5188 /* Write data to DR */
5189 hi2c->Instance->DR = *hi2c->pBuffPtr;
5190
5191 /* Increment Buffer pointer */
5192 hi2c->pBuffPtr++;
5193
5194 /* Update counter */
5195 hi2c->XferCount--;
5196 }
5197 else
5198 {
5199 /* Call TxCpltCallback() directly if no stop mode is set */
5200 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5201 {
5202 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5203
5204 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5205 hi2c->Mode = HAL_I2C_MODE_NONE;
5206 hi2c->State = HAL_I2C_STATE_READY;
5207
5208 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5209 hi2c->MasterTxCpltCallback(hi2c);
5210 #else
5211 HAL_I2C_MasterTxCpltCallback(hi2c);
5212 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5213 }
5214 else /* Generate Stop condition then Call TxCpltCallback() */
5215 {
5216 /* Disable EVT, BUF and ERR interrupt */
5217 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5218
5219 /* Generate Stop */
5220 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5221
5222 hi2c->PreviousState = I2C_STATE_NONE;
5223 hi2c->State = HAL_I2C_STATE_READY;
5224 hi2c->Mode = HAL_I2C_MODE_NONE;
5225
5226 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5227 hi2c->MasterTxCpltCallback(hi2c);
5228 #else
5229 HAL_I2C_MasterTxCpltCallback(hi2c);
5230 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5231 }
5232 }
5233 }
5234 else
5235 {
5236 /* Do nothing */
5237 }
5238 }
5239
5240 /**
5241 * @brief Handle TXE and BTF flag for Memory transmitter
5242 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5243 * the configuration information for I2C module
5244 * @retval None
5245 */
I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef * hi2c)5246 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5247 {
5248 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5249 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5250
5251 if (hi2c->EventCount == 0U)
5252 {
5253 /* If Memory address size is 8Bit */
5254 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5255 {
5256 /* Send Memory Address */
5257 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5258
5259 hi2c->EventCount += 2U;
5260 }
5261 /* If Memory address size is 16Bit */
5262 else
5263 {
5264 /* Send MSB of Memory Address */
5265 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5266
5267 hi2c->EventCount++;
5268 }
5269 }
5270 else if (hi2c->EventCount == 1U)
5271 {
5272 /* Send LSB of Memory Address */
5273 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5274
5275 hi2c->EventCount++;
5276 }
5277 else if (hi2c->EventCount == 2U)
5278 {
5279 if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5280 {
5281 /* Generate Restart */
5282 hi2c->Instance->CR1 |= I2C_CR1_START;
5283 }
5284 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5285 {
5286 /* Write data to DR */
5287 hi2c->Instance->DR = *hi2c->pBuffPtr;
5288
5289 /* Increment Buffer pointer */
5290 hi2c->pBuffPtr++;
5291
5292 /* Update counter */
5293 hi2c->XferCount--;
5294 }
5295 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5296 {
5297 /* Generate Stop condition then Call TxCpltCallback() */
5298 /* Disable EVT, BUF and ERR interrupt */
5299 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5300
5301 /* Generate Stop */
5302 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5303
5304 hi2c->PreviousState = I2C_STATE_NONE;
5305 hi2c->State = HAL_I2C_STATE_READY;
5306 hi2c->Mode = HAL_I2C_MODE_NONE;
5307 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5308 hi2c->MemTxCpltCallback(hi2c);
5309 #else
5310 HAL_I2C_MemTxCpltCallback(hi2c);
5311 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5312 }
5313 else
5314 {
5315 /* Do nothing */
5316 }
5317 }
5318 else
5319 {
5320 /* Do nothing */
5321 }
5322 }
5323
5324 /**
5325 * @brief Handle RXNE flag for Master
5326 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5327 * the configuration information for I2C module
5328 * @retval None
5329 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)5330 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5331 {
5332 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5333 {
5334 uint32_t tmp;
5335
5336 tmp = hi2c->XferCount;
5337 if (tmp > 3U)
5338 {
5339 /* Read data from DR */
5340 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5341
5342 /* Increment Buffer pointer */
5343 hi2c->pBuffPtr++;
5344
5345 /* Update counter */
5346 hi2c->XferCount--;
5347
5348 if (hi2c->XferCount == (uint16_t)3)
5349 {
5350 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5351 on BTF subroutine */
5352 /* Disable BUF interrupt */
5353 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5354 }
5355 }
5356 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5357 {
5358 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5359 {
5360 /* Disable Acknowledge */
5361 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5362
5363 /* Disable EVT, BUF and ERR interrupt */
5364 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5365
5366 /* Read data from DR */
5367 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5368
5369 /* Increment Buffer pointer */
5370 hi2c->pBuffPtr++;
5371
5372 /* Update counter */
5373 hi2c->XferCount--;
5374
5375 hi2c->State = HAL_I2C_STATE_READY;
5376
5377 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5378 {
5379 hi2c->Mode = HAL_I2C_MODE_NONE;
5380 hi2c->PreviousState = I2C_STATE_NONE;
5381
5382 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5383 hi2c->MemRxCpltCallback(hi2c);
5384 #else
5385 HAL_I2C_MemRxCpltCallback(hi2c);
5386 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5387 }
5388 else
5389 {
5390 hi2c->Mode = HAL_I2C_MODE_NONE;
5391 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5392
5393 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5394 hi2c->MasterRxCpltCallback(hi2c);
5395 #else
5396 HAL_I2C_MasterRxCpltCallback(hi2c);
5397 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5398 }
5399 }
5400 else
5401 {
5402 /* Disable EVT, BUF and ERR interrupt */
5403 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5404
5405 /* Read data from DR */
5406 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5407
5408 /* Increment Buffer pointer */
5409 hi2c->pBuffPtr++;
5410
5411 /* Update counter */
5412 hi2c->XferCount--;
5413
5414 hi2c->State = HAL_I2C_STATE_READY;
5415 hi2c->Mode = HAL_I2C_MODE_NONE;
5416
5417 /* Call user error callback */
5418 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5419 hi2c->ErrorCallback(hi2c);
5420 #else
5421 HAL_I2C_ErrorCallback(hi2c);
5422 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5423 }
5424 }
5425 else
5426 {
5427 /* Do nothing */
5428 }
5429 }
5430 }
5431
5432 /**
5433 * @brief Handle BTF flag for Master receiver
5434 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5435 * the configuration information for I2C module
5436 * @retval None
5437 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)5438 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5439 {
5440 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5441 uint32_t CurrentXferOptions = hi2c->XferOptions;
5442
5443 if (hi2c->XferCount == 4U)
5444 {
5445 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5446 on BTF subroutine if there is a reception delay between N-1 and N byte */
5447 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5448
5449 /* Read data from DR */
5450 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5451
5452 /* Increment Buffer pointer */
5453 hi2c->pBuffPtr++;
5454
5455 /* Update counter */
5456 hi2c->XferCount--;
5457 }
5458 else if (hi2c->XferCount == 3U)
5459 {
5460 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5461 on BTF subroutine if there is a reception delay between N-1 and N byte */
5462 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5463
5464 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5465 {
5466 /* Disable Acknowledge */
5467 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5468 }
5469
5470 /* Read data from DR */
5471 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5472
5473 /* Increment Buffer pointer */
5474 hi2c->pBuffPtr++;
5475
5476 /* Update counter */
5477 hi2c->XferCount--;
5478 }
5479 else if (hi2c->XferCount == 2U)
5480 {
5481 /* Prepare next transfer or stop current transfer */
5482 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5483 {
5484 /* Disable Acknowledge */
5485 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5486 }
5487 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5488 {
5489 /* Enable Acknowledge */
5490 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5491 }
5492 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5493 {
5494 /* Generate Stop */
5495 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5496 }
5497 else
5498 {
5499 /* Do nothing */
5500 }
5501
5502 /* Read data from DR */
5503 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5504
5505 /* Increment Buffer pointer */
5506 hi2c->pBuffPtr++;
5507
5508 /* Update counter */
5509 hi2c->XferCount--;
5510
5511 /* Read data from DR */
5512 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5513
5514 /* Increment Buffer pointer */
5515 hi2c->pBuffPtr++;
5516
5517 /* Update counter */
5518 hi2c->XferCount--;
5519
5520 /* Disable EVT and ERR interrupt */
5521 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5522
5523 hi2c->State = HAL_I2C_STATE_READY;
5524 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5525 {
5526 hi2c->Mode = HAL_I2C_MODE_NONE;
5527 hi2c->PreviousState = I2C_STATE_NONE;
5528 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5529 hi2c->MemRxCpltCallback(hi2c);
5530 #else
5531 HAL_I2C_MemRxCpltCallback(hi2c);
5532 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5533 }
5534 else
5535 {
5536 hi2c->Mode = HAL_I2C_MODE_NONE;
5537 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5538 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5539 hi2c->MasterRxCpltCallback(hi2c);
5540 #else
5541 HAL_I2C_MasterRxCpltCallback(hi2c);
5542 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5543 }
5544 }
5545 else
5546 {
5547 /* Read data from DR */
5548 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5549
5550 /* Increment Buffer pointer */
5551 hi2c->pBuffPtr++;
5552
5553 /* Update counter */
5554 hi2c->XferCount--;
5555 }
5556 }
5557
5558 /**
5559 * @brief Handle SB flag for Master
5560 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5561 * the configuration information for I2C module
5562 * @retval None
5563 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)5564 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5565 {
5566 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5567 {
5568 if (hi2c->EventCount == 0U)
5569 {
5570 /* Send slave address */
5571 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5572 }
5573 else
5574 {
5575 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5576 }
5577 }
5578 else
5579 {
5580 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5581 {
5582 /* Send slave 7 Bits address */
5583 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5584 {
5585 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5586 }
5587 else
5588 {
5589 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5590 }
5591
5592 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5593 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5594 {
5595 /* Enable DMA Request */
5596 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5597 }
5598 }
5599 else
5600 {
5601 if (hi2c->EventCount == 0U)
5602 {
5603 /* Send header of slave address */
5604 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5605 }
5606 else if (hi2c->EventCount == 1U)
5607 {
5608 /* Send header of slave address */
5609 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5610 }
5611 else
5612 {
5613 /* Do nothing */
5614 }
5615 }
5616 }
5617 }
5618
5619 /**
5620 * @brief Handle ADD10 flag for Master
5621 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5622 * the configuration information for I2C module
5623 * @retval None
5624 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)5625 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5626 {
5627 /* Send slave address */
5628 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5629
5630 if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
5631 {
5632 if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
5633 {
5634 /* Enable DMA Request */
5635 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5636 }
5637 }
5638 }
5639
5640 /**
5641 * @brief Handle ADDR flag for Master
5642 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5643 * the configuration information for I2C module
5644 * @retval None
5645 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)5646 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5647 {
5648 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5649 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5650 uint32_t CurrentXferOptions = hi2c->XferOptions;
5651 uint32_t Prev_State = hi2c->PreviousState;
5652
5653 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5654 {
5655 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5656 {
5657 /* Clear ADDR flag */
5658 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5659 }
5660 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5661 {
5662 /* Clear ADDR flag */
5663 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5664
5665 /* Generate Restart */
5666 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5667
5668 hi2c->EventCount++;
5669 }
5670 else
5671 {
5672 if (hi2c->XferCount == 0U)
5673 {
5674 /* Clear ADDR flag */
5675 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5676
5677 /* Generate Stop */
5678 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5679 }
5680 else if (hi2c->XferCount == 1U)
5681 {
5682 if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5683 {
5684 /* Disable Acknowledge */
5685 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5686
5687 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5688 {
5689 /* Disable Acknowledge */
5690 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5691
5692 /* Clear ADDR flag */
5693 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5694 }
5695 else
5696 {
5697 /* Clear ADDR flag */
5698 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5699
5700 /* Generate Stop */
5701 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5702 }
5703 }
5704 /* Prepare next transfer or stop current transfer */
5705 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5706 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5707 {
5708 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5709 {
5710 /* Disable Acknowledge */
5711 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5712 }
5713 else
5714 {
5715 /* Enable Acknowledge */
5716 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5717 }
5718
5719 /* Clear ADDR flag */
5720 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5721 }
5722 else
5723 {
5724 /* Disable Acknowledge */
5725 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5726
5727 /* Clear ADDR flag */
5728 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5729
5730 /* Generate Stop */
5731 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5732 }
5733 }
5734 else if (hi2c->XferCount == 2U)
5735 {
5736 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5737 {
5738 /* Disable Acknowledge */
5739 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5740
5741 /* Enable Pos */
5742 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5743 }
5744 else
5745 {
5746 /* Enable Acknowledge */
5747 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5748 }
5749
5750 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5751 {
5752 /* Enable Last DMA bit */
5753 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5754 }
5755
5756 /* Clear ADDR flag */
5757 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5758 }
5759 else
5760 {
5761 /* Enable Acknowledge */
5762 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5763
5764 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5765 {
5766 /* Enable Last DMA bit */
5767 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5768 }
5769
5770 /* Clear ADDR flag */
5771 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5772 }
5773
5774 /* Reset Event counter */
5775 hi2c->EventCount = 0U;
5776 }
5777 }
5778 else
5779 {
5780 /* Clear ADDR flag */
5781 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5782 }
5783 }
5784
5785 /**
5786 * @brief Handle TXE flag for Slave
5787 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5788 * the configuration information for I2C module
5789 * @retval None
5790 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)5791 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5792 {
5793 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5794 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5795
5796 if (hi2c->XferCount != 0U)
5797 {
5798 /* Write data to DR */
5799 hi2c->Instance->DR = *hi2c->pBuffPtr;
5800
5801 /* Increment Buffer pointer */
5802 hi2c->pBuffPtr++;
5803
5804 /* Update counter */
5805 hi2c->XferCount--;
5806
5807 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5808 {
5809 /* Last Byte is received, disable Interrupt */
5810 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5811
5812 /* Set state at HAL_I2C_STATE_LISTEN */
5813 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5814 hi2c->State = HAL_I2C_STATE_LISTEN;
5815
5816 /* Call the corresponding callback to inform upper layer of End of Transfer */
5817 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5818 hi2c->SlaveTxCpltCallback(hi2c);
5819 #else
5820 HAL_I2C_SlaveTxCpltCallback(hi2c);
5821 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5822 }
5823 }
5824 }
5825
5826 /**
5827 * @brief Handle BTF flag for Slave transmitter
5828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5829 * the configuration information for I2C module
5830 * @retval None
5831 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)5832 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
5833 {
5834 if (hi2c->XferCount != 0U)
5835 {
5836 /* Write data to DR */
5837 hi2c->Instance->DR = *hi2c->pBuffPtr;
5838
5839 /* Increment Buffer pointer */
5840 hi2c->pBuffPtr++;
5841
5842 /* Update counter */
5843 hi2c->XferCount--;
5844 }
5845 }
5846
5847 /**
5848 * @brief Handle RXNE flag for Slave
5849 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5850 * the configuration information for I2C module
5851 * @retval None
5852 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)5853 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
5854 {
5855 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5856 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5857
5858 if (hi2c->XferCount != 0U)
5859 {
5860 /* Read data from DR */
5861 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5862
5863 /* Increment Buffer pointer */
5864 hi2c->pBuffPtr++;
5865
5866 /* Update counter */
5867 hi2c->XferCount--;
5868
5869 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
5870 {
5871 /* Last Byte is received, disable Interrupt */
5872 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5873
5874 /* Set state at HAL_I2C_STATE_LISTEN */
5875 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5876 hi2c->State = HAL_I2C_STATE_LISTEN;
5877
5878 /* Call the corresponding callback to inform upper layer of End of Transfer */
5879 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5880 hi2c->SlaveRxCpltCallback(hi2c);
5881 #else
5882 HAL_I2C_SlaveRxCpltCallback(hi2c);
5883 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5884 }
5885 }
5886 }
5887
5888 /**
5889 * @brief Handle BTF flag for Slave receiver
5890 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5891 * the configuration information for I2C module
5892 * @retval None
5893 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)5894 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
5895 {
5896 if (hi2c->XferCount != 0U)
5897 {
5898 /* Read data from DR */
5899 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5900
5901 /* Increment Buffer pointer */
5902 hi2c->pBuffPtr++;
5903
5904 /* Update counter */
5905 hi2c->XferCount--;
5906 }
5907 }
5908
5909 /**
5910 * @brief Handle ADD flag for Slave
5911 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5912 * the configuration information for I2C module
5913 * @param IT2Flags Interrupt2 flags to handle.
5914 * @retval None
5915 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c,uint32_t IT2Flags)5916 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
5917 {
5918 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
5919 uint16_t SlaveAddrCode;
5920
5921 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5922 {
5923 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
5924 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
5925
5926 /* Transfer Direction requested by Master */
5927 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
5928 {
5929 TransferDirection = I2C_DIRECTION_TRANSMIT;
5930 }
5931
5932 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
5933 {
5934 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
5935 }
5936 else
5937 {
5938 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
5939 }
5940
5941 /* Process Unlocked */
5942 __HAL_UNLOCK(hi2c);
5943
5944 /* Call Slave Addr callback */
5945 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5946 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
5947 #else
5948 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
5949 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5950 }
5951 else
5952 {
5953 /* Clear ADDR flag */
5954 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5955
5956 /* Process Unlocked */
5957 __HAL_UNLOCK(hi2c);
5958 }
5959 }
5960
5961 /**
5962 * @brief Handle STOPF flag for Slave
5963 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5964 * the configuration information for I2C module
5965 * @retval None
5966 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)5967 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
5968 {
5969 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5970 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5971
5972 /* Disable EVT, BUF and ERR interrupt */
5973 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5974
5975 /* Clear STOPF flag */
5976 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
5977
5978 /* Disable Acknowledge */
5979 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5980
5981 /* If a DMA is ongoing, Update handle size context */
5982 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5983 {
5984 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
5985 {
5986 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
5987
5988 if (hi2c->XferCount != 0U)
5989 {
5990 /* Set ErrorCode corresponding to a Non-Acknowledge */
5991 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5992 }
5993
5994 /* Disable, stop the current DMA */
5995 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5996
5997 /* Abort DMA Xfer if any */
5998 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
5999 {
6000 /* Set the I2C DMA Abort callback :
6001 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6002 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6003
6004 /* Abort DMA RX */
6005 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6006 {
6007 /* Call Directly XferAbortCallback function in case of error */
6008 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6009 }
6010 }
6011 }
6012 else
6013 {
6014 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
6015
6016 if (hi2c->XferCount != 0U)
6017 {
6018 /* Set ErrorCode corresponding to a Non-Acknowledge */
6019 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6020 }
6021
6022 /* Disable, stop the current DMA */
6023 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6024
6025 /* Abort DMA Xfer if any */
6026 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6027 {
6028 /* Set the I2C DMA Abort callback :
6029 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6030 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6031
6032 /* Abort DMA TX */
6033 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6034 {
6035 /* Call Directly XferAbortCallback function in case of error */
6036 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6037 }
6038 }
6039 }
6040 }
6041
6042 /* All data are not transferred, so set error code accordingly */
6043 if (hi2c->XferCount != 0U)
6044 {
6045 /* Store Last receive data if any */
6046 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6047 {
6048 /* Read data from DR */
6049 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6050
6051 /* Increment Buffer pointer */
6052 hi2c->pBuffPtr++;
6053
6054 /* Update counter */
6055 hi2c->XferCount--;
6056 }
6057
6058 /* Store Last receive data if any */
6059 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6060 {
6061 /* Read data from DR */
6062 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6063
6064 /* Increment Buffer pointer */
6065 hi2c->pBuffPtr++;
6066
6067 /* Update counter */
6068 hi2c->XferCount--;
6069 }
6070
6071 if (hi2c->XferCount != 0U)
6072 {
6073 /* Set ErrorCode corresponding to a Non-Acknowledge */
6074 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6075 }
6076 }
6077
6078 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6079 {
6080 /* Call the corresponding callback to inform upper layer of End of Transfer */
6081 I2C_ITError(hi2c);
6082 }
6083 else
6084 {
6085 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6086 {
6087 /* Set state at HAL_I2C_STATE_LISTEN */
6088 hi2c->PreviousState = I2C_STATE_NONE;
6089 hi2c->State = HAL_I2C_STATE_LISTEN;
6090
6091 /* Call the corresponding callback to inform upper layer of End of Transfer */
6092 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6093 hi2c->SlaveRxCpltCallback(hi2c);
6094 #else
6095 HAL_I2C_SlaveRxCpltCallback(hi2c);
6096 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6097 }
6098
6099 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6100 {
6101 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6102 hi2c->PreviousState = I2C_STATE_NONE;
6103 hi2c->State = HAL_I2C_STATE_READY;
6104 hi2c->Mode = HAL_I2C_MODE_NONE;
6105
6106 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6107 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6108 hi2c->ListenCpltCallback(hi2c);
6109 #else
6110 HAL_I2C_ListenCpltCallback(hi2c);
6111 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6112 }
6113 else
6114 {
6115 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6116 {
6117 hi2c->PreviousState = I2C_STATE_NONE;
6118 hi2c->State = HAL_I2C_STATE_READY;
6119 hi2c->Mode = HAL_I2C_MODE_NONE;
6120
6121 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6122 hi2c->SlaveRxCpltCallback(hi2c);
6123 #else
6124 HAL_I2C_SlaveRxCpltCallback(hi2c);
6125 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6126 }
6127 }
6128 }
6129 }
6130
6131 /**
6132 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6133 * the configuration information for I2C module
6134 * @retval None
6135 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)6136 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6137 {
6138 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6139 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6140 uint32_t CurrentXferOptions = hi2c->XferOptions;
6141
6142 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6143 (CurrentState == HAL_I2C_STATE_LISTEN))
6144 {
6145 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6146
6147 /* Disable EVT, BUF and ERR interrupt */
6148 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6149
6150 /* Clear AF flag */
6151 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6152
6153 /* Disable Acknowledge */
6154 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6155
6156 hi2c->PreviousState = I2C_STATE_NONE;
6157 hi2c->State = HAL_I2C_STATE_READY;
6158 hi2c->Mode = HAL_I2C_MODE_NONE;
6159
6160 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6161 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6162 hi2c->ListenCpltCallback(hi2c);
6163 #else
6164 HAL_I2C_ListenCpltCallback(hi2c);
6165 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6166 }
6167 else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6168 {
6169 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6170 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6171 hi2c->State = HAL_I2C_STATE_READY;
6172 hi2c->Mode = HAL_I2C_MODE_NONE;
6173
6174 /* Disable EVT, BUF and ERR interrupt */
6175 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6176
6177 /* Clear AF flag */
6178 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6179
6180 /* Disable Acknowledge */
6181 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6182
6183 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6184 hi2c->SlaveTxCpltCallback(hi2c);
6185 #else
6186 HAL_I2C_SlaveTxCpltCallback(hi2c);
6187 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6188 }
6189 else
6190 {
6191 /* Clear AF flag only */
6192 /* State Listen, but XferOptions == FIRST or NEXT */
6193 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6194 }
6195 }
6196
6197 /**
6198 * @brief I2C interrupts error process
6199 * @param hi2c I2C handle.
6200 * @retval None
6201 */
I2C_ITError(I2C_HandleTypeDef * hi2c)6202 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6203 {
6204 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6205 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6206 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6207 uint32_t CurrentError;
6208
6209 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6210 {
6211 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6212 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6213 }
6214
6215 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6216 {
6217 /* keep HAL_I2C_STATE_LISTEN */
6218 hi2c->PreviousState = I2C_STATE_NONE;
6219 hi2c->State = HAL_I2C_STATE_LISTEN;
6220 }
6221 else
6222 {
6223 /* If state is an abort treatment on going, don't change state */
6224 /* This change will be do later */
6225 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6226 {
6227 hi2c->State = HAL_I2C_STATE_READY;
6228 hi2c->Mode = HAL_I2C_MODE_NONE;
6229 }
6230 hi2c->PreviousState = I2C_STATE_NONE;
6231 }
6232
6233 /* Abort DMA transfer */
6234 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6235 {
6236 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6237
6238 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6239 {
6240 /* Set the DMA Abort callback :
6241 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6242 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6243
6244 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6245 {
6246 /* Disable I2C peripheral to prevent dummy data in buffer */
6247 __HAL_I2C_DISABLE(hi2c);
6248
6249 hi2c->State = HAL_I2C_STATE_READY;
6250
6251 /* Call Directly XferAbortCallback function in case of error */
6252 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6253 }
6254 }
6255 else
6256 {
6257 /* Set the DMA Abort callback :
6258 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6259 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6260
6261 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6262 {
6263 /* Store Last receive data if any */
6264 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6265 {
6266 /* Read data from DR */
6267 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6268
6269 /* Increment Buffer pointer */
6270 hi2c->pBuffPtr++;
6271 }
6272
6273 /* Disable I2C peripheral to prevent dummy data in buffer */
6274 __HAL_I2C_DISABLE(hi2c);
6275
6276 hi2c->State = HAL_I2C_STATE_READY;
6277
6278 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6279 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6280 }
6281 }
6282 }
6283 else if (hi2c->State == HAL_I2C_STATE_ABORT)
6284 {
6285 hi2c->State = HAL_I2C_STATE_READY;
6286 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6287
6288 /* Store Last receive data if any */
6289 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6290 {
6291 /* Read data from DR */
6292 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6293
6294 /* Increment Buffer pointer */
6295 hi2c->pBuffPtr++;
6296 }
6297
6298 /* Disable I2C peripheral to prevent dummy data in buffer */
6299 __HAL_I2C_DISABLE(hi2c);
6300
6301 /* Call the corresponding callback to inform upper layer of End of Transfer */
6302 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6303 hi2c->AbortCpltCallback(hi2c);
6304 #else
6305 HAL_I2C_AbortCpltCallback(hi2c);
6306 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6307 }
6308 else
6309 {
6310 /* Store Last receive data if any */
6311 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6312 {
6313 /* Read data from DR */
6314 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6315
6316 /* Increment Buffer pointer */
6317 hi2c->pBuffPtr++;
6318 }
6319
6320 /* Call user error callback */
6321 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6322 hi2c->ErrorCallback(hi2c);
6323 #else
6324 HAL_I2C_ErrorCallback(hi2c);
6325 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6326 }
6327
6328 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6329 CurrentError = hi2c->ErrorCode;
6330
6331 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6332 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6333 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
6334 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6335 {
6336 /* Disable EVT, BUF and ERR interrupt */
6337 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6338 }
6339
6340 /* So may inform upper layer that listen phase is stopped */
6341 /* during NACK error treatment */
6342 CurrentState = hi2c->State;
6343 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6344 {
6345 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6346 hi2c->PreviousState = I2C_STATE_NONE;
6347 hi2c->State = HAL_I2C_STATE_READY;
6348 hi2c->Mode = HAL_I2C_MODE_NONE;
6349
6350 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6351 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6352 hi2c->ListenCpltCallback(hi2c);
6353 #else
6354 HAL_I2C_ListenCpltCallback(hi2c);
6355 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6356 }
6357 }
6358
6359 /**
6360 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6361 * the configuration information for I2C module
6362 * @param DevAddress Target device address: The device 7 bits address value
6363 * in datasheet must be shifted to the left before calling the interface
6364 * @param Timeout Timeout duration
6365 * @param Tickstart Tick start value
6366 * @retval HAL status
6367 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6368 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6369 {
6370 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6371 uint32_t CurrentXferOptions = hi2c->XferOptions;
6372
6373 /* Generate Start condition if first transfer */
6374 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6375 {
6376 /* Generate Start */
6377 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6378 }
6379 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6380 {
6381 /* Generate ReStart */
6382 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6383 }
6384 else
6385 {
6386 /* Do nothing */
6387 }
6388
6389 /* Wait until SB flag is set */
6390 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6391 {
6392 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6393 {
6394 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6395 }
6396 return HAL_TIMEOUT;
6397 }
6398
6399 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6400 {
6401 /* Send slave address */
6402 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6403 }
6404 else
6405 {
6406 /* Send header of slave address */
6407 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6408
6409 /* Wait until ADD10 flag is set */
6410 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6411 {
6412 return HAL_ERROR;
6413 }
6414
6415 /* Send slave address */
6416 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6417 }
6418
6419 /* Wait until ADDR flag is set */
6420 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6421 {
6422 return HAL_ERROR;
6423 }
6424
6425 return HAL_OK;
6426 }
6427
6428 /**
6429 * @brief Master sends target device address for read request.
6430 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6431 * the configuration information for I2C module
6432 * @param DevAddress Target device address: The device 7 bits address value
6433 * in datasheet must be shifted to the left before calling the interface
6434 * @param Timeout Timeout duration
6435 * @param Tickstart Tick start value
6436 * @retval HAL status
6437 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6438 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6439 {
6440 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6441 uint32_t CurrentXferOptions = hi2c->XferOptions;
6442
6443 /* Enable Acknowledge */
6444 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6445
6446 /* Generate Start condition if first transfer */
6447 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6448 {
6449 /* Generate Start */
6450 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6451 }
6452 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6453 {
6454 /* Generate ReStart */
6455 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6456 }
6457 else
6458 {
6459 /* Do nothing */
6460 }
6461
6462 /* Wait until SB flag is set */
6463 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6464 {
6465 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6466 {
6467 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6468 }
6469 return HAL_TIMEOUT;
6470 }
6471
6472 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6473 {
6474 /* Send slave address */
6475 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6476 }
6477 else
6478 {
6479 /* Send header of slave address */
6480 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6481
6482 /* Wait until ADD10 flag is set */
6483 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6484 {
6485 return HAL_ERROR;
6486 }
6487
6488 /* Send slave address */
6489 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6490
6491 /* Wait until ADDR flag is set */
6492 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6493 {
6494 return HAL_ERROR;
6495 }
6496
6497 /* Clear ADDR flag */
6498 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6499
6500 /* Generate Restart */
6501 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6502
6503 /* Wait until SB flag is set */
6504 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6505 {
6506 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6507 {
6508 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6509 }
6510 return HAL_TIMEOUT;
6511 }
6512
6513 /* Send header of slave address */
6514 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6515 }
6516
6517 /* Wait until ADDR flag is set */
6518 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6519 {
6520 return HAL_ERROR;
6521 }
6522
6523 return HAL_OK;
6524 }
6525
6526 /**
6527 * @brief Master sends target device address followed by internal memory address for write request.
6528 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6529 * the configuration information for I2C module
6530 * @param DevAddress Target device address: The device 7 bits address value
6531 * in datasheet must be shifted to the left before calling the interface
6532 * @param MemAddress Internal memory address
6533 * @param MemAddSize Size of internal memory address
6534 * @param Timeout Timeout duration
6535 * @param Tickstart Tick start value
6536 * @retval HAL status
6537 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6538 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6539 {
6540 /* Generate Start */
6541 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6542
6543 /* Wait until SB flag is set */
6544 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6545 {
6546 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6547 {
6548 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6549 }
6550 return HAL_TIMEOUT;
6551 }
6552
6553 /* Send slave address */
6554 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6555
6556 /* Wait until ADDR flag is set */
6557 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6558 {
6559 return HAL_ERROR;
6560 }
6561
6562 /* Clear ADDR flag */
6563 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6564
6565 /* Wait until TXE flag is set */
6566 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6567 {
6568 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6569 {
6570 /* Generate Stop */
6571 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6572 }
6573 return HAL_ERROR;
6574 }
6575
6576 /* If Memory address size is 8Bit */
6577 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6578 {
6579 /* Send Memory Address */
6580 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6581 }
6582 /* If Memory address size is 16Bit */
6583 else
6584 {
6585 /* Send MSB of Memory Address */
6586 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6587
6588 /* Wait until TXE flag is set */
6589 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6590 {
6591 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6592 {
6593 /* Generate Stop */
6594 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6595 }
6596 return HAL_ERROR;
6597 }
6598
6599 /* Send LSB of Memory Address */
6600 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6601 }
6602
6603 return HAL_OK;
6604 }
6605
6606 /**
6607 * @brief Master sends target device address followed by internal memory address for read request.
6608 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6609 * the configuration information for I2C module
6610 * @param DevAddress Target device address: The device 7 bits address value
6611 * in datasheet must be shifted to the left before calling the interface
6612 * @param MemAddress Internal memory address
6613 * @param MemAddSize Size of internal memory address
6614 * @param Timeout Timeout duration
6615 * @param Tickstart Tick start value
6616 * @retval HAL status
6617 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6618 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6619 {
6620 /* Enable Acknowledge */
6621 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6622
6623 /* Generate Start */
6624 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6625
6626 /* Wait until SB flag is set */
6627 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6628 {
6629 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6630 {
6631 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6632 }
6633 return HAL_TIMEOUT;
6634 }
6635
6636 /* Send slave address */
6637 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6638
6639 /* Wait until ADDR flag is set */
6640 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6641 {
6642 return HAL_ERROR;
6643 }
6644
6645 /* Clear ADDR flag */
6646 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6647
6648 /* Wait until TXE flag is set */
6649 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6650 {
6651 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6652 {
6653 /* Generate Stop */
6654 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6655 }
6656 return HAL_ERROR;
6657 }
6658
6659 /* If Memory address size is 8Bit */
6660 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6661 {
6662 /* Send Memory Address */
6663 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6664 }
6665 /* If Memory address size is 16Bit */
6666 else
6667 {
6668 /* Send MSB of Memory Address */
6669 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6670
6671 /* Wait until TXE flag is set */
6672 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6673 {
6674 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6675 {
6676 /* Generate Stop */
6677 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6678 }
6679 return HAL_ERROR;
6680 }
6681
6682 /* Send LSB of Memory Address */
6683 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6684 }
6685
6686 /* Wait until TXE flag is set */
6687 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6688 {
6689 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6690 {
6691 /* Generate Stop */
6692 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6693 }
6694 return HAL_ERROR;
6695 }
6696
6697 /* Generate Restart */
6698 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6699
6700 /* Wait until SB flag is set */
6701 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6702 {
6703 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6704 {
6705 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6706 }
6707 return HAL_TIMEOUT;
6708 }
6709
6710 /* Send slave address */
6711 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6712
6713 /* Wait until ADDR flag is set */
6714 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6715 {
6716 return HAL_ERROR;
6717 }
6718
6719 return HAL_OK;
6720 }
6721
6722 /**
6723 * @brief DMA I2C process complete callback.
6724 * @param hdma DMA handle
6725 * @retval None
6726 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)6727 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6728 {
6729 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6730
6731 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6732 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6733 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6734 uint32_t CurrentXferOptions = hi2c->XferOptions;
6735
6736 /* Disable EVT and ERR interrupt */
6737 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6738
6739 /* Clear Complete callback */
6740 if (hi2c->hdmatx != NULL)
6741 {
6742 hi2c->hdmatx->XferCpltCallback = NULL;
6743 }
6744 if (hi2c->hdmarx != NULL)
6745 {
6746 hi2c->hdmarx->XferCpltCallback = NULL;
6747 }
6748
6749 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6750 {
6751 /* Disable DMA Request */
6752 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6753
6754 hi2c->XferCount = 0U;
6755
6756 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6757 {
6758 /* Set state at HAL_I2C_STATE_LISTEN */
6759 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6760 hi2c->State = HAL_I2C_STATE_LISTEN;
6761
6762 /* Call the corresponding callback to inform upper layer of End of Transfer */
6763 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6764 hi2c->SlaveTxCpltCallback(hi2c);
6765 #else
6766 HAL_I2C_SlaveTxCpltCallback(hi2c);
6767 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6768 }
6769 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6770 {
6771 /* Set state at HAL_I2C_STATE_LISTEN */
6772 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6773 hi2c->State = HAL_I2C_STATE_LISTEN;
6774
6775 /* Call the corresponding callback to inform upper layer of End of Transfer */
6776 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6777 hi2c->SlaveRxCpltCallback(hi2c);
6778 #else
6779 HAL_I2C_SlaveRxCpltCallback(hi2c);
6780 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6781 }
6782 else
6783 {
6784 /* Do nothing */
6785 }
6786
6787 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6788 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6789 }
6790 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
6791 else if (hi2c->Mode != HAL_I2C_MODE_NONE)
6792 {
6793 if (hi2c->XferCount == (uint16_t)1)
6794 {
6795 /* Disable Acknowledge */
6796 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6797 }
6798
6799 /* Disable EVT and ERR interrupt */
6800 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6801
6802 /* Prepare next transfer or stop current transfer */
6803 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
6804 {
6805 /* Generate Stop */
6806 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6807 }
6808
6809 /* Disable Last DMA */
6810 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6811
6812 /* Disable DMA Request */
6813 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6814
6815 hi2c->XferCount = 0U;
6816
6817 /* Check if Errors has been detected during transfer */
6818 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6819 {
6820 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6821 hi2c->ErrorCallback(hi2c);
6822 #else
6823 HAL_I2C_ErrorCallback(hi2c);
6824 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6825 }
6826 else
6827 {
6828 hi2c->State = HAL_I2C_STATE_READY;
6829
6830 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6831 {
6832 hi2c->Mode = HAL_I2C_MODE_NONE;
6833 hi2c->PreviousState = I2C_STATE_NONE;
6834
6835 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6836 hi2c->MemRxCpltCallback(hi2c);
6837 #else
6838 HAL_I2C_MemRxCpltCallback(hi2c);
6839 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6840 }
6841 else
6842 {
6843 hi2c->Mode = HAL_I2C_MODE_NONE;
6844 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6845
6846 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6847 hi2c->MasterRxCpltCallback(hi2c);
6848 #else
6849 HAL_I2C_MasterRxCpltCallback(hi2c);
6850 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6851 }
6852 }
6853 }
6854 else
6855 {
6856 /* Do nothing */
6857 }
6858 }
6859
6860 /**
6861 * @brief DMA I2C communication error callback.
6862 * @param hdma DMA handle
6863 * @retval None
6864 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6865 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6866 {
6867 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6868
6869 /* Clear Complete callback */
6870 if (hi2c->hdmatx != NULL)
6871 {
6872 hi2c->hdmatx->XferCpltCallback = NULL;
6873 }
6874 if (hi2c->hdmarx != NULL)
6875 {
6876 hi2c->hdmarx->XferCpltCallback = NULL;
6877 }
6878
6879 /* Ignore DMA FIFO error */
6880 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
6881 {
6882 /* Disable Acknowledge */
6883 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
6884
6885 hi2c->XferCount = 0U;
6886
6887 hi2c->State = HAL_I2C_STATE_READY;
6888 hi2c->Mode = HAL_I2C_MODE_NONE;
6889
6890 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
6891
6892 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6893 hi2c->ErrorCallback(hi2c);
6894 #else
6895 HAL_I2C_ErrorCallback(hi2c);
6896 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6897 }
6898 }
6899
6900 /**
6901 * @brief DMA I2C communication abort callback
6902 * (To be called at end of DMA Abort procedure).
6903 * @param hdma DMA handle.
6904 * @retval None
6905 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6906 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6907 {
6908 __IO uint32_t count = 0U;
6909 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6910
6911 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6912 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6913
6914 /* During abort treatment, check that there is no pending STOP request */
6915 /* Wait until STOP flag is reset */
6916 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
6917 do
6918 {
6919 if (count == 0U)
6920 {
6921 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6922 break;
6923 }
6924 count--;
6925 }
6926 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
6927
6928 /* Clear Complete callback */
6929 if (hi2c->hdmatx != NULL)
6930 {
6931 hi2c->hdmatx->XferCpltCallback = NULL;
6932 }
6933 if (hi2c->hdmarx != NULL)
6934 {
6935 hi2c->hdmarx->XferCpltCallback = NULL;
6936 }
6937
6938 /* Disable Acknowledge */
6939 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6940
6941 hi2c->XferCount = 0U;
6942
6943 /* Reset XferAbortCallback */
6944 if (hi2c->hdmatx != NULL)
6945 {
6946 hi2c->hdmatx->XferAbortCallback = NULL;
6947 }
6948 if (hi2c->hdmarx != NULL)
6949 {
6950 hi2c->hdmarx->XferAbortCallback = NULL;
6951 }
6952
6953 /* Disable I2C peripheral to prevent dummy data in buffer */
6954 __HAL_I2C_DISABLE(hi2c);
6955
6956 /* Check if come from abort from user */
6957 if (hi2c->State == HAL_I2C_STATE_ABORT)
6958 {
6959 hi2c->State = HAL_I2C_STATE_READY;
6960 hi2c->Mode = HAL_I2C_MODE_NONE;
6961 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6962
6963 /* Call the corresponding callback to inform upper layer of End of Transfer */
6964 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6965 hi2c->AbortCpltCallback(hi2c);
6966 #else
6967 HAL_I2C_AbortCpltCallback(hi2c);
6968 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6969 }
6970 else
6971 {
6972 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6973 {
6974 /* Renable I2C peripheral */
6975 __HAL_I2C_ENABLE(hi2c);
6976
6977 /* Enable Acknowledge */
6978 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6979
6980 /* keep HAL_I2C_STATE_LISTEN */
6981 hi2c->PreviousState = I2C_STATE_NONE;
6982 hi2c->State = HAL_I2C_STATE_LISTEN;
6983 }
6984 else
6985 {
6986 hi2c->State = HAL_I2C_STATE_READY;
6987 hi2c->Mode = HAL_I2C_MODE_NONE;
6988 }
6989
6990 /* Call the corresponding callback to inform upper layer of End of Transfer */
6991 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6992 hi2c->ErrorCallback(hi2c);
6993 #else
6994 HAL_I2C_ErrorCallback(hi2c);
6995 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6996 }
6997 }
6998
6999 /**
7000 * @brief This function handles I2C Communication Timeout.
7001 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7002 * the configuration information for I2C module
7003 * @param Flag specifies the I2C flag to check.
7004 * @param Status The new Flag status (SET or RESET).
7005 * @param Timeout Timeout duration
7006 * @param Tickstart Tick start value
7007 * @retval HAL status
7008 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7009 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7010 {
7011 /* Wait until flag is set */
7012 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7013 {
7014 /* Check for the Timeout */
7015 if (Timeout != HAL_MAX_DELAY)
7016 {
7017 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7018 {
7019 hi2c->PreviousState = I2C_STATE_NONE;
7020 hi2c->State = HAL_I2C_STATE_READY;
7021 hi2c->Mode = HAL_I2C_MODE_NONE;
7022 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7023
7024 /* Process Unlocked */
7025 __HAL_UNLOCK(hi2c);
7026
7027 return HAL_ERROR;
7028 }
7029 }
7030 }
7031 return HAL_OK;
7032 }
7033
7034 /**
7035 * @brief This function handles I2C Communication Timeout for Master addressing phase.
7036 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7037 * the configuration information for I2C module
7038 * @param Flag specifies the I2C flag to check.
7039 * @param Timeout Timeout duration
7040 * @param Tickstart Tick start value
7041 * @retval HAL status
7042 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)7043 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7044 {
7045 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7046 {
7047 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7048 {
7049 /* Generate Stop */
7050 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7051
7052 /* Clear AF Flag */
7053 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7054
7055 hi2c->PreviousState = I2C_STATE_NONE;
7056 hi2c->State = HAL_I2C_STATE_READY;
7057 hi2c->Mode = HAL_I2C_MODE_NONE;
7058 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7059
7060 /* Process Unlocked */
7061 __HAL_UNLOCK(hi2c);
7062
7063 return HAL_ERROR;
7064 }
7065
7066 /* Check for the Timeout */
7067 if (Timeout != HAL_MAX_DELAY)
7068 {
7069 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7070 {
7071 hi2c->PreviousState = I2C_STATE_NONE;
7072 hi2c->State = HAL_I2C_STATE_READY;
7073 hi2c->Mode = HAL_I2C_MODE_NONE;
7074 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7075
7076 /* Process Unlocked */
7077 __HAL_UNLOCK(hi2c);
7078
7079 return HAL_ERROR;
7080 }
7081 }
7082 }
7083 return HAL_OK;
7084 }
7085
7086 /**
7087 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
7088 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7089 * the configuration information for the specified I2C.
7090 * @param Timeout Timeout duration
7091 * @param Tickstart Tick start value
7092 * @retval HAL status
7093 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7094 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7095 {
7096 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7097 {
7098 /* Check if a NACK is detected */
7099 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7100 {
7101 return HAL_ERROR;
7102 }
7103
7104 /* Check for the Timeout */
7105 if (Timeout != HAL_MAX_DELAY)
7106 {
7107 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7108 {
7109 hi2c->PreviousState = I2C_STATE_NONE;
7110 hi2c->State = HAL_I2C_STATE_READY;
7111 hi2c->Mode = HAL_I2C_MODE_NONE;
7112 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7113
7114 /* Process Unlocked */
7115 __HAL_UNLOCK(hi2c);
7116
7117 return HAL_ERROR;
7118 }
7119 }
7120 }
7121 return HAL_OK;
7122 }
7123
7124 /**
7125 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
7126 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7127 * the configuration information for the specified I2C.
7128 * @param Timeout Timeout duration
7129 * @param Tickstart Tick start value
7130 * @retval HAL status
7131 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7132 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7133 {
7134 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7135 {
7136 /* Check if a NACK is detected */
7137 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7138 {
7139 return HAL_ERROR;
7140 }
7141
7142 /* Check for the Timeout */
7143 if (Timeout != HAL_MAX_DELAY)
7144 {
7145 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7146 {
7147 hi2c->PreviousState = I2C_STATE_NONE;
7148 hi2c->State = HAL_I2C_STATE_READY;
7149 hi2c->Mode = HAL_I2C_MODE_NONE;
7150 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7151
7152 /* Process Unlocked */
7153 __HAL_UNLOCK(hi2c);
7154
7155 return HAL_ERROR;
7156 }
7157 }
7158 }
7159 return HAL_OK;
7160 }
7161
7162 /**
7163 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7164 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7165 * the configuration information for the specified I2C.
7166 * @param Timeout Timeout duration
7167 * @param Tickstart Tick start value
7168 * @retval HAL status
7169 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7170 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7171 {
7172 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7173 {
7174 /* Check if a NACK is detected */
7175 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7176 {
7177 return HAL_ERROR;
7178 }
7179
7180 /* Check for the Timeout */
7181 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7182 {
7183 hi2c->PreviousState = I2C_STATE_NONE;
7184 hi2c->State = HAL_I2C_STATE_READY;
7185 hi2c->Mode = HAL_I2C_MODE_NONE;
7186 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7187
7188 /* Process Unlocked */
7189 __HAL_UNLOCK(hi2c);
7190
7191 return HAL_ERROR;
7192 }
7193 }
7194 return HAL_OK;
7195 }
7196
7197 /**
7198 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
7199 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7200 * the configuration information for the specified I2C.
7201 * @retval HAL status
7202 */
I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef * hi2c)7203 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7204 {
7205 __IO uint32_t count = 0U;
7206
7207 /* Wait until STOP flag is reset */
7208 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7209 do
7210 {
7211 count--;
7212 if (count == 0U)
7213 {
7214 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7215
7216 return HAL_ERROR;
7217 }
7218 }
7219 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7220
7221 return HAL_OK;
7222 }
7223
7224 /**
7225 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7226 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7227 * the configuration information for the specified I2C.
7228 * @param Timeout Timeout duration
7229 * @param Tickstart Tick start value
7230 * @retval HAL status
7231 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7232 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7233 {
7234
7235 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7236 {
7237 /* Check if a STOPF is detected */
7238 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7239 {
7240 /* Clear STOP Flag */
7241 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7242
7243 hi2c->PreviousState = I2C_STATE_NONE;
7244 hi2c->State = HAL_I2C_STATE_READY;
7245 hi2c->Mode = HAL_I2C_MODE_NONE;
7246 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7247
7248 /* Process Unlocked */
7249 __HAL_UNLOCK(hi2c);
7250
7251 return HAL_ERROR;
7252 }
7253
7254 /* Check for the Timeout */
7255 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7256 {
7257 hi2c->PreviousState = I2C_STATE_NONE;
7258 hi2c->State = HAL_I2C_STATE_READY;
7259 hi2c->Mode = HAL_I2C_MODE_NONE;
7260 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7261
7262 /* Process Unlocked */
7263 __HAL_UNLOCK(hi2c);
7264
7265 return HAL_ERROR;
7266 }
7267 }
7268 return HAL_OK;
7269 }
7270
7271 /**
7272 * @brief This function handles Acknowledge failed detection during an I2C Communication.
7273 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7274 * the configuration information for the specified I2C.
7275 * @retval HAL status
7276 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)7277 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7278 {
7279 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7280 {
7281 /* Clear NACKF Flag */
7282 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7283
7284 hi2c->PreviousState = I2C_STATE_NONE;
7285 hi2c->State = HAL_I2C_STATE_READY;
7286 hi2c->Mode = HAL_I2C_MODE_NONE;
7287 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7288
7289 /* Process Unlocked */
7290 __HAL_UNLOCK(hi2c);
7291
7292 return HAL_ERROR;
7293 }
7294 return HAL_OK;
7295 }
7296
7297 /**
7298 * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
7299 * @param hi2c I2C handle.
7300 * @retval None
7301 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7302 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7303 {
7304 /* if user set XferOptions to I2C_OTHER_FRAME */
7305 /* it request implicitly to generate a restart condition */
7306 /* set XferOptions to I2C_FIRST_FRAME */
7307 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7308 {
7309 hi2c->XferOptions = I2C_FIRST_FRAME;
7310 }
7311 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7312 /* it request implicitly to generate a restart condition */
7313 /* then generate a stop condition at the end of transfer */
7314 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7315 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7316 {
7317 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7318 }
7319 else
7320 {
7321 /* Nothing to do */
7322 }
7323 }
7324
7325 /**
7326 * @}
7327 */
7328
7329 #endif /* HAL_I2C_MODULE_ENABLED */
7330 /**
7331 * @}
7332 */
7333
7334 /**
7335 * @}
7336 */
7337
7338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7339