1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization, de-initialization, set config and get config functions
9 * + DES/TDES, AES processing functions
10 * + DMA callback functions
11 * + CRYP IRQ handler management
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
20
21 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
22 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
23 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
24 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
25 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
26 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
27 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
28 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
29 (+++) Configure and enable two DMA streams one for managing data transfer from
30 memory to peripheral (input stream) and another stream for managing data
31 transfer from peripheral to memory (output stream)
32 (+++) Associate the initialized DMA handle to the CRYP DMA handle
33 using __HAL_LINKDMA()
34 (+++) Configure the priority and enable the NVIC for the transfer complete
35 interrupt on the two DMA Streams. The output stream should have higher
36 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
37
38 (#)Initialize the CRYP according to the specified parameters :
39 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
40 (##) The key size: 128, 192 or 256.
41 (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
42 (##) The initialization vector (counter). It is not used in ECB mode.
43 (##) The key buffer used for encryption/decryption.
44 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
45 (##) The HeaderSize The size of header buffer in word.
46 (##) The B0 block is the first authentication block used only in AES CCM mode.
47
48 (#)Three processing (encryption/decryption) functions are available:
49 (##) Polling mode: encryption and decryption APIs are blocking functions
50 i.e. they process the data and wait till the processing is finished,
51 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
52 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
53 i.e. they process the data under interrupt,
54 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
55 (##) DMA mode: encryption and decryption APIs are not blocking functions
56 i.e. the data transfer is ensured by DMA,
57 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
58
59 (#)When the processing function is called at first time after HAL_CRYP_Init()
60 the CRYP peripheral is configured and processes the buffer in input.
61 At second call, no need to Initialize the CRYP, user have to get current configuration via
62 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
63 new parametres, finally user can start encryption/decryption.
64
65 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
66
67 (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
68 without having to configure again the Key or the Initialization Vector between each API call,
69 the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
70 Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
71 or HAL_CRYP_Decrypt_DMA().
72
73 [..]
74 The cryptographic processor supports following standards:
75 (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
76 (##)64-bit data block processing
77 (##) chaining modes supported :
78 (+++) Electronic Code Book(ECB)
79 (+++) Cipher Block Chaining (CBC)
80 (##) keys length supported :64-bit, 128-bit and 192-bit.
81 (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
82 (##)128-bit data block processing
83 (##) chaining modes supported :
84 (+++) Electronic Code Book(ECB)
85 (+++) Cipher Block Chaining (CBC)
86 (+++) Counter mode (CTR)
87 (+++) Galois/counter mode (GCM/GMAC)
88 (+++) Counter with Cipher Block Chaining-Message(CCM)
89 (##) keys length Supported :
90 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
91 (+++) for TinyAES IP: 128-bit and 256-bit
92
93 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
94 (#) Algorithm supported :
95 (##) Galois/counter mode (GCM)
96 (##) Galois message authentication code (GMAC) :is exactly the same as
97 GCM algorithm composed only by an header.
98 (#) Four phases are performed in GCM :
99 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
100 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
101 computation only.
102 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
103 encryption + data XORing. It works in a similar way for ciphertext (C).
104 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
105 (#) structure of message construction in GCM is defined as below :
106 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
107 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
108 this part of the message is only authenticated, not encrypted.
109 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
110 GCM standard specifies that ciphertext has same bit length as the plaintext.
111 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
112 (on 64 bits)
113
114 [..] This section describe The AES Counter with Cipher Block Chaining-Message
115 Authentication Code (CCM) supported by both CRYP1 IP:
116 (#) Specific parameters for CCM :
117
118 (##) B0 block : According to NIST Special Publication 800-38C,
119 The first block B0 is formatted as follows, where l(m) is encoded in
120 most-significant-byte first order(see below table 3)
121
122 (+++) Q: a bit string representation of the octet length of P (plaintext)
123 (+++) q The octet length of the binary representation of the octet length of the payload
124 (+++) A nonce (N), n The octet length of the where n+q=15.
125 (+++) Flags: most significant octet containing four flags for control information,
126 (+++) t The octet length of the MAC.
127 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
128 the associated data length expressed in bytes (a) defined as below:
129 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
130 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
131 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
132 (##) CTRx block : control blocks
133 (+++) Generation of CTR1 from first block B0 information :
134 equal to B0 with first 5 bits zeroed and most significant bits storing octet
135 length of P also zeroed, then incremented by one ( see below Table 4)
136 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
137
138 (#) Four phases are performed in CCM for CRYP1 IP:
139 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
140 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
141 computation only.
142 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
143 encryption + data XORing. It works in a similar way for ciphertext (C).
144 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
145
146 *** Callback registration ***
147 =============================================
148
149 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
150 allows the user to configure dynamically the driver callbacks.
151 Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
152 to register an interrupt callback.
153
154 Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
155 (+) InCpltCallback : Input FIFO transfer completed callback.
156 (+) OutCpltCallback : Output FIFO transfer completed callback.
157 (+) ErrorCallback : callback for error detection.
158 (+) MspInitCallback : CRYP MspInit.
159 (+) MspDeInitCallback : CRYP MspDeInit.
160 This function takes as parameters the HAL peripheral handle, the Callback ID
161 and a pointer to the user callback function.
162
163 Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
164 weak function.
165 @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
166 and the Callback ID.
167 This function allows to reset following callbacks:
168 (+) InCpltCallback : Input FIFO transfer completed callback.
169 (+) OutCpltCallback : Output FIFO transfer completed callback.
170 (+) ErrorCallback : callback for error detection.
171 (+) MspInitCallback : CRYP MspInit.
172 (+) MspDeInitCallback : CRYP MspDeInit.
173
174 By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
175 all callbacks are set to the corresponding weak functions :
176 examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
177 Exception done for MspInit and MspDeInit functions that are
178 reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
179 these callbacks are null (not registered beforehand).
180 if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
181 keep and use the user MspInit/MspDeInit functions (registered beforehand)
182
183 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
184 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
185 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
186 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
187 In that case first register the MspInit/MspDeInit user callbacks
188 using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
189 or @ref HAL_CRYP_Init() function.
190
191 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
192 not defined, the callback registration feature is not available and all callbacks
193 are set to the corresponding weak functions.
194
195 Table 1. Initial Counter Block (ICB)
196 +-------------------------------------------------------+
197 | Initialization vector (IV) | Counter |
198 |----------------|----------------|-----------|---------|
199 127 95 63 31 0
200
201
202 Bit Number Register Contents
203 ---------- --------------- -----------
204 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
205 95 ...64 CRYP_IV1L[31:0] B0[95:64]
206 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
207 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
208
209 Table 2. GCM last block definition
210
211 +-------------------------------------------------------------------+
212 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
213 |-----------|--------------------|-----------|----------------------|
214 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
215 |-----------|--------------------|-----------|----------------------|
216
217 Table 3. B0 block
218 Octet Number Contents
219 ------------ ---------
220 0 Flags
221 1 ... 15-q Nonce N
222 16-q ... 15 Q
223
224 the Flags field is formatted as follows:
225
226 Bit Number Contents
227 ---------- ----------------------
228 7 Reserved (always zero)
229 6 Adata
230 5 ... 3 (t-2)/2
231 2 ... 0 [q-1]3
232
233 Table 4. CTRx block
234 Bit Number Register Contents
235 ---------- --------------- -----------
236 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
237 bit 0 that is set to 1
238 95 ...64 CRYP_IV1L[31:0] B0[95:64]
239 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
240 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
241
242 @endverbatim
243 ******************************************************************************
244 * @attention
245 *
246 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
247 * All rights reserved.</center></h2>
248 *
249 * This software component is licensed by ST under BSD 3-Clause license,
250 * the "License"; You may not use this file except in compliance with the
251 * License. You may obtain a copy of the License at:
252 * opensource.org/licenses/BSD-3-Clause
253 *
254 ******************************************************************************
255 */
256
257 /* Includes ------------------------------------------------------------------*/
258 #include "stm32f4xx_hal.h"
259
260 /** @addtogroup STM32F4xx_HAL_Driver
261 * @{
262 */
263
264 #if defined (AES) || defined (CRYP)
265
266 /** @defgroup CRYP CRYP
267 * @brief CRYP HAL module driver.
268 * @{
269 */
270
271
272 #ifdef HAL_CRYP_MODULE_ENABLED
273
274 /* Private typedef -----------------------------------------------------------*/
275 /* Private define ------------------------------------------------------------*/
276 /** @addtogroup CRYP_Private_Defines
277 * @{
278 */
279 #define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
280 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
281 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
282
283 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
284 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
285
286 #if defined(AES)
287 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
288 #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
289 #define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
290 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
291 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
292 #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
293 #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
294 #define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
295 #else /* CRYP */
296 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
297 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
298 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
299 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
300 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
301 #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
302 #endif /* End CRYP or AES */
303
304 /* CTR1 information to use in CCM algorithm */
305 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
306 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
307 #define CRYP_CCM_CTR1_2 0x00000001U
308
309
310 /**
311 * @}
312 */
313
314
315 /* Private macro -------------------------------------------------------------*/
316 /** @addtogroup CRYP_Private_Macros
317 * @{
318 */
319
320 #if defined(CRYP)
321
322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
323 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
324 }while(0)
325
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
327
328 #else /*AES*/
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
330 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
331 }while(0)
332 #endif /* End AES or CRYP*/
333
334
335 /**
336 * @}
337 */
338
339 /* Private struct -------------------------------------------------------------*/
340 /* Private variables ---------------------------------------------------------*/
341 /* Private function prototypes -----------------------------------------------*/
342 /** @addtogroup CRYP_Private_Functions_prototypes
343 * @{
344 */
345
346 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
347 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
348 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
349 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
350 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
351 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
352 #if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
353 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
354 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
355 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
356 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
357 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
358 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
359 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
360 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
362 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
363 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
364 #endif /* AES or GCM CCM defined*/
365 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
366 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
368 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
369 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
370 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
371 #if defined (CRYP)
372 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
373 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
374 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
375 #endif /* GCM CCM defined*/
376 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
377 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
378 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379 #else /*AES*/
380 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
381 #endif /* End CRYP or AES */
382
383 /**
384 * @}
385 */
386
387 /* Exported functions ---------------------------------------------------------*/
388
389 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
390 * @{
391 */
392
393
394 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
395 * @brief Initialization and Configuration functions.
396 *
397 @verbatim
398 ========================================================================================
399 ##### Initialization, de-initialization and Set and Get configuration functions #####
400 ========================================================================================
401 [..] This section provides functions allowing to:
402 (+) Initialize the CRYP
403 (+) DeInitialize the CRYP
404 (+) Initialize the CRYP MSP
405 (+) DeInitialize the CRYP MSP
406 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
407 Parameters which are configured in This section are :
408 (+) Key size
409 (+) Data Type : 32,16, 8 or 1bit
410 (+) AlgoMode :
411 - for CRYP1 IP :
412 ECB and CBC in DES/TDES Standard
413 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
414 - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
415 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
416
417
418 @endverbatim
419 * @{
420 */
421
422
423 /**
424 * @brief Initializes the CRYP according to the specified
425 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
426 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
427 * the configuration information for CRYP module
428 * @retval HAL status
429 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)430 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
431 {
432 /* Check the CRYP handle allocation */
433 if (hcryp == NULL)
434 {
435 return HAL_ERROR;
436 }
437
438 /* Check parameters */
439 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
440 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
441 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
442 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
443
444 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
445 if (hcryp->State == HAL_CRYP_STATE_RESET)
446 {
447 /* Allocate lock resource and initialize it */
448 hcryp->Lock = HAL_UNLOCKED;
449
450 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
451 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
452 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
453
454 if (hcryp->MspInitCallback == NULL)
455 {
456 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
457 }
458
459 /* Init the low level hardware */
460 hcryp->MspInitCallback(hcryp);
461 }
462 #else
463 if (hcryp->State == HAL_CRYP_STATE_RESET)
464 {
465 /* Allocate lock resource and initialize it */
466 hcryp->Lock = HAL_UNLOCKED;
467
468 /* Init the low level hardware */
469 HAL_CRYP_MspInit(hcryp);
470 }
471 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
472
473 /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type and Algorithm */
474 #if defined (CRYP)
475
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
477 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
478
479 #else /*AES*/
480
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
482 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
483
484 #endif /* End AES or CRYP*/
485
486 /* Reset Error Code field */
487 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
488
489 /* Change the CRYP state */
490 hcryp->State = HAL_CRYP_STATE_READY;
491
492 /* Set the default CRYP phase */
493 hcryp->Phase = CRYP_PHASE_READY;
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief De-Initializes the CRYP peripheral.
501 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
502 * the configuration information for CRYP module
503 * @retval HAL status
504 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)505 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
506 {
507 /* Check the CRYP handle allocation */
508 if (hcryp == NULL)
509 {
510 return HAL_ERROR;
511 }
512
513 /* Set the default CRYP phase */
514 hcryp->Phase = CRYP_PHASE_READY;
515
516 /* Reset CrypInCount and CrypOutCount */
517 hcryp->CrypInCount = 0;
518 hcryp->CrypOutCount = 0;
519 hcryp->CrypHeaderCount = 0;
520
521 /* Disable the CRYP peripheral clock */
522 __HAL_CRYP_DISABLE(hcryp);
523
524 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
525
526 if (hcryp->MspDeInitCallback == NULL)
527 {
528 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
529 }
530 /* DeInit the low level hardware */
531 hcryp->MspDeInitCallback(hcryp);
532
533 #else
534
535 /* DeInit the low level hardware: CLOCK, NVIC.*/
536 HAL_CRYP_MspDeInit(hcryp);
537
538 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
539
540 /* Change the CRYP state */
541 hcryp->State = HAL_CRYP_STATE_RESET;
542
543 /* Release Lock */
544 __HAL_UNLOCK(hcryp);
545
546 /* Return function status */
547 return HAL_OK;
548 }
549
550 /**
551 * @brief Configure the CRYP according to the specified
552 * parameters in the CRYP_ConfigTypeDef
553 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
554 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
555 * the configuration information for CRYP module
556 * @retval HAL status
557 */
HAL_CRYP_SetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)558 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
559 {
560 /* Check the CRYP handle allocation */
561 if ((hcryp == NULL) || (pConf == NULL))
562 {
563 return HAL_ERROR;
564 }
565
566 /* Check parameters */
567 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
568 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
569 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
570
571 if (hcryp->State == HAL_CRYP_STATE_READY)
572 {
573 /* Change the CRYP state */
574 hcryp->State = HAL_CRYP_STATE_BUSY;
575
576 /* Process locked */
577 __HAL_LOCK(hcryp);
578
579 /* Set CRYP parameters */
580 hcryp->Init.DataType = pConf->DataType;
581 hcryp->Init.pKey = pConf->pKey;
582 hcryp->Init.Algorithm = pConf->Algorithm;
583 hcryp->Init.KeySize = pConf->KeySize;
584 hcryp->Init.pInitVect = pConf->pInitVect;
585 hcryp->Init.Header = pConf->Header;
586 hcryp->Init.HeaderSize = pConf->HeaderSize;
587 hcryp->Init.B0 = pConf->B0;
588 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
589
590 /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
591 #if defined (CRYP)
592
593 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
594 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
595
596 #else /*AES*/
597 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
598 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
599
600 /*clear error flags*/
601 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
602
603 #endif /* End AES or CRYP */
604
605 /* Process Unlocked */
606 __HAL_UNLOCK(hcryp);
607
608 /* Reset Error Code field */
609 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
610
611 /* Change the CRYP state */
612 hcryp->State = HAL_CRYP_STATE_READY;
613
614 /* Set the default CRYP phase */
615 hcryp->Phase = CRYP_PHASE_READY;
616
617 /* Return function status */
618 return HAL_OK;
619 }
620 else
621 {
622 /* Process Unlocked */
623 __HAL_UNLOCK(hcryp);
624
625 /* Busy error code field */
626 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
627 return HAL_ERROR;
628 }
629 }
630
631 /**
632 * @brief Get CRYP Configuration parameters in associated handle.
633 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
634 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
635 * the configuration information for CRYP module
636 * @retval HAL status
637 */
HAL_CRYP_GetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)638 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
639 {
640 /* Check the CRYP handle allocation */
641 if ((hcryp == NULL) || (pConf == NULL))
642 {
643 return HAL_ERROR;
644 }
645
646 if (hcryp->State == HAL_CRYP_STATE_READY)
647 {
648 /* Change the CRYP state */
649 hcryp->State = HAL_CRYP_STATE_BUSY;
650
651 /* Process locked */
652 __HAL_LOCK(hcryp);
653
654 /* Get CRYP parameters */
655 pConf->DataType = hcryp->Init.DataType;
656 pConf->pKey = hcryp->Init.pKey;
657 pConf->Algorithm = hcryp->Init.Algorithm;
658 pConf->KeySize = hcryp->Init.KeySize ;
659 pConf->pInitVect = hcryp->Init.pInitVect;
660 pConf->Header = hcryp->Init.Header ;
661 pConf->HeaderSize = hcryp->Init.HeaderSize;
662 pConf->B0 = hcryp->Init.B0;
663 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
664
665 /* Process Unlocked */
666 __HAL_UNLOCK(hcryp);
667
668 /* Change the CRYP state */
669 hcryp->State = HAL_CRYP_STATE_READY;
670
671 /* Return function status */
672 return HAL_OK;
673 }
674 else
675 {
676 /* Process Unlocked */
677 __HAL_UNLOCK(hcryp);
678
679 /* Busy error code field */
680 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
681 return HAL_ERROR;
682 }
683 }
684 /**
685 * @brief Initializes the CRYP MSP.
686 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
687 * the configuration information for CRYP module
688 * @retval None
689 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)690 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
691 {
692 /* Prevent unused argument(s) compilation warning */
693 UNUSED(hcryp);
694
695 /* NOTE : This function Should not be modified, when the callback is needed,
696 the HAL_CRYP_MspInit could be implemented in the user file
697 */
698 }
699
700 /**
701 * @brief DeInitializes CRYP MSP.
702 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
703 * the configuration information for CRYP module
704 * @retval None
705 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)706 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
707 {
708 /* Prevent unused argument(s) compilation warning */
709 UNUSED(hcryp);
710
711 /* NOTE : This function Should not be modified, when the callback is needed,
712 the HAL_CRYP_MspDeInit could be implemented in the user file
713 */
714 }
715
716 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
717 /**
718 * @brief Register a User CRYP Callback
719 * To be used instead of the weak predefined callback
720 * @param hcryp cryp handle
721 * @param CallbackID ID of the callback to be registered
722 * This parameter can be one of the following values:
723 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
724 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
725 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
726 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
727 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
728 * @param pCallback pointer to the Callback function
729 * @retval status
730 */
HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID,pCRYP_CallbackTypeDef pCallback)731 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
732 pCRYP_CallbackTypeDef pCallback)
733 {
734 HAL_StatusTypeDef status = HAL_OK;
735
736 if (pCallback == NULL)
737 {
738 /* Update the error code */
739 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
740
741 return HAL_ERROR;
742 }
743 /* Process locked */
744 __HAL_LOCK(hcryp);
745
746 if (hcryp->State == HAL_CRYP_STATE_READY)
747 {
748 switch (CallbackID)
749 {
750 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
751 hcryp->InCpltCallback = pCallback;
752 break;
753
754 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
755 hcryp->OutCpltCallback = pCallback;
756 break;
757
758 case HAL_CRYP_ERROR_CB_ID :
759 hcryp->ErrorCallback = pCallback;
760 break;
761
762 case HAL_CRYP_MSPINIT_CB_ID :
763 hcryp->MspInitCallback = pCallback;
764 break;
765
766 case HAL_CRYP_MSPDEINIT_CB_ID :
767 hcryp->MspDeInitCallback = pCallback;
768 break;
769
770 default :
771 /* Update the error code */
772 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
773 /* Return error status */
774 status = HAL_ERROR;
775 break;
776 }
777 }
778 else if (hcryp->State == HAL_CRYP_STATE_RESET)
779 {
780 switch (CallbackID)
781 {
782 case HAL_CRYP_MSPINIT_CB_ID :
783 hcryp->MspInitCallback = pCallback;
784 break;
785
786 case HAL_CRYP_MSPDEINIT_CB_ID :
787 hcryp->MspDeInitCallback = pCallback;
788 break;
789
790 default :
791 /* Update the error code */
792 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
793 /* Return error status */
794 status = HAL_ERROR;
795 break;
796 }
797 }
798 else
799 {
800 /* Update the error code */
801 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
802 /* Return error status */
803 status = HAL_ERROR;
804 }
805
806 /* Release Lock */
807 __HAL_UNLOCK(hcryp);
808
809 return status;
810 }
811
812 /**
813 * @brief Unregister an CRYP Callback
814 * CRYP callback is redirected to the weak predefined callback
815 * @param hcryp cryp handle
816 * @param CallbackID ID of the callback to be unregistered
817 * This parameter can be one of the following values:
818 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
819 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
820 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
821 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
822 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
823 * @retval status
824 */
HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID)825 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
826 {
827 HAL_StatusTypeDef status = HAL_OK;
828
829 /* Process locked */
830 __HAL_LOCK(hcryp);
831
832 if (hcryp->State == HAL_CRYP_STATE_READY)
833 {
834 switch (CallbackID)
835 {
836 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
837 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
838 break;
839
840 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
841 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
842 break;
843
844 case HAL_CRYP_ERROR_CB_ID :
845 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
846 break;
847
848 case HAL_CRYP_MSPINIT_CB_ID :
849 hcryp->MspInitCallback = HAL_CRYP_MspInit;
850 break;
851
852 case HAL_CRYP_MSPDEINIT_CB_ID :
853 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
854 break;
855
856 default :
857 /* Update the error code */
858 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
859 /* Return error status */
860 status = HAL_ERROR;
861 break;
862 }
863 }
864 else if (hcryp->State == HAL_CRYP_STATE_RESET)
865 {
866 switch (CallbackID)
867 {
868 case HAL_CRYP_MSPINIT_CB_ID :
869 hcryp->MspInitCallback = HAL_CRYP_MspInit;
870 break;
871
872 case HAL_CRYP_MSPDEINIT_CB_ID :
873 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
874 break;
875
876 default :
877 /* Update the error code */
878 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
879 /* Return error status */
880 status = HAL_ERROR;
881 break;
882 }
883 }
884 else
885 {
886 /* Update the error code */
887 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
888 /* Return error status */
889 status = HAL_ERROR;
890 }
891
892 /* Release Lock */
893 __HAL_UNLOCK(hcryp);
894
895 return status;
896 }
897 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
898 /**
899 * @}
900 */
901
902 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
903 * @brief processing functions.
904 *
905 @verbatim
906 ==============================================================================
907 ##### Encrypt Decrypt functions #####
908 ==============================================================================
909 [..] This section provides API allowing to Encrypt/Decrypt Data following
910 Standard DES/TDES or AES, and Algorithm configured by the user:
911 (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
912 - Electronic Code Book(ECB)
913 - Cipher Block Chaining (CBC)
914 (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
915 - Electronic Code Book(ECB)
916 - Cipher Block Chaining (CBC)
917 - Counter mode (CTR)
918 - Cipher Block Chaining (CBC)
919 - Counter mode (CTR)
920 - Galois/counter mode (GCM)
921 - Counter with Cipher Block Chaining-Message(CCM)
922 [..] Three processing functions are available:
923 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
924 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
925 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
926
927 @endverbatim
928 * @{
929 */
930
931
932 /**
933 * @brief Encryption mode.
934 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
935 * the configuration information for CRYP module
936 * @param Input: Pointer to the input buffer (plaintext)
937 * @param Size: Length of the plaintext buffer in word.
938 * @param Output: Pointer to the output buffer(ciphertext)
939 * @param Timeout: Specify Timeout value
940 * @retval HAL status
941 */
HAL_CRYP_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)942 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
943 uint32_t Timeout)
944 {
945 uint32_t algo;
946 HAL_StatusTypeDef status;
947
948 if (hcryp->State == HAL_CRYP_STATE_READY)
949 {
950 /* Change state Busy */
951 hcryp->State = HAL_CRYP_STATE_BUSY;
952
953 /* Process locked */
954 __HAL_LOCK(hcryp);
955
956 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
957 hcryp->CrypInCount = 0U;
958 hcryp->CrypOutCount = 0U;
959 hcryp->pCrypInBuffPtr = Input;
960 hcryp->pCrypOutBuffPtr = Output;
961
962 /* Calculate Size parameter in Byte*/
963 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
964 {
965 hcryp->Size = Size * 4U;
966 }
967 else
968 {
969 hcryp->Size = Size;
970 }
971
972 #if defined (CRYP)
973 /* Set Encryption operating mode*/
974 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
975
976 /* algo get algorithm selected */
977 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
978
979 switch (algo)
980 {
981 case CRYP_DES_ECB:
982 case CRYP_DES_CBC:
983 case CRYP_TDES_ECB:
984 case CRYP_TDES_CBC:
985
986 /*Set Key */
987 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
988 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
989 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
990 {
991 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
992 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
993 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
994 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
995 }
996
997 /*Set Initialization Vector (IV)*/
998 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
999 {
1000 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1001 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1002 }
1003
1004 /* Flush FIFO */
1005 HAL_CRYP_FIFO_FLUSH(hcryp);
1006
1007 /* Set the phase */
1008 hcryp->Phase = CRYP_PHASE_PROCESS;
1009
1010 /* Statrt DES/TDES encryption process */
1011 status = CRYP_TDES_Process(hcryp, Timeout);
1012 break;
1013
1014 case CRYP_AES_ECB:
1015 case CRYP_AES_CBC:
1016 case CRYP_AES_CTR:
1017
1018 /* AES encryption */
1019 status = CRYP_AES_Encrypt(hcryp, Timeout);
1020 break;
1021 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1022 case CRYP_AES_GCM:
1023
1024 /* AES GCM encryption */
1025 status = CRYP_AESGCM_Process(hcryp, Timeout);
1026
1027 break;
1028
1029 case CRYP_AES_CCM:
1030
1031 /* AES CCM encryption */
1032 status = CRYP_AESCCM_Process(hcryp, Timeout);
1033 break;
1034 #endif /* GCM CCM defined*/
1035 default:
1036 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1037 /* Change the CRYP peripheral state */
1038 hcryp->State = HAL_CRYP_STATE_READY;
1039 /* Process unlocked */
1040 __HAL_UNLOCK(hcryp);
1041 return HAL_ERROR;
1042 }
1043
1044 #else /*AES*/
1045
1046 /* Set the operating mode*/
1047 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1048
1049 /* algo get algorithm selected */
1050 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1051
1052 switch (algo)
1053 {
1054
1055 case CRYP_AES_ECB:
1056 case CRYP_AES_CBC:
1057 case CRYP_AES_CTR:
1058
1059 /* AES encryption */
1060 status = CRYP_AES_Encrypt(hcryp, Timeout);
1061 break;
1062
1063 case CRYP_AES_GCM_GMAC:
1064
1065 /* AES GCM encryption */
1066 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1067 break;
1068
1069 case CRYP_AES_CCM:
1070
1071 /* AES CCM encryption */
1072 status = CRYP_AESCCM_Process(hcryp, Timeout);
1073 break;
1074
1075 default:
1076 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1077 /* Change the CRYP peripheral state */
1078 hcryp->State = HAL_CRYP_STATE_READY;
1079 /* Process unlocked */
1080 __HAL_UNLOCK(hcryp);
1081 return HAL_ERROR;
1082 }
1083 #endif /*end AES or CRYP */
1084
1085 if (status == HAL_OK)
1086 {
1087 /* Change the CRYP peripheral state */
1088 hcryp->State = HAL_CRYP_STATE_READY;
1089
1090 /* Process unlocked */
1091 __HAL_UNLOCK(hcryp);
1092 }
1093 }
1094 else
1095 {
1096 /* Busy error code field */
1097 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1098 return HAL_ERROR;
1099 }
1100
1101 /* Return function status */
1102 return HAL_OK;
1103 }
1104
1105 /**
1106 * @brief Decryption mode.
1107 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1108 * the configuration information for CRYP module
1109 * @param Input: Pointer to the input buffer (ciphertext )
1110 * @param Size: Length of the plaintext buffer in word.
1111 * @param Output: Pointer to the output buffer(plaintext)
1112 * @param Timeout: Specify Timeout value
1113 * @retval HAL status
1114 */
HAL_CRYP_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1115 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1116 uint32_t Timeout)
1117 {
1118 HAL_StatusTypeDef status;
1119 uint32_t algo;
1120
1121 if (hcryp->State == HAL_CRYP_STATE_READY)
1122 {
1123 /* Change state Busy */
1124 hcryp->State = HAL_CRYP_STATE_BUSY;
1125
1126 /* Process locked */
1127 __HAL_LOCK(hcryp);
1128
1129 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1130 hcryp->CrypInCount = 0U;
1131 hcryp->CrypOutCount = 0U;
1132 hcryp->pCrypInBuffPtr = Input;
1133 hcryp->pCrypOutBuffPtr = Output;
1134
1135 /* Calculate Size parameter in Byte*/
1136 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1137 {
1138 hcryp->Size = Size * 4U;
1139 }
1140 else
1141 {
1142 hcryp->Size = Size;
1143 }
1144
1145 #if defined (CRYP)
1146
1147 /* Set Decryption operating mode*/
1148 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1149
1150 /* algo get algorithm selected */
1151 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1152
1153 switch (algo)
1154 {
1155 case CRYP_DES_ECB:
1156 case CRYP_DES_CBC:
1157 case CRYP_TDES_ECB:
1158 case CRYP_TDES_CBC:
1159
1160 /*Set Key */
1161 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1162 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1163 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1164 {
1165 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1166 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1167 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1168 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1169 }
1170
1171 /*Set Initialization Vector (IV)*/
1172 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1173 {
1174 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1175 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1176 }
1177
1178 /* Flush FIFO */
1179 HAL_CRYP_FIFO_FLUSH(hcryp);
1180
1181 /* Set the phase */
1182 hcryp->Phase = CRYP_PHASE_PROCESS;
1183
1184 /* Start DES/TDES decryption process */
1185 status = CRYP_TDES_Process(hcryp, Timeout);
1186
1187 break;
1188
1189 case CRYP_AES_ECB:
1190 case CRYP_AES_CBC:
1191 case CRYP_AES_CTR:
1192
1193 /* AES decryption */
1194 status = CRYP_AES_Decrypt(hcryp, Timeout);
1195 break;
1196 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1197 case CRYP_AES_GCM:
1198
1199 /* AES GCM decryption */
1200 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1201 break;
1202
1203 case CRYP_AES_CCM:
1204
1205 /* AES CCM decryption */
1206 status = CRYP_AESCCM_Process(hcryp, Timeout);
1207 break;
1208 #endif /* GCM CCM defined*/
1209 default:
1210 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1211 /* Change the CRYP peripheral state */
1212 hcryp->State = HAL_CRYP_STATE_READY;
1213 /* Process unlocked */
1214 __HAL_UNLOCK(hcryp);
1215 return HAL_ERROR;
1216 }
1217
1218 #else /*AES*/
1219
1220 /* Set Decryption operating mode*/
1221 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1222
1223 /* algo get algorithm selected */
1224 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1225
1226 switch (algo)
1227 {
1228
1229 case CRYP_AES_ECB:
1230 case CRYP_AES_CBC:
1231 case CRYP_AES_CTR:
1232
1233 /* AES decryption */
1234 status = CRYP_AES_Decrypt(hcryp, Timeout);
1235 break;
1236
1237 case CRYP_AES_GCM_GMAC:
1238
1239 /* AES GCM decryption */
1240 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1241 break;
1242
1243 case CRYP_AES_CCM:
1244
1245 /* AES CCM decryption */
1246 status = CRYP_AESCCM_Process(hcryp, Timeout);
1247 break;
1248
1249 default:
1250 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1251 /* Change the CRYP peripheral state */
1252 hcryp->State = HAL_CRYP_STATE_READY;
1253 /* Process unlocked */
1254 __HAL_UNLOCK(hcryp);
1255 return HAL_ERROR;
1256 }
1257 #endif /* End AES or CRYP */
1258
1259 if (status == HAL_OK)
1260 {
1261 /* Change the CRYP peripheral state */
1262 hcryp->State = HAL_CRYP_STATE_READY;
1263
1264 /* Process unlocked */
1265 __HAL_UNLOCK(hcryp);
1266 }
1267 }
1268 else
1269 {
1270 /* Busy error code field */
1271 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1272 return HAL_ERROR;
1273 }
1274
1275 /* Return function status */
1276 return HAL_OK;
1277 }
1278
1279 /**
1280 * @brief Encryption in interrupt mode.
1281 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1282 * the configuration information for CRYP module
1283 * @param Input: Pointer to the input buffer (plaintext)
1284 * @param Size: Length of the plaintext buffer in word
1285 * @param Output: Pointer to the output buffer(ciphertext)
1286 * @retval HAL status
1287 */
HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1288 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1289 {
1290 uint32_t algo;
1291 HAL_StatusTypeDef status = HAL_OK;
1292
1293 if (hcryp->State == HAL_CRYP_STATE_READY)
1294 {
1295 /* Change state Busy */
1296 hcryp->State = HAL_CRYP_STATE_BUSY;
1297
1298 /* Process locked */
1299 __HAL_LOCK(hcryp);
1300
1301 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1302 hcryp->CrypInCount = 0U;
1303 hcryp->CrypOutCount = 0U;
1304 hcryp->pCrypInBuffPtr = Input;
1305 hcryp->pCrypOutBuffPtr = Output;
1306
1307 /* Calculate Size parameter in Byte*/
1308 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1309 {
1310 hcryp->Size = Size * 4U;
1311 }
1312 else
1313 {
1314 hcryp->Size = Size;
1315 }
1316
1317 #if defined (CRYP)
1318
1319 /* Set encryption operating mode*/
1320 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1321
1322 /* algo get algorithm selected */
1323 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1324
1325 switch (algo)
1326 {
1327 case CRYP_DES_ECB:
1328 case CRYP_DES_CBC:
1329 case CRYP_TDES_ECB:
1330 case CRYP_TDES_CBC:
1331
1332 /*Set Key */
1333 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1334 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1335 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1336 {
1337 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1338 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1339 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1340 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1341 }
1342 /* Set the Initialization Vector*/
1343 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1344 {
1345 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1346 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1347 }
1348
1349 /* Flush FIFO */
1350 HAL_CRYP_FIFO_FLUSH(hcryp);
1351
1352 /* Set the phase */
1353 hcryp->Phase = CRYP_PHASE_PROCESS;
1354
1355 /* Enable interrupts */
1356 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1357
1358 /* Enable CRYP to start DES/TDES process*/
1359 __HAL_CRYP_ENABLE(hcryp);
1360 break;
1361
1362 case CRYP_AES_ECB:
1363 case CRYP_AES_CBC:
1364 case CRYP_AES_CTR:
1365
1366 status = CRYP_AES_Encrypt_IT(hcryp);
1367 break;
1368 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1369 case CRYP_AES_GCM:
1370
1371 status = CRYP_AESGCM_Process_IT(hcryp) ;
1372 break;
1373
1374 case CRYP_AES_CCM:
1375
1376 status = CRYP_AESCCM_Process_IT(hcryp);
1377 break;
1378 #endif /* GCM CCM defined*/
1379 default:
1380 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1381 /* Change the CRYP peripheral state */
1382 hcryp->State = HAL_CRYP_STATE_READY;
1383 /* Process unlocked */
1384 __HAL_UNLOCK(hcryp);
1385 status = HAL_ERROR;
1386 break;
1387 }
1388
1389 #else /* AES */
1390
1391 /* Set encryption operating mode*/
1392 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1393
1394 /* algo get algorithm selected */
1395 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1396
1397 switch (algo)
1398 {
1399 case CRYP_AES_ECB:
1400 case CRYP_AES_CBC:
1401 case CRYP_AES_CTR:
1402
1403 /* AES encryption */
1404 status = CRYP_AES_Encrypt_IT(hcryp);
1405 break;
1406
1407 case CRYP_AES_GCM_GMAC:
1408
1409 /* AES GCM encryption */
1410 status = CRYP_AESGCM_Process_IT(hcryp) ;
1411 break;
1412
1413 case CRYP_AES_CCM:
1414
1415 /* AES CCM encryption */
1416 status = CRYP_AESCCM_Process_IT(hcryp);
1417 break;
1418
1419 default:
1420 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1421 /* Change the CRYP peripheral state */
1422 hcryp->State = HAL_CRYP_STATE_READY;
1423 /* Process unlocked */
1424 __HAL_UNLOCK(hcryp);
1425 status = HAL_ERROR;
1426 break;
1427 }
1428 #endif /*end AES or CRYP*/
1429
1430 }
1431 else
1432 {
1433 /* Busy error code field */
1434 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1435 status = HAL_ERROR;
1436 }
1437
1438 /* Return function status */
1439 return status;
1440 }
1441
1442 /**
1443 * @brief Decryption in itnterrupt mode.
1444 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1445 * the configuration information for CRYP module
1446 * @param Input: Pointer to the input buffer (ciphertext )
1447 * @param Size: Length of the plaintext buffer in word.
1448 * @param Output: Pointer to the output buffer(plaintext)
1449 * @retval HAL status
1450 */
HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1451 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1452 {
1453 uint32_t algo;
1454 HAL_StatusTypeDef status = HAL_OK;
1455
1456 if (hcryp->State == HAL_CRYP_STATE_READY)
1457 {
1458 /* Change state Busy */
1459 hcryp->State = HAL_CRYP_STATE_BUSY;
1460
1461 /* Process locked */
1462 __HAL_LOCK(hcryp);
1463
1464 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1465 hcryp->CrypInCount = 0U;
1466 hcryp->CrypOutCount = 0U;
1467 hcryp->pCrypInBuffPtr = Input;
1468 hcryp->pCrypOutBuffPtr = Output;
1469
1470 /* Calculate Size parameter in Byte*/
1471 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1472 {
1473 hcryp->Size = Size * 4U;
1474 }
1475 else
1476 {
1477 hcryp->Size = Size;
1478 }
1479
1480 #if defined (CRYP)
1481
1482 /* Set decryption operating mode*/
1483 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1484
1485 /* algo get algorithm selected */
1486 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1487
1488 switch (algo)
1489 {
1490 case CRYP_DES_ECB:
1491 case CRYP_DES_CBC:
1492 case CRYP_TDES_ECB:
1493 case CRYP_TDES_CBC:
1494
1495 /*Set Key */
1496 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1497 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1498 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1499 {
1500 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1501 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1502 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1503 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1504 }
1505
1506 /* Set the Initialization Vector*/
1507 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1508 {
1509 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1510 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1511 }
1512 /* Flush FIFO */
1513 HAL_CRYP_FIFO_FLUSH(hcryp);
1514
1515 /* Set the phase */
1516 hcryp->Phase = CRYP_PHASE_PROCESS;
1517
1518 /* Enable interrupts */
1519 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1520
1521 /* Enable CRYP and start DES/TDES process*/
1522 __HAL_CRYP_ENABLE(hcryp);
1523
1524 break;
1525
1526 case CRYP_AES_ECB:
1527 case CRYP_AES_CBC:
1528 case CRYP_AES_CTR:
1529
1530 /* AES decryption */
1531 status = CRYP_AES_Decrypt_IT(hcryp);
1532 break;
1533 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1534 case CRYP_AES_GCM:
1535
1536 /* AES GCM decryption */
1537 status = CRYP_AESGCM_Process_IT(hcryp) ;
1538 break;
1539
1540 case CRYP_AES_CCM:
1541
1542 /* AES CCMdecryption */
1543 status = CRYP_AESCCM_Process_IT(hcryp);
1544 break;
1545 #endif /* GCM CCM defined*/
1546 default:
1547 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1548 /* Change the CRYP peripheral state */
1549 hcryp->State = HAL_CRYP_STATE_READY;
1550 /* Process unlocked */
1551 __HAL_UNLOCK(hcryp);
1552 status = HAL_ERROR;
1553 break;
1554 }
1555
1556 #else /*AES*/
1557
1558 /* Set decryption operating mode*/
1559 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1560
1561 /* algo get algorithm selected */
1562 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1563
1564 switch (algo)
1565 {
1566 case CRYP_AES_ECB:
1567 case CRYP_AES_CBC:
1568 case CRYP_AES_CTR:
1569
1570 /* AES decryption */
1571 status = CRYP_AES_Decrypt_IT(hcryp);
1572 break;
1573
1574 case CRYP_AES_GCM_GMAC:
1575
1576 /* AES GCM decryption */
1577 status = CRYP_AESGCM_Process_IT(hcryp) ;
1578 break;
1579
1580 case CRYP_AES_CCM:
1581
1582 /* AES CCM decryption */
1583 status = CRYP_AESCCM_Process_IT(hcryp);
1584 break;
1585
1586 default:
1587 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1588 /* Change the CRYP peripheral state */
1589 hcryp->State = HAL_CRYP_STATE_READY;
1590 /* Process unlocked */
1591 __HAL_UNLOCK(hcryp);
1592 status = HAL_ERROR;
1593 break;
1594 }
1595 #endif /* End AES or CRYP */
1596
1597 }
1598 else
1599 {
1600 /* Busy error code field */
1601 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1602 status = HAL_ERROR;
1603 }
1604
1605 /* Return function status */
1606 return status;
1607 }
1608
1609 /**
1610 * @brief Encryption in DMA mode.
1611 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1612 * the configuration information for CRYP module
1613 * @param Input: Pointer to the input buffer (plaintext)
1614 * @param Size: Length of the plaintext buffer in word.
1615 * @param Output: Pointer to the output buffer(ciphertext)
1616 * @retval HAL status
1617 */
HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1618 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1619 {
1620 uint32_t algo;
1621 HAL_StatusTypeDef status = HAL_OK;
1622 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1623
1624 if (hcryp->State == HAL_CRYP_STATE_READY)
1625 {
1626 /* Change state Busy */
1627 hcryp->State = HAL_CRYP_STATE_BUSY;
1628
1629 /* Process locked */
1630 __HAL_LOCK(hcryp);
1631
1632 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1633 hcryp->CrypInCount = 0U;
1634 hcryp->CrypOutCount = 0U;
1635 hcryp->pCrypInBuffPtr = Input;
1636 hcryp->pCrypOutBuffPtr = Output;
1637
1638 /* Calculate Size parameter in Byte*/
1639 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1640 {
1641 hcryp->Size = Size * 4U;
1642 }
1643 else
1644 {
1645 hcryp->Size = Size;
1646 }
1647
1648 #if defined (CRYP)
1649
1650 /* Set encryption operating mode*/
1651 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1652
1653 /* algo get algorithm selected */
1654 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1655
1656 switch (algo)
1657 {
1658 case CRYP_DES_ECB:
1659 case CRYP_DES_CBC:
1660 case CRYP_TDES_ECB:
1661 case CRYP_TDES_CBC:
1662
1663 /*Set Key */
1664 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1665 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1666 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1667 {
1668 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1669 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1670 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1671 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1672 }
1673
1674 /* Set the Initialization Vector*/
1675 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1676 {
1677 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1678 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1679 }
1680
1681 /* Flush FIFO */
1682 HAL_CRYP_FIFO_FLUSH(hcryp);
1683
1684 /* Set the phase */
1685 hcryp->Phase = CRYP_PHASE_PROCESS;
1686
1687 /* Start DMA process transfer for DES/TDES */
1688 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1689 (uint32_t)(hcryp->pCrypOutBuffPtr));
1690 break;
1691
1692 case CRYP_AES_ECB:
1693 case CRYP_AES_CBC:
1694 case CRYP_AES_CTR:
1695
1696 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1697 {
1698 if (hcryp->KeyIVConfig == 1U)
1699 {
1700 /* If the Key and IV configuration has to be done only once
1701 and if it has already been done, skip it */
1702 DoKeyIVConfig = 0U;
1703 }
1704 else
1705 {
1706 /* If the Key and IV configuration has to be done only once
1707 and if it has not been done already, do it and set KeyIVConfig
1708 to keep track it won't have to be done again next time */
1709 hcryp->KeyIVConfig = 1U;
1710 }
1711 }
1712
1713 if (DoKeyIVConfig == 1U)
1714 {
1715 /* Set the Key*/
1716 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1717
1718 /* Set the Initialization Vector*/
1719 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1720 {
1721 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1722 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
1723 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
1724 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
1725 }
1726 } /* if (DoKeyIVConfig == 1U) */
1727
1728 /* Set the phase */
1729 hcryp->Phase = CRYP_PHASE_PROCESS;
1730
1731 /* Start DMA process transfer for AES */
1732 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1733 (uint32_t)(hcryp->pCrypOutBuffPtr));
1734 break;
1735 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1736 case CRYP_AES_GCM:
1737 /* AES GCM encryption */
1738 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1739 break;
1740
1741 case CRYP_AES_CCM:
1742 /* AES CCM encryption */
1743 status = CRYP_AESCCM_Process_DMA(hcryp);
1744 break;
1745 #endif /* GCM CCM defined*/
1746 default:
1747 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1748 /* Change the CRYP peripheral state */
1749 hcryp->State = HAL_CRYP_STATE_READY;
1750 /* Process unlocked */
1751 __HAL_UNLOCK(hcryp);
1752 status = HAL_ERROR;
1753 break;
1754 }
1755
1756 #else /*AES*/
1757 /* Set encryption operating mode*/
1758 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1759
1760 /* algo get algorithm selected */
1761 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1762
1763 switch (algo)
1764 {
1765
1766 case CRYP_AES_ECB:
1767 case CRYP_AES_CBC:
1768 case CRYP_AES_CTR:
1769
1770 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1771 {
1772 if (hcryp->KeyIVConfig == 1U)
1773 {
1774 /* If the Key and IV configuration has to be done only once
1775 and if it has already been done, skip it */
1776 DoKeyIVConfig = 0U;
1777 }
1778 else
1779 {
1780 /* If the Key and IV configuration has to be done only once
1781 and if it has not been done already, do it and set KeyIVConfig
1782 to keep track it won't have to be done again next time */
1783 hcryp->KeyIVConfig = 1U;
1784 }
1785 }
1786
1787 if (DoKeyIVConfig == 1U)
1788 {
1789 /* Set the Key*/
1790 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1791
1792 /* Set the Initialization Vector*/
1793 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1794 {
1795 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
1796 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1797 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
1798 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
1799 }
1800 } /* if (DoKeyIVConfig == 1U) */
1801 /* Set the phase */
1802 hcryp->Phase = CRYP_PHASE_PROCESS;
1803
1804 /* Start DMA process transfer for AES */
1805 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1806 break;
1807
1808 case CRYP_AES_GCM_GMAC:
1809 /* AES GCM encryption */
1810 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1811 break;
1812
1813 case CRYP_AES_CCM:
1814 /* AES CCM encryption */
1815 status = CRYP_AESCCM_Process_DMA(hcryp);
1816 break;
1817
1818 default:
1819 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1820 /* Change the CRYP peripheral state */
1821 hcryp->State = HAL_CRYP_STATE_READY;
1822 /* Process unlocked */
1823 __HAL_UNLOCK(hcryp);
1824 status = HAL_ERROR;
1825 break;
1826 }
1827 #endif /* End AES or CRYP */
1828
1829 }
1830 else
1831 {
1832 /* Busy error code field */
1833 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1834 status = HAL_ERROR;
1835 }
1836
1837 /* Return function status */
1838 return status;
1839 }
1840
1841 /**
1842 * @brief Decryption in DMA mode.
1843 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1844 * the configuration information for CRYP module
1845 * @param Input: Pointer to the input buffer (ciphertext )
1846 * @param Size: Length of the plaintext buffer in word
1847 * @param Output: Pointer to the output buffer(plaintext)
1848 * @retval HAL status
1849 */
HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1850 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1851 {
1852 uint32_t algo;
1853 HAL_StatusTypeDef status = HAL_OK;
1854
1855 if (hcryp->State == HAL_CRYP_STATE_READY)
1856 {
1857
1858 /* Change state Busy */
1859 hcryp->State = HAL_CRYP_STATE_BUSY;
1860
1861 /* Process locked */
1862 __HAL_LOCK(hcryp);
1863
1864 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1865 hcryp->CrypInCount = 0U;
1866 hcryp->CrypOutCount = 0U;
1867 hcryp->pCrypInBuffPtr = Input;
1868 hcryp->pCrypOutBuffPtr = Output;
1869
1870 /* Calculate Size parameter in Byte*/
1871 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1872 {
1873 hcryp->Size = Size * 4U;
1874 }
1875 else
1876 {
1877 hcryp->Size = Size;
1878 }
1879
1880 #if defined (CRYP)
1881
1882 /* Set decryption operating mode*/
1883 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1884
1885 /* algo get algorithm selected */
1886 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1887
1888 switch (algo)
1889 {
1890 case CRYP_DES_ECB:
1891 case CRYP_DES_CBC:
1892 case CRYP_TDES_ECB:
1893 case CRYP_TDES_CBC:
1894
1895 /*Set Key */
1896 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1897 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1898 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1899 {
1900 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1901 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1902 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1903 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1904 }
1905
1906 /* Set the Initialization Vector*/
1907 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1908 {
1909 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1910 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1911 }
1912
1913 /* Flush FIFO */
1914 HAL_CRYP_FIFO_FLUSH(hcryp);
1915
1916 /* Set the phase */
1917 hcryp->Phase = CRYP_PHASE_PROCESS;
1918
1919 /* Start DMA process transfer for DES/TDES */
1920 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1921 (uint32_t)(hcryp->pCrypOutBuffPtr));
1922 break;
1923
1924 case CRYP_AES_ECB:
1925 case CRYP_AES_CBC:
1926 case CRYP_AES_CTR:
1927
1928 /* AES decryption */
1929 status = CRYP_AES_Decrypt_DMA(hcryp);
1930 break;
1931 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1932 case CRYP_AES_GCM:
1933 /* AES GCM decryption */
1934 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1935 break;
1936
1937 case CRYP_AES_CCM:
1938 /* AES CCM decryption */
1939 status = CRYP_AESCCM_Process_DMA(hcryp);
1940 break;
1941 #endif /* GCM CCM defined*/
1942 default:
1943 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1944 /* Change the CRYP peripheral state */
1945 hcryp->State = HAL_CRYP_STATE_READY;
1946 /* Process unlocked */
1947 __HAL_UNLOCK(hcryp);
1948 status = HAL_ERROR;
1949 break;
1950 }
1951
1952 #else /*AES*/
1953
1954 /* Set decryption operating mode*/
1955 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1956
1957 /* algo get algorithm selected */
1958 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1959
1960 switch (algo)
1961 {
1962
1963 case CRYP_AES_ECB:
1964 case CRYP_AES_CBC:
1965 case CRYP_AES_CTR:
1966
1967 /* AES decryption */
1968 status = CRYP_AES_Decrypt_DMA(hcryp);
1969 break;
1970
1971 case CRYP_AES_GCM_GMAC:
1972 /* AES GCM decryption */
1973 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1974 break;
1975
1976 case CRYP_AES_CCM:
1977 /* AES CCM decryption */
1978 status = CRYP_AESCCM_Process_DMA(hcryp);
1979 break;
1980
1981 default:
1982 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1983 /* Change the CRYP peripheral state */
1984 hcryp->State = HAL_CRYP_STATE_READY;
1985 /* Process unlocked */
1986 __HAL_UNLOCK(hcryp);
1987 status = HAL_ERROR;
1988 break;
1989 }
1990 #endif /* End AES or CRYP */
1991 }
1992 else
1993 {
1994 /* Busy error code field */
1995 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1996 status = HAL_ERROR;
1997 }
1998
1999 /* Return function status */
2000 return status;
2001 }
2002
2003 /**
2004 * @}
2005 */
2006
2007 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
2008 * @brief CRYP IRQ handler.
2009 *
2010 @verbatim
2011 ==============================================================================
2012 ##### CRYP IRQ handler management #####
2013 ==============================================================================
2014 [..] This section provides CRYP IRQ handler and callback functions.
2015 (+) HAL_CRYP_IRQHandler CRYP interrupt request
2016 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
2017 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
2018 (+) HAL_CRYP_ErrorCallback CRYP error callback
2019 (+) HAL_CRYP_GetState return the CRYP state
2020 (+) HAL_CRYP_GetError return the CRYP error code
2021 @endverbatim
2022 * @{
2023 */
2024
2025 /**
2026 * @brief This function handles cryptographic interrupt request.
2027 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2028 * the configuration information for CRYP module
2029 * @retval None
2030 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)2031 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2032 {
2033
2034 #if defined (CRYP)
2035
2036 uint32_t itstatus = hcryp->Instance->MISR;
2037
2038 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2039 {
2040 if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
2041 || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
2042 {
2043 CRYP_TDES_IT(hcryp); /* DES or TDES*/
2044 }
2045 else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2046 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2047 {
2048 CRYP_AES_IT(hcryp); /*AES*/
2049 }
2050 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
2051 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
2052 {
2053 /* if header phase */
2054 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2055 {
2056 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2057 }
2058 else /* if payload phase */
2059 {
2060 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2061 }
2062 }
2063 #endif /* GCM CCM defined*/
2064 else
2065 {
2066 /* Nothing to do */
2067 }
2068 }
2069
2070 #else /*AES*/
2071 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
2072 {
2073 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2074 {
2075
2076 /* Clear computation complete flag */
2077 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2078
2079 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
2080 {
2081
2082 /* if header phase */
2083 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2084 {
2085 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2086 }
2087 else /* if payload phase */
2088 {
2089 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2090 }
2091 }
2092 else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
2093 {
2094 /* if header phase */
2095 if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
2096 {
2097 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2098 }
2099 else /* if payload phase */
2100 {
2101 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2102 }
2103 }
2104 else /* AES Algorithm ECB,CBC or CTR*/
2105 {
2106 CRYP_AES_IT(hcryp);
2107 }
2108 }
2109 }
2110 /* Check if error occurred */
2111 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
2112 {
2113 /* If write Error occurred */
2114 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
2115 {
2116 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2117 }
2118 /* If read Error occurred */
2119 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
2120 {
2121 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2122 }
2123 }
2124 #endif /* End AES or CRYP */
2125 }
2126
2127 /**
2128 * @brief Return the CRYP error code.
2129 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2130 * the configuration information for the CRYP IP
2131 * @retval CRYP error code
2132 */
HAL_CRYP_GetError(CRYP_HandleTypeDef * hcryp)2133 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2134 {
2135 return hcryp->ErrorCode;
2136 }
2137
2138 /**
2139 * @brief Returns the CRYP state.
2140 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2141 * the configuration information for CRYP module.
2142 * @retval HAL state
2143 */
HAL_CRYP_GetState(CRYP_HandleTypeDef * hcryp)2144 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2145 {
2146 return hcryp->State;
2147 }
2148
2149 /**
2150 * @brief Input FIFO transfer completed callback.
2151 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2152 * the configuration information for CRYP module.
2153 * @retval None
2154 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)2155 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2156 {
2157 /* Prevent unused argument(s) compilation warning */
2158 UNUSED(hcryp);
2159
2160 /* NOTE : This function Should not be modified, when the callback is needed,
2161 the HAL_CRYP_InCpltCallback could be implemented in the user file
2162 */
2163 }
2164
2165 /**
2166 * @brief Output FIFO transfer completed callback.
2167 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2168 * the configuration information for CRYP module.
2169 * @retval None
2170 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)2171 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2172 {
2173 /* Prevent unused argument(s) compilation warning */
2174 UNUSED(hcryp);
2175
2176 /* NOTE : This function Should not be modified, when the callback is needed,
2177 the HAL_CRYP_OutCpltCallback could be implemented in the user file
2178 */
2179 }
2180
2181 /**
2182 * @brief CRYP error callback.
2183 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2184 * the configuration information for CRYP module.
2185 * @retval None
2186 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)2187 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2188 {
2189 /* Prevent unused argument(s) compilation warning */
2190 UNUSED(hcryp);
2191
2192 /* NOTE : This function Should not be modified, when the callback is needed,
2193 the HAL_CRYP_ErrorCallback could be implemented in the user file
2194 */
2195 }
2196 /**
2197 * @}
2198 */
2199
2200 /* Private functions ---------------------------------------------------------*/
2201 /** @addtogroup CRYP_Private_Functions
2202 * @{
2203 */
2204
2205 #if defined (CRYP)
2206
2207 /**
2208 * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
2209 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2210 * the configuration information for CRYP module
2211 * @param Timeout: specify Timeout value
2212 * @retval HAL status
2213 */
CRYP_TDES_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2214 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2215 {
2216 uint32_t temp[2]; /* Temporary CrypOutBuff */
2217 uint16_t incount; /* Temporary CrypInCount Value */
2218 uint16_t outcount; /* Temporary CrypOutCount Value */
2219 uint32_t i;
2220
2221 /* Enable CRYP */
2222 __HAL_CRYP_ENABLE(hcryp);
2223 /*Temporary CrypOutCount Value*/
2224 outcount = hcryp->CrypOutCount;
2225
2226 /*Start processing*/
2227 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2228 {
2229 /* Temporary CrypInCount Value */
2230 incount = hcryp->CrypInCount;
2231 /* Write plain data and get cipher data */
2232 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
2233 {
2234 /* Write the input block in the IN FIFO */
2235 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2236 hcryp->CrypInCount++;
2237 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2238 hcryp->CrypInCount++;
2239 }
2240
2241 /* Wait for OFNE flag to be raised */
2242 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2243 {
2244 /* Disable the CRYP peripheral clock */
2245 __HAL_CRYP_DISABLE(hcryp);
2246
2247 /* Change state & errorCode*/
2248 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2249 hcryp->State = HAL_CRYP_STATE_READY;
2250
2251 /* Process unlocked */
2252 __HAL_UNLOCK(hcryp);
2253 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2254 /*Call registered error callback*/
2255 hcryp->ErrorCallback(hcryp);
2256 #else
2257 /*Call legacy weak error callback*/
2258 HAL_CRYP_ErrorCallback(hcryp);
2259 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2260 }
2261
2262 /*Temporary CrypOutCount Value*/
2263 outcount = hcryp->CrypOutCount;
2264
2265 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
2266 {
2267 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2268 for (i = 0U; i < 2U; i++)
2269 {
2270 temp[i] = hcryp->Instance->DOUT;
2271 }
2272 i = 0U;
2273 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2274 {
2275 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2276 hcryp->CrypOutCount++;
2277 i++;
2278 }
2279 }
2280 /*Temporary CrypOutCount Value*/
2281 outcount = hcryp->CrypOutCount;
2282 }
2283 /* Disable CRYP */
2284 __HAL_CRYP_DISABLE(hcryp);
2285 /* Change the CRYP state */
2286 hcryp->State = HAL_CRYP_STATE_READY;
2287
2288 /* Return function status */
2289 return HAL_OK;
2290 }
2291
2292 /**
2293 * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
2294 * @note The function is called under interruption only, once
2295 * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
2296 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2297 * the configuration information for CRYP module.
2298 * @retval none
2299 */
CRYP_TDES_IT(CRYP_HandleTypeDef * hcryp)2300 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2301 {
2302 uint32_t temp[2]; /* Temporary CrypOutBuff */
2303 uint32_t i;
2304
2305 if (hcryp->State == HAL_CRYP_STATE_BUSY)
2306 {
2307 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
2308 {
2309 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
2310 {
2311 /* Write input block in the IN FIFO */
2312 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2313 hcryp->CrypInCount++;
2314 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2315 hcryp->CrypInCount++;
2316
2317 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
2318 {
2319 /* Disable interruption */
2320 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2321 /* Call the input data transfer complete callback */
2322 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2323 /*Call registered Input complete callback*/
2324 hcryp->InCpltCallback(hcryp);
2325 #else
2326 /*Call legacy weak Input complete callback*/
2327 HAL_CRYP_InCpltCallback(hcryp);
2328 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2329 }
2330 }
2331 }
2332 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
2333 {
2334 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
2335 {
2336 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2337 for (i = 0U; i < 2U; i++)
2338 {
2339 temp[i] = hcryp->Instance->DOUT;
2340 }
2341 i = 0U;
2342 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2343 {
2344 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2345 hcryp->CrypOutCount++;
2346 i++;
2347 }
2348 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
2349 {
2350 /* Disable interruption */
2351 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2352
2353 /* Disable CRYP */
2354 __HAL_CRYP_DISABLE(hcryp);
2355
2356 /* Process unlocked */
2357 __HAL_UNLOCK(hcryp);
2358
2359 /* Change the CRYP state */
2360 hcryp->State = HAL_CRYP_STATE_READY;
2361 /* Call output transfer complete callback */
2362 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2363 /*Call registered Output complete callback*/
2364 hcryp->OutCpltCallback(hcryp);
2365 #else
2366 /*Call legacy weak Output complete callback*/
2367 HAL_CRYP_OutCpltCallback(hcryp);
2368 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2369 }
2370 }
2371 }
2372 }
2373 else
2374 {
2375 /* Process unlocked */
2376 __HAL_UNLOCK(hcryp);
2377 /* Busy error code field */
2378 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2379 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2380 /*Call registered error callback*/
2381 hcryp->ErrorCallback(hcryp);
2382 #else
2383 /*Call legacy weak error callback*/
2384 HAL_CRYP_ErrorCallback(hcryp);
2385 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2386 }
2387 }
2388
2389 #endif /* CRYP */
2390
2391 /**
2392 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2393 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2394 * @param Timeout: specify Timeout value
2395 * @retval HAL status
2396 */
CRYP_AES_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2397 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2398 {
2399 uint16_t outcount; /* Temporary CrypOutCount Value */
2400 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2401
2402 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2403 {
2404 if (hcryp->KeyIVConfig == 1U)
2405 {
2406 /* If the Key and IV configuration has to be done only once
2407 and if it has already been done, skip it */
2408 DoKeyIVConfig = 0U;
2409 }
2410 else
2411 {
2412 /* If the Key and IV configuration has to be done only once
2413 and if it has not been done already, do it and set KeyIVConfig
2414 to keep track it won't have to be done again next time */
2415 hcryp->KeyIVConfig = 1U;
2416 }
2417 }
2418
2419 if (DoKeyIVConfig == 1U)
2420 {
2421
2422 /* Set the Key*/
2423 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2424
2425 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2426 {
2427 /* Set the Initialization Vector*/
2428 #if defined (AES)
2429 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2430 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2431 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2432 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2433 #else /* CRYP */
2434 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2435 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2436 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2437 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2438 #endif /* End AES or CRYP */
2439 }
2440 } /* if (DoKeyIVConfig == 1U) */
2441
2442 /* Set the phase */
2443 hcryp->Phase = CRYP_PHASE_PROCESS;
2444
2445 /* Enable CRYP */
2446 __HAL_CRYP_ENABLE(hcryp);
2447
2448 /*Temporary CrypOutCount Value*/
2449 outcount = hcryp->CrypOutCount;
2450
2451 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2452 {
2453 /* Write plain Ddta and get cipher data */
2454 CRYP_AES_ProcessData(hcryp, Timeout);
2455 /*Temporary CrypOutCount Value*/
2456 outcount = hcryp->CrypOutCount;
2457 }
2458
2459 /* Disable CRYP */
2460 __HAL_CRYP_DISABLE(hcryp);
2461
2462 /* Change the CRYP state */
2463 hcryp->State = HAL_CRYP_STATE_READY;
2464
2465 /* Return function status */
2466 return HAL_OK;
2467 }
2468
2469 /**
2470 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2471 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2472 * the configuration information for CRYP module
2473 * @retval HAL status
2474 */
CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef * hcryp)2475 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2476 {
2477 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2478
2479 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2480 {
2481 if (hcryp->KeyIVConfig == 1U)
2482 {
2483 /* If the Key and IV configuration has to be done only once
2484 and if it has already been done, skip it */
2485 DoKeyIVConfig = 0U;
2486 }
2487 else
2488 {
2489 /* If the Key and IV configuration has to be done only once
2490 and if it has not been done already, do it and set KeyIVConfig
2491 to keep track it won't have to be done again next time */
2492 hcryp->KeyIVConfig = 1U;
2493 }
2494 }
2495
2496 if (DoKeyIVConfig == 1U)
2497 {
2498 /* Set the Key*/
2499 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2500
2501 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2502 {
2503 /* Set the Initialization Vector*/
2504 #if defined (AES)
2505 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2506 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2507 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2508 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2509
2510 #else /* CRYP */
2511 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2512 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2513 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2514 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2515 #endif /* End AES or CRYP */
2516 }
2517 } /* if (DoKeyIVConfig == 1U) */
2518
2519 /* Set the phase */
2520 hcryp->Phase = CRYP_PHASE_PROCESS;
2521
2522 if (hcryp->Size != 0U)
2523 {
2524 #if defined (AES)
2525
2526 /* Enable computation complete flag and error interrupts */
2527 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2528
2529 /* Enable CRYP */
2530 __HAL_CRYP_ENABLE(hcryp);
2531
2532 /* Write the input block in the IN FIFO */
2533 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2534 hcryp->CrypInCount++;
2535 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2536 hcryp->CrypInCount++;
2537 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2538 hcryp->CrypInCount++;
2539 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2540 hcryp->CrypInCount++;
2541
2542 #else /* CRYP */
2543
2544 /* Enable interrupts */
2545 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2546
2547 /* Enable CRYP */
2548 __HAL_CRYP_ENABLE(hcryp);
2549
2550 #endif /* End AES or CRYP */
2551 }
2552 else
2553 {
2554 /* Change the CRYP state */
2555 hcryp->State = HAL_CRYP_STATE_READY;
2556
2557 /* Process unlocked */
2558 __HAL_UNLOCK(hcryp);
2559 }
2560
2561 /* Return function status */
2562 return HAL_OK;
2563 }
2564
2565 /**
2566 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2567 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2568 * @param Timeout: Specify Timeout value
2569 * @retval HAL status
2570 */
CRYP_AES_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2571 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2572 {
2573 uint16_t outcount; /* Temporary CrypOutCount Value */
2574 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2575
2576 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2577 {
2578 if (hcryp->KeyIVConfig == 1U)
2579 {
2580 /* If the Key and IV configuration has to be done only once
2581 and if it has already been done, skip it */
2582 DoKeyIVConfig = 0U;
2583 }
2584 else
2585 {
2586 /* If the Key and IV configuration has to be done only once
2587 and if it has not been done already, do it and set KeyIVConfig
2588 to keep track it won't have to be done again next time */
2589 hcryp->KeyIVConfig = 1U;
2590 }
2591 }
2592
2593 if (DoKeyIVConfig == 1U)
2594 {
2595 /* Key preparation for ECB/CBC */
2596 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2597 {
2598 #if defined (AES)
2599 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2600 {
2601 /* Set key preparation for decryption operating mode*/
2602 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2603
2604 /* Set the Key*/
2605 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2606
2607 /* Enable CRYP */
2608 __HAL_CRYP_ENABLE(hcryp);
2609
2610 /* Wait for CCF flag to be raised */
2611 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2612 {
2613 /* Disable the CRYP peripheral clock */
2614 __HAL_CRYP_DISABLE(hcryp);
2615
2616 /* Change state & error code*/
2617 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2618 hcryp->State = HAL_CRYP_STATE_READY;
2619
2620 /* Process unlocked */
2621 __HAL_UNLOCK(hcryp);
2622 return HAL_ERROR;
2623 }
2624 /* Clear CCF Flag */
2625 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2626
2627 /* Return to decryption operating mode(Mode 3)*/
2628 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2629 }
2630 else /*Mode 4 : decryption & Key preparation*/
2631 {
2632 /* Set the Key*/
2633 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2634
2635 /* Set decryption & Key preparation operating mode*/
2636 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2637 }
2638 #else /* CRYP */
2639 /* change ALGOMODE to key preparation for decryption*/
2640 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2641
2642 /* Set the Key*/
2643 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2644
2645 /* Enable CRYP */
2646 __HAL_CRYP_ENABLE(hcryp);
2647
2648 /* Wait for BUSY flag to be raised */
2649 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2650 {
2651 /* Disable the CRYP peripheral clock */
2652 __HAL_CRYP_DISABLE(hcryp);
2653
2654 /* Change state */
2655 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2656 hcryp->State = HAL_CRYP_STATE_READY;
2657
2658 /* Process unlocked */
2659 __HAL_UNLOCK(hcryp);
2660 return HAL_ERROR;
2661 }
2662 /* Turn back to ALGOMODE of the configuration */
2663 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2664
2665 #endif /* End AES or CRYP */
2666 }
2667 else /*Algorithm CTR */
2668 {
2669 /* Set the Key*/
2670 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2671 }
2672
2673 /* Set IV */
2674 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2675 {
2676 /* Set the Initialization Vector*/
2677 #if defined (AES)
2678 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2679 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2680 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2681 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2682 #else /* CRYP */
2683 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2684 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2685 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2686 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2687 #endif /* End AES or CRYP */
2688 }
2689 } /* if (DoKeyIVConfig == 1U) */
2690 /* Set the phase */
2691 hcryp->Phase = CRYP_PHASE_PROCESS;
2692
2693 /* Enable CRYP */
2694 __HAL_CRYP_ENABLE(hcryp);
2695
2696 /*Temporary CrypOutCount Value*/
2697 outcount = hcryp->CrypOutCount;
2698
2699 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2700 {
2701 /* Write plain data and get cipher data */
2702 CRYP_AES_ProcessData(hcryp, Timeout);
2703 /*Temporary CrypOutCount Value*/
2704 outcount = hcryp->CrypOutCount;
2705 }
2706
2707 /* Disable CRYP */
2708 __HAL_CRYP_DISABLE(hcryp);
2709
2710 /* Change the CRYP state */
2711 hcryp->State = HAL_CRYP_STATE_READY;
2712
2713 /* Return function status */
2714 return HAL_OK;
2715 }
2716 /**
2717 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2718 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2719 * the configuration information for CRYP module
2720 * @retval HAL status
2721 */
CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef * hcryp)2722 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2723 {
2724 __IO uint32_t count = 0U;
2725 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2726
2727 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2728 {
2729 if (hcryp->KeyIVConfig == 1U)
2730 {
2731 /* If the Key and IV configuration has to be done only once
2732 and if it has already been done, skip it */
2733 DoKeyIVConfig = 0U;
2734 }
2735 else
2736 {
2737 /* If the Key and IV configuration has to be done only once
2738 and if it has not been done already, do it and set KeyIVConfig
2739 to keep track it won't have to be done again next time */
2740 hcryp->KeyIVConfig = 1U;
2741 }
2742 }
2743
2744 if (DoKeyIVConfig == 1U)
2745 {
2746 /* Key preparation for ECB/CBC */
2747 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2748 {
2749 #if defined (AES)
2750 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2751 {
2752 /* Set key preparation for decryption operating mode*/
2753 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2754
2755 /* Set the Key*/
2756 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2757
2758 /* Enable CRYP */
2759 __HAL_CRYP_ENABLE(hcryp);
2760
2761 /* Wait for CCF flag to be raised */
2762 count = CRYP_TIMEOUT_KEYPREPARATION;
2763 do
2764 {
2765 count-- ;
2766 if (count == 0U)
2767 {
2768 /* Disable the CRYP peripheral clock */
2769 __HAL_CRYP_DISABLE(hcryp);
2770
2771 /* Change state */
2772 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2773 hcryp->State = HAL_CRYP_STATE_READY;
2774
2775 /* Process unlocked */
2776 __HAL_UNLOCK(hcryp);
2777 return HAL_ERROR;
2778 }
2779 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2780
2781 /* Clear CCF Flag */
2782 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2783
2784 /* Return to decryption operating mode(Mode 3)*/
2785 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2786 }
2787 else /*Mode 4 : decryption & key preparation*/
2788 {
2789 /* Set the Key*/
2790 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2791
2792 /* Set decryption & key preparation operating mode*/
2793 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2794 }
2795 #else /* CRYP */
2796
2797 /* change ALGOMODE to key preparation for decryption*/
2798 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2799
2800 /* Set the Key*/
2801 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2802
2803 /* Enable CRYP */
2804 __HAL_CRYP_ENABLE(hcryp);
2805
2806 /* Wait for BUSY flag to be raised */
2807 count = CRYP_TIMEOUT_KEYPREPARATION;
2808 do
2809 {
2810 count-- ;
2811 if (count == 0U)
2812 {
2813 /* Change state */
2814 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2815 hcryp->State = HAL_CRYP_STATE_READY;
2816
2817 /* Process unlocked */
2818 __HAL_UNLOCK(hcryp);
2819 return HAL_ERROR;
2820 }
2821 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2822
2823 /* Turn back to ALGOMODE of the configuration */
2824 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2825
2826 #endif /* End AES or CRYP */
2827 }
2828
2829 else /*Algorithm CTR */
2830 {
2831 /* Set the Key*/
2832 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2833 }
2834
2835 /* Set IV */
2836 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2837 {
2838 /* Set the Initialization Vector*/
2839 #if defined (AES)
2840 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2841 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2842 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2843 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2844 #else /* CRYP */
2845 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2846 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2847 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2848 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2849 #endif /* End AES or CRYP */
2850 }
2851 } /* if (DoKeyIVConfig == 1U) */
2852
2853 /* Set the phase */
2854 hcryp->Phase = CRYP_PHASE_PROCESS;
2855 if (hcryp->Size != 0U)
2856 {
2857
2858 #if defined (AES)
2859
2860 /* Enable computation complete flag and error interrupts */
2861 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2862
2863 /* Enable CRYP */
2864 __HAL_CRYP_ENABLE(hcryp);
2865
2866 /* Write the input block in the IN FIFO */
2867 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2868 hcryp->CrypInCount++;
2869 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2870 hcryp->CrypInCount++;
2871 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2872 hcryp->CrypInCount++;
2873 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2874 hcryp->CrypInCount++;
2875
2876 #else /* CRYP */
2877
2878 /* Enable interrupts */
2879 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2880
2881 /* Enable CRYP */
2882 __HAL_CRYP_ENABLE(hcryp);
2883
2884 #endif /* End AES or CRYP */
2885 }
2886 else
2887 {
2888 /* Process locked */
2889 __HAL_UNLOCK(hcryp);
2890
2891 /* Change the CRYP state */
2892 hcryp->State = HAL_CRYP_STATE_READY;
2893 }
2894
2895 /* Return function status */
2896 return HAL_OK;
2897 }
2898 /**
2899 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
2900 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2901 * the configuration information for CRYP module
2902 * @retval HAL status
2903 */
CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef * hcryp)2904 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2905 {
2906 __IO uint32_t count = 0U;
2907 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2908
2909 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2910 {
2911 if (hcryp->KeyIVConfig == 1U)
2912 {
2913 /* If the Key and IV configuration has to be done only once
2914 and if it has already been done, skip it */
2915 DoKeyIVConfig = 0U;
2916 }
2917 else
2918 {
2919 /* If the Key and IV configuration has to be done only once
2920 and if it has not been done already, do it and set KeyIVConfig
2921 to keep track it won't have to be done again next time */
2922 hcryp->KeyIVConfig = 1U;
2923 }
2924 }
2925 if (DoKeyIVConfig == 1U)
2926 {
2927 /* Key preparation for ECB/CBC */
2928 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2929 {
2930 #if defined (AES)
2931 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
2932 {
2933 /* Set key preparation for decryption operating mode*/
2934 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2935
2936 /* Set the Key*/
2937 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2938
2939 /* Enable CRYP */
2940 __HAL_CRYP_ENABLE(hcryp);
2941
2942 /* Wait for CCF flag to be raised */
2943 count = CRYP_TIMEOUT_KEYPREPARATION;
2944 do
2945 {
2946 count-- ;
2947 if (count == 0U)
2948 {
2949 /* Disable the CRYP peripheral clock */
2950 __HAL_CRYP_DISABLE(hcryp);
2951
2952 /* Change state */
2953 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2954 hcryp->State = HAL_CRYP_STATE_READY;
2955
2956 /* Process unlocked */
2957 __HAL_UNLOCK(hcryp);
2958 return HAL_ERROR;
2959 }
2960 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2961
2962 /* Clear CCF Flag */
2963 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2964
2965 /* Return to decryption operating mode(Mode 3)*/
2966 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2967 }
2968 else /*Mode 4 : decryption & key preparation*/
2969 {
2970 /* Set the Key*/
2971 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2972
2973 /* Set decryption & Key preparation operating mode*/
2974 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2975 }
2976 #else /* CRYP */
2977 /* change ALGOMODE to key preparation for decryption*/
2978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2979
2980 /* Set the Key*/
2981 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2982
2983 /* Enable CRYP */
2984 __HAL_CRYP_ENABLE(hcryp);
2985
2986 /* Wait for BUSY flag to be raised */
2987 count = CRYP_TIMEOUT_KEYPREPARATION;
2988 do
2989 {
2990 count-- ;
2991 if (count == 0U)
2992 {
2993 /* Disable the CRYP peripheral clock */
2994 __HAL_CRYP_DISABLE(hcryp);
2995
2996 /* Change state */
2997 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2998 hcryp->State = HAL_CRYP_STATE_READY;
2999
3000 /* Process unlocked */
3001 __HAL_UNLOCK(hcryp);
3002 return HAL_ERROR;
3003 }
3004 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
3005
3006 /* Turn back to ALGOMODE of the configuration */
3007 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3008
3009 #endif /* End AES or CRYP */
3010 }
3011 else /*Algorithm CTR */
3012 {
3013 /* Set the Key*/
3014 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3015 }
3016
3017 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3018 {
3019 /* Set the Initialization Vector*/
3020 #if defined (AES)
3021 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3022 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3023 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3024 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3025 #else /* CRYP */
3026 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3027 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3028 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3029 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3030 #endif /* End AES or CRYP */
3031 }
3032 } /* if (DoKeyIVConfig == 1U) */
3033
3034 /* Set the phase */
3035 hcryp->Phase = CRYP_PHASE_PROCESS;
3036
3037 if (hcryp->Size != 0U)
3038 {
3039 /* Set the input and output addresses and start DMA transfer */
3040 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3041 }
3042 else
3043 {
3044 /* Process unlocked */
3045 __HAL_UNLOCK(hcryp);
3046
3047 /* Change the CRYP state */
3048 hcryp->State = HAL_CRYP_STATE_READY;
3049 }
3050
3051 /* Return function status */
3052 return HAL_OK;
3053 }
3054
3055
3056 /**
3057 * @brief DMA CRYP input data process complete callback.
3058 * @param hdma: DMA handle
3059 * @retval None
3060 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)3061 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3062 {
3063 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3064
3065 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3066 in the DMACR register */
3067 #if defined (CRYP)
3068 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3069
3070 #else /* AES */
3071 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
3072
3073 /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
3074 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3075 {
3076 /* Clear CCF flag */
3077 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3078
3079 /* Change the CRYP state to ready */
3080 hcryp->State = HAL_CRYP_STATE_READY;
3081
3082 /* Process Unlocked */
3083 __HAL_UNLOCK(hcryp);
3084 }
3085 #endif /* End AES or CRYP */
3086
3087 /* Call input data transfer complete callback */
3088 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3089 /*Call registered Input complete callback*/
3090 hcryp->InCpltCallback(hcryp);
3091 #else
3092 /*Call legacy weak Input complete callback*/
3093 HAL_CRYP_InCpltCallback(hcryp);
3094 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3095 }
3096
3097 /**
3098 * @brief DMA CRYP output data process complete callback.
3099 * @param hdma: DMA handle
3100 * @retval None
3101 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)3102 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3103 {
3104 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3105
3106 /* Disable the DMA transfer for output FIFO request by resetting
3107 the DOEN bit in the DMACR register */
3108
3109 #if defined (CRYP)
3110
3111 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3112 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
3113 if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3114 {
3115 /* Disable CRYP (not allowed in GCM)*/
3116 __HAL_CRYP_DISABLE(hcryp);
3117 }
3118
3119 #else /*NO GCM CCM */
3120 /* Disable CRYP */
3121 __HAL_CRYP_DISABLE(hcryp);
3122 #endif /* GCM CCM defined*/
3123 #else /* AES */
3124
3125 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
3126
3127 /* Clear CCF flag */
3128 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3129
3130 if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3131 {
3132 /* Disable CRYP (not allowed in GCM)*/
3133 __HAL_CRYP_DISABLE(hcryp);
3134 }
3135 #endif /* End AES or CRYP */
3136
3137 /* Change the CRYP state to ready */
3138 hcryp->State = HAL_CRYP_STATE_READY;
3139
3140 /* Process unlocked */
3141 __HAL_UNLOCK(hcryp);
3142 /* Call output data transfer complete callback */
3143 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3144 /*Call registered Output complete callback*/
3145 hcryp->OutCpltCallback(hcryp);
3146 #else
3147 /*Call legacy weak Output complete callback*/
3148 HAL_CRYP_OutCpltCallback(hcryp);
3149 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3150 }
3151
3152 /**
3153 * @brief DMA CRYP communication error callback.
3154 * @param hdma: DMA handle
3155 * @retval None
3156 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)3157 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3158 {
3159 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3160
3161 /* Change the CRYP peripheral state */
3162 hcryp->State = HAL_CRYP_STATE_READY;
3163
3164 /* DMA error code field */
3165 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3166
3167 #if defined (AES)
3168
3169 /* Clear CCF flag */
3170 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3171
3172 #endif /* AES */
3173
3174 /* Call error callback */
3175 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3176 /*Call registered error callback*/
3177 hcryp->ErrorCallback(hcryp);
3178 #else
3179 /*Call legacy weak error callback*/
3180 HAL_CRYP_ErrorCallback(hcryp);
3181 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3182 }
3183
3184 /**
3185 * @brief Set the DMA configuration and start the DMA transfer
3186 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3187 * the configuration information for CRYP module
3188 * @param inputaddr: address of the input buffer
3189 * @param Size: size of the input buffer, must be a multiple of 16.
3190 * @param outputaddr: address of the output buffer
3191 * @retval None
3192 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)3193 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3194 {
3195 /* Set the CRYP DMA transfer complete callback */
3196 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3197
3198 /* Set the DMA input error callback */
3199 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3200
3201 /* Set the CRYP DMA transfer complete callback */
3202 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3203
3204 /* Set the DMA output error callback */
3205 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3206
3207 #if defined (CRYP)
3208
3209 /* Enable CRYP */
3210 __HAL_CRYP_ENABLE(hcryp);
3211
3212 /* Enable the input DMA Stream */
3213 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
3214 {
3215 /* DMA error code field */
3216 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3217
3218 /* Call error callback */
3219 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3220 /*Call registered error callback*/
3221 hcryp->ErrorCallback(hcryp);
3222 #else
3223 /*Call legacy weak error callback*/
3224 HAL_CRYP_ErrorCallback(hcryp);
3225 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3226 }
3227 /* Enable the output DMA Stream */
3228 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
3229 {
3230 /* DMA error code field */
3231 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3232
3233 /* Call error callback */
3234 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3235 /*Call registered error callback*/
3236 hcryp->ErrorCallback(hcryp);
3237 #else
3238 /*Call legacy weak error callback*/
3239 HAL_CRYP_ErrorCallback(hcryp);
3240 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3241 }
3242 /* Enable In/Out DMA request */
3243 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
3244
3245 #else /* AES */
3246
3247 if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3248 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3249 {
3250 /* Enable CRYP (not allowed in GCM & CCM)*/
3251 __HAL_CRYP_ENABLE(hcryp);
3252 }
3253
3254 /* Enable the DMA input stream */
3255 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
3256 {
3257 /* DMA error code field */
3258 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3259
3260 /* Call error callback */
3261 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3262 /*Call registered error callback*/
3263 hcryp->ErrorCallback(hcryp);
3264 #else
3265 /*Call legacy weak error callback*/
3266 HAL_CRYP_ErrorCallback(hcryp);
3267 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3268 }
3269 /* Enable the DMA output stream */
3270 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
3271 {
3272 /* DMA error code field */
3273 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3274
3275 /* Call error callback */
3276 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3277 /*Call registered error callback*/
3278 hcryp->ErrorCallback(hcryp);
3279 #else
3280 /*Call legacy weak error callback*/
3281 HAL_CRYP_ErrorCallback(hcryp);
3282 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3283 }
3284 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
3285 /* Enable In and Out DMA requests */
3286 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3287 {
3288 /* Enable only In DMA requests for CCM*/
3289 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
3290 }
3291 else
3292 {
3293 /* Enable In and Out DMA requests */
3294 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
3295 }
3296 #endif /* End AES or CRYP */
3297 }
3298
3299 /**
3300 * @brief Process Data: Write Input data in polling mode and used in AES functions.
3301 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3302 * the configuration information for CRYP module
3303 * @param Timeout: Specify Timeout value
3304 * @retval None
3305 */
CRYP_AES_ProcessData(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3306 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3307 {
3308
3309 uint32_t temp[4]; /* Temporary CrypOutBuff */
3310 uint32_t i;
3311 #if defined (CRYP)
3312 uint16_t incount; /* Temporary CrypInCount Value */
3313 uint16_t outcount; /* Temporary CrypOutCount Value */
3314 #endif
3315
3316 #if defined (CRYP)
3317
3318 /*Temporary CrypOutCount Value*/
3319 incount = hcryp->CrypInCount;
3320
3321 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3322 {
3323 /* Write the input block in the IN FIFO */
3324 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3325 hcryp->CrypInCount++;
3326 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3327 hcryp->CrypInCount++;
3328 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3329 hcryp->CrypInCount++;
3330 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3331 hcryp->CrypInCount++;
3332 }
3333
3334 /* Wait for OFNE flag to be raised */
3335 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3336 {
3337 /* Disable the CRYP peripheral clock */
3338 __HAL_CRYP_DISABLE(hcryp);
3339
3340 /* Change state & error code*/
3341 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3342 hcryp->State = HAL_CRYP_STATE_READY;
3343
3344 /* Process unlocked */
3345 __HAL_UNLOCK(hcryp);
3346 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3347 /*Call registered error callback*/
3348 hcryp->ErrorCallback(hcryp);
3349 #else
3350 /*Call legacy weak error callback*/
3351 HAL_CRYP_ErrorCallback(hcryp);
3352 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3353 }
3354
3355 /*Temporary CrypOutCount Value*/
3356 outcount = hcryp->CrypOutCount;
3357
3358 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3359 {
3360 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3361 for (i = 0U; i < 4U; i++)
3362 {
3363 temp[i] = hcryp->Instance->DOUT;
3364 }
3365 i = 0U;
3366 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3367 {
3368 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3369 hcryp->CrypOutCount++;
3370 i++;
3371 }
3372 }
3373
3374 #else /* AES */
3375
3376 /* Write the input block in the IN FIFO */
3377 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3378 hcryp->CrypInCount++;
3379 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3380 hcryp->CrypInCount++;
3381 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3382 hcryp->CrypInCount++;
3383 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3384 hcryp->CrypInCount++;
3385
3386 /* Wait for CCF flag to be raised */
3387 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3388 {
3389 /* Disable the CRYP peripheral clock */
3390 __HAL_CRYP_DISABLE(hcryp);
3391
3392 /* Change state */
3393 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3394 hcryp->State = HAL_CRYP_STATE_READY;
3395
3396 /* Process unlocked */
3397 __HAL_UNLOCK(hcryp);
3398 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3399 /*Call registered error callback*/
3400 hcryp->ErrorCallback(hcryp);
3401 #else
3402 /*Call legacy weak error callback*/
3403 HAL_CRYP_ErrorCallback(hcryp);
3404 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3405 }
3406
3407 /* Clear CCF Flag */
3408 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3409
3410 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3411 for (i = 0U; i < 4U; i++)
3412 {
3413 temp[i] = hcryp->Instance->DOUTR;
3414 }
3415 i = 0U;
3416 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3417 {
3418 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3419 hcryp->CrypOutCount++;
3420 i++;
3421 }
3422 #endif /* End AES or CRYP */
3423 }
3424
3425 /**
3426 * @brief Handle CRYP block input/output data handling under interruption.
3427 * @note The function is called under interruption only, once
3428 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3429 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3430 * the configuration information for CRYP module.
3431 * @retval HAL status
3432 */
CRYP_AES_IT(CRYP_HandleTypeDef * hcryp)3433 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3434 {
3435 uint32_t temp[4]; /* Temporary CrypOutBuff */
3436 uint32_t i;
3437 #if defined (CRYP)
3438 uint16_t incount; /* Temporary CrypInCount Value */
3439 uint16_t outcount; /* Temporary CrypOutCount Value */
3440 #endif
3441
3442 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3443 {
3444 #if defined (CRYP)
3445
3446 /*Temporary CrypOutCount Value*/
3447 incount = hcryp->CrypInCount;
3448 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3449 {
3450 /* Write the input block in the IN FIFO */
3451 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3452 hcryp->CrypInCount++;
3453 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3454 hcryp->CrypInCount++;
3455 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3456 hcryp->CrypInCount++;
3457 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3458 hcryp->CrypInCount++;
3459 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
3460 {
3461 /* Disable interrupts */
3462 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3463
3464 /* Call the input data transfer complete callback */
3465 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3466 /*Call registered Input complete callback*/
3467 hcryp->InCpltCallback(hcryp);
3468 #else
3469 /*Call legacy weak Input complete callback*/
3470 HAL_CRYP_InCpltCallback(hcryp);
3471 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3472 }
3473 }
3474 /*Temporary CrypOutCount Value*/
3475 outcount = hcryp->CrypOutCount;
3476
3477 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3478 {
3479 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3480 for (i = 0U; i < 4U; i++)
3481 {
3482 temp[i] = hcryp->Instance->DOUT;
3483 }
3484 i = 0U;
3485 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3486 {
3487 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3488 hcryp->CrypOutCount++;
3489 i++;
3490 }
3491 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
3492 {
3493 /* Disable interrupts */
3494 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3495
3496 /* Change the CRYP state */
3497 hcryp->State = HAL_CRYP_STATE_READY;
3498
3499 /* Disable CRYP */
3500 __HAL_CRYP_DISABLE(hcryp);
3501
3502 /* Process unlocked */
3503 __HAL_UNLOCK(hcryp);
3504
3505 /* Call Output transfer complete callback */
3506 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3507 /*Call registered Output complete callback*/
3508 hcryp->OutCpltCallback(hcryp);
3509 #else
3510 /*Call legacy weak Output complete callback*/
3511 HAL_CRYP_OutCpltCallback(hcryp);
3512 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3513 }
3514 }
3515
3516 #else /*AES*/
3517
3518 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3519 for (i = 0U; i < 4U; i++)
3520 {
3521 temp[i] = hcryp->Instance->DOUTR;
3522 }
3523 i = 0U;
3524 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3525 {
3526 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3527 hcryp->CrypOutCount++;
3528 i++;
3529 }
3530
3531 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3532 {
3533 /* Disable Computation Complete flag and errors interrupts */
3534 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
3535
3536 /* Change the CRYP state */
3537 hcryp->State = HAL_CRYP_STATE_READY;
3538
3539 /* Disable CRYP */
3540 __HAL_CRYP_DISABLE(hcryp);
3541
3542 /* Process Unlocked */
3543 __HAL_UNLOCK(hcryp);
3544
3545 /* Call Output transfer complete callback */
3546 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3547 /*Call registered Output complete callback*/
3548 hcryp->OutCpltCallback(hcryp);
3549 #else
3550 /*Call legacy weak Output complete callback*/
3551 HAL_CRYP_OutCpltCallback(hcryp);
3552 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3553 }
3554 else
3555 {
3556 /* Write the input block in the IN FIFO */
3557 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3558 hcryp->CrypInCount++;
3559 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3560 hcryp->CrypInCount++;
3561 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3562 hcryp->CrypInCount++;
3563 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3564 hcryp->CrypInCount++;
3565
3566 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3567 {
3568 /* Call Input transfer complete callback */
3569 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3570 /*Call registered Input complete callback*/
3571 hcryp->InCpltCallback(hcryp);
3572 #else
3573 /*Call legacy weak Input complete callback*/
3574 HAL_CRYP_InCpltCallback(hcryp);
3575 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3576 }
3577 }
3578 #endif /* End AES or CRYP */
3579
3580 }
3581 else
3582 {
3583 /* Busy error code field */
3584 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3585 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3586 /*Call registered error callback*/
3587 hcryp->ErrorCallback(hcryp);
3588 #else
3589 /*Call legacy weak error callback*/
3590 HAL_CRYP_ErrorCallback(hcryp);
3591 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3592 }
3593 }
3594
3595 /**
3596 * @brief Writes Key in Key registers.
3597 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3598 * the configuration information for CRYP module
3599 * @param KeySize: Size of Key
3600 * @retval None
3601 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint32_t KeySize)3602 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3603 {
3604 #if defined (CRYP)
3605
3606 switch (KeySize)
3607 {
3608 case CRYP_KEYSIZE_256B:
3609 hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
3610 hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3611 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3612 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3613 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3614 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3615 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
3616 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
3617 break;
3618 case CRYP_KEYSIZE_192B:
3619 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
3620 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3621 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3622 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3623 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3624 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3625 break;
3626 case CRYP_KEYSIZE_128B:
3627 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
3628 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3629 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3630 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3631
3632 break;
3633 default:
3634 break;
3635 }
3636 #else /*AES*/
3637 switch (KeySize)
3638 {
3639 case CRYP_KEYSIZE_256B:
3640 hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
3641 hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
3642 hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
3643 hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
3644 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
3645 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
3646 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
3647 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
3648 break;
3649 case CRYP_KEYSIZE_128B:
3650 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
3651 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
3652 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
3653 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
3654
3655 break;
3656 default:
3657 break;
3658 }
3659 #endif /* End AES or CRYP */
3660 }
3661
3662 #if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
3663 /**
3664 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
3665 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3666 * the configuration information for CRYP module
3667 * @param Timeout: Timeout duration
3668 * @retval HAL status
3669 */
CRYP_AESGCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3670 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3671 {
3672 uint32_t tickstart;
3673 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3674 uint16_t outcount; /* Temporary CrypOutCount Value */
3675 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3676
3677 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3678 {
3679 if (hcryp->KeyIVConfig == 1U)
3680 {
3681 /* If the Key and IV configuration has to be done only once
3682 and if it has already been done, skip it */
3683 DoKeyIVConfig = 0U;
3684 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3685 }
3686 else
3687 {
3688 /* If the Key and IV configuration has to be done only once
3689 and if it has not been done already, do it and set KeyIVConfig
3690 to keep track it won't have to be done again next time */
3691 hcryp->KeyIVConfig = 1U;
3692 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3693 }
3694 }
3695 else
3696 {
3697 hcryp->SizesSum = hcryp->Size;
3698 }
3699
3700 if (DoKeyIVConfig == 1U)
3701 {
3702 /* Reset CrypHeaderCount */
3703 hcryp->CrypHeaderCount = 0U;
3704
3705 /****************************** Init phase **********************************/
3706
3707 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3708
3709 /* Set the key */
3710 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3711
3712 #if defined(CRYP)
3713
3714 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3715 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3716 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3717 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3718 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3719
3720 /* Enable the CRYP peripheral */
3721 __HAL_CRYP_ENABLE(hcryp);
3722
3723 /* Get tick */
3724 tickstart = HAL_GetTick();
3725
3726 /*Wait for the CRYPEN bit to be cleared*/
3727 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3728 {
3729 /* Check for the Timeout */
3730 if (Timeout != HAL_MAX_DELAY)
3731 {
3732 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3733 {
3734 /* Disable the CRYP peripheral clock */
3735 __HAL_CRYP_DISABLE(hcryp);
3736
3737 /* Change state */
3738 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3739 hcryp->State = HAL_CRYP_STATE_READY;
3740
3741 /* Process unlocked */
3742 __HAL_UNLOCK(hcryp);
3743 return HAL_ERROR;
3744 }
3745 }
3746 }
3747
3748 #else /* AES */
3749 /* Workaround 1 : only AES.
3750 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3751 enabling the IP, datatype different from 32 bits can be configured.*/
3752 /* Select DATATYPE 32 */
3753 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3754
3755 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3756 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3757 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3758 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3759 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3760
3761 /* Enable the CRYP peripheral */
3762 __HAL_CRYP_ENABLE(hcryp);
3763
3764 /* just wait for hash computation */
3765 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3766 {
3767 /* Change state */
3768 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3769 hcryp->State = HAL_CRYP_STATE_READY;
3770
3771 /* Process unlocked & return error */
3772 __HAL_UNLOCK(hcryp);
3773 return HAL_ERROR;
3774 }
3775 /* Clear CCF flag */
3776 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3777
3778 #endif /* End AES or CRYP */
3779
3780 /************************ Header phase *************************************/
3781
3782 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3783 {
3784 return HAL_ERROR;
3785 }
3786
3787 /*************************Payload phase ************************************/
3788
3789 /* Set the phase */
3790 hcryp->Phase = CRYP_PHASE_PROCESS;
3791
3792 #if defined(CRYP)
3793
3794 /* Disable the CRYP peripheral */
3795 __HAL_CRYP_DISABLE(hcryp);
3796
3797 /* Select payload phase once the header phase is performed */
3798 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3799
3800 /* Enable the CRYP peripheral */
3801 __HAL_CRYP_ENABLE(hcryp);
3802
3803 #else /* AES */
3804
3805 /* Select payload phase once the header phase is performed */
3806 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3807
3808 #endif /* End AES or CRYP */
3809 } /* if (DoKeyIVConfig == 1U) */
3810
3811 if ((hcryp->Size % 16U) != 0U)
3812 {
3813 /* recalculate wordsize */
3814 wordsize = ((wordsize / 4U) * 4U) ;
3815 }
3816
3817 /* Get tick */
3818 tickstart = HAL_GetTick();
3819 /*Temporary CrypOutCount Value*/
3820 outcount = hcryp->CrypOutCount;
3821
3822 /* Write input data and get output Data */
3823 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3824 {
3825 /* Write plain data and get cipher data */
3826 CRYP_AES_ProcessData(hcryp, Timeout);
3827
3828 /*Temporary CrypOutCount Value*/
3829 outcount = hcryp->CrypOutCount;
3830
3831 /* Check for the Timeout */
3832 if (Timeout != HAL_MAX_DELAY)
3833 {
3834 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3835 {
3836 /* Disable the CRYP peripheral clock */
3837 __HAL_CRYP_DISABLE(hcryp);
3838
3839 /* Change state & error code */
3840 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3841 hcryp->State = HAL_CRYP_STATE_READY;
3842
3843 /* Process unlocked */
3844 __HAL_UNLOCK(hcryp);
3845 return HAL_ERROR;
3846 }
3847 }
3848 }
3849
3850 if ((hcryp->Size % 16U) != 0U)
3851 {
3852 /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3853 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3854 is selected, then the TAG message will be wrong.*/
3855 CRYP_Workaround(hcryp, Timeout);
3856 }
3857
3858 /* Return function status */
3859 return HAL_OK;
3860 }
3861
3862 /**
3863 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
3864 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3865 * the configuration information for CRYP module
3866 * @retval HAL status
3867 */
CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef * hcryp)3868 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3869 {
3870 __IO uint32_t count = 0U;
3871 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3872 #if defined(AES)
3873 uint32_t loopcounter;
3874 uint32_t lastwordsize;
3875 uint32_t npblb;
3876 #endif /* AES */
3877
3878 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3879 {
3880 if (hcryp->KeyIVConfig == 1U)
3881 {
3882 /* If the Key and IV configuration has to be done only once
3883 and if it has already been done, skip it */
3884 DoKeyIVConfig = 0U;
3885 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3886 }
3887 else
3888 {
3889 /* If the Key and IV configuration has to be done only once
3890 and if it has not been done already, do it and set KeyIVConfig
3891 to keep track it won't have to be done again next time */
3892 hcryp->KeyIVConfig = 1U;
3893 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3894 }
3895 }
3896 else
3897 {
3898 hcryp->SizesSum = hcryp->Size;
3899 }
3900
3901 /* Configure Key, IV and process message (header and payload) */
3902 if (DoKeyIVConfig == 1U)
3903 {
3904 /* Reset CrypHeaderCount */
3905 hcryp->CrypHeaderCount = 0U;
3906
3907 /******************************* Init phase *********************************/
3908
3909 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3910
3911 /* Set the key */
3912 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3913
3914 #if defined(CRYP)
3915 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3916 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3917 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3918 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3919 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3920
3921 /* Enable the CRYP peripheral */
3922 __HAL_CRYP_ENABLE(hcryp);
3923
3924 /*Wait for the CRYPEN bit to be cleared*/
3925 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3926 do
3927 {
3928 count-- ;
3929 if (count == 0U)
3930 {
3931 /* Disable the CRYP peripheral clock */
3932 __HAL_CRYP_DISABLE(hcryp);
3933
3934 /* Change state */
3935 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3936 hcryp->State = HAL_CRYP_STATE_READY;
3937
3938 /* Process unlocked */
3939 __HAL_UNLOCK(hcryp);
3940 return HAL_ERROR;
3941 }
3942 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3943
3944 #else /* AES */
3945
3946 /* Workaround 1 : only AES
3947 Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3948 enabling the IP, datatype different from 32 bits can be configured.*/
3949 /* Select DATATYPE 32 */
3950 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3951
3952 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3953 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3954 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3955 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3956 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3957
3958 /* Enable the CRYP peripheral */
3959 __HAL_CRYP_ENABLE(hcryp);
3960
3961 /* just wait for hash computation */
3962 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3963 do
3964 {
3965 count-- ;
3966 if (count == 0U)
3967 {
3968 /* Disable the CRYP peripheral clock */
3969 __HAL_CRYP_DISABLE(hcryp);
3970
3971 /* Change state */
3972 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3973 hcryp->State = HAL_CRYP_STATE_READY;
3974
3975 /* Process unlocked */
3976 __HAL_UNLOCK(hcryp);
3977 return HAL_ERROR;
3978 }
3979 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3980
3981 /* Clear CCF flag */
3982 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3983
3984 #endif /* End AES or CRYP */
3985
3986 /***************************** Header phase *********************************/
3987
3988 #if defined(CRYP)
3989
3990 /* Select header phase */
3991 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3992
3993 /* Enable interrupts */
3994 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
3995
3996 /* Enable CRYP */
3997 __HAL_CRYP_ENABLE(hcryp);
3998
3999 #else /* AES */
4000
4001 /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
4002 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
4003
4004 /* Select header phase */
4005 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4006
4007 /* Enable computation complete flag and error interrupts */
4008 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4009
4010 /* Enable the CRYP peripheral */
4011 __HAL_CRYP_ENABLE(hcryp);
4012
4013 if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
4014 {
4015 /* Set the phase */
4016 hcryp->Phase = CRYP_PHASE_PROCESS;
4017
4018 /* Select payload phase once the header phase is performed */
4019 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
4020
4021 /* Write the payload Input block in the IN FIFO */
4022 if (hcryp->Size == 0U)
4023 {
4024 /* Disable interrupts */
4025 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4026
4027 /* Change the CRYP state */
4028 hcryp->State = HAL_CRYP_STATE_READY;
4029
4030 /* Process unlocked */
4031 __HAL_UNLOCK(hcryp);
4032 }
4033 else if (hcryp->Size >= 16U)
4034 {
4035 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4036 hcryp->CrypInCount++;
4037 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4038 hcryp->CrypInCount++;
4039 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4040 hcryp->CrypInCount++;
4041 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4042 hcryp->CrypInCount++;
4043 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4044 {
4045 /* Call Input transfer complete callback */
4046 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4047 /*Call registered Input complete callback*/
4048 hcryp->InCpltCallback(hcryp);
4049 #else
4050 /*Call legacy weak Input complete callback*/
4051 HAL_CRYP_InCpltCallback(hcryp);
4052 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4053 }
4054 }
4055 else /* Size < 16Bytes : first block is the last block*/
4056 {
4057 /* Workaround not implemented*/
4058 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4059 Workaround is implemented in polling mode, so if last block of
4060 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4061
4062 /* Compute the number of padding bytes in last block of payload */
4063 npblb = 16U - (uint32_t)(hcryp->Size);
4064
4065 /* Number of valid words (lastwordsize) in last block */
4066 if ((npblb % 4U) == 0U)
4067 {
4068 lastwordsize = (16U - npblb) / 4U;
4069 }
4070 else
4071 {
4072 lastwordsize = ((16U - npblb) / 4U) + 1U;
4073 }
4074
4075 /* last block optionally pad the data with zeros*/
4076 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4077 {
4078 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4079 hcryp->CrypInCount++;
4080 }
4081 while (loopcounter < 4U)
4082 {
4083 /* pad the data with zeros to have a complete block */
4084 hcryp->Instance->DINR = 0x0U;
4085 loopcounter++;
4086 }
4087 }
4088 }
4089 else if ((hcryp->Init.HeaderSize) < 4U)
4090 {
4091 for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
4092 {
4093 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4094 hcryp->CrypHeaderCount++ ;
4095 }
4096 while (loopcounter < 4U)
4097 {
4098 /* pad the data with zeros to have a complete block */
4099 hcryp->Instance->DINR = 0x0U;
4100 loopcounter++;
4101 }
4102 /* Set the phase */
4103 hcryp->Phase = CRYP_PHASE_PROCESS;
4104
4105 /* Select payload phase once the header phase is performed */
4106 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4107
4108 /* Call Input transfer complete callback */
4109 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4110 /*Call registered Input complete callback*/
4111 hcryp->InCpltCallback(hcryp);
4112 #else
4113 /*Call legacy weak Input complete callback*/
4114 HAL_CRYP_InCpltCallback(hcryp);
4115 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4116 }
4117 else if ((hcryp->Init.HeaderSize) >= 4U)
4118 {
4119 /* Write the input block in the IN FIFO */
4120 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4121 hcryp->CrypHeaderCount++;
4122 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4123 hcryp->CrypHeaderCount++;
4124 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4125 hcryp->CrypHeaderCount++;
4126 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4127 hcryp->CrypHeaderCount++;
4128 }
4129 else
4130 {
4131 /* Nothing to do */
4132 }
4133
4134 #endif /* End AES or CRYP */
4135 } /* end of if (DoKeyIVConfig == 1U) */
4136
4137 /* Return function status */
4138 return HAL_OK;
4139 }
4140
4141
4142 /**
4143 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
4144 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4145 * the configuration information for CRYP module
4146 * @retval HAL status
4147 */
CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef * hcryp)4148 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4149 {
4150 __IO uint32_t count = 0U;
4151 uint32_t wordsize;
4152 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4153
4154 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4155 {
4156 if (hcryp->KeyIVConfig == 1U)
4157 {
4158 /* If the Key and IV configuration has to be done only once
4159 and if it has already been done, skip it */
4160 DoKeyIVConfig = 0U;
4161 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4162 }
4163 else
4164 {
4165 /* If the Key and IV configuration has to be done only once
4166 and if it has not been done already, do it and set KeyIVConfig
4167 to keep track it won't have to be done again next time */
4168 hcryp->KeyIVConfig = 1U;
4169 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4170 }
4171 }
4172 else
4173 {
4174 hcryp->SizesSum = hcryp->Size;
4175 }
4176
4177 if (DoKeyIVConfig == 1U)
4178 {
4179 /* Reset CrypHeaderCount */
4180 hcryp->CrypHeaderCount = 0U;
4181
4182 /*************************** Init phase ************************************/
4183
4184 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4185
4186 /* Set the key */
4187 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4188
4189 #if defined(CRYP)
4190 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4191 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4192 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4193 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4194 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4195
4196 /* Enable the CRYP peripheral */
4197 __HAL_CRYP_ENABLE(hcryp);
4198
4199 /*Wait for the CRYPEN bit to be cleared*/
4200 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4201 do
4202 {
4203 count-- ;
4204 if (count == 0U)
4205 {
4206 /* Disable the CRYP peripheral clock */
4207 __HAL_CRYP_DISABLE(hcryp);
4208
4209 /* Change state */
4210 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4211 hcryp->State = HAL_CRYP_STATE_READY;
4212
4213 /* Process unlocked */
4214 __HAL_UNLOCK(hcryp);
4215 return HAL_ERROR;
4216 }
4217 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4218
4219 #else /* AES */
4220
4221 /*Workaround 1 : only AES
4222 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
4223 enabling the IP, datatype different from 32 bits can be configured.*/
4224 /* Select DATATYPE 32 */
4225 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
4226
4227 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4228 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4229 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4230 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4231 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4232
4233 /* Enable the CRYP peripheral */
4234 __HAL_CRYP_ENABLE(hcryp);
4235
4236 /* just wait for hash computation */
4237 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4238 do
4239 {
4240 count-- ;
4241 if (count == 0U)
4242 {
4243 /* Disable the CRYP peripheral clock */
4244 __HAL_CRYP_DISABLE(hcryp);
4245
4246 /* Change state */
4247 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4248 hcryp->State = HAL_CRYP_STATE_READY;
4249
4250 /* Process unlocked */
4251 __HAL_UNLOCK(hcryp);
4252 return HAL_ERROR;
4253 }
4254 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4255
4256 /* Clear CCF flag */
4257 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4258
4259 #endif /* End AES or CRYP */
4260
4261 /************************ Header phase *************************************/
4262
4263 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4264 {
4265 return HAL_ERROR;
4266 }
4267
4268 /************************ Payload phase ************************************/
4269
4270 /* Set the phase */
4271 hcryp->Phase = CRYP_PHASE_PROCESS;
4272
4273 #if defined(CRYP)
4274
4275 /* Disable the CRYP peripheral */
4276 __HAL_CRYP_DISABLE(hcryp);
4277
4278 #endif /* CRYP */
4279
4280 /* Select payload phase once the header phase is performed */
4281 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4282
4283 } /* if (DoKeyIVConfig == 1U) */
4284
4285 if (hcryp->Size != 0U)
4286 {
4287 /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4288 Workaround is implemented in polling mode, so if last block of
4289 payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
4290 /* Set the input and output addresses and start DMA transfer */
4291 if ((hcryp->Size % 16U) == 0U)
4292 {
4293 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
4294 }
4295 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
4296 {
4297 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
4298
4299 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
4300 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
4301 (uint32_t)(hcryp->pCrypOutBuffPtr));
4302 }
4303 }
4304 else
4305 {
4306 /* Process unLocked */
4307 __HAL_UNLOCK(hcryp);
4308
4309 /* Change the CRYP state and phase */
4310 hcryp->State = HAL_CRYP_STATE_READY;
4311 }
4312
4313 /* Return function status */
4314 return HAL_OK;
4315 }
4316
4317
4318 /**
4319 * @brief AES CCM encryption/decryption processing in polling mode
4320 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4321 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4322 * the configuration information for CRYP module
4323 * @param Timeout: Timeout duration
4324 * @retval HAL status
4325 */
CRYP_AESCCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4326 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4327 {
4328 uint32_t tickstart;
4329 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4330 uint16_t outcount; /* Temporary CrypOutCount Value */
4331 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4332 #if defined(AES)
4333 uint32_t loopcounter;
4334 uint32_t npblb;
4335 uint32_t lastwordsize;
4336 #endif /* AES */
4337
4338 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4339 {
4340 if (hcryp->KeyIVConfig == 1U)
4341 {
4342 /* If the Key and IV configuration has to be done only once
4343 and if it has already been done, skip it */
4344 DoKeyIVConfig = 0U;
4345 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4346 }
4347 else
4348 {
4349 /* If the Key and IV configuration has to be done only once
4350 and if it has not been done already, do it and set KeyIVConfig
4351 to keep track it won't have to be done again next time */
4352 hcryp->KeyIVConfig = 1U;
4353 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4354 }
4355 }
4356 else
4357 {
4358 hcryp->SizesSum = hcryp->Size;
4359 }
4360
4361 if (DoKeyIVConfig == 1U)
4362 {
4363
4364 /* Reset CrypHeaderCount */
4365 hcryp->CrypHeaderCount = 0U;
4366
4367 #if defined(CRYP)
4368
4369 /********************** Init phase ******************************************/
4370
4371 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4372
4373 /* Set the key */
4374 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4375
4376 /* Set the initialization vector (IV) with CTR1 information */
4377 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4378 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4379 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4380 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4381
4382
4383 /* Enable the CRYP peripheral */
4384 __HAL_CRYP_ENABLE(hcryp);
4385
4386 /*Write B0 packet into CRYP_DIN Register*/
4387 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4388 {
4389 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4390 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4391 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4392 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4393 }
4394 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4395 {
4396 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4397 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4398 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4399 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4400 }
4401 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4402 {
4403 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4404 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4405 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4406 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4407 }
4408 else
4409 {
4410 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4411 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4412 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4413 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4414 }
4415 /* Get tick */
4416 tickstart = HAL_GetTick();
4417
4418 /*Wait for the CRYPEN bit to be cleared*/
4419 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4420 {
4421 /* Check for the Timeout */
4422 if (Timeout != HAL_MAX_DELAY)
4423 {
4424 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4425 {
4426 /* Disable the CRYP peripheral clock */
4427 __HAL_CRYP_DISABLE(hcryp);
4428
4429 /* Change state */
4430 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4431 hcryp->State = HAL_CRYP_STATE_READY;
4432
4433 /* Process unlocked */
4434 __HAL_UNLOCK(hcryp);
4435 return HAL_ERROR;
4436 }
4437 }
4438 }
4439 #else /* AES */
4440 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4441 /* Select header phase */
4442 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4443
4444 /* configured encryption mode */
4445 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4446
4447 /* Set the key */
4448 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4449
4450 /* Set the initialization vector with zero values*/
4451 hcryp->Instance->IVR3 = 0U;
4452 hcryp->Instance->IVR2 = 0U;
4453 hcryp->Instance->IVR1 = 0U;
4454 hcryp->Instance->IVR0 = 0U;
4455
4456 /* Enable the CRYP peripheral */
4457 __HAL_CRYP_ENABLE(hcryp);
4458
4459 /*Write the B0 packet into CRYP_DIN*/
4460 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4461 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4462 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4463 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4464
4465 /* wait until the end of computation */
4466 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4467 {
4468 /* Change state */
4469 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4470 hcryp->State = HAL_CRYP_STATE_READY;
4471
4472 /* Process unlocked & return error */
4473 __HAL_UNLOCK(hcryp);
4474 return HAL_ERROR;
4475 }
4476 /* Clear CCF flag */
4477 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4478
4479 /* Set the phase */
4480 hcryp->Phase = CRYP_PHASE_PROCESS;
4481
4482 /* From that point the whole message must be processed, first the Header then the payload.
4483 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4484
4485 if (hcryp->Init.HeaderSize != 0U)
4486 {
4487 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4488 {
4489 /* HeaderSize %4, no padding */
4490 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4491 {
4492 /* Write the Input block in the Data Input register */
4493 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4494 hcryp->CrypHeaderCount++ ;
4495 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4496 hcryp->CrypHeaderCount++ ;
4497 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4498 hcryp->CrypHeaderCount++ ;
4499 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4500 hcryp->CrypHeaderCount++ ;
4501
4502 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4503 {
4504 /* Disable the CRYP peripheral clock */
4505 __HAL_CRYP_DISABLE(hcryp);
4506
4507 /* Change state */
4508 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4509 hcryp->State = HAL_CRYP_STATE_READY;
4510
4511 /* Process unlocked */
4512 __HAL_UNLOCK(hcryp);
4513 return HAL_ERROR;
4514 }
4515 /* Clear CCF Flag */
4516 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4517 }
4518 }
4519 else
4520 {
4521 /*Write Header block in the IN FIFO without last block */
4522 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4523 {
4524 /* Write the input block in the data input register */
4525 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4526 hcryp->CrypHeaderCount++ ;
4527 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4528 hcryp->CrypHeaderCount++ ;
4529 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4530 hcryp->CrypHeaderCount++ ;
4531 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4532 hcryp->CrypHeaderCount++ ;
4533
4534 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4535 {
4536 /* Disable the CRYP peripheral clock */
4537 __HAL_CRYP_DISABLE(hcryp);
4538
4539 /* Change state */
4540 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4541 hcryp->State = HAL_CRYP_STATE_READY;
4542
4543 /* Process unlocked */
4544 __HAL_UNLOCK(hcryp);
4545 return HAL_ERROR;
4546 }
4547 /* Clear CCF Flag */
4548 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4549 }
4550 /* Last block optionally pad the data with zeros*/
4551 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4552 {
4553 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4554 hcryp->CrypHeaderCount++ ;
4555 }
4556 while (loopcounter < 4U)
4557 {
4558 /* Pad the data with zeros to have a complete block */
4559 hcryp->Instance->DINR = 0x0U;
4560 loopcounter++;
4561 }
4562
4563 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4564 {
4565 /* Disable the CRYP peripheral clock */
4566 __HAL_CRYP_DISABLE(hcryp);
4567
4568 /* Change state */
4569 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4570 hcryp->State = HAL_CRYP_STATE_READY;
4571
4572 /* Process unlocked */
4573 __HAL_UNLOCK(hcryp);
4574 return HAL_ERROR;
4575 }
4576 /* Clear CCF flag */
4577 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4578 }
4579 }
4580 } /* if (DoKeyIVConfig == 1U) */
4581 /* Then the payload: cleartext payload (not the ciphertext payload).
4582 Write input Data, no output Data to get */
4583 if (hcryp->Size != 0U)
4584 {
4585 if ((hcryp->Size % 16U) != 0U)
4586 {
4587 /* recalculate wordsize */
4588 wordsize = ((wordsize / 4U) * 4U) ;
4589 }
4590
4591 /* Get tick */
4592 tickstart = HAL_GetTick();
4593 /*Temporary CrypOutCount Value*/
4594 outcount = hcryp->CrypOutCount;
4595
4596 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4597 {
4598 /* Write plain data and get cipher data */
4599 CRYP_AES_ProcessData(hcryp, Timeout);
4600
4601 /*Temporary CrypOutCount Value*/
4602 outcount = hcryp->CrypOutCount;
4603
4604 /* Check for the Timeout */
4605 if (Timeout != HAL_MAX_DELAY)
4606 {
4607 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4608 {
4609 /* Disable the CRYP peripheral clock */
4610 __HAL_CRYP_DISABLE(hcryp);
4611
4612 /* Change state */
4613 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4614 hcryp->State = HAL_CRYP_STATE_READY;
4615
4616 /* Process unlocked */
4617 __HAL_UNLOCK(hcryp);
4618 return HAL_ERROR;
4619 }
4620 }
4621 }
4622
4623 if ((hcryp->Size % 16U) != 0U)
4624 {
4625 /* Compute the number of padding bytes in last block of payload */
4626 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4627
4628 /* Number of valid words (lastwordsize) in last block */
4629 if ((npblb % 4U) == 0U)
4630 {
4631 lastwordsize = (16U - npblb) / 4U;
4632 }
4633 else
4634 {
4635 lastwordsize = ((16U - npblb) / 4U) + 1U;
4636 }
4637 /* Last block optionally pad the data with zeros*/
4638 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
4639 {
4640 /* Write the last input block in the IN FIFO */
4641 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4642 hcryp->CrypInCount++;
4643 }
4644 while (loopcounter < 4U)
4645 {
4646 /* Pad the data with zeros to have a complete block */
4647 hcryp->Instance->DINR = 0U;
4648 loopcounter++;
4649 }
4650 /* Wait for CCF flag to be raised */
4651 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4652 {
4653 /* Disable the CRYP peripheral clock */
4654 __HAL_CRYP_DISABLE(hcryp);
4655
4656 /* Change state */
4657 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4658 hcryp->State = HAL_CRYP_STATE_READY;
4659
4660 /* Process unlocked */
4661 __HAL_UNLOCK(hcryp);
4662 return HAL_ERROR;
4663 }
4664 /* Clear CCF flag */
4665 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4666
4667 }
4668 }
4669 #endif /* End AES or CRYP */
4670
4671 #if defined(CRYP)
4672
4673 /************************* Header phase *************************************/
4674 /* Header block(B1) : associated data length expressed in bytes concatenated
4675 with Associated Data (A)*/
4676
4677 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4678 {
4679 return HAL_ERROR;
4680 }
4681
4682 /********************** Payload phase ***************************************/
4683
4684 /* Set the phase */
4685 hcryp->Phase = CRYP_PHASE_PROCESS;
4686
4687 /* Disable the CRYP peripheral */
4688 __HAL_CRYP_DISABLE(hcryp);
4689
4690 /* Select payload phase once the header phase is performed */
4691 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4692
4693 /* Enable the CRYP peripheral */
4694 __HAL_CRYP_ENABLE(hcryp);
4695
4696 } /* if (DoKeyIVConfig == 1U) */
4697
4698 if ((hcryp->Size % 16U) != 0U)
4699 {
4700 /* recalculate wordsize */
4701 wordsize = ((wordsize / 4U) * 4U) ;
4702 }
4703 /* Get tick */
4704 tickstart = HAL_GetTick();
4705 /*Temporary CrypOutCount Value*/
4706 outcount = hcryp->CrypOutCount;
4707
4708 /* Write input data and get output data */
4709 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4710 {
4711 /* Write plain data and get cipher data */
4712 CRYP_AES_ProcessData(hcryp, Timeout);
4713
4714 /* Check for the Timeout */
4715 if (Timeout != HAL_MAX_DELAY)
4716 {
4717 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4718 {
4719 /* Disable the CRYP peripheral clock */
4720 __HAL_CRYP_DISABLE(hcryp);
4721
4722 /* Change state */
4723 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4724 hcryp->State = HAL_CRYP_STATE_READY;
4725
4726 /* Process unlocked */
4727 __HAL_UNLOCK(hcryp);
4728 return HAL_ERROR;
4729 }
4730 }
4731 }
4732
4733 if ((hcryp->Size % 16U) != 0U)
4734 {
4735 /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
4736 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
4737 is selected, then the TAG message will be wrong.*/
4738 CRYP_Workaround(hcryp, Timeout);
4739 }
4740 #endif /* CRYP */
4741
4742 /* Return function status */
4743 return HAL_OK;
4744 }
4745
4746 /**
4747 * @brief AES CCM encryption/decryption process in interrupt mode
4748 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4749 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4750 * the configuration information for CRYP module
4751 * @retval HAL status
4752 */
4753 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4754 {
4755 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4756 #if defined(CRYP)
4757 __IO uint32_t count = 0U;
4758 #endif /* CRYP */
4759
4760 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4761 {
4762 if (hcryp->KeyIVConfig == 1U)
4763 {
4764 /* If the Key and IV configuration has to be done only once
4765 and if it has already been done, skip it */
4766 DoKeyIVConfig = 0U;
4767 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4768 }
4769 else
4770 {
4771 /* If the Key and IV configuration has to be done only once
4772 and if it has not been done already, do it and set KeyIVConfig
4773 to keep track it won't have to be done again next time */
4774 hcryp->KeyIVConfig = 1U;
4775 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4776 }
4777 }
4778 else
4779 {
4780 hcryp->SizesSum = hcryp->Size;
4781 }
4782
4783 /* Configure Key, IV and process message (header and payload) */
4784 if (DoKeyIVConfig == 1U)
4785 {
4786 /* Reset CrypHeaderCount */
4787 hcryp->CrypHeaderCount = 0U;
4788
4789 #if defined(CRYP)
4790
4791 /************ Init phase ************/
4792
4793 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4794
4795 /* Set the key */
4796 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4797
4798 /* Set the initialization vector (IV) with CTR1 information */
4799 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4800 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4801 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4802 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4803
4804 /* Enable the CRYP peripheral */
4805 __HAL_CRYP_ENABLE(hcryp);
4806
4807 /*Write the B0 packet into CRYP_DIN Register*/
4808 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4809 {
4810 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4811 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4812 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4813 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4814 }
4815 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4816 {
4817 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4818 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4819 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4820 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4821 }
4822 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4823 {
4824 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4825 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4826 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4827 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4828 }
4829 else
4830 {
4831 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4832 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4833 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4834 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4835 }
4836 /*Wait for the CRYPEN bit to be cleared*/
4837 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4838 do
4839 {
4840 count-- ;
4841 if (count == 0U)
4842 {
4843 /* Disable the CRYP peripheral clock */
4844 __HAL_CRYP_DISABLE(hcryp);
4845
4846 /* Change state */
4847 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4848 hcryp->State = HAL_CRYP_STATE_READY;
4849
4850 /* Process unlocked */
4851 __HAL_UNLOCK(hcryp);
4852 return HAL_ERROR;
4853 }
4854 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4855
4856 /* Select header phase */
4857 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4858
4859 } /* end of if (DoKeyIVConfig == 1U) */
4860
4861 /* Enable interrupts */
4862 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4863
4864 /* Enable CRYP */
4865 __HAL_CRYP_ENABLE(hcryp);
4866
4867 #else /* AES */
4868
4869 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4870 /* Select header phase */
4871 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4872
4873 /* configured mode and encryption mode */
4874 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4875
4876 /* Set the key */
4877 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4878
4879 /* Set the initialization vector with zero values*/
4880 hcryp->Instance->IVR3 = 0U;
4881 hcryp->Instance->IVR2 = 0U;
4882 hcryp->Instance->IVR1 = 0U;
4883 hcryp->Instance->IVR0 = 0U;
4884
4885 /* Enable interrupts */
4886 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4887 /* Enable the CRYP peripheral */
4888 __HAL_CRYP_ENABLE(hcryp);
4889
4890 /*Write the B0 packet into CRYP_DIN*/
4891 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4892 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4893 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4894 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4895
4896 } /* end of if (DoKeyIVConfig == 1U) */
4897 #endif /* End AES or CRYP */
4898
4899 /* Return function status */
4900 return HAL_OK;
4901 }
4902 /**
4903 * @brief AES CCM encryption/decryption process in DMA mode
4904 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4905 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4906 * the configuration information for CRYP module
4907 * @retval HAL status
4908 */
4909 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4910 {
4911 uint32_t wordsize;
4912 __IO uint32_t count = 0U;
4913 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4914 #if defined(AES)
4915 uint32_t loopcounter;
4916 uint32_t npblb;
4917 uint32_t lastwordsize;
4918 #endif
4919
4920 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4921 {
4922 if (hcryp->KeyIVConfig == 1U)
4923 {
4924 /* If the Key and IV configuration has to be done only once
4925 and if it has already been done, skip it */
4926 DoKeyIVConfig = 0U;
4927 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4928 }
4929 else
4930 {
4931 /* If the Key and IV configuration has to be done only once
4932 and if it has not been done already, do it and set KeyIVConfig
4933 to keep track it won't have to be done again next time */
4934 hcryp->KeyIVConfig = 1U;
4935 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4936 }
4937 }
4938 else
4939 {
4940 hcryp->SizesSum = hcryp->Size;
4941 }
4942
4943 if (DoKeyIVConfig == 1U)
4944 {
4945
4946 /* Reset CrypHeaderCount */
4947 hcryp->CrypHeaderCount = 0U;
4948
4949 #if defined(CRYP)
4950
4951 /************************** Init phase **************************************/
4952
4953 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4954
4955 /* Set the key */
4956 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4957
4958 /* Set the initialization vector (IV) with CTR1 information */
4959 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4960 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4961 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4962 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4963
4964 /* Enable the CRYP peripheral */
4965 __HAL_CRYP_ENABLE(hcryp);
4966
4967 /*Write the B0 packet into CRYP_DIN Register*/
4968 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4969 {
4970 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4971 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4972 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4973 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4974 }
4975 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4976 {
4977 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4978 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4979 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4980 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4981 }
4982 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4983 {
4984 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4985 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4986 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4987 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4988 }
4989 else
4990 {
4991 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4992 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4993 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4994 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4995 }
4996
4997 /*Wait for the CRYPEN bit to be cleared*/
4998 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4999 do
5000 {
5001 count-- ;
5002 if (count == 0U)
5003 {
5004 /* Disable the CRYP peripheral clock */
5005 __HAL_CRYP_DISABLE(hcryp);
5006
5007 /* Change state */
5008 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5009 hcryp->State = HAL_CRYP_STATE_READY;
5010
5011 /* Process unlocked */
5012 __HAL_UNLOCK(hcryp);
5013 return HAL_ERROR;
5014 }
5015 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
5016
5017 #else /* AES */
5018
5019 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
5020 /* Select header phase */
5021 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5022
5023 /* configured encryption mode */
5024 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
5025
5026 /* Set the key */
5027 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5028
5029 /* Set the initialization vector with zero values*/
5030 hcryp->Instance->IVR3 = 0U;
5031 hcryp->Instance->IVR2 = 0U;
5032 hcryp->Instance->IVR1 = 0U;
5033 hcryp->Instance->IVR0 = 0U;
5034
5035 /* Enable the CRYP peripheral */
5036 __HAL_CRYP_ENABLE(hcryp);
5037
5038 /*Write the B0 packet into CRYP_DIN*/
5039 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
5040 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
5041 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
5042 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
5043
5044 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5045 do
5046 {
5047 count-- ;
5048 if (count == 0U)
5049 {
5050 /* Disable the CRYP peripheral clock */
5051 __HAL_CRYP_DISABLE(hcryp);
5052
5053 /* Change state */
5054 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5055 hcryp->State = HAL_CRYP_STATE_READY;
5056
5057 /* Process Unlocked */
5058 __HAL_UNLOCK(hcryp);
5059 return HAL_ERROR;
5060 }
5061 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5062 /* Clear CCF flag */
5063 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5064
5065 /* Set the phase */
5066 hcryp->Phase = CRYP_PHASE_PROCESS;
5067
5068 /* From that point the whole message must be processed, first the Header then the payload.
5069 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
5070
5071 if (hcryp->Init.HeaderSize != 0U)
5072 {
5073 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5074 {
5075 /* HeaderSize %4, no padding */
5076 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5077 {
5078 /* Write the Input block in the Data Input register */
5079 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5080 hcryp->CrypHeaderCount++ ;
5081 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5082 hcryp->CrypHeaderCount++ ;
5083 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5084 hcryp->CrypHeaderCount++ ;
5085 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5086 hcryp->CrypHeaderCount++ ;
5087
5088 /* wait until the end of computation */
5089 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5090 do
5091 {
5092 count-- ;
5093 if (count == 0U)
5094 {
5095 /* Disable the CRYP peripheral clock */
5096 __HAL_CRYP_DISABLE(hcryp);
5097
5098 /* Change state */
5099 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5100 hcryp->State = HAL_CRYP_STATE_READY;
5101
5102 /* Process Unlocked */
5103 __HAL_UNLOCK(hcryp);
5104 return HAL_ERROR;
5105 }
5106 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5107 /* Clear CCF flag */
5108 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5109 }
5110 }
5111 else
5112 {
5113 /*Write Header block in the IN FIFO without last block */
5114 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5115 {
5116 /* Write the input block in the data input register */
5117 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5118 hcryp->CrypHeaderCount++ ;
5119 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5120 hcryp->CrypHeaderCount++ ;
5121 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5122 hcryp->CrypHeaderCount++ ;
5123 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5124 hcryp->CrypHeaderCount++ ;
5125
5126 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5127 do
5128 {
5129 count-- ;
5130 if (count == 0U)
5131 {
5132 /* Disable the CRYP peripheral clock */
5133 __HAL_CRYP_DISABLE(hcryp);
5134
5135 /* Change state */
5136 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5137 hcryp->State = HAL_CRYP_STATE_READY;
5138
5139 /* Process Unlocked */
5140 __HAL_UNLOCK(hcryp);
5141 return HAL_ERROR;
5142 }
5143 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5144 /* Clear CCF flag */
5145 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5146 }
5147 /* Last block optionally pad the data with zeros*/
5148 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5149 {
5150 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5151 hcryp->CrypHeaderCount++ ;
5152 }
5153 while (loopcounter < 4U)
5154 {
5155 /* Pad the data with zeros to have a complete block */
5156 hcryp->Instance->DINR = 0x0U;
5157 loopcounter++;
5158 }
5159
5160 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5161 do
5162 {
5163 count-- ;
5164 if (count == 0U)
5165 {
5166 /* Disable the CRYP peripheral clock */
5167 __HAL_CRYP_DISABLE(hcryp);
5168
5169 /* Change state */
5170 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5171 hcryp->State = HAL_CRYP_STATE_READY;
5172
5173 /* Process Unlocked */
5174 __HAL_UNLOCK(hcryp);
5175 return HAL_ERROR;
5176 }
5177 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5178 /* Clear CCF flag */
5179 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5180 }
5181 }
5182 } /* if (DoKeyIVConfig == 1U) */
5183 /* Then the payload: cleartext payload (not the ciphertext payload).
5184 Write input Data, no output Data to get */
5185 if (hcryp->Size != 0U)
5186 {
5187 if (hcryp->Size >= 16U)
5188 {
5189 if ((hcryp->Size % 16U) == 0U)
5190 {
5191 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
5192 }
5193 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
5194 {
5195 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
5196
5197 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
5198 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
5199 (uint32_t)(hcryp->pCrypOutBuffPtr));
5200 }
5201 }
5202 if ((hcryp->Size < 16U) != 0U)
5203 {
5204 /* Compute the number of padding bytes in last block of payload */
5205 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5206
5207 /* Number of valid words (lastwordsize) in last block */
5208 if ((npblb % 4U) == 0U)
5209 {
5210 lastwordsize = (16U - npblb) / 4U;
5211 }
5212 else
5213 {
5214 lastwordsize = ((16U - npblb) / 4U) + 1U;
5215 }
5216 /* Last block optionally pad the data with zeros*/
5217 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
5218 {
5219 /* Write the last input block in the IN FIFO */
5220 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5221 hcryp->CrypInCount++;
5222 }
5223 while (loopcounter < 4U)
5224 {
5225 /* Pad the data with zeros to have a complete block */
5226 hcryp->Instance->DINR = 0U;
5227 loopcounter++;
5228 }
5229 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5230 do
5231 {
5232 count-- ;
5233 if (count == 0U)
5234 {
5235 /* Disable the CRYP peripheral clock */
5236 __HAL_CRYP_DISABLE(hcryp);
5237
5238 /* Change state */
5239 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5240 hcryp->State = HAL_CRYP_STATE_READY;
5241
5242 /* Process Unlocked */
5243 __HAL_UNLOCK(hcryp);
5244 return HAL_ERROR;
5245 }
5246 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5247 /* Clear CCF flag */
5248 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5249
5250 /* Process unlocked */
5251 __HAL_UNLOCK(hcryp);
5252
5253 /* Change the CRYP state and phase */
5254 hcryp->State = HAL_CRYP_STATE_READY;
5255 }
5256 }
5257 else
5258 {
5259 /* Process unLocked */
5260 __HAL_UNLOCK(hcryp);
5261
5262 /* Change the CRYP state and phase */
5263 hcryp->State = HAL_CRYP_STATE_READY;
5264 }
5265 #endif /* AES */
5266 #if defined(CRYP)
5267 /********************* Header phase *****************************************/
5268
5269 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5270 {
5271 return HAL_ERROR;
5272 }
5273
5274 /******************** Payload phase *****************************************/
5275
5276 /* Set the phase */
5277 hcryp->Phase = CRYP_PHASE_PROCESS;
5278
5279 /* Disable the CRYP peripheral */
5280 __HAL_CRYP_DISABLE(hcryp);
5281
5282 /* Select payload phase once the header phase is performed */
5283 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5284
5285 } /* if (DoKeyIVConfig == 1U) */
5286 if (hcryp->Size != 0U)
5287 {
5288 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
5289 Workaround is implemented in polling mode, so if last block of
5290 payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
5291 /* Set the input and output addresses and start DMA transfer */
5292 if ((hcryp->Size % 16U) == 0U)
5293 {
5294 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
5295 }
5296 else
5297 {
5298 wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
5299
5300 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
5301 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
5302 (uint32_t)(hcryp->pCrypOutBuffPtr));
5303 }
5304 }
5305 else /*Size = 0*/
5306 {
5307 /* Process unlocked */
5308 __HAL_UNLOCK(hcryp);
5309
5310 /* Change the CRYP state and phase */
5311 hcryp->State = HAL_CRYP_STATE_READY;
5312 }
5313 #endif /* CRYP */
5314 /* Return function status */
5315 return HAL_OK;
5316 }
5317
5318 /**
5319 * @brief Sets the payload phase in iterrupt mode
5320 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5321 * the configuration information for CRYP module
5322 * @retval state
5323 */
5324 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
5325 {
5326 uint32_t loopcounter;
5327 uint32_t temp[4]; /* Temporary CrypOutBuff */
5328 uint32_t lastwordsize;
5329 uint32_t npblb;
5330 uint32_t i;
5331 #if defined(AES)
5332 uint16_t outcount; /* Temporary CrypOutCount Value */
5333 #endif /* AES */
5334
5335 /***************************** Payload phase *******************************/
5336
5337 #if defined(CRYP)
5338 if (hcryp->Size == 0U)
5339 {
5340 /* Disable interrupts */
5341 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
5342
5343 /* Process unlocked */
5344 __HAL_UNLOCK(hcryp);
5345
5346 /* Change the CRYP state */
5347 hcryp->State = HAL_CRYP_STATE_READY;
5348 }
5349
5350 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5351 {
5352 /* Write the input block in the IN FIFO */
5353 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5354 hcryp->CrypInCount++;
5355 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5356 hcryp->CrypInCount++;
5357 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5358 hcryp->CrypInCount++;
5359 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5360 hcryp->CrypInCount++;
5361 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
5362 {
5363 /* Disable interrupts */
5364 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5365
5366 /* Call the input data transfer complete callback */
5367 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5368 /*Call registered Input complete callback*/
5369 hcryp->InCpltCallback(hcryp);
5370 #else
5371 /*Call legacy weak Input complete callback*/
5372 HAL_CRYP_InCpltCallback(hcryp);
5373 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5374 }
5375 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
5376 {
5377 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
5378 for (i = 0U; i < 4U; i++)
5379 {
5380 temp[i] = hcryp->Instance->DOUT;
5381 }
5382 i = 0U;
5383 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5384 {
5385 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5386 hcryp->CrypOutCount++;
5387 i++;
5388 }
5389 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
5390 {
5391 /* Disable interrupts */
5392 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
5393
5394 /* Change the CRYP state */
5395 hcryp->State = HAL_CRYP_STATE_READY;
5396
5397 /* Disable CRYP */
5398 __HAL_CRYP_DISABLE(hcryp);
5399
5400 /* Process unlocked */
5401 __HAL_UNLOCK(hcryp);
5402
5403 /* Call output transfer complete callback */
5404 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5405 /*Call registered Output complete callback*/
5406 hcryp->OutCpltCallback(hcryp);
5407 #else
5408 /*Call legacy weak Output complete callback*/
5409 HAL_CRYP_OutCpltCallback(hcryp);
5410 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5411 }
5412 }
5413 }
5414 else if ((hcryp->Size % 16U) != 0U)
5415 {
5416 /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
5417 Workaround is implemented in polling mode, so if last block of
5418 payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
5419
5420 /* Compute the number of padding bytes in last block of payload */
5421 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5422
5423 /* Number of valid words (lastwordsize) in last block */
5424 if ((npblb % 4U) == 0U)
5425 {
5426 lastwordsize = (16U - npblb) / 4U;
5427 }
5428 else
5429 {
5430 lastwordsize = ((16U - npblb) / 4U) + 1U;
5431 }
5432
5433 /* Last block optionally pad the data with zeros*/
5434 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5435 {
5436 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5437 hcryp->CrypInCount++;
5438 }
5439 while (loopcounter < 4U)
5440 {
5441 /* Pad the data with zeros to have a complete block */
5442 hcryp->Instance->DIN = 0x0U;
5443 loopcounter++;
5444 }
5445 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5446
5447 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
5448 {
5449 for (i = 0U; i < 4U; i++)
5450 {
5451 temp[i] = hcryp->Instance->DOUT;
5452 }
5453 if (((hcryp->Size) / 4U) == 0U)
5454 {
5455 for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
5456 {
5457 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5458 hcryp->CrypOutCount++;
5459 }
5460 }
5461 i = 0x0U;
5462 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5463 {
5464 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5465 hcryp->CrypOutCount++;
5466 i++;
5467 }
5468 }
5469 if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
5470 {
5471 /* Disable interrupts */
5472 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
5473
5474 /* Change the CRYP peripheral state */
5475 hcryp->State = HAL_CRYP_STATE_READY;
5476
5477 /* Process unlocked */
5478 __HAL_UNLOCK(hcryp);
5479
5480 /* Call output transfer complete callback */
5481 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5482 /*Call registered Output complete callback*/
5483 hcryp->OutCpltCallback(hcryp);
5484 #else
5485 /*Call legacy weak Output complete callback*/
5486 HAL_CRYP_OutCpltCallback(hcryp);
5487 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5488 }
5489 }
5490 else
5491 {
5492 /* Nothing to do */
5493 }
5494 #else /* AES */
5495
5496 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
5497 for (i = 0U; i < 4U; i++)
5498 {
5499 temp[i] = hcryp->Instance->DOUTR;
5500 }
5501 i = 0U;
5502 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
5503 {
5504 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5505 hcryp->CrypOutCount++;
5506 i++;
5507 }
5508 /*Temporary CrypOutCount Value*/
5509 outcount = hcryp->CrypOutCount;
5510
5511 if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
5512 {
5513 /* Disable computation complete flag and errors interrupts */
5514 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
5515
5516 /* Change the CRYP state */
5517 hcryp->State = HAL_CRYP_STATE_READY;
5518
5519 /* Process unlocked */
5520 __HAL_UNLOCK(hcryp);
5521
5522 /* Call output transfer complete callback */
5523 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5524 /*Call registered Output complete callback*/
5525 hcryp->OutCpltCallback(hcryp);
5526 #else
5527 /*Call legacy weak Output complete callback*/
5528 HAL_CRYP_OutCpltCallback(hcryp);
5529 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5530 }
5531
5532 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5533 {
5534 /* Write the input block in the IN FIFO */
5535 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5536 hcryp->CrypInCount++;
5537 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5538 hcryp->CrypInCount++;
5539 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5540 hcryp->CrypInCount++;
5541 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5542 hcryp->CrypInCount++;
5543 if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
5544 {
5545 /* Call Input transfer complete callback */
5546 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5547 /*Call registered Input complete callback*/
5548 hcryp->InCpltCallback(hcryp);
5549 #else
5550 /*Call legacy weak Input complete callback*/
5551 HAL_CRYP_InCpltCallback(hcryp);
5552 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5553 }
5554 }
5555 else /* Last block of payload < 128bit*/
5556 {
5557 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5558 generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
5559 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
5560
5561 /* Compute the number of padding bytes in last block of payload */
5562 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5563
5564 /* Number of valid words (lastwordsize) in last block */
5565 if ((npblb % 4U) == 0U)
5566 {
5567 lastwordsize = (16U - npblb) / 4U;
5568 }
5569 else
5570 {
5571 lastwordsize = ((16U - npblb) / 4U) + 1U;
5572 }
5573
5574 /* Last block optionally pad the data with zeros*/
5575 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5576 {
5577 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5578 hcryp->CrypInCount++;
5579 }
5580 while (loopcounter < 4U)
5581 {
5582 /* pad the data with zeros to have a complete block */
5583 hcryp->Instance->DINR = 0x0U;
5584 loopcounter++;
5585 }
5586 }
5587 #endif /* AES */
5588
5589 }
5590
5591
5592 /**
5593 * @brief Sets the header phase in polling mode
5594 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5595 * the configuration information for CRYP module(Header & HeaderSize)
5596 * @param Timeout: Timeout value
5597 * @retval state
5598 */
5599 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5600 {
5601 uint32_t loopcounter;
5602
5603 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5604
5605 if ((hcryp->Init.HeaderSize != 0U))
5606 {
5607
5608 #if defined(CRYP)
5609
5610 /* Select header phase */
5611 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5612
5613 /* Enable the CRYP peripheral */
5614 __HAL_CRYP_ENABLE(hcryp);
5615
5616 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5617 {
5618 /* HeaderSize %4, no padding */
5619 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5620 {
5621 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5622 hcryp->CrypHeaderCount++ ;
5623 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5624 hcryp->CrypHeaderCount++ ;
5625 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5626 hcryp->CrypHeaderCount++ ;
5627 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5628 hcryp->CrypHeaderCount++ ;
5629
5630 /* Wait for IFEM to be raised */
5631 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5632 {
5633 /* Disable the CRYP peripheral clock */
5634 __HAL_CRYP_DISABLE(hcryp);
5635
5636 /* Change state */
5637 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5638 hcryp->State = HAL_CRYP_STATE_READY;
5639
5640 /* Process unlocked */
5641 __HAL_UNLOCK(hcryp);
5642 return HAL_ERROR;
5643 }
5644 }
5645 }
5646 else
5647 {
5648 /*Write header block in the IN FIFO without last block */
5649 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5650 {
5651 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5652 hcryp->CrypHeaderCount++ ;
5653 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5654 hcryp->CrypHeaderCount++ ;
5655 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5656 hcryp->CrypHeaderCount++ ;
5657 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5658 hcryp->CrypHeaderCount++ ;
5659
5660 /* Wait for IFEM to be raised */
5661 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5662 {
5663 /* Disable the CRYP peripheral clock */
5664 __HAL_CRYP_DISABLE(hcryp);
5665
5666 /* Change state */
5667 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5668 hcryp->State = HAL_CRYP_STATE_READY;
5669
5670 /* Process unlocked */
5671 __HAL_UNLOCK(hcryp);
5672 return HAL_ERROR;
5673 }
5674 }
5675 /* Last block optionally pad the data with zeros*/
5676 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5677 {
5678 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5679 hcryp->CrypHeaderCount++ ;
5680 }
5681 while (loopcounter < 4U)
5682 {
5683 /* pad the data with zeros to have a complete block */
5684 hcryp->Instance->DIN = 0x0U;
5685 loopcounter++;
5686 }
5687 /* Wait for CCF IFEM to be raised */
5688 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5689 {
5690 /* Disable the CRYP peripheral clock */
5691 __HAL_CRYP_DISABLE(hcryp);
5692
5693 /* Change state */
5694 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5695 hcryp->State = HAL_CRYP_STATE_READY;
5696
5697 /* Process unlocked */
5698 __HAL_UNLOCK(hcryp);
5699 return HAL_ERROR;
5700 }
5701 }
5702 /* Wait until the complete message has been processed */
5703 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5704 {
5705 /* Disable the CRYP peripheral clock */
5706 __HAL_CRYP_DISABLE(hcryp);
5707
5708 /* Change state */
5709 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5710 hcryp->State = HAL_CRYP_STATE_READY;
5711
5712 /* Process unlocked & return error */
5713 __HAL_UNLOCK(hcryp);
5714 return HAL_ERROR;
5715 }
5716
5717 #else /* AES */
5718
5719 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5720 {
5721 /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5722 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5723
5724 /* Select header phase */
5725 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5726
5727 /* Enable the CRYP peripheral */
5728 __HAL_CRYP_ENABLE(hcryp);
5729
5730 }
5731 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5732 {
5733 /* HeaderSize %4, no padding */
5734 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5735 {
5736 /* Write the input block in the data input register */
5737 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5738 hcryp->CrypHeaderCount++ ;
5739 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5740 hcryp->CrypHeaderCount++ ;
5741 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5742 hcryp->CrypHeaderCount++ ;
5743 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5744 hcryp->CrypHeaderCount++ ;
5745
5746 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5747 {
5748 /* Disable the CRYP peripheral clock */
5749 __HAL_CRYP_DISABLE(hcryp);
5750
5751 /* Change state */
5752 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5753 hcryp->State = HAL_CRYP_STATE_READY;
5754
5755 /* Process unlocked */
5756 __HAL_UNLOCK(hcryp);
5757 return HAL_ERROR;
5758 }
5759 /* Clear CCF flag */
5760 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5761 }
5762 }
5763 else
5764 {
5765 /*Write header block in the IN FIFO without last block */
5766 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5767 {
5768 /* Write the input block in the data input register */
5769 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5770 hcryp->CrypHeaderCount++ ;
5771 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5772 hcryp->CrypHeaderCount++ ;
5773 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5774 hcryp->CrypHeaderCount++ ;
5775 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5776 hcryp->CrypHeaderCount++ ;
5777
5778 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5779 {
5780 /* Disable the CRYP peripheral clock */
5781 __HAL_CRYP_DISABLE(hcryp);
5782
5783 /* Change state */
5784 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5785 hcryp->State = HAL_CRYP_STATE_READY;
5786
5787 /* Process unlocked */
5788 __HAL_UNLOCK(hcryp);
5789 return HAL_ERROR;
5790 }
5791 /* Clear CCF flag */
5792 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5793 }
5794 /* Last block optionally pad the data with zeros*/
5795 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5796 {
5797 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5798 hcryp->CrypHeaderCount++ ;
5799 }
5800 while (loopcounter < 4U)
5801 {
5802 /*Pad the data with zeros to have a complete block */
5803 hcryp->Instance->DINR = 0x0U;
5804 loopcounter++;
5805 }
5806
5807 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5808 {
5809 /* Disable the CRYP peripheral clock */
5810 __HAL_CRYP_DISABLE(hcryp);
5811
5812 /* Change state */
5813 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5814 hcryp->State = HAL_CRYP_STATE_READY;
5815
5816 /* Process unlocked */
5817 __HAL_UNLOCK(hcryp);
5818 return HAL_ERROR;
5819 }
5820 /* Clear CCF flag */
5821 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5822 }
5823 #endif /* End AES or CRYP */
5824 }
5825 else
5826 {
5827 #if defined(AES)
5828 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5829 {
5830 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5831 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5832
5833 /* Select header phase */
5834 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5835
5836 /* Enable the CRYP peripheral */
5837 __HAL_CRYP_ENABLE(hcryp);
5838 }
5839 #endif /* AES */
5840 }
5841 /* Return function status */
5842 return HAL_OK;
5843 }
5844
5845 /**
5846 * @brief Sets the header phase when using DMA in process
5847 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5848 * the configuration information for CRYP module(Header & HeaderSize)
5849 * @retval None
5850 */
5851 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5852 {
5853 __IO uint32_t count = 0U;
5854 uint32_t loopcounter;
5855
5856 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5857 if ((hcryp->Init.HeaderSize != 0U))
5858 {
5859
5860 #if defined(CRYP)
5861
5862 /* Select header phase */
5863 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5864
5865 /* Enable the CRYP peripheral */
5866 __HAL_CRYP_ENABLE(hcryp);
5867
5868 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5869 {
5870 /* HeaderSize %4, no padding */
5871 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5872 {
5873 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5874 hcryp->CrypHeaderCount++ ;
5875 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5876 hcryp->CrypHeaderCount++ ;
5877 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5878 hcryp->CrypHeaderCount++ ;
5879 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5880 hcryp->CrypHeaderCount++ ;
5881
5882 /* Wait for IFEM to be raised */
5883 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5884 do
5885 {
5886 count-- ;
5887 if (count == 0U)
5888 {
5889 /* Disable the CRYP peripheral clock */
5890 __HAL_CRYP_DISABLE(hcryp);
5891
5892 /* Change state */
5893 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5894 hcryp->State = HAL_CRYP_STATE_READY;
5895
5896 /* Process unlocked */
5897 __HAL_UNLOCK(hcryp);
5898 return HAL_ERROR;
5899 }
5900 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5901 }
5902 }
5903 else
5904 {
5905 /*Write header block in the IN FIFO without last block */
5906 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5907 {
5908 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5909 hcryp->CrypHeaderCount++ ;
5910 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5911 hcryp->CrypHeaderCount++ ;
5912 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5913 hcryp->CrypHeaderCount++ ;
5914 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5915 hcryp->CrypHeaderCount++ ;
5916
5917 /* Wait for IFEM to be raised */
5918 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5919 do
5920 {
5921 count-- ;
5922 if (count == 0U)
5923 {
5924 /* Disable the CRYP peripheral clock */
5925 __HAL_CRYP_DISABLE(hcryp);
5926
5927 /* Change state */
5928 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5929 hcryp->State = HAL_CRYP_STATE_READY;
5930
5931 /* Process unlocked */
5932 __HAL_UNLOCK(hcryp);
5933 return HAL_ERROR;
5934 }
5935 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5936 }
5937 /* Last block optionally pad the data with zeros*/
5938 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5939 {
5940 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5941 hcryp->CrypHeaderCount++ ;
5942 }
5943 while (loopcounter < 4U)
5944 {
5945 /* Pad the data with zeros to have a complete block */
5946 hcryp->Instance->DIN = 0x0U;
5947 loopcounter++;
5948 }
5949 /* Wait for IFEM to be raised */
5950 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5951 do
5952 {
5953 count-- ;
5954 if (count == 0U)
5955 {
5956 /* Disable the CRYP peripheral clock */
5957 __HAL_CRYP_DISABLE(hcryp);
5958
5959 /* Change state */
5960 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5961 hcryp->State = HAL_CRYP_STATE_READY;
5962
5963 /* Process unlocked */
5964 __HAL_UNLOCK(hcryp);
5965 return HAL_ERROR;
5966 }
5967 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5968 }
5969 /* Wait until the complete message has been processed */
5970 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5971 do
5972 {
5973 count-- ;
5974 if (count == 0U)
5975 {
5976 /* Disable the CRYP peripheral clock */
5977 __HAL_CRYP_DISABLE(hcryp);
5978
5979 /* Change state */
5980 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5981 hcryp->State = HAL_CRYP_STATE_READY;
5982
5983 /* Process unlocked */
5984 __HAL_UNLOCK(hcryp);
5985 return HAL_ERROR;
5986 }
5987 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
5988
5989 #else /* AES */
5990
5991 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5992 {
5993 /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5994 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5995
5996 /* Select header phase */
5997 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5998
5999 /* Enable the CRYP peripheral */
6000 __HAL_CRYP_ENABLE(hcryp);
6001 }
6002 if ((hcryp->Init.HeaderSize % 4U) == 0U)
6003 {
6004 /* HeaderSize %4, no padding */
6005 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
6006 {
6007 /* Write the input block in the data input register */
6008 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6009 hcryp->CrypHeaderCount++ ;
6010 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6011 hcryp->CrypHeaderCount++ ;
6012 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6013 hcryp->CrypHeaderCount++ ;
6014 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6015 hcryp->CrypHeaderCount++ ;
6016
6017 /*Wait on CCF flag*/
6018 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6019 do
6020 {
6021 count-- ;
6022 if (count == 0U)
6023 {
6024 /* Disable the CRYP peripheral clock */
6025 __HAL_CRYP_DISABLE(hcryp);
6026
6027 /* Change state */
6028 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6029 hcryp->State = HAL_CRYP_STATE_READY;
6030
6031 /* Process unlocked */
6032 __HAL_UNLOCK(hcryp);
6033 return HAL_ERROR;
6034 }
6035 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6036
6037 /* Clear CCF flag */
6038 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6039 }
6040 }
6041 else
6042 {
6043 /*Write header block in the IN FIFO without last block */
6044 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
6045 {
6046 /* Write the Input block in the Data Input register */
6047 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6048 hcryp->CrypHeaderCount++ ;
6049 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6050 hcryp->CrypHeaderCount++ ;
6051 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6052 hcryp->CrypHeaderCount++ ;
6053 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6054 hcryp->CrypHeaderCount++ ;
6055
6056 /*Wait on CCF flag*/
6057 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6058 do
6059 {
6060 count-- ;
6061 if (count == 0U)
6062 {
6063 /* Disable the CRYP peripheral clock */
6064 __HAL_CRYP_DISABLE(hcryp);
6065
6066 /* Change state */
6067 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6068 hcryp->State = HAL_CRYP_STATE_READY;
6069
6070 /* Process unlocked */
6071 __HAL_UNLOCK(hcryp);
6072 return HAL_ERROR;
6073 }
6074 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6075
6076 /* Clear CCF flag */
6077 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6078 }
6079 /* Last block optionally pad the data with zeros*/
6080 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
6081 {
6082 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6083 hcryp->CrypHeaderCount++ ;
6084 }
6085 while (loopcounter < 4U)
6086 {
6087 /* Pad the data with zeros to have a complete block */
6088 hcryp->Instance->DINR = 0x0U;
6089 loopcounter++;
6090 }
6091
6092 /*Wait on CCF flag*/
6093 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6094 do
6095 {
6096 count-- ;
6097 if (count == 0U)
6098 {
6099 /* Disable the CRYP peripheral clock */
6100 __HAL_CRYP_DISABLE(hcryp);
6101
6102 /* Change state */
6103 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6104 hcryp->State = HAL_CRYP_STATE_READY;
6105
6106 /* Process unlocked */
6107 __HAL_UNLOCK(hcryp);
6108 return HAL_ERROR;
6109 }
6110 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6111
6112 /* Clear CCF flag */
6113 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6114 }
6115 #endif /* End AES or CRYP */
6116 }
6117 else
6118 {
6119 #if defined(AES)
6120 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6121 {
6122 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6123 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6124
6125 /* Select header phase */
6126 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6127
6128 /* Enable the CRYP peripheral */
6129 __HAL_CRYP_ENABLE(hcryp);
6130 }
6131 #endif /* AES */
6132 }
6133 /* Return function status */
6134 return HAL_OK;
6135 }
6136
6137 /**
6138 * @brief Sets the header phase in interrupt mode
6139 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6140 * the configuration information for CRYP module(Header & HeaderSize)
6141 * @retval None
6142 */
6143 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
6144 {
6145 uint32_t loopcounter;
6146 #if defined(AES)
6147 uint32_t lastwordsize;
6148 uint32_t npblb;
6149 #endif
6150 /***************************** Header phase *********************************/
6151
6152 #if defined(CRYP)
6153 if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
6154 {
6155 /* Disable interrupts */
6156 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6157
6158 /* Disable the CRYP peripheral */
6159 __HAL_CRYP_DISABLE(hcryp);
6160
6161 /* Set the phase */
6162 hcryp->Phase = CRYP_PHASE_PROCESS;
6163
6164 /* Select payload phase once the header phase is performed */
6165 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6166
6167 /* Enable Interrupts */
6168 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6169
6170 /* Enable the CRYP peripheral */
6171 __HAL_CRYP_ENABLE(hcryp);
6172 }
6173 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
6174
6175 {
6176 /* HeaderSize %4, no padding */
6177 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6178 hcryp->CrypHeaderCount++ ;
6179 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6180 hcryp->CrypHeaderCount++ ;
6181 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6182 hcryp->CrypHeaderCount++ ;
6183 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6184 hcryp->CrypHeaderCount++ ;
6185 }
6186 else
6187 {
6188 /* Last block optionally pad the data with zeros*/
6189 for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
6190 {
6191 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6192 hcryp->CrypHeaderCount++ ;
6193 }
6194 while (loopcounter < 4U)
6195 {
6196 /* Pad the data with zeros to have a complete block */
6197 hcryp->Instance->DIN = 0x0U;
6198 loopcounter++;
6199 }
6200 }
6201 #else /* AES */
6202
6203 if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
6204 {
6205 /* Set the phase */
6206 hcryp->Phase = CRYP_PHASE_PROCESS;
6207
6208 /* Payload phase not supported in CCM AES2 */
6209 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6210 {
6211 /* Select payload phase once the header phase is performed */
6212 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
6213 }
6214 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
6215 {
6216 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
6217 hcryp->CrypHeaderCount++;
6218 }
6219 /* Write the payload Input block in the IN FIFO */
6220 if (hcryp->Size == 0U)
6221 {
6222 /* Disable interrupts */
6223 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
6224
6225 /* Change the CRYP state */
6226 hcryp->State = HAL_CRYP_STATE_READY;
6227
6228 /* Process unlocked */
6229 __HAL_UNLOCK(hcryp);
6230 }
6231 else if (hcryp->Size >= 16U)
6232 {
6233 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6234 hcryp->CrypInCount++;
6235 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6236 hcryp->CrypInCount++;
6237 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6238 hcryp->CrypInCount++;
6239 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6240 hcryp->CrypInCount++;
6241
6242 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6243 {
6244 /* Call the input data transfer complete callback */
6245 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6246 /*Call registered Input complete callback*/
6247 hcryp->InCpltCallback(hcryp);
6248 #else
6249 /*Call legacy weak Input complete callback*/
6250 HAL_CRYP_InCpltCallback(hcryp);
6251 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6252 }
6253 }
6254 else /* Size < 4 words : first block is the last block*/
6255 {
6256 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
6257 generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
6258 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
6259
6260 /* Compute the number of padding bytes in last block of payload */
6261 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6262
6263 /* Number of valid words (lastwordsize) in last block */
6264 if ((npblb % 4U) == 0U)
6265 {
6266 lastwordsize = (16U - npblb) / 4U;
6267 }
6268 else
6269 {
6270 lastwordsize = ((16U - npblb) / 4U) + 1U;
6271 }
6272
6273 /* Last block optionally pad the data with zeros*/
6274 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6275 {
6276 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6277 hcryp->CrypInCount++;
6278 }
6279 while (loopcounter < 4U)
6280 {
6281 /* Pad the data with zeros to have a complete block */
6282 hcryp->Instance->DINR = 0x0U;
6283 loopcounter++;
6284 }
6285 }
6286 }
6287 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
6288 {
6289 /* Write the input block in the IN FIFO */
6290 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6291 hcryp->CrypHeaderCount++;
6292 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6293 hcryp->CrypHeaderCount++;
6294 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6295 hcryp->CrypHeaderCount++;
6296 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6297 hcryp->CrypHeaderCount++;
6298 }
6299 else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
6300 {
6301 /* Last block optionally pad the data with zeros*/
6302 for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
6303 {
6304 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6305 hcryp->CrypHeaderCount++ ;
6306 }
6307 while (loopcounter < 4U)
6308 {
6309 /* pad the data with zeros to have a complete block */
6310 hcryp->Instance->DINR = 0x0U;
6311 loopcounter++;
6312 }
6313 }
6314 #endif /* End AES or CRYP */
6315 }
6316
6317
6318 /**
6319 * @brief Workaround used for GCM/CCM mode.
6320 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6321 * the configuration information for CRYP module
6322 * @param Timeout: specify Timeout value
6323 * @retval None
6324 */
6325 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6326 {
6327 uint32_t lastwordsize;
6328 uint32_t npblb;
6329 #if defined(CRYP)
6330 uint32_t iv1temp;
6331 uint32_t temp[4] = {0};
6332 uint32_t temp2[4] = {0};
6333 #endif /* CRYP */
6334 uint32_t intermediate_data[4] = {0};
6335 uint32_t index;
6336
6337 /* Compute the number of padding bytes in last block of payload */
6338 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6339
6340 /* Number of valid words (lastwordsize) in last block */
6341 if ((npblb % 4U) == 0U)
6342 {
6343 lastwordsize = (16U - npblb) / 4U;
6344 }
6345 else
6346 {
6347 lastwordsize = ((16U - npblb) / 4U) + 1U;
6348 }
6349
6350 #if defined(CRYP)
6351
6352 /* Workaround 2, case GCM encryption */
6353 if (hcryp->Init.Algorithm == CRYP_AES_GCM)
6354 {
6355 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6356 {
6357 /*Workaround in order to properly compute authentication tags while doing
6358 a GCM encryption with the last block of payload size inferior to 128 bits*/
6359 /* Disable CRYP to start the final phase */
6360 __HAL_CRYP_DISABLE(hcryp);
6361
6362 /*Update CRYP_IV1R register and ALGOMODE*/
6363 hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
6364 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6365
6366 /* Enable CRYP to start the final phase */
6367 __HAL_CRYP_ENABLE(hcryp);
6368 }
6369 /* Last block optionally pad the data with zeros*/
6370 for (index = 0; index < lastwordsize; index ++)
6371 {
6372 /* Write the last input block in the IN FIFO */
6373 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6374 hcryp->CrypInCount++;
6375 }
6376 while (index < 4U)
6377 {
6378 /* Pad the data with zeros to have a complete block */
6379 hcryp->Instance->DIN = 0U;
6380 index++;
6381 }
6382 /* Wait for OFNE flag to be raised */
6383 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6384 {
6385 /* Disable the CRYP peripheral clock */
6386 __HAL_CRYP_DISABLE(hcryp);
6387
6388 /* Change state */
6389 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6390 hcryp->State = HAL_CRYP_STATE_READY;
6391
6392 /* Process Unlocked */
6393 __HAL_UNLOCK(hcryp);
6394 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6395 /*Call registered error callback*/
6396 hcryp->ErrorCallback(hcryp);
6397 #else
6398 /*Call legacy weak error callback*/
6399 HAL_CRYP_ErrorCallback(hcryp);
6400 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6401 }
6402 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6403 {
6404 for (index = 0U; index < 4U; index++)
6405 {
6406 /* Read the output block from the output FIFO */
6407 intermediate_data[index] = hcryp->Instance->DOUT;
6408
6409 /* Intermediate data buffer to be used in for the workaround*/
6410 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6411 hcryp->CrypOutCount++;
6412 }
6413 }
6414
6415 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6416 {
6417 /*workaround in order to properly compute authentication tags while doing
6418 a GCM encryption with the last block of payload size inferior to 128 bits*/
6419 /* Change the AES mode to GCM mode and Select Final phase */
6420 /* configured CHMOD GCM */
6421 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
6422
6423 /* configured final phase */
6424 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
6425
6426 if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
6427 {
6428 if ((npblb % 4U) == 1U)
6429 {
6430 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6431 }
6432 if ((npblb % 4U) == 2U)
6433 {
6434 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6435 }
6436 if ((npblb % 4U) == 3U)
6437 {
6438 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6439 }
6440 }
6441 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
6442 {
6443 if ((npblb % 4U) == 1U)
6444 {
6445 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6446 }
6447 if ((npblb % 4U) == 2U)
6448 {
6449 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6450 }
6451 if ((npblb % 4U) == 3U)
6452 {
6453 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6454 }
6455 }
6456 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
6457 {
6458 if ((npblb % 4U) == 1U)
6459 {
6460 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6461 }
6462 if ((npblb % 4U) == 2U)
6463 {
6464 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6465 }
6466 if ((npblb % 4U) == 3U)
6467 {
6468 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6469 }
6470 }
6471 else /*CRYP_DATATYPE_1B*/
6472 {
6473 if ((npblb % 4U) == 1U)
6474 {
6475 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6476 }
6477 if ((npblb % 4U) == 2U)
6478 {
6479 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6480 }
6481 if ((npblb % 4U) == 3U)
6482 {
6483 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6484 }
6485 }
6486 for (index = 0U; index < lastwordsize; index ++)
6487 {
6488 /*Write the intermediate_data in the IN FIFO */
6489 hcryp->Instance->DIN = intermediate_data[index];
6490 }
6491 while (index < 4U)
6492 {
6493 /* Pad the data with zeros to have a complete block */
6494 hcryp->Instance->DIN = 0x0U;
6495 index++;
6496 }
6497 /* Wait for OFNE flag to be raised */
6498 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6499 {
6500 /* Disable the CRYP peripheral clock */
6501 __HAL_CRYP_DISABLE(hcryp);
6502
6503 /* Change state */
6504 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6505 hcryp->State = HAL_CRYP_STATE_READY;
6506
6507 /* Process unlocked */
6508 __HAL_UNLOCK(hcryp);
6509 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6510 /*Call registered error callback*/
6511 hcryp->ErrorCallback(hcryp);
6512 #else
6513 /*Call legacy weak error callback*/
6514 HAL_CRYP_ErrorCallback(hcryp);
6515 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6516 }
6517
6518 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6519 {
6520 for (index = 0U; index < 4U; index++)
6521 {
6522 intermediate_data[index] = hcryp->Instance->DOUT;
6523 }
6524 }
6525 }
6526 } /* End of GCM encryption */
6527 else
6528 {
6529 /* Workaround 2, case CCM decryption, in order to properly compute
6530 authentication tags while doing a CCM decryption with the last block
6531 of payload size inferior to 128 bits*/
6532
6533 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6534 {
6535 iv1temp = hcryp->Instance->CSGCMCCM7R;
6536
6537 /* Disable CRYP to start the final phase */
6538 __HAL_CRYP_DISABLE(hcryp);
6539
6540 temp[0] = hcryp->Instance->CSGCMCCM0R;
6541 temp[1] = hcryp->Instance->CSGCMCCM1R;
6542 temp[2] = hcryp->Instance->CSGCMCCM2R;
6543 temp[3] = hcryp->Instance->CSGCMCCM3R;
6544
6545 hcryp->Instance->IV1RR = iv1temp;
6546
6547 /* Configured CHMOD CTR */
6548 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6549
6550 /* Enable CRYP to start the final phase */
6551 __HAL_CRYP_ENABLE(hcryp);
6552 }
6553 /* Last block optionally pad the data with zeros*/
6554 for (index = 0; index < lastwordsize; index ++)
6555 {
6556 /* Write the last Input block in the IN FIFO */
6557 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6558 hcryp->CrypInCount++;
6559 }
6560 while (index < 4U)
6561 {
6562 /* Pad the data with zeros to have a complete block */
6563 hcryp->Instance->DIN = 0U;
6564 index++;
6565 }
6566 /* Wait for OFNE flag to be raised */
6567 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6568 {
6569 /* Disable the CRYP peripheral clock */
6570 __HAL_CRYP_DISABLE(hcryp);
6571
6572 /* Change state */
6573 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6574 hcryp->State = HAL_CRYP_STATE_READY;
6575
6576 /* Process Unlocked */
6577 __HAL_UNLOCK(hcryp);
6578 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6579 /*Call registered error callback*/
6580 hcryp->ErrorCallback(hcryp);
6581 #else
6582 /*Call legacy weak error callback*/
6583 HAL_CRYP_ErrorCallback(hcryp);
6584 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6585 }
6586
6587 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6588 {
6589 for (index = 0U; index < 4U; index++)
6590 {
6591 /* Read the Output block from the Output FIFO */
6592 intermediate_data[index] = hcryp->Instance->DOUT;
6593
6594 /*intermediate data buffer to be used in for the workaround*/
6595 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6596 hcryp->CrypOutCount++;
6597 }
6598 }
6599
6600 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6601 {
6602 temp2[0] = hcryp->Instance->CSGCMCCM0R;
6603 temp2[1] = hcryp->Instance->CSGCMCCM1R;
6604 temp2[2] = hcryp->Instance->CSGCMCCM2R;
6605 temp2[3] = hcryp->Instance->CSGCMCCM3R;
6606
6607 /* configured CHMOD CCM */
6608 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
6609
6610 /* configured Header phase */
6611 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
6612
6613 /*set to zero the bits corresponding to the padded bits*/
6614 for (index = lastwordsize; index < 4U; index ++)
6615 {
6616 intermediate_data[index] = 0U;
6617 }
6618 if ((npblb % 4U) == 1U)
6619 {
6620 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6621 }
6622 if ((npblb % 4U) == 2U)
6623 {
6624 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6625 }
6626 if ((npblb % 4U) == 3U)
6627 {
6628 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6629 }
6630 for (index = 0U; index < 4U ; index ++)
6631 {
6632 intermediate_data[index] ^= temp[index];
6633 intermediate_data[index] ^= temp2[index];
6634 }
6635 for (index = 0U; index < 4U; index ++)
6636 {
6637 /* Write the last Input block in the IN FIFO */
6638 hcryp->Instance->DIN = intermediate_data[index] ;
6639 }
6640
6641 /* Wait for BUSY flag to be raised */
6642 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
6643 {
6644 /* Disable the CRYP peripheral clock */
6645 __HAL_CRYP_DISABLE(hcryp);
6646
6647 /* Change state */
6648 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6649 hcryp->State = HAL_CRYP_STATE_READY;
6650
6651 /* Process Unlocked */
6652 __HAL_UNLOCK(hcryp);
6653 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6654 /*Call registered error callback*/
6655 hcryp->ErrorCallback(hcryp);
6656 #else
6657 /*Call legacy weak error callback*/
6658 HAL_CRYP_ErrorCallback(hcryp);
6659 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6660 }
6661 }
6662 } /* End of CCM WKA*/
6663
6664 /* Process Unlocked */
6665 __HAL_UNLOCK(hcryp);
6666
6667 #else /* AES */
6668
6669 /*Workaround 2: case GCM encryption, during payload phase and before inserting
6670 the last block of paylaod, which size is inferior to 128 bits */
6671
6672 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6673 {
6674 /* configured CHMOD CTR */
6675 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6676 }
6677 /* last block optionally pad the data with zeros*/
6678 for (index = 0U; index < lastwordsize; index ++)
6679 {
6680 /* Write the last Input block in the IN FIFO */
6681 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6682 hcryp->CrypInCount++;
6683 }
6684 while (index < 4U)
6685 {
6686 /* pad the data with zeros to have a complete block */
6687 hcryp->Instance->DINR = 0U;
6688 index++;
6689 }
6690 /* Wait for CCF flag to be raised */
6691 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6692 {
6693 hcryp->State = HAL_CRYP_STATE_READY;
6694 __HAL_UNLOCK(hcryp);
6695 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6696 /*Call registered error callback*/
6697 hcryp->ErrorCallback(hcryp);
6698 #else
6699 /*Call legacy weak error callback*/
6700 HAL_CRYP_ErrorCallback(hcryp);
6701 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6702 }
6703
6704 /* Clear CCF Flag */
6705 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6706
6707 for (index = 0U; index < 4U; index++)
6708 {
6709 /* Read the Output block from the Output FIFO */
6710 intermediate_data[index] = hcryp->Instance->DOUTR;
6711
6712 /*intermediate data buffer to be used in the workaround*/
6713 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6714 hcryp->CrypOutCount++;
6715 }
6716
6717 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6718 {
6719 /* configured CHMOD GCM */
6720 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6721
6722 /* Select final phase */
6723 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6724
6725 if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
6726 {
6727 if ((npblb % 4U) == 1U)
6728 {
6729 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6730 }
6731 if ((npblb % 4U) == 2U)
6732 {
6733 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6734 }
6735 if ((npblb % 4U) == 3U)
6736 {
6737 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6738 }
6739 }
6740 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
6741 {
6742 if ((npblb % 4U) == 1U)
6743 {
6744 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6745 }
6746 if ((npblb % 4U) == 2U)
6747 {
6748 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6749 }
6750 if ((npblb % 4U) == 3U)
6751 {
6752 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6753 }
6754 }
6755 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
6756 {
6757 if ((npblb % 4U) == 1U)
6758 {
6759 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6760 }
6761 if ((npblb % 4U) == 2U)
6762 {
6763 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6764 }
6765 if ((npblb % 4U) == 3U)
6766 {
6767 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6768 }
6769 }
6770 else /*CRYP_DATATYPE_1B*/
6771 {
6772 if ((npblb % 4U) == 1U)
6773 {
6774 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6775 }
6776 if ((npblb % 4U) == 2U)
6777 {
6778 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6779 }
6780 if ((npblb % 4U) == 3U)
6781 {
6782 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6783 }
6784 }
6785
6786 /*Write the intermediate_data in the IN FIFO */
6787 for (index = 0U; index < lastwordsize; index ++)
6788 {
6789 hcryp->Instance->DINR = intermediate_data[index];
6790 }
6791 while (index < 4U)
6792 {
6793 /* pad the data with zeros to have a complete block */
6794 hcryp->Instance->DINR = 0U;
6795 index++;
6796 }
6797 /* Wait for CCF flag to be raised */
6798 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6799 {
6800 /* Disable the CRYP peripheral clock */
6801 __HAL_CRYP_DISABLE(hcryp);
6802
6803 /* Change state */
6804 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6805 hcryp->State = HAL_CRYP_STATE_READY;
6806
6807 /* Process Unlocked */
6808 __HAL_UNLOCK(hcryp);
6809 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6810 /*Call registered error callback*/
6811 hcryp->ErrorCallback(hcryp);
6812 #else
6813 /*Call legacy weak error callback*/
6814 HAL_CRYP_ErrorCallback(hcryp);
6815 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6816 }
6817 /* Clear CCF Flag */
6818 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6819
6820 for (index = 0U; index < 4U; index++)
6821 {
6822 intermediate_data[index] = hcryp->Instance->DOUTR;
6823 }
6824 }/*End of Workaround 2*/
6825 #endif /* End AES or CRYP */
6826 }
6827 #endif /* AES or GCM CCM defined*/
6828 #if defined (CRYP)
6829 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
6830 /**
6831 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
6832 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6833 * the configuration information for CRYP module.
6834 * @param Timeout: Timeout duration.
6835 * @retval HAL status
6836 */
6837 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6838 {
6839 uint32_t tickstart;
6840
6841 /* Get timeout */
6842 tickstart = HAL_GetTick();
6843
6844 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
6845 {
6846 /* Check for the Timeout */
6847 if (Timeout != HAL_MAX_DELAY)
6848 {
6849 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6850 {
6851 return HAL_ERROR;
6852 }
6853 }
6854 }
6855 return HAL_OK;
6856 }
6857 #endif /* GCM CCM defined*/
6858 /**
6859 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
6860 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6861 * the configuration information for CRYP module.
6862 * @param Timeout: Timeout duration.
6863 * @retval HAL status
6864 */
6865 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6866 {
6867 uint32_t tickstart;
6868
6869 /* Get timeout */
6870 tickstart = HAL_GetTick();
6871
6872 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
6873 {
6874 /* Check for the Timeout */
6875 if (Timeout != HAL_MAX_DELAY)
6876 {
6877 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6878 {
6879 return HAL_ERROR;
6880 }
6881 }
6882 }
6883 return HAL_OK;
6884 }
6885
6886
6887 /**
6888 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
6889 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6890 * the configuration information for CRYP module.
6891 * @param Timeout: Timeout duration.
6892 * @retval HAL status
6893 */
6894 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6895 {
6896 uint32_t tickstart;
6897
6898 /* Get timeout */
6899 tickstart = HAL_GetTick();
6900
6901 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
6902 {
6903 /* Check for the Timeout */
6904 if (Timeout != HAL_MAX_DELAY)
6905 {
6906 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6907 {
6908 return HAL_ERROR;
6909 }
6910 }
6911 }
6912 return HAL_OK;
6913 }
6914
6915 #else /* AES */
6916
6917 /**
6918 * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
6919 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6920 * the configuration information for CRYP module.
6921 * @param Timeout: Timeout duration.
6922 * @retval HAL status
6923 */
6924 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6925 {
6926 uint32_t tickstart;
6927
6928 /* Get timeout */
6929 tickstart = HAL_GetTick();
6930
6931 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
6932 {
6933 /* Check for the Timeout */
6934 if (Timeout != HAL_MAX_DELAY)
6935 {
6936 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6937 {
6938 return HAL_ERROR;
6939 }
6940 }
6941 }
6942 return HAL_OK;
6943 }
6944
6945 #endif /* End AES or CRYP */
6946
6947
6948 /**
6949 * @}
6950 */
6951
6952
6953
6954 /**
6955 * @}
6956 */
6957
6958 /**
6959 * @}
6960 */
6961
6962 #endif /* HAL_CRYP_MODULE_ENABLED */
6963
6964
6965 /**
6966 * @}
6967 */
6968 #endif /* TinyAES or CRYP*/
6969 /**
6970 * @}
6971 */
6972
6973 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6974