1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
7 * + Initialization and de-initialization functions
8 * + IO operation functions
9 * + State and errors functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### ADC Peripheral features #####
14 ==============================================================================
15 [..]
16 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
17 (#) Interrupt generation at the end of conversion, end of injected conversion,
18 and in case of analog watchdog or overrun events
19 (#) Single and continuous conversion modes.
20 (#) Scan mode for automatic conversion of channel 0 to channel x.
21 (#) Data alignment with in-built data coherency.
22 (#) Channel-wise programmable sampling time.
23 (#) External trigger option with configurable polarity for both regular and
24 injected conversion.
25 (#) Dual/Triple mode (on devices with 2 ADCs or more).
26 (#) Configurable DMA data storage in Dual/Triple ADC mode.
27 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
28 (#) ADC conversion type (refer to the datasheets).
29 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
30 slower speed.
31 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
32 (#) DMA request generation during regular channel conversion.
33
34
35 ##### How to use this driver #####
36 ==============================================================================
37 [..]
38 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
39 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
40 (##) ADC pins configuration
41 (+++) Enable the clock for the ADC GPIOs using the following function:
42 __HAL_RCC_GPIOx_CLK_ENABLE()
43 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
44 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
45 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
46 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
47 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
48 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
49 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
50 (+++) Configure and enable two DMA streams stream for managing data
51 transfer from peripheral to memory (output stream)
52 (+++) Associate the initialized DMA handle to the CRYP DMA handle
53 using __HAL_LINKDMA()
54 (+++) Configure the priority and enable the NVIC for the transfer complete
55 interrupt on the two DMA Streams. The output stream should have higher
56 priority than the input stream.
57
58 *** Configuration of ADC, groups regular/injected, channels parameters ***
59 ==============================================================================
60 [..]
61 (#) Configure the ADC parameters (resolution, data alignment, ...)
62 and regular group parameters (conversion trigger, sequencer, ...)
63 using function HAL_ADC_Init().
64
65 (#) Configure the channels for regular group parameters (channel number,
66 channel rank into sequencer, ..., into regular group)
67 using function HAL_ADC_ConfigChannel().
68
69 (#) Optionally, configure the injected group parameters (conversion trigger,
70 sequencer, ..., of injected group)
71 and the channels for injected group parameters (channel number,
72 channel rank into sequencer, ..., into injected group)
73 using function HAL_ADCEx_InjectedConfigChannel().
74
75 (#) Optionally, configure the analog watchdog parameters (channels
76 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
77
78 (#) Optionally, for devices with several ADC instances: configure the
79 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
80
81 *** Execution of ADC conversions ***
82 ==============================================================================
83 [..]
84 (#) ADC driver can be used among three modes: polling, interruption,
85 transfer by DMA.
86
87 *** Polling mode IO operation ***
88 =================================
89 [..]
90 (+) Start the ADC peripheral using HAL_ADC_Start()
91 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
92 user can specify the value of timeout according to his end application
93 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
94 (+) Stop the ADC peripheral using HAL_ADC_Stop()
95
96 *** Interrupt mode IO operation ***
97 ===================================
98 [..]
99 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
100 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
101 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
102 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
103 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
104 add his own code by customization of function pointer HAL_ADC_ErrorCallback
105 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
106
107 *** DMA mode IO operation ***
108 ==============================
109 [..]
110 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
111 of data to be transferred at each end of conversion
112 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
114 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
115 add his own code by customization of function pointer HAL_ADC_ErrorCallback
116 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
117
118 *** ADC HAL driver macros list ***
119 =============================================
120 [..]
121 Below the list of most used macros in ADC HAL driver.
122
123 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
124 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
125 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
126 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
127 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
128 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
129 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
130 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
131
132 [..]
133 (@) You can refer to the ADC HAL driver header file for more useful macros
134
135 *** Deinitialization of ADC ***
136 ==============================================================================
137 [..]
138 (#) Disable the ADC interface
139 (++) ADC clock can be hard reset and disabled at RCC top level.
140 (++) Hard reset of ADC peripherals
141 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
142 (++) ADC clock disable using the equivalent macro/functions as configuration step.
143 (+++) Example:
144 Into HAL_ADC_MspDeInit() (recommended code location) or with
145 other device clock parameters configuration:
146 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
147 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
148 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
149 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
150
151 (#) ADC pins configuration
152 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
153
154 (#) Optionally, in case of usage of ADC with interruptions:
155 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
156
157 (#) Optionally, in case of usage of DMA:
158 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
159 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
160 *** Callback registration ***
161 ==============================================================================
162 [..]
163
164 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
165 allows the user to configure dynamically the driver callbacks.
166 Use Functions @ref HAL_ADC_RegisterCallback()
167 to register an interrupt callback.
168 [..]
169
170 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
171 (+) ConvCpltCallback : ADC conversion complete callback
172 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
173 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
174 (+) ErrorCallback : ADC error callback
175 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
176 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
177 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
178 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
179 (+) EndOfSamplingCallback : ADC end of sampling callback
180 (+) MspInitCallback : ADC Msp Init callback
181 (+) MspDeInitCallback : ADC Msp DeInit callback
182 This function takes as parameters the HAL peripheral handle, the Callback ID
183 and a pointer to the user callback function.
184 [..]
185
186 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
187 weak function.
188 [..]
189
190 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
191 and the Callback ID.
192 This function allows to reset following callbacks:
193 (+) ConvCpltCallback : ADC conversion complete callback
194 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
195 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
196 (+) ErrorCallback : ADC error callback
197 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
198 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
199 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
200 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
201 (+) EndOfSamplingCallback : ADC end of sampling callback
202 (+) MspInitCallback : ADC Msp Init callback
203 (+) MspDeInitCallback : ADC Msp DeInit callback
204 [..]
205
206 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
207 all callbacks are set to the corresponding weak functions:
208 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
209 Exception done for MspInit and MspDeInit functions that are
210 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
211 these callbacks are null (not registered beforehand).
212 [..]
213
214 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
215 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
216 [..]
217
218 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
219 Exception done MspInit/MspDeInit functions that can be registered/unregistered
220 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
221 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
222 [..]
223
224 Then, the user first registers the MspInit/MspDeInit user callbacks
225 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
226 or @ref HAL_ADC_Init() function.
227 [..]
228
229 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
230 not defined, the callback registration feature is not available and all callbacks
231 are set to the corresponding weak functions.
232
233 @endverbatim
234 ******************************************************************************
235 * @attention
236 *
237 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
238 * All rights reserved.</center></h2>
239 *
240 * This software component is licensed by ST under BSD 3-Clause license,
241 * the "License"; You may not use this file except in compliance with the
242 * License. You may obtain a copy of the License at:
243 * opensource.org/licenses/BSD-3-Clause
244 *
245 ******************************************************************************
246 */
247
248 /* Includes ------------------------------------------------------------------*/
249 #include "stm32f4xx_hal.h"
250
251 /** @addtogroup STM32F4xx_HAL_Driver
252 * @{
253 */
254
255 /** @defgroup ADC ADC
256 * @brief ADC driver modules
257 * @{
258 */
259
260 #ifdef HAL_ADC_MODULE_ENABLED
261
262 /* Private typedef -----------------------------------------------------------*/
263 /* Private define ------------------------------------------------------------*/
264 /* Private macro -------------------------------------------------------------*/
265 /* Private variables ---------------------------------------------------------*/
266 /** @addtogroup ADC_Private_Functions
267 * @{
268 */
269 /* Private function prototypes -----------------------------------------------*/
270 static void ADC_Init(ADC_HandleTypeDef* hadc);
271 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
272 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
273 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
274 /**
275 * @}
276 */
277 /* Exported functions --------------------------------------------------------*/
278 /** @defgroup ADC_Exported_Functions ADC Exported Functions
279 * @{
280 */
281
282 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
283 * @brief Initialization and Configuration functions
284 *
285 @verbatim
286 ===============================================================================
287 ##### Initialization and de-initialization functions #####
288 ===============================================================================
289 [..] This section provides functions allowing to:
290 (+) Initialize and configure the ADC.
291 (+) De-initialize the ADC.
292
293 @endverbatim
294 * @{
295 */
296
297 /**
298 * @brief Initializes the ADCx peripheral according to the specified parameters
299 * in the ADC_InitStruct and initializes the ADC MSP.
300 *
301 * @note This function is used to configure the global features of the ADC (
302 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
303 * the rest of the configuration parameters are specific to the regular
304 * channels group (scan mode activation, continuous mode activation,
305 * External trigger source and edge, DMA continuous request after the
306 * last transfer and End of conversion selection).
307 *
308 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
309 * the configuration information for the specified ADC.
310 * @retval HAL status
311 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)312 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
313 {
314 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
315
316 /* Check ADC handle */
317 if(hadc == NULL)
318 {
319 return HAL_ERROR;
320 }
321
322 /* Check the parameters */
323 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
324 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
325 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
326 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
327 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
328 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
329 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
330 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
331 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
332 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
333 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
334
335 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
336 {
337 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
338 }
339
340 if(hadc->State == HAL_ADC_STATE_RESET)
341 {
342 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
343 /* Init the ADC Callback settings */
344 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
345 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
346 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
347 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
348 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
349 if (hadc->MspInitCallback == NULL)
350 {
351 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
352 }
353
354 /* Init the low level hardware */
355 hadc->MspInitCallback(hadc);
356 #else
357 /* Init the low level hardware */
358 HAL_ADC_MspInit(hadc);
359 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
360
361 /* Initialize ADC error code */
362 ADC_CLEAR_ERRORCODE(hadc);
363
364 /* Allocate lock resource and initialize it */
365 hadc->Lock = HAL_UNLOCKED;
366 }
367
368 /* Configuration of ADC parameters if previous preliminary actions are */
369 /* correctly completed. */
370 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
371 {
372 /* Set ADC state */
373 ADC_STATE_CLR_SET(hadc->State,
374 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
375 HAL_ADC_STATE_BUSY_INTERNAL);
376
377 /* Set ADC parameters */
378 ADC_Init(hadc);
379
380 /* Set ADC error code to none */
381 ADC_CLEAR_ERRORCODE(hadc);
382
383 /* Set the ADC state */
384 ADC_STATE_CLR_SET(hadc->State,
385 HAL_ADC_STATE_BUSY_INTERNAL,
386 HAL_ADC_STATE_READY);
387 }
388 else
389 {
390 tmp_hal_status = HAL_ERROR;
391 }
392
393 /* Release Lock */
394 __HAL_UNLOCK(hadc);
395
396 /* Return function status */
397 return tmp_hal_status;
398 }
399
400 /**
401 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
402 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
403 * the configuration information for the specified ADC.
404 * @retval HAL status
405 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)406 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
407 {
408 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
409
410 /* Check ADC handle */
411 if(hadc == NULL)
412 {
413 return HAL_ERROR;
414 }
415
416 /* Check the parameters */
417 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
418
419 /* Set ADC state */
420 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
421
422 /* Stop potential conversion on going, on regular and injected groups */
423 /* Disable ADC peripheral */
424 __HAL_ADC_DISABLE(hadc);
425
426 /* Configuration of ADC parameters if previous preliminary actions are */
427 /* correctly completed. */
428 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
429 {
430 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
431 if (hadc->MspDeInitCallback == NULL)
432 {
433 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
434 }
435
436 /* DeInit the low level hardware: RCC clock, NVIC */
437 hadc->MspDeInitCallback(hadc);
438 #else
439 /* DeInit the low level hardware: RCC clock, NVIC */
440 HAL_ADC_MspDeInit(hadc);
441 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
442
443 /* Set ADC error code to none */
444 ADC_CLEAR_ERRORCODE(hadc);
445
446 /* Set ADC state */
447 hadc->State = HAL_ADC_STATE_RESET;
448 }
449
450 /* Process unlocked */
451 __HAL_UNLOCK(hadc);
452
453 /* Return function status */
454 return tmp_hal_status;
455 }
456
457 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
458 /**
459 * @brief Register a User ADC Callback
460 * To be used instead of the weak predefined callback
461 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
462 * the configuration information for the specified ADC.
463 * @param CallbackID ID of the callback to be registered
464 * This parameter can be one of the following values:
465 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
466 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
467 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
468 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
469 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
470 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
471 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
472 * @param pCallback pointer to the Callback function
473 * @retval HAL status
474 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)475 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
476 {
477 HAL_StatusTypeDef status = HAL_OK;
478
479 if (pCallback == NULL)
480 {
481 /* Update the error code */
482 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
483
484 return HAL_ERROR;
485 }
486
487 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
488 {
489 switch (CallbackID)
490 {
491 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
492 hadc->ConvCpltCallback = pCallback;
493 break;
494
495 case HAL_ADC_CONVERSION_HALF_CB_ID :
496 hadc->ConvHalfCpltCallback = pCallback;
497 break;
498
499 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
500 hadc->LevelOutOfWindowCallback = pCallback;
501 break;
502
503 case HAL_ADC_ERROR_CB_ID :
504 hadc->ErrorCallback = pCallback;
505 break;
506
507 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
508 hadc->InjectedConvCpltCallback = pCallback;
509 break;
510
511 case HAL_ADC_MSPINIT_CB_ID :
512 hadc->MspInitCallback = pCallback;
513 break;
514
515 case HAL_ADC_MSPDEINIT_CB_ID :
516 hadc->MspDeInitCallback = pCallback;
517 break;
518
519 default :
520 /* Update the error code */
521 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
522
523 /* Return error status */
524 status = HAL_ERROR;
525 break;
526 }
527 }
528 else if (HAL_ADC_STATE_RESET == hadc->State)
529 {
530 switch (CallbackID)
531 {
532 case HAL_ADC_MSPINIT_CB_ID :
533 hadc->MspInitCallback = pCallback;
534 break;
535
536 case HAL_ADC_MSPDEINIT_CB_ID :
537 hadc->MspDeInitCallback = pCallback;
538 break;
539
540 default :
541 /* Update the error code */
542 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
543
544 /* Return error status */
545 status = HAL_ERROR;
546 break;
547 }
548 }
549 else
550 {
551 /* Update the error code */
552 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
553
554 /* Return error status */
555 status = HAL_ERROR;
556 }
557
558 return status;
559 }
560
561 /**
562 * @brief Unregister a ADC Callback
563 * ADC callback is redirected to the weak predefined callback
564 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
565 * the configuration information for the specified ADC.
566 * @param CallbackID ID of the callback to be unregistered
567 * This parameter can be one of the following values:
568 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
569 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
570 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
571 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
572 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
573 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
574 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
575 * @retval HAL status
576 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)577 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
578 {
579 HAL_StatusTypeDef status = HAL_OK;
580
581 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
582 {
583 switch (CallbackID)
584 {
585 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
586 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
587 break;
588
589 case HAL_ADC_CONVERSION_HALF_CB_ID :
590 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
591 break;
592
593 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
594 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
595 break;
596
597 case HAL_ADC_ERROR_CB_ID :
598 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
599 break;
600
601 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
602 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
603 break;
604
605 case HAL_ADC_MSPINIT_CB_ID :
606 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
607 break;
608
609 case HAL_ADC_MSPDEINIT_CB_ID :
610 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
611 break;
612
613 default :
614 /* Update the error code */
615 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
616
617 /* Return error status */
618 status = HAL_ERROR;
619 break;
620 }
621 }
622 else if (HAL_ADC_STATE_RESET == hadc->State)
623 {
624 switch (CallbackID)
625 {
626 case HAL_ADC_MSPINIT_CB_ID :
627 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
628 break;
629
630 case HAL_ADC_MSPDEINIT_CB_ID :
631 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
632 break;
633
634 default :
635 /* Update the error code */
636 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
637
638 /* Return error status */
639 status = HAL_ERROR;
640 break;
641 }
642 }
643 else
644 {
645 /* Update the error code */
646 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
647
648 /* Return error status */
649 status = HAL_ERROR;
650 }
651
652 return status;
653 }
654
655 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
656
657 /**
658 * @brief Initializes the ADC MSP.
659 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
660 * the configuration information for the specified ADC.
661 * @retval None
662 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)663 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
664 {
665 /* Prevent unused argument(s) compilation warning */
666 UNUSED(hadc);
667 /* NOTE : This function Should not be modified, when the callback is needed,
668 the HAL_ADC_MspInit could be implemented in the user file
669 */
670 }
671
672 /**
673 * @brief DeInitializes the ADC MSP.
674 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
675 * the configuration information for the specified ADC.
676 * @retval None
677 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)678 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
679 {
680 /* Prevent unused argument(s) compilation warning */
681 UNUSED(hadc);
682 /* NOTE : This function Should not be modified, when the callback is needed,
683 the HAL_ADC_MspDeInit could be implemented in the user file
684 */
685 }
686
687 /**
688 * @}
689 */
690
691 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
692 * @brief IO operation functions
693 *
694 @verbatim
695 ===============================================================================
696 ##### IO operation functions #####
697 ===============================================================================
698 [..] This section provides functions allowing to:
699 (+) Start conversion of regular channel.
700 (+) Stop conversion of regular channel.
701 (+) Start conversion of regular channel and enable interrupt.
702 (+) Stop conversion of regular channel and disable interrupt.
703 (+) Start conversion of regular channel and enable DMA transfer.
704 (+) Stop conversion of regular channel and disable DMA transfer.
705 (+) Handle ADC interrupt request.
706
707 @endverbatim
708 * @{
709 */
710
711 /**
712 * @brief Enables ADC and starts conversion of the regular channels.
713 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
714 * the configuration information for the specified ADC.
715 * @retval HAL status
716 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)717 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
718 {
719 __IO uint32_t counter = 0U;
720 ADC_Common_TypeDef *tmpADC_Common;
721
722 /* Check the parameters */
723 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
724 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
725
726 /* Process locked */
727 __HAL_LOCK(hadc);
728
729 /* Enable the ADC peripheral */
730 /* Check if ADC peripheral is disabled in order to enable it and wait during
731 Tstab time the ADC's stabilization */
732 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
733 {
734 /* Enable the Peripheral */
735 __HAL_ADC_ENABLE(hadc);
736
737 /* Delay for ADC stabilization time */
738 /* Compute number of CPU cycles to wait for */
739 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
740 while(counter != 0U)
741 {
742 counter--;
743 }
744 }
745
746 /* Start conversion if ADC is effectively enabled */
747 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
748 {
749 /* Set ADC state */
750 /* - Clear state bitfield related to regular group conversion results */
751 /* - Set state bitfield related to regular group operation */
752 ADC_STATE_CLR_SET(hadc->State,
753 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
754 HAL_ADC_STATE_REG_BUSY);
755
756 /* If conversions on group regular are also triggering group injected, */
757 /* update ADC state. */
758 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
759 {
760 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
761 }
762
763 /* State machine update: Check if an injected conversion is ongoing */
764 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
765 {
766 /* Reset ADC error code fields related to conversions on group regular */
767 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
768 }
769 else
770 {
771 /* Reset ADC all error code fields */
772 ADC_CLEAR_ERRORCODE(hadc);
773 }
774
775 /* Process unlocked */
776 /* Unlock before starting ADC conversions: in case of potential */
777 /* interruption, to let the process to ADC IRQ Handler. */
778 __HAL_UNLOCK(hadc);
779
780 /* Pointer to the common control register to which is belonging hadc */
781 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
782 /* control register) */
783 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
784
785 /* Clear regular group conversion flag and overrun flag */
786 /* (To ensure of no unknown state from potential previous ADC operations) */
787 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
788
789 /* Check if Multimode enabled */
790 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
791 {
792 #if defined(ADC2) && defined(ADC3)
793 if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
794 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
795 {
796 #endif /* ADC2 || ADC3 */
797 /* if no external trigger present enable software conversion of regular channels */
798 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
799 {
800 /* Enable the selected ADC software conversion for regular group */
801 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
802 }
803 #if defined(ADC2) && defined(ADC3)
804 }
805 #endif /* ADC2 || ADC3 */
806 }
807 else
808 {
809 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
810 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
811 {
812 /* Enable the selected ADC software conversion for regular group */
813 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
814 }
815 }
816 }
817
818 /* Return function status */
819 return HAL_OK;
820 }
821
822 /**
823 * @brief Disables ADC and stop conversion of regular channels.
824 *
825 * @note Caution: This function will stop also injected channels.
826 *
827 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
828 * the configuration information for the specified ADC.
829 *
830 * @retval HAL status.
831 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)832 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
833 {
834 /* Check the parameters */
835 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
836
837 /* Process locked */
838 __HAL_LOCK(hadc);
839
840 /* Stop potential conversion on going, on regular and injected groups */
841 /* Disable ADC peripheral */
842 __HAL_ADC_DISABLE(hadc);
843
844 /* Check if ADC is effectively disabled */
845 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
846 {
847 /* Set ADC state */
848 ADC_STATE_CLR_SET(hadc->State,
849 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
850 HAL_ADC_STATE_READY);
851 }
852
853 /* Process unlocked */
854 __HAL_UNLOCK(hadc);
855
856 /* Return function status */
857 return HAL_OK;
858 }
859
860 /**
861 * @brief Poll for regular conversion complete
862 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
863 * conversion) are cleared by this function.
864 * @note This function cannot be used in a particular setup: ADC configured
865 * in DMA mode and polling for end of each conversion (ADC init
866 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
867 * In this case, DMA resets the flag EOC and polling cannot be
868 * performed on each conversion. Nevertheless, polling can still
869 * be performed on the complete sequence.
870 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
871 * the configuration information for the specified ADC.
872 * @param Timeout Timeout value in millisecond.
873 * @retval HAL status
874 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)875 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
876 {
877 uint32_t tickstart = 0U;
878
879 /* Verification that ADC configuration is compliant with polling for */
880 /* each conversion: */
881 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
882 /* several ranks and polling for end of each conversion. */
883 /* For code simplicity sake, this particular case is generalized to */
884 /* ADC configured in DMA mode and polling for end of each conversion. */
885 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
886 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
887 {
888 /* Update ADC state machine to error */
889 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
890
891 /* Process unlocked */
892 __HAL_UNLOCK(hadc);
893
894 return HAL_ERROR;
895 }
896
897 /* Get tick */
898 tickstart = HAL_GetTick();
899
900 /* Check End of conversion flag */
901 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
902 {
903 /* Check if timeout is disabled (set to infinite wait) */
904 if(Timeout != HAL_MAX_DELAY)
905 {
906 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
907 {
908 /* Update ADC state machine to timeout */
909 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
910
911 /* Process unlocked */
912 __HAL_UNLOCK(hadc);
913
914 return HAL_TIMEOUT;
915 }
916 }
917 }
918
919 /* Clear regular group conversion flag */
920 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
921
922 /* Update ADC state machine */
923 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
924
925 /* Determine whether any further conversion upcoming on group regular */
926 /* by external trigger, continuous mode or scan sequence on going. */
927 /* Note: On STM32F4, there is no independent flag of end of sequence. */
928 /* The test of scan sequence on going is done either with scan */
929 /* sequence disabled or with end of conversion flag set to */
930 /* of end of sequence. */
931 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
932 (hadc->Init.ContinuousConvMode == DISABLE) &&
933 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
934 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
935 {
936 /* Set ADC state */
937 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
938
939 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
940 {
941 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
942 }
943 }
944
945 /* Return ADC state */
946 return HAL_OK;
947 }
948
949 /**
950 * @brief Poll for conversion event
951 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
952 * the configuration information for the specified ADC.
953 * @param EventType the ADC event type.
954 * This parameter can be one of the following values:
955 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
956 * @arg ADC_OVR_EVENT: ADC Overrun event.
957 * @param Timeout Timeout value in millisecond.
958 * @retval HAL status
959 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)960 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
961 {
962 uint32_t tickstart = 0U;
963
964 /* Check the parameters */
965 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
966 assert_param(IS_ADC_EVENT_TYPE(EventType));
967
968 /* Get tick */
969 tickstart = HAL_GetTick();
970
971 /* Check selected event flag */
972 while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
973 {
974 /* Check for the Timeout */
975 if(Timeout != HAL_MAX_DELAY)
976 {
977 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
978 {
979 /* Update ADC state machine to timeout */
980 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
981
982 /* Process unlocked */
983 __HAL_UNLOCK(hadc);
984
985 return HAL_TIMEOUT;
986 }
987 }
988 }
989
990 /* Analog watchdog (level out of window) event */
991 if(EventType == ADC_AWD_EVENT)
992 {
993 /* Set ADC state */
994 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
995
996 /* Clear ADC analog watchdog flag */
997 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
998 }
999 /* Overrun event */
1000 else
1001 {
1002 /* Set ADC state */
1003 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1004 /* Set ADC error code to overrun */
1005 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1006
1007 /* Clear ADC overrun flag */
1008 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1009 }
1010
1011 /* Return ADC state */
1012 return HAL_OK;
1013 }
1014
1015
1016 /**
1017 * @brief Enables the interrupt and starts ADC conversion of regular channels.
1018 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1019 * the configuration information for the specified ADC.
1020 * @retval HAL status.
1021 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1022 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1023 {
1024 __IO uint32_t counter = 0U;
1025 ADC_Common_TypeDef *tmpADC_Common;
1026
1027 /* Check the parameters */
1028 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1029 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1030
1031 /* Process locked */
1032 __HAL_LOCK(hadc);
1033
1034 /* Enable the ADC peripheral */
1035 /* Check if ADC peripheral is disabled in order to enable it and wait during
1036 Tstab time the ADC's stabilization */
1037 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1038 {
1039 /* Enable the Peripheral */
1040 __HAL_ADC_ENABLE(hadc);
1041
1042 /* Delay for ADC stabilization time */
1043 /* Compute number of CPU cycles to wait for */
1044 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
1045 while(counter != 0U)
1046 {
1047 counter--;
1048 }
1049 }
1050
1051 /* Start conversion if ADC is effectively enabled */
1052 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1053 {
1054 /* Set ADC state */
1055 /* - Clear state bitfield related to regular group conversion results */
1056 /* - Set state bitfield related to regular group operation */
1057 ADC_STATE_CLR_SET(hadc->State,
1058 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1059 HAL_ADC_STATE_REG_BUSY);
1060
1061 /* If conversions on group regular are also triggering group injected, */
1062 /* update ADC state. */
1063 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1064 {
1065 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1066 }
1067
1068 /* State machine update: Check if an injected conversion is ongoing */
1069 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1070 {
1071 /* Reset ADC error code fields related to conversions on group regular */
1072 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1073 }
1074 else
1075 {
1076 /* Reset ADC all error code fields */
1077 ADC_CLEAR_ERRORCODE(hadc);
1078 }
1079
1080 /* Process unlocked */
1081 /* Unlock before starting ADC conversions: in case of potential */
1082 /* interruption, to let the process to ADC IRQ Handler. */
1083 __HAL_UNLOCK(hadc);
1084
1085 /* Pointer to the common control register to which is belonging hadc */
1086 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1087 /* control register) */
1088 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1089
1090 /* Clear regular group conversion flag and overrun flag */
1091 /* (To ensure of no unknown state from potential previous ADC operations) */
1092 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1093
1094 /* Enable end of conversion interrupt for regular group */
1095 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1096
1097 /* Check if Multimode enabled */
1098 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
1099 {
1100 #if defined(ADC2) && defined(ADC3)
1101 if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
1102 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
1103 {
1104 #endif /* ADC2 || ADC3 */
1105 /* if no external trigger present enable software conversion of regular channels */
1106 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1107 {
1108 /* Enable the selected ADC software conversion for regular group */
1109 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1110 }
1111 #if defined(ADC2) && defined(ADC3)
1112 }
1113 #endif /* ADC2 || ADC3 */
1114 }
1115 else
1116 {
1117 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1118 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1119 {
1120 /* Enable the selected ADC software conversion for regular group */
1121 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1122 }
1123 }
1124 }
1125
1126 /* Return function status */
1127 return HAL_OK;
1128 }
1129
1130 /**
1131 * @brief Disables the interrupt and stop ADC conversion of regular channels.
1132 *
1133 * @note Caution: This function will stop also injected channels.
1134 *
1135 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1136 * the configuration information for the specified ADC.
1137 * @retval HAL status.
1138 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1139 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1140 {
1141 /* Check the parameters */
1142 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1143
1144 /* Process locked */
1145 __HAL_LOCK(hadc);
1146
1147 /* Stop potential conversion on going, on regular and injected groups */
1148 /* Disable ADC peripheral */
1149 __HAL_ADC_DISABLE(hadc);
1150
1151 /* Check if ADC is effectively disabled */
1152 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1153 {
1154 /* Disable ADC end of conversion interrupt for regular group */
1155 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1156
1157 /* Set ADC state */
1158 ADC_STATE_CLR_SET(hadc->State,
1159 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1160 HAL_ADC_STATE_READY);
1161 }
1162
1163 /* Process unlocked */
1164 __HAL_UNLOCK(hadc);
1165
1166 /* Return function status */
1167 return HAL_OK;
1168 }
1169
1170 /**
1171 * @brief Handles ADC interrupt request
1172 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1173 * the configuration information for the specified ADC.
1174 * @retval None
1175 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)1176 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1177 {
1178 uint32_t tmp1 = 0U, tmp2 = 0U;
1179
1180 /* Check the parameters */
1181 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1182 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
1183 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
1184
1185 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
1186 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
1187 /* Check End of conversion flag for regular channels */
1188 if(tmp1 && tmp2)
1189 {
1190 /* Update state machine on conversion status if not in error state */
1191 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1192 {
1193 /* Set ADC state */
1194 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1195 }
1196
1197 /* Determine whether any further conversion upcoming on group regular */
1198 /* by external trigger, continuous mode or scan sequence on going. */
1199 /* Note: On STM32F4, there is no independent flag of end of sequence. */
1200 /* The test of scan sequence on going is done either with scan */
1201 /* sequence disabled or with end of conversion flag set to */
1202 /* of end of sequence. */
1203 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1204 (hadc->Init.ContinuousConvMode == DISABLE) &&
1205 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1206 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1207 {
1208 /* Disable ADC end of single conversion interrupt on group regular */
1209 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1210 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1211 /* by overrun IRQ process below. */
1212 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1213
1214 /* Set ADC state */
1215 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1216
1217 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1218 {
1219 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1220 }
1221 }
1222
1223 /* Conversion complete callback */
1224 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1225 hadc->ConvCpltCallback(hadc);
1226 #else
1227 HAL_ADC_ConvCpltCallback(hadc);
1228 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1229
1230 /* Clear regular group conversion flag */
1231 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1232 }
1233
1234 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
1235 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
1236 /* Check End of conversion flag for injected channels */
1237 if(tmp1 && tmp2)
1238 {
1239 /* Update state machine on conversion status if not in error state */
1240 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1241 {
1242 /* Set ADC state */
1243 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1244 }
1245
1246 /* Determine whether any further conversion upcoming on group injected */
1247 /* by external trigger, scan sequence on going or by automatic injected */
1248 /* conversion from group regular (same conditions as group regular */
1249 /* interruption disabling above). */
1250 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
1251 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
1252 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
1253 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1254 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1255 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
1256 {
1257 /* Disable ADC end of single conversion interrupt on group injected */
1258 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1259
1260 /* Set ADC state */
1261 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1262
1263 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1264 {
1265 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1266 }
1267 }
1268
1269 /* Conversion complete callback */
1270 /* Conversion complete callback */
1271 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1272 hadc->InjectedConvCpltCallback(hadc);
1273 #else
1274 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1275 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1276
1277 /* Clear injected group conversion flag */
1278 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1279 }
1280
1281 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
1282 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
1283 /* Check Analog watchdog flag */
1284 if(tmp1 && tmp2)
1285 {
1286 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1287 {
1288 /* Set ADC state */
1289 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1290
1291 /* Level out of window callback */
1292 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1293 hadc->LevelOutOfWindowCallback(hadc);
1294 #else
1295 HAL_ADC_LevelOutOfWindowCallback(hadc);
1296 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1297
1298 /* Clear the ADC analog watchdog flag */
1299 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1300 }
1301 }
1302
1303 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
1304 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
1305 /* Check Overrun flag */
1306 if(tmp1 && tmp2)
1307 {
1308 /* Note: On STM32F4, ADC overrun can be set through other parameters */
1309 /* refer to description of parameter "EOCSelection" for more */
1310 /* details. */
1311
1312 /* Set ADC error code to overrun */
1313 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1314
1315 /* Clear ADC overrun flag */
1316 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1317
1318 /* Error callback */
1319 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1320 hadc->ErrorCallback(hadc);
1321 #else
1322 HAL_ADC_ErrorCallback(hadc);
1323 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1324
1325 /* Clear the Overrun flag */
1326 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1327 }
1328 }
1329
1330 /**
1331 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
1332 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1333 * the configuration information for the specified ADC.
1334 * @param pData The destination Buffer address.
1335 * @param Length The length of data to be transferred from ADC peripheral to memory.
1336 * @retval HAL status
1337 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1338 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1339 {
1340 __IO uint32_t counter = 0U;
1341 ADC_Common_TypeDef *tmpADC_Common;
1342
1343 /* Check the parameters */
1344 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1345 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1346
1347 /* Process locked */
1348 __HAL_LOCK(hadc);
1349
1350 /* Enable the ADC peripheral */
1351 /* Check if ADC peripheral is disabled in order to enable it and wait during
1352 Tstab time the ADC's stabilization */
1353 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1354 {
1355 /* Enable the Peripheral */
1356 __HAL_ADC_ENABLE(hadc);
1357
1358 /* Delay for ADC stabilization time */
1359 /* Compute number of CPU cycles to wait for */
1360 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
1361 while(counter != 0U)
1362 {
1363 counter--;
1364 }
1365 }
1366
1367 /* Start conversion if ADC is effectively enabled */
1368 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1369 {
1370 /* Set ADC state */
1371 /* - Clear state bitfield related to regular group conversion results */
1372 /* - Set state bitfield related to regular group operation */
1373 ADC_STATE_CLR_SET(hadc->State,
1374 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1375 HAL_ADC_STATE_REG_BUSY);
1376
1377 /* If conversions on group regular are also triggering group injected, */
1378 /* update ADC state. */
1379 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1380 {
1381 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1382 }
1383
1384 /* State machine update: Check if an injected conversion is ongoing */
1385 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1386 {
1387 /* Reset ADC error code fields related to conversions on group regular */
1388 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1389 }
1390 else
1391 {
1392 /* Reset ADC all error code fields */
1393 ADC_CLEAR_ERRORCODE(hadc);
1394 }
1395
1396 /* Process unlocked */
1397 /* Unlock before starting ADC conversions: in case of potential */
1398 /* interruption, to let the process to ADC IRQ Handler. */
1399 __HAL_UNLOCK(hadc);
1400
1401 /* Pointer to the common control register to which is belonging hadc */
1402 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1403 /* control register) */
1404 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1405
1406 /* Set the DMA transfer complete callback */
1407 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1408
1409 /* Set the DMA half transfer complete callback */
1410 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1411
1412 /* Set the DMA error callback */
1413 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1414
1415
1416 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1417 /* start (in case of SW start): */
1418
1419 /* Clear regular group conversion flag and overrun flag */
1420 /* (To ensure of no unknown state from potential previous ADC operations) */
1421 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1422
1423 /* Enable ADC overrun interrupt */
1424 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1425
1426 /* Enable ADC DMA mode */
1427 hadc->Instance->CR2 |= ADC_CR2_DMA;
1428
1429 /* Start the DMA channel */
1430 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1431
1432 /* Check if Multimode enabled */
1433 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
1434 {
1435 #if defined(ADC2) && defined(ADC3)
1436 if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
1437 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
1438 {
1439 #endif /* ADC2 || ADC3 */
1440 /* if no external trigger present enable software conversion of regular channels */
1441 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1442 {
1443 /* Enable the selected ADC software conversion for regular group */
1444 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1445 }
1446 #if defined(ADC2) && defined(ADC3)
1447 }
1448 #endif /* ADC2 || ADC3 */
1449 }
1450 else
1451 {
1452 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1453 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1454 {
1455 /* Enable the selected ADC software conversion for regular group */
1456 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1457 }
1458 }
1459 }
1460
1461 /* Return function status */
1462 return HAL_OK;
1463 }
1464
1465 /**
1466 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
1467 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1468 * the configuration information for the specified ADC.
1469 * @retval HAL status
1470 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)1471 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1472 {
1473 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1474
1475 /* Check the parameters */
1476 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1477
1478 /* Process locked */
1479 __HAL_LOCK(hadc);
1480
1481 /* Stop potential conversion on going, on regular and injected groups */
1482 /* Disable ADC peripheral */
1483 __HAL_ADC_DISABLE(hadc);
1484
1485 /* Check if ADC is effectively disabled */
1486 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1487 {
1488 /* Disable the selected ADC DMA mode */
1489 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
1490
1491 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1492 /* DMA transfer is on going) */
1493 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1494
1495 /* Disable ADC overrun interrupt */
1496 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1497
1498 /* Set ADC state */
1499 ADC_STATE_CLR_SET(hadc->State,
1500 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1501 HAL_ADC_STATE_READY);
1502 }
1503
1504 /* Process unlocked */
1505 __HAL_UNLOCK(hadc);
1506
1507 /* Return function status */
1508 return tmp_hal_status;
1509 }
1510
1511 /**
1512 * @brief Gets the converted value from data register of regular channel.
1513 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1514 * the configuration information for the specified ADC.
1515 * @retval Converted value
1516 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)1517 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1518 {
1519 /* Return the selected ADC converted value */
1520 return hadc->Instance->DR;
1521 }
1522
1523 /**
1524 * @brief Regular conversion complete callback in non blocking mode
1525 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1526 * the configuration information for the specified ADC.
1527 * @retval None
1528 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)1529 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1530 {
1531 /* Prevent unused argument(s) compilation warning */
1532 UNUSED(hadc);
1533 /* NOTE : This function Should not be modified, when the callback is needed,
1534 the HAL_ADC_ConvCpltCallback could be implemented in the user file
1535 */
1536 }
1537
1538 /**
1539 * @brief Regular conversion half DMA transfer callback in non blocking mode
1540 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1541 * the configuration information for the specified ADC.
1542 * @retval None
1543 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)1544 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1545 {
1546 /* Prevent unused argument(s) compilation warning */
1547 UNUSED(hadc);
1548 /* NOTE : This function Should not be modified, when the callback is needed,
1549 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
1550 */
1551 }
1552
1553 /**
1554 * @brief Analog watchdog callback in non blocking mode
1555 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1556 * the configuration information for the specified ADC.
1557 * @retval None
1558 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)1559 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1560 {
1561 /* Prevent unused argument(s) compilation warning */
1562 UNUSED(hadc);
1563 /* NOTE : This function Should not be modified, when the callback is needed,
1564 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
1565 */
1566 }
1567
1568 /**
1569 * @brief Error ADC callback.
1570 * @note In case of error due to overrun when using ADC with DMA transfer
1571 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
1572 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
1573 * - If needed, restart a new ADC conversion using function
1574 * "HAL_ADC_Start_DMA()"
1575 * (this function is also clearing overrun flag)
1576 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1577 * the configuration information for the specified ADC.
1578 * @retval None
1579 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)1580 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1581 {
1582 /* Prevent unused argument(s) compilation warning */
1583 UNUSED(hadc);
1584 /* NOTE : This function Should not be modified, when the callback is needed,
1585 the HAL_ADC_ErrorCallback could be implemented in the user file
1586 */
1587 }
1588
1589 /**
1590 * @}
1591 */
1592
1593 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1594 * @brief Peripheral Control functions
1595 *
1596 @verbatim
1597 ===============================================================================
1598 ##### Peripheral Control functions #####
1599 ===============================================================================
1600 [..] This section provides functions allowing to:
1601 (+) Configure regular channels.
1602 (+) Configure injected channels.
1603 (+) Configure multimode.
1604 (+) Configure the analog watch dog.
1605
1606 @endverbatim
1607 * @{
1608 */
1609
1610 /**
1611 * @brief Configures for the selected ADC regular channel its corresponding
1612 * rank in the sequencer and its sample time.
1613 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1614 * the configuration information for the specified ADC.
1615 * @param sConfig ADC configuration structure.
1616 * @retval HAL status
1617 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)1618 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1619 {
1620 __IO uint32_t counter = 0U;
1621 ADC_Common_TypeDef *tmpADC_Common;
1622
1623 /* Check the parameters */
1624 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1625 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1626 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1627
1628 /* Process locked */
1629 __HAL_LOCK(hadc);
1630
1631 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1632 if (sConfig->Channel > ADC_CHANNEL_9)
1633 {
1634 /* Clear the old sample time */
1635 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
1636
1637 /* Set the new sample time */
1638 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
1639 }
1640 else /* ADC_Channel include in ADC_Channel_[0..9] */
1641 {
1642 /* Clear the old sample time */
1643 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
1644
1645 /* Set the new sample time */
1646 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
1647 }
1648
1649 /* For Rank 1 to 6 */
1650 if (sConfig->Rank < 7U)
1651 {
1652 /* Clear the old SQx bits for the selected rank */
1653 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
1654
1655 /* Set the SQx bits for the selected rank */
1656 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
1657 }
1658 /* For Rank 7 to 12 */
1659 else if (sConfig->Rank < 13U)
1660 {
1661 /* Clear the old SQx bits for the selected rank */
1662 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
1663
1664 /* Set the SQx bits for the selected rank */
1665 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
1666 }
1667 /* For Rank 13 to 16 */
1668 else
1669 {
1670 /* Clear the old SQx bits for the selected rank */
1671 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
1672
1673 /* Set the SQx bits for the selected rank */
1674 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
1675 }
1676
1677 /* Pointer to the common control register to which is belonging hadc */
1678 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1679 /* control register) */
1680 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1681
1682 /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
1683 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
1684 {
1685 /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
1686 if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
1687 {
1688 tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
1689 }
1690 /* Enable the VBAT channel*/
1691 tmpADC_Common->CCR |= ADC_CCR_VBATE;
1692 }
1693
1694 /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
1695 Channel_17 is selected for VREFINT enable TSVREFE */
1696 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
1697 {
1698 /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
1699 if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
1700 {
1701 tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
1702 }
1703 /* Enable the Temperature sensor and VREFINT channel*/
1704 tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
1705
1706 if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
1707 {
1708 /* Delay for temperature sensor stabilization time */
1709 /* Compute number of CPU cycles to wait for */
1710 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
1711 while(counter != 0U)
1712 {
1713 counter--;
1714 }
1715 }
1716 }
1717
1718 /* Process unlocked */
1719 __HAL_UNLOCK(hadc);
1720
1721 /* Return function status */
1722 return HAL_OK;
1723 }
1724
1725 /**
1726 * @brief Configures the analog watchdog.
1727 * @note Analog watchdog thresholds can be modified while ADC conversion
1728 * is on going.
1729 * In this case, some constraints must be taken into account:
1730 * The programmed threshold values are effective from the next
1731 * ADC EOC (end of unitary conversion).
1732 * Considering that registers write delay may happen due to
1733 * bus activity, this might cause an uncertainty on the
1734 * effective timing of the new programmed threshold values.
1735 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1736 * the configuration information for the specified ADC.
1737 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
1738 * that contains the configuration information of ADC analog watchdog.
1739 * @retval HAL status
1740 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)1741 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1742 {
1743 #ifdef USE_FULL_ASSERT
1744 uint32_t tmp = 0U;
1745 #endif /* USE_FULL_ASSERT */
1746
1747 /* Check the parameters */
1748 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
1749 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1750 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1751
1752 #ifdef USE_FULL_ASSERT
1753 tmp = ADC_GET_RESOLUTION(hadc);
1754 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
1755 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
1756 #endif /* USE_FULL_ASSERT */
1757
1758 /* Process locked */
1759 __HAL_LOCK(hadc);
1760
1761 if(AnalogWDGConfig->ITMode == ENABLE)
1762 {
1763 /* Enable the ADC Analog watchdog interrupt */
1764 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1765 }
1766 else
1767 {
1768 /* Disable the ADC Analog watchdog interrupt */
1769 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1770 }
1771
1772 /* Clear AWDEN, JAWDEN and AWDSGL bits */
1773 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
1774
1775 /* Set the analog watchdog enable mode */
1776 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
1777
1778 /* Set the high threshold */
1779 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1780
1781 /* Set the low threshold */
1782 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1783
1784 /* Clear the Analog watchdog channel select bits */
1785 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
1786
1787 /* Set the Analog watchdog channel */
1788 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
1789
1790 /* Process unlocked */
1791 __HAL_UNLOCK(hadc);
1792
1793 /* Return function status */
1794 return HAL_OK;
1795 }
1796
1797 /**
1798 * @}
1799 */
1800
1801 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
1802 * @brief ADC Peripheral State functions
1803 *
1804 @verbatim
1805 ===============================================================================
1806 ##### Peripheral State and errors functions #####
1807 ===============================================================================
1808 [..]
1809 This subsection provides functions allowing to
1810 (+) Check the ADC state
1811 (+) Check the ADC Error
1812
1813 @endverbatim
1814 * @{
1815 */
1816
1817 /**
1818 * @brief return the ADC state
1819 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1820 * the configuration information for the specified ADC.
1821 * @retval HAL state
1822 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)1823 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1824 {
1825 /* Return ADC state */
1826 return hadc->State;
1827 }
1828
1829 /**
1830 * @brief Return the ADC error code
1831 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1832 * the configuration information for the specified ADC.
1833 * @retval ADC Error Code
1834 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)1835 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1836 {
1837 return hadc->ErrorCode;
1838 }
1839
1840 /**
1841 * @}
1842 */
1843
1844 /** @addtogroup ADC_Private_Functions
1845 * @{
1846 */
1847
1848 /**
1849 * @brief Initializes the ADCx peripheral according to the specified parameters
1850 * in the ADC_InitStruct without initializing the ADC MSP.
1851 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1852 * the configuration information for the specified ADC.
1853 * @retval None
1854 */
ADC_Init(ADC_HandleTypeDef * hadc)1855 static void ADC_Init(ADC_HandleTypeDef* hadc)
1856 {
1857 ADC_Common_TypeDef *tmpADC_Common;
1858
1859 /* Set ADC parameters */
1860 /* Pointer to the common control register to which is belonging hadc */
1861 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1862 /* control register) */
1863 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1864
1865 /* Set the ADC clock prescaler */
1866 tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
1867 tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
1868
1869 /* Set ADC scan mode */
1870 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
1871 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
1872
1873 /* Set ADC resolution */
1874 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
1875 hadc->Instance->CR1 |= hadc->Init.Resolution;
1876
1877 /* Set ADC data alignment */
1878 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
1879 hadc->Instance->CR2 |= hadc->Init.DataAlign;
1880
1881 /* Enable external trigger if trigger selection is different of software */
1882 /* start. */
1883 /* Note: This configuration keeps the hardware feature of parameter */
1884 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
1885 /* software start. */
1886 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
1887 {
1888 /* Select external trigger to start conversion */
1889 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1890 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
1891
1892 /* Select external trigger polarity */
1893 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1894 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
1895 }
1896 else
1897 {
1898 /* Reset the external trigger */
1899 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1900 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1901 }
1902
1903 /* Enable or disable ADC continuous conversion mode */
1904 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
1905 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
1906
1907 if(hadc->Init.DiscontinuousConvMode != DISABLE)
1908 {
1909 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
1910
1911 /* Enable the selected ADC regular discontinuous mode */
1912 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
1913
1914 /* Set the number of channels to be converted in discontinuous mode */
1915 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
1916 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
1917 }
1918 else
1919 {
1920 /* Disable the selected ADC regular discontinuous mode */
1921 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
1922 }
1923
1924 /* Set ADC number of conversion */
1925 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
1926 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
1927
1928 /* Enable or disable ADC DMA continuous request */
1929 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
1930 hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
1931
1932 /* Enable or disable ADC end of conversion selection */
1933 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
1934 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
1935 }
1936
1937 /**
1938 * @brief DMA transfer complete callback.
1939 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1940 * the configuration information for the specified DMA module.
1941 * @retval None
1942 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)1943 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1944 {
1945 /* Retrieve ADC handle corresponding to current DMA handle */
1946 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1947
1948 /* Update state machine on conversion status if not in error state */
1949 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
1950 {
1951 /* Update ADC state machine */
1952 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1953
1954 /* Determine whether any further conversion upcoming on group regular */
1955 /* by external trigger, continuous mode or scan sequence on going. */
1956 /* Note: On STM32F4, there is no independent flag of end of sequence. */
1957 /* The test of scan sequence on going is done either with scan */
1958 /* sequence disabled or with end of conversion flag set to */
1959 /* of end of sequence. */
1960 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1961 (hadc->Init.ContinuousConvMode == DISABLE) &&
1962 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1963 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1964 {
1965 /* Disable ADC end of single conversion interrupt on group regular */
1966 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1967 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1968 /* by overrun IRQ process below. */
1969 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1970
1971 /* Set ADC state */
1972 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1973
1974 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1975 {
1976 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1977 }
1978 }
1979
1980 /* Conversion complete callback */
1981 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1982 hadc->ConvCpltCallback(hadc);
1983 #else
1984 HAL_ADC_ConvCpltCallback(hadc);
1985 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1986 }
1987 else /* DMA and-or internal error occurred */
1988 {
1989 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
1990 {
1991 /* Call HAL ADC Error Callback function */
1992 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1993 hadc->ErrorCallback(hadc);
1994 #else
1995 HAL_ADC_ErrorCallback(hadc);
1996 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1997 }
1998 else
1999 {
2000 /* Call DMA error callback */
2001 hadc->DMA_Handle->XferErrorCallback(hdma);
2002 }
2003 }
2004 }
2005
2006 /**
2007 * @brief DMA half transfer complete callback.
2008 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2009 * the configuration information for the specified DMA module.
2010 * @retval None
2011 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)2012 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2013 {
2014 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2015 /* Half conversion callback */
2016 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2017 hadc->ConvHalfCpltCallback(hadc);
2018 #else
2019 HAL_ADC_ConvHalfCpltCallback(hadc);
2020 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2021 }
2022
2023 /**
2024 * @brief DMA error callback
2025 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2026 * the configuration information for the specified DMA module.
2027 * @retval None
2028 */
ADC_DMAError(DMA_HandleTypeDef * hdma)2029 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2030 {
2031 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2032 hadc->State= HAL_ADC_STATE_ERROR_DMA;
2033 /* Set ADC error code to DMA error */
2034 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
2035 /* Error callback */
2036 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2037 hadc->ErrorCallback(hadc);
2038 #else
2039 HAL_ADC_ErrorCallback(hadc);
2040 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2041 }
2042
2043 /**
2044 * @}
2045 */
2046
2047 /**
2048 * @}
2049 */
2050
2051 #endif /* HAL_ADC_MODULE_ENABLED */
2052 /**
2053 * @}
2054 */
2055
2056 /**
2057 * @}
2058 */
2059
2060 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2061