1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_fmpsmbus.h 4 * @author MCD Application Team 5 * @brief Header file of FMPSMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F4xx_HAL_FMPSMBUS_H 22 #define STM32F4xx_HAL_FMPSMBUS_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(FMPI2C_CR1_PE) 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f4xx_hal_def.h" 31 32 /** @addtogroup STM32F4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup FMPSMBUS 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types 42 * @{ 43 */ 44 45 /** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition 46 * @brief FMPSMBUS Configuration Structure definition 47 * @{ 48 */ 49 typedef struct 50 { 51 uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. 52 This parameter calculated by referring to FMPSMBUS initialization 53 section in Reference manual */ 54 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 55 This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ 56 57 uint32_t OwnAddress1; /*!< Specifies the first device own address. 58 This parameter can be a 7-bit or 10-bit address. */ 59 60 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 61 This parameter can be a value of @ref FMPSMBUS_addressing_mode */ 62 63 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 64 This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ 65 66 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 67 This parameter can be a 7-bit address. */ 68 69 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected 70 This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ 71 72 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 73 This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ 74 75 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 76 This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ 77 78 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 79 This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ 80 81 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 82 This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ 83 84 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. 85 (Enable bits and different timeout values) 86 This parameter calculated by referring to FMPSMBUS initialization 87 section in Reference manual */ 88 } FMPSMBUS_InitTypeDef; 89 /** 90 * @} 91 */ 92 93 /** @defgroup HAL_state_definition HAL state definition 94 * @brief HAL State definition 95 * @{ 96 */ 97 #define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ 98 #define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ 99 #define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ 100 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 101 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 102 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 103 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 104 #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 105 #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 106 #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition 112 * @brief FMPSMBUS Error Code definition 113 * @{ 114 */ 115 #define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 116 #define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 117 #define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 118 #define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 119 #define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 120 #define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 121 #define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 122 #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 123 #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 124 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 125 #define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 126 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 127 #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 128 /** 129 * @} 130 */ 131 132 /** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition 133 * @brief FMPSMBUS handle Structure definition 134 * @{ 135 */ 136 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 137 typedef struct __FMPSMBUS_HandleTypeDef 138 #else 139 typedef struct 140 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 141 { 142 FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ 143 144 FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ 145 146 uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ 147 148 uint16_t XferSize; /*!< FMPSMBUS transfer size */ 149 150 __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ 151 152 __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ 153 154 __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ 155 156 HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ 157 158 __IO uint32_t State; /*!< FMPSMBUS communication state */ 159 160 __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ 161 162 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 163 void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */ 164 void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */ 165 void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */ 166 void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */ 167 void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */ 168 void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */ 169 170 void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */ 171 172 void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */ 173 void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */ 174 175 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 176 } FMPSMBUS_HandleTypeDef; 177 178 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 179 /** 180 * @brief HAL FMPSMBUS Callback ID enumeration definition 181 */ 182 typedef enum 183 { 184 HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ 185 HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ 186 HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ 187 HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ 188 HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ 189 HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ 190 191 HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ 192 HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ 193 194 } HAL_FMPSMBUS_CallbackIDTypeDef; 195 196 /** 197 * @brief HAL FMPSMBUS Callback pointer definition 198 */ 199 typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */ 200 typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */ 201 202 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 203 /** 204 * @} 205 */ 206 207 /** 208 * @} 209 */ 210 /* Exported constants --------------------------------------------------------*/ 211 212 /** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants 213 * @{ 214 */ 215 216 /** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter 217 * @{ 218 */ 219 #define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) 220 #define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF 221 /** 222 * @} 223 */ 224 225 /** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode 226 * @{ 227 */ 228 #define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 229 #define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 230 /** 231 * @} 232 */ 233 234 /** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode 235 * @{ 236 */ 237 238 #define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) 239 #define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN 240 /** 241 * @} 242 */ 243 244 /** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks 245 * @{ 246 */ 247 248 #define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) 249 #define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) 250 #define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) 251 #define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) 252 #define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) 253 #define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) 254 #define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) 255 #define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) 256 /** 257 * @} 258 */ 259 260 261 /** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode 262 * @{ 263 */ 264 #define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) 265 #define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN 266 /** 267 * @} 268 */ 269 270 /** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode 271 * @{ 272 */ 273 #define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) 274 #define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH 275 /** 276 * @} 277 */ 278 279 /** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode 280 * @{ 281 */ 282 #define FMPSMBUS_PEC_DISABLE (0x00000000U) 283 #define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN 284 /** 285 * @} 286 */ 287 288 /** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode 289 * @{ 290 */ 291 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN 292 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) 293 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN 294 /** 295 * @} 296 */ 297 298 /** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition 299 * @{ 300 */ 301 302 #define FMPSMBUS_SOFTEND_MODE (0x00000000U) 303 #define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD 304 #define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND 305 #define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE 306 /** 307 * @} 308 */ 309 310 /** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition 311 * @{ 312 */ 313 314 #define FMPSMBUS_NO_STARTSTOP (0x00000000U) 315 #define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) 316 #define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) 317 #define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) 318 /** 319 * @} 320 */ 321 322 /** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition 323 * @{ 324 */ 325 326 /* List of XferOptions in usage of : 327 * 1- Restart condition when direction change 328 * 2- No Restart condition in other use cases 329 */ 330 #define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE 331 #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) 332 #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 333 #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 334 #define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) 335 #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 336 #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 337 338 /* List of XferOptions in usage of : 339 * 1- Restart condition in all use cases (direction change or not) 340 */ 341 #define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 342 #define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 343 #define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 344 #define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 345 /** 346 * @} 347 */ 348 349 /** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition 350 * @brief FMPSMBUS Interrupt definition 351 * Elements values convention: 0xXXXXXXXX 352 * - XXXXXXXX : Interrupt control mask 353 * @{ 354 */ 355 #define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE 356 #define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE 357 #define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE 358 #define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE 359 #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE 360 #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE 361 #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE 362 #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) 363 #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI) 364 #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) 365 #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) 366 /** 367 * @} 368 */ 369 370 /** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition 371 * @brief Flag definition 372 * Elements values convention: 0xXXXXYYYY 373 * - XXXXXXXX : Flag mask 374 * @{ 375 */ 376 377 #define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE 378 #define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS 379 #define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE 380 #define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR 381 #define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF 382 #define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF 383 #define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC 384 #define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR 385 #define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR 386 #define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO 387 #define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR 388 #define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR 389 #define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT 390 #define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT 391 #define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY 392 #define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR 393 /** 394 * @} 395 */ 396 397 /** 398 * @} 399 */ 400 401 /* Exported macros ------------------------------------------------------------*/ 402 /** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros 403 * @{ 404 */ 405 406 /** @brief Reset FMPSMBUS handle state. 407 * @param __HANDLE__ specifies the FMPSMBUS Handle. 408 * @retval None 409 */ 410 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 411 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 412 (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ 413 (__HANDLE__)->MspInitCallback = NULL; \ 414 (__HANDLE__)->MspDeInitCallback = NULL; \ 415 } while(0) 416 #else 417 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) 418 #endif 419 420 /** @brief Enable the specified FMPSMBUS interrupts. 421 * @param __HANDLE__ specifies the FMPSMBUS Handle. 422 * @param __INTERRUPT__ specifies the interrupt source to enable. 423 * This parameter can be one of the following values: 424 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 425 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 426 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 427 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 428 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 429 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 430 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 431 * 432 * @retval None 433 */ 434 #define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 435 436 /** @brief Disable the specified FMPSMBUS interrupts. 437 * @param __HANDLE__ specifies the FMPSMBUS Handle. 438 * @param __INTERRUPT__ specifies the interrupt source to disable. 439 * This parameter can be one of the following values: 440 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 441 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 442 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 443 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 444 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 445 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 446 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 447 * 448 * @retval None 449 */ 450 #define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 451 452 /** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not. 453 * @param __HANDLE__ specifies the FMPSMBUS Handle. 454 * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. 455 * This parameter can be one of the following values: 456 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 457 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 458 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 459 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 460 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 461 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 462 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 463 * 464 * @retval The new state of __IT__ (SET or RESET). 465 */ 466 #define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 467 468 /** @brief Check whether the specified FMPSMBUS flag is set or not. 469 * @param __HANDLE__ specifies the FMPSMBUS Handle. 470 * @param __FLAG__ specifies the flag to check. 471 * This parameter can be one of the following values: 472 * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty 473 * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status 474 * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty 475 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 476 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 477 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 478 * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) 479 * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload 480 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 481 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 482 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 483 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 484 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 485 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 486 * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy 487 * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) 488 * 489 * @retval The new state of __FLAG__ (SET or RESET). 490 */ 491 #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) 492 #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 493 494 /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. 495 * @param __HANDLE__ specifies the FMPSMBUS Handle. 496 * @param __FLAG__ specifies the flag to clear. 497 * This parameter can be any combination of the following values: 498 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 499 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 500 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 501 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 502 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 503 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 504 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 505 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 506 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 507 * 508 * @retval None 509 */ 510 #define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 511 512 /** @brief Enable the specified FMPSMBUS peripheral. 513 * @param __HANDLE__ specifies the FMPSMBUS Handle. 514 * @retval None 515 */ 516 #define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 517 518 /** @brief Disable the specified FMPSMBUS peripheral. 519 * @param __HANDLE__ specifies the FMPSMBUS Handle. 520 * @retval None 521 */ 522 #define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 523 524 /** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode. 525 * @param __HANDLE__ specifies the FMPSMBUS Handle. 526 * @retval None 527 */ 528 #define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) 529 530 /** 531 * @} 532 */ 533 534 535 /* Private constants ---------------------------------------------------------*/ 536 537 /* Private macros ------------------------------------------------------------*/ 538 /** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros 539 * @{ 540 */ 541 542 #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ 543 ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) 544 545 #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 546 547 #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ 548 ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) 549 550 #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ 551 ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) 552 553 #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ 554 ((MASK) == FMPSMBUS_OA2_MASK01) || \ 555 ((MASK) == FMPSMBUS_OA2_MASK02) || \ 556 ((MASK) == FMPSMBUS_OA2_MASK03) || \ 557 ((MASK) == FMPSMBUS_OA2_MASK04) || \ 558 ((MASK) == FMPSMBUS_OA2_MASK05) || \ 559 ((MASK) == FMPSMBUS_OA2_MASK06) || \ 560 ((MASK) == FMPSMBUS_OA2_MASK07)) 561 562 #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ 563 ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) 564 565 #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ 566 ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) 567 568 #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ 569 ((PEC) == FMPSMBUS_PEC_ENABLE)) 570 571 #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ 572 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ 573 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) 574 575 #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ 576 ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ 577 ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ 578 ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ 579 ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 580 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 581 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ 582 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE ))) 583 584 585 #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ 586 ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ 587 ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ 588 ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) 589 590 591 #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 592 ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ 593 ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ 594 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 595 ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ 596 ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ 597 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 598 ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) 599 600 #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ 601 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 602 ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ 603 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 604 605 #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN))) 606 #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) 607 608 #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ 609 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) 610 611 #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) 612 #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) 613 #define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) 614 #define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) 615 #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) 616 617 #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 618 #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 619 620 #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 621 #define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 622 623 /** 624 * @} 625 */ 626 627 /* Exported functions --------------------------------------------------------*/ 628 /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions 629 * @{ 630 */ 631 632 /** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 633 * @{ 634 */ 635 636 /* Initialization and de-initialization functions ****************************/ 637 HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); 638 HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 639 void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 640 void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 641 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); 642 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); 643 644 /* Callbacks Register/UnRegister functions ***********************************/ 645 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 646 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback); 647 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); 648 649 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback); 650 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 651 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 652 /** 653 * @} 654 */ 655 656 /** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions 657 * @{ 658 */ 659 660 /* IO operation functions *****************************************************/ 661 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 662 * @{ 663 */ 664 /******* Blocking mode: Polling */ 665 HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); 666 /** 667 * @} 668 */ 669 670 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 671 * @{ 672 */ 673 /******* Non-Blocking mode: Interrupt */ 674 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 675 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 676 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); 677 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 678 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 679 680 HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 681 HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 682 HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 683 HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 684 /** 685 * @} 686 */ 687 688 /** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 689 * @{ 690 */ 691 /******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 692 void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 693 void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 694 void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 695 void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 696 void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 697 void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 698 void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 699 void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 700 void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 701 702 /** 703 * @} 704 */ 705 706 /** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 707 * @{ 708 */ 709 710 /* Peripheral State and Errors functions **************************************************/ 711 uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); 712 uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); 713 714 /** 715 * @} 716 */ 717 718 /** 719 * @} 720 */ 721 722 /* Private Functions ---------------------------------------------------------*/ 723 /** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions 724 * @{ 725 */ 726 /* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ 727 /** 728 * @} 729 */ 730 731 /** 732 * @} 733 */ 734 735 /** 736 * @} 737 */ 738 739 /** 740 * @} 741 */ 742 743 #endif /* FMPI2C_CR1_PE */ 744 #ifdef __cplusplus 745 } 746 #endif 747 748 749 #endif /* STM32F4xx_HAL_FMPSMBUS_H */ 750 751 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 752