1/** 2 ****************************************************************************** 3 * @file startup_stm32f407xx.s 4 * @author MCD Application Team 5 * @brief STM32F407xx Devices vector table for GCC based toolchains. 6 * This module performs: 7 * - Set the initial SP 8 * - Set the initial PC == Reset_Handler, 9 * - Set the vector table entries with the exceptions ISR address 10 * - Branches to main in the C library (which eventually 11 * calls main()). 12 * After Reset the Cortex-M4 processor is in Thread mode, 13 * priority is Privileged, and the Stack is set to Main. 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> 18 * 19 * Redistribution and use in source and binary forms, with or without modification, 20 * are permitted provided that the following conditions are met: 21 * 1. Redistributions of source code must retain the above copyright notice, 22 * this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright notice, 24 * this list of conditions and the following disclaimer in the documentation 25 * and/or other materials provided with the distribution. 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 ****************************************************************************** 42 */ 43 44 .syntax unified 45 .cpu cortex-m4 46 .fpu softvfp 47 .thumb 48 49.global g_pfnVectors 50.global Default_Handler 51 52/* start address for the initialization values of the .data section. 53defined in linker script */ 54.word _sidata 55/* start address for the .data section. defined in linker script */ 56.word _sdata 57/* end address for the .data section. defined in linker script */ 58.word _edata 59/* start address for the .bss section. defined in linker script */ 60.word _sbss 61/* end address for the .bss section. defined in linker script */ 62.word _ebss 63/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ 64 65/** 66 * @brief This is the code that gets called when the processor first 67 * starts execution following a reset event. Only the absolutely 68 * necessary set is performed, after which the application 69 * supplied main() routine is called. 70 * @param None 71 * @retval : None 72*/ 73 74 .section .text.Reset_Handler 75 .weak Reset_Handler 76 .type Reset_Handler, %function 77Reset_Handler: 78 ldr sp, =_estack /* set stack pointer */ 79 80/* Copy the data segment initializers from flash to SRAM */ 81 movs r1, #0 82 b LoopCopyDataInit 83 84CopyDataInit: 85 ldr r3, =_sidata 86 ldr r3, [r3, r1] 87 str r3, [r0, r1] 88 adds r1, r1, #4 89 90LoopCopyDataInit: 91 ldr r0, =_sdata 92 ldr r3, =_edata 93 adds r2, r0, r1 94 cmp r2, r3 95 bcc CopyDataInit 96 ldr r2, =_sbss 97 b LoopFillZerobss 98/* Zero fill the bss segment. */ 99FillZerobss: 100 movs r3, #0 101 str r3, [r2], #4 102 103LoopFillZerobss: 104 ldr r3, = _ebss 105 cmp r2, r3 106 bcc FillZerobss 107 108/* Call the clock system intitialization function.*/ 109 bl SystemInit 110/* Call static constructors */ 111 bl __libc_init_array 112/* Call the application's entry point.*/ 113 bl main 114 bx lr 115.size Reset_Handler, .-Reset_Handler 116 117/** 118 * @brief This is the code that gets called when the processor receives an 119 * unexpected interrupt. This simply enters an infinite loop, preserving 120 * the system state for examination by a debugger. 121 * @param None 122 * @retval None 123*/ 124 .section .text.Default_Handler,"ax",%progbits 125Default_Handler: 126Infinite_Loop: 127 b Infinite_Loop 128 .size Default_Handler, .-Default_Handler 129/****************************************************************************** 130* 131* The minimal vector table for a Cortex M3. Note that the proper constructs 132* must be placed on this to ensure that it ends up at physical address 133* 0x0000.0000. 134* 135*******************************************************************************/ 136 .section .isr_vector,"a",%progbits 137 .type g_pfnVectors, %object 138 .size g_pfnVectors, .-g_pfnVectors 139 140 141g_pfnVectors: 142 .word _estack 143 .word Reset_Handler 144 .word NMI_Handler 145 .word HardFault_Handler 146 .word MemManage_Handler 147 .word BusFault_Handler 148 .word UsageFault_Handler 149 .word 0 150 .word 0 151 .word 0 152 .word 0 153 .word SVC_Handler 154 .word DebugMon_Handler 155 .word 0 156 .word PendSV_Handler 157 .word SysTick_Handler 158 159 /* External Interrupts */ 160 .word WWDG_IRQHandler /* Window WatchDog */ 161 .word PVD_IRQHandler /* PVD through EXTI Line detection */ 162 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ 163 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ 164 .word FLASH_IRQHandler /* FLASH */ 165 .word RCC_IRQHandler /* RCC */ 166 .word EXTI0_IRQHandler /* EXTI Line0 */ 167 .word EXTI1_IRQHandler /* EXTI Line1 */ 168 .word EXTI2_IRQHandler /* EXTI Line2 */ 169 .word EXTI3_IRQHandler /* EXTI Line3 */ 170 .word EXTI4_IRQHandler /* EXTI Line4 */ 171 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ 172 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ 173 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ 174 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ 175 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ 176 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ 177 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ 178 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ 179 .word CAN1_TX_IRQHandler /* CAN1 TX */ 180 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ 181 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 182 .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 183 .word EXTI9_5_IRQHandler /* External Line[9:5]s */ 184 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ 185 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ 186 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ 187 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 188 .word TIM2_IRQHandler /* TIM2 */ 189 .word TIM3_IRQHandler /* TIM3 */ 190 .word TIM4_IRQHandler /* TIM4 */ 191 .word I2C1_EV_IRQHandler /* I2C1 Event */ 192 .word I2C1_ER_IRQHandler /* I2C1 Error */ 193 .word I2C2_EV_IRQHandler /* I2C2 Event */ 194 .word I2C2_ER_IRQHandler /* I2C2 Error */ 195 .word SPI1_IRQHandler /* SPI1 */ 196 .word SPI2_IRQHandler /* SPI2 */ 197 .word USART1_IRQHandler /* USART1 */ 198 .word USART2_IRQHandler /* USART2 */ 199 .word USART3_IRQHandler /* USART3 */ 200 .word EXTI15_10_IRQHandler /* External Line[15:10]s */ 201 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ 202 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ 203 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ 204 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ 205 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ 206 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ 207 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ 208 .word FSMC_IRQHandler /* FSMC */ 209 .word SDIO_IRQHandler /* SDIO */ 210 .word TIM5_IRQHandler /* TIM5 */ 211 .word SPI3_IRQHandler /* SPI3 */ 212 .word UART4_IRQHandler /* UART4 */ 213 .word UART5_IRQHandler /* UART5 */ 214 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ 215 .word TIM7_IRQHandler /* TIM7 */ 216 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ 217 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ 218 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ 219 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ 220 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ 221 .word ETH_IRQHandler /* Ethernet */ 222 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ 223 .word CAN2_TX_IRQHandler /* CAN2 TX */ 224 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ 225 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ 226 .word CAN2_SCE_IRQHandler /* CAN2 SCE */ 227 .word OTG_FS_IRQHandler /* USB OTG FS */ 228 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ 229 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ 230 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ 231 .word USART6_IRQHandler /* USART6 */ 232 .word I2C3_EV_IRQHandler /* I2C3 event */ 233 .word I2C3_ER_IRQHandler /* I2C3 error */ 234 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ 235 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ 236 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ 237 .word OTG_HS_IRQHandler /* USB OTG HS */ 238 .word DCMI_IRQHandler /* DCMI */ 239 .word 0 /* CRYP crypto */ 240 .word HASH_RNG_IRQHandler /* Hash and Rng */ 241 .word FPU_IRQHandler /* FPU */ 242 243 244/******************************************************************************* 245* 246* Provide weak aliases for each Exception handler to the Default_Handler. 247* As they are weak aliases, any function with the same name will override 248* this definition. 249* 250*******************************************************************************/ 251 .weak NMI_Handler 252 .thumb_set NMI_Handler,Default_Handler 253 254 .weak HardFault_Handler 255 .thumb_set HardFault_Handler,Default_Handler 256 257 .weak MemManage_Handler 258 .thumb_set MemManage_Handler,Default_Handler 259 260 .weak BusFault_Handler 261 .thumb_set BusFault_Handler,Default_Handler 262 263 .weak UsageFault_Handler 264 .thumb_set UsageFault_Handler,Default_Handler 265 266 .weak SVC_Handler 267 .thumb_set SVC_Handler,Default_Handler 268 269 .weak DebugMon_Handler 270 .thumb_set DebugMon_Handler,Default_Handler 271 272 .weak PendSV_Handler 273 .thumb_set PendSV_Handler,Default_Handler 274 275 .weak SysTick_Handler 276 .thumb_set SysTick_Handler,Default_Handler 277 278 .weak WWDG_IRQHandler 279 .thumb_set WWDG_IRQHandler,Default_Handler 280 281 .weak PVD_IRQHandler 282 .thumb_set PVD_IRQHandler,Default_Handler 283 284 .weak TAMP_STAMP_IRQHandler 285 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 286 287 .weak RTC_WKUP_IRQHandler 288 .thumb_set RTC_WKUP_IRQHandler,Default_Handler 289 290 .weak FLASH_IRQHandler 291 .thumb_set FLASH_IRQHandler,Default_Handler 292 293 .weak RCC_IRQHandler 294 .thumb_set RCC_IRQHandler,Default_Handler 295 296 .weak EXTI0_IRQHandler 297 .thumb_set EXTI0_IRQHandler,Default_Handler 298 299 .weak EXTI1_IRQHandler 300 .thumb_set EXTI1_IRQHandler,Default_Handler 301 302 .weak EXTI2_IRQHandler 303 .thumb_set EXTI2_IRQHandler,Default_Handler 304 305 .weak EXTI3_IRQHandler 306 .thumb_set EXTI3_IRQHandler,Default_Handler 307 308 .weak EXTI4_IRQHandler 309 .thumb_set EXTI4_IRQHandler,Default_Handler 310 311 .weak DMA1_Stream0_IRQHandler 312 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler 313 314 .weak DMA1_Stream1_IRQHandler 315 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler 316 317 .weak DMA1_Stream2_IRQHandler 318 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler 319 320 .weak DMA1_Stream3_IRQHandler 321 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 322 323 .weak DMA1_Stream4_IRQHandler 324 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler 325 326 .weak DMA1_Stream5_IRQHandler 327 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler 328 329 .weak DMA1_Stream6_IRQHandler 330 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler 331 332 .weak ADC_IRQHandler 333 .thumb_set ADC_IRQHandler,Default_Handler 334 335 .weak CAN1_TX_IRQHandler 336 .thumb_set CAN1_TX_IRQHandler,Default_Handler 337 338 .weak CAN1_RX0_IRQHandler 339 .thumb_set CAN1_RX0_IRQHandler,Default_Handler 340 341 .weak CAN1_RX1_IRQHandler 342 .thumb_set CAN1_RX1_IRQHandler,Default_Handler 343 344 .weak CAN1_SCE_IRQHandler 345 .thumb_set CAN1_SCE_IRQHandler,Default_Handler 346 347 .weak EXTI9_5_IRQHandler 348 .thumb_set EXTI9_5_IRQHandler,Default_Handler 349 350 .weak TIM1_BRK_TIM9_IRQHandler 351 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler 352 353 .weak TIM1_UP_TIM10_IRQHandler 354 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler 355 356 .weak TIM1_TRG_COM_TIM11_IRQHandler 357 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler 358 359 .weak TIM1_CC_IRQHandler 360 .thumb_set TIM1_CC_IRQHandler,Default_Handler 361 362 .weak TIM2_IRQHandler 363 .thumb_set TIM2_IRQHandler,Default_Handler 364 365 .weak TIM3_IRQHandler 366 .thumb_set TIM3_IRQHandler,Default_Handler 367 368 .weak TIM4_IRQHandler 369 .thumb_set TIM4_IRQHandler,Default_Handler 370 371 .weak I2C1_EV_IRQHandler 372 .thumb_set I2C1_EV_IRQHandler,Default_Handler 373 374 .weak I2C1_ER_IRQHandler 375 .thumb_set I2C1_ER_IRQHandler,Default_Handler 376 377 .weak I2C2_EV_IRQHandler 378 .thumb_set I2C2_EV_IRQHandler,Default_Handler 379 380 .weak I2C2_ER_IRQHandler 381 .thumb_set I2C2_ER_IRQHandler,Default_Handler 382 383 .weak SPI1_IRQHandler 384 .thumb_set SPI1_IRQHandler,Default_Handler 385 386 .weak SPI2_IRQHandler 387 .thumb_set SPI2_IRQHandler,Default_Handler 388 389 .weak USART1_IRQHandler 390 .thumb_set USART1_IRQHandler,Default_Handler 391 392 .weak USART2_IRQHandler 393 .thumb_set USART2_IRQHandler,Default_Handler 394 395 .weak USART3_IRQHandler 396 .thumb_set USART3_IRQHandler,Default_Handler 397 398 .weak EXTI15_10_IRQHandler 399 .thumb_set EXTI15_10_IRQHandler,Default_Handler 400 401 .weak RTC_Alarm_IRQHandler 402 .thumb_set RTC_Alarm_IRQHandler,Default_Handler 403 404 .weak OTG_FS_WKUP_IRQHandler 405 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler 406 407 .weak TIM8_BRK_TIM12_IRQHandler 408 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler 409 410 .weak TIM8_UP_TIM13_IRQHandler 411 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler 412 413 .weak TIM8_TRG_COM_TIM14_IRQHandler 414 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler 415 416 .weak TIM8_CC_IRQHandler 417 .thumb_set TIM8_CC_IRQHandler,Default_Handler 418 419 .weak DMA1_Stream7_IRQHandler 420 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler 421 422 .weak FSMC_IRQHandler 423 .thumb_set FSMC_IRQHandler,Default_Handler 424 425 .weak SDIO_IRQHandler 426 .thumb_set SDIO_IRQHandler,Default_Handler 427 428 .weak TIM5_IRQHandler 429 .thumb_set TIM5_IRQHandler,Default_Handler 430 431 .weak SPI3_IRQHandler 432 .thumb_set SPI3_IRQHandler,Default_Handler 433 434 .weak UART4_IRQHandler 435 .thumb_set UART4_IRQHandler,Default_Handler 436 437 .weak UART5_IRQHandler 438 .thumb_set UART5_IRQHandler,Default_Handler 439 440 .weak TIM6_DAC_IRQHandler 441 .thumb_set TIM6_DAC_IRQHandler,Default_Handler 442 443 .weak TIM7_IRQHandler 444 .thumb_set TIM7_IRQHandler,Default_Handler 445 446 .weak DMA2_Stream0_IRQHandler 447 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler 448 449 .weak DMA2_Stream1_IRQHandler 450 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler 451 452 .weak DMA2_Stream2_IRQHandler 453 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler 454 455 .weak DMA2_Stream3_IRQHandler 456 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler 457 458 .weak DMA2_Stream4_IRQHandler 459 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler 460 461 .weak ETH_IRQHandler 462 .thumb_set ETH_IRQHandler,Default_Handler 463 464 .weak ETH_WKUP_IRQHandler 465 .thumb_set ETH_WKUP_IRQHandler,Default_Handler 466 467 .weak CAN2_TX_IRQHandler 468 .thumb_set CAN2_TX_IRQHandler,Default_Handler 469 470 .weak CAN2_RX0_IRQHandler 471 .thumb_set CAN2_RX0_IRQHandler,Default_Handler 472 473 .weak CAN2_RX1_IRQHandler 474 .thumb_set CAN2_RX1_IRQHandler,Default_Handler 475 476 .weak CAN2_SCE_IRQHandler 477 .thumb_set CAN2_SCE_IRQHandler,Default_Handler 478 479 .weak OTG_FS_IRQHandler 480 .thumb_set OTG_FS_IRQHandler,Default_Handler 481 482 .weak DMA2_Stream5_IRQHandler 483 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler 484 485 .weak DMA2_Stream6_IRQHandler 486 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler 487 488 .weak DMA2_Stream7_IRQHandler 489 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler 490 491 .weak USART6_IRQHandler 492 .thumb_set USART6_IRQHandler,Default_Handler 493 494 .weak I2C3_EV_IRQHandler 495 .thumb_set I2C3_EV_IRQHandler,Default_Handler 496 497 .weak I2C3_ER_IRQHandler 498 .thumb_set I2C3_ER_IRQHandler,Default_Handler 499 500 .weak OTG_HS_EP1_OUT_IRQHandler 501 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler 502 503 .weak OTG_HS_EP1_IN_IRQHandler 504 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler 505 506 .weak OTG_HS_WKUP_IRQHandler 507 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler 508 509 .weak OTG_HS_IRQHandler 510 .thumb_set OTG_HS_IRQHandler,Default_Handler 511 512 .weak DCMI_IRQHandler 513 .thumb_set DCMI_IRQHandler,Default_Handler 514 515 .weak HASH_RNG_IRQHandler 516 .thumb_set HASH_RNG_IRQHandler,Default_Handler 517 518 .weak FPU_IRQHandler 519 .thumb_set FPU_IRQHandler,Default_Handler 520 521/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 522