1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
102 allows the user to configure dynamically the driver callbacks.
103
104 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
105 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
106 the Callback ID and a pointer to the user callback function.
107
108 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
109 weak function.
110 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
111 and the Callback ID.
112
113 These functions allow to register/unregister following callbacks:
114 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
115 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
116 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
117 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
118 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
119 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
120 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
121 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
122 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
123 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
124 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
125 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
126 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
127 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
128 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
129 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
130 (+) TriggerCallback : TIM Trigger Callback.
131 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
132 (+) IC_CaptureCallback : TIM Input Capture Callback.
133 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
134 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
135 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
136 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
137 (+) ErrorCallback : TIM Error Callback.
138 (+) CommutationCallback : TIM Commutation Callback.
139 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
140 (+) BreakCallback : TIM Break Callback.
141
142 By default, after the Init and when the state is HAL_TIM_STATE_RESET
143 all interrupt callbacks are set to the corresponding weak functions:
144 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
145
146 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
147 functionalities in the Init / DeInit only when these callbacks are null
148 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
149 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
150
151 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
152 Exception done MspInit / MspDeInit that can be registered / unregistered
153 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
154 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
155 In that case first register the MspInit/MspDeInit user callbacks
156 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
157
158 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
159 not defined, the callback registration feature is not available and all callbacks
160 are set to the corresponding weak functions.
161
162 @endverbatim
163 ******************************************************************************
164 * @attention
165 *
166 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
167 * All rights reserved.</center></h2>
168 *
169 * This software component is licensed by ST under BSD 3-Clause license,
170 * the "License"; You may not use this file except in compliance with the
171 * License. You may obtain a copy of the License at:
172 * opensource.org/licenses/BSD-3-Clause
173 *
174 ******************************************************************************
175 */
176
177 /* Includes ------------------------------------------------------------------*/
178 #include "stm32f4xx_hal.h"
179
180 /** @addtogroup STM32F4xx_HAL_Driver
181 * @{
182 */
183
184 /** @defgroup TIM TIM
185 * @brief TIM HAL module driver
186 * @{
187 */
188
189 #ifdef HAL_TIM_MODULE_ENABLED
190
191 /* Private typedef -----------------------------------------------------------*/
192 /* Private define ------------------------------------------------------------*/
193 /* Private macro -------------------------------------------------------------*/
194 /* Private variables ---------------------------------------------------------*/
195 /* Private function prototypes -----------------------------------------------*/
196 /** @addtogroup TIM_Private_Functions
197 * @{
198 */
199 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
200 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
201 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
202 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
203 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
204 uint32_t TIM_ICFilter);
205 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
206 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
207 uint32_t TIM_ICFilter);
208 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
209 uint32_t TIM_ICFilter);
210 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
211 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
212 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
213 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
214 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
215 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
216 TIM_SlaveConfigTypeDef *sSlaveConfig);
217 /**
218 * @}
219 */
220 /* Exported functions --------------------------------------------------------*/
221
222 /** @defgroup TIM_Exported_Functions TIM Exported Functions
223 * @{
224 */
225
226 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
227 * @brief Time Base functions
228 *
229 @verbatim
230 ==============================================================================
231 ##### Time Base functions #####
232 ==============================================================================
233 [..]
234 This section provides functions allowing to:
235 (+) Initialize and configure the TIM base.
236 (+) De-initialize the TIM base.
237 (+) Start the Time Base.
238 (+) Stop the Time Base.
239 (+) Start the Time Base and enable interrupt.
240 (+) Stop the Time Base and disable interrupt.
241 (+) Start the Time Base and enable DMA transfer.
242 (+) Stop the Time Base and disable DMA transfer.
243
244 @endverbatim
245 * @{
246 */
247 /**
248 * @brief Initializes the TIM Time base Unit according to the specified
249 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
250 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
251 * requires a timer reset to avoid unexpected direction
252 * due to DIR bit readonly in center aligned mode.
253 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
254 * @param htim TIM Base handle
255 * @retval HAL status
256 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)257 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
258 {
259 /* Check the TIM handle allocation */
260 if (htim == NULL)
261 {
262 return HAL_ERROR;
263 }
264
265 /* Check the parameters */
266 assert_param(IS_TIM_INSTANCE(htim->Instance));
267 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
268 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
269 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
270
271 if (htim->State == HAL_TIM_STATE_RESET)
272 {
273 /* Allocate lock resource and initialize it */
274 htim->Lock = HAL_UNLOCKED;
275
276 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
277 /* Reset interrupt callbacks to legacy weak callbacks */
278 TIM_ResetCallback(htim);
279
280 if (htim->Base_MspInitCallback == NULL)
281 {
282 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
283 }
284 /* Init the low level hardware : GPIO, CLOCK, NVIC */
285 htim->Base_MspInitCallback(htim);
286 #else
287 /* Init the low level hardware : GPIO, CLOCK, NVIC */
288 HAL_TIM_Base_MspInit(htim);
289 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
290 }
291
292 /* Set the TIM state */
293 htim->State = HAL_TIM_STATE_BUSY;
294
295 /* Set the Time Base configuration */
296 TIM_Base_SetConfig(htim->Instance, &htim->Init);
297
298 /* Initialize the TIM state*/
299 htim->State = HAL_TIM_STATE_READY;
300
301 return HAL_OK;
302 }
303
304 /**
305 * @brief DeInitializes the TIM Base peripheral
306 * @param htim TIM Base handle
307 * @retval HAL status
308 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)309 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
310 {
311 /* Check the parameters */
312 assert_param(IS_TIM_INSTANCE(htim->Instance));
313
314 htim->State = HAL_TIM_STATE_BUSY;
315
316 /* Disable the TIM Peripheral Clock */
317 __HAL_TIM_DISABLE(htim);
318
319 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
320 if (htim->Base_MspDeInitCallback == NULL)
321 {
322 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
323 }
324 /* DeInit the low level hardware */
325 htim->Base_MspDeInitCallback(htim);
326 #else
327 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
328 HAL_TIM_Base_MspDeInit(htim);
329 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
330
331 /* Change TIM state */
332 htim->State = HAL_TIM_STATE_RESET;
333
334 /* Release Lock */
335 __HAL_UNLOCK(htim);
336
337 return HAL_OK;
338 }
339
340 /**
341 * @brief Initializes the TIM Base MSP.
342 * @param htim TIM Base handle
343 * @retval None
344 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)345 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
346 {
347 /* Prevent unused argument(s) compilation warning */
348 UNUSED(htim);
349
350 /* NOTE : This function should not be modified, when the callback is needed,
351 the HAL_TIM_Base_MspInit could be implemented in the user file
352 */
353 }
354
355 /**
356 * @brief DeInitializes TIM Base MSP.
357 * @param htim TIM Base handle
358 * @retval None
359 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)360 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
361 {
362 /* Prevent unused argument(s) compilation warning */
363 UNUSED(htim);
364
365 /* NOTE : This function should not be modified, when the callback is needed,
366 the HAL_TIM_Base_MspDeInit could be implemented in the user file
367 */
368 }
369
370
371 /**
372 * @brief Starts the TIM Base generation.
373 * @param htim TIM Base handle
374 * @retval HAL status
375 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)376 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
377 {
378 uint32_t tmpsmcr;
379
380 /* Check the parameters */
381 assert_param(IS_TIM_INSTANCE(htim->Instance));
382
383 /* Set the TIM state */
384 htim->State = HAL_TIM_STATE_BUSY;
385
386 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
387 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
388 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
389 {
390 __HAL_TIM_ENABLE(htim);
391 }
392
393 /* Change the TIM state*/
394 htim->State = HAL_TIM_STATE_READY;
395
396 /* Return function status */
397 return HAL_OK;
398 }
399
400 /**
401 * @brief Stops the TIM Base generation.
402 * @param htim TIM Base handle
403 * @retval HAL status
404 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)405 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
406 {
407 /* Check the parameters */
408 assert_param(IS_TIM_INSTANCE(htim->Instance));
409
410 /* Set the TIM state */
411 htim->State = HAL_TIM_STATE_BUSY;
412
413 /* Disable the Peripheral */
414 __HAL_TIM_DISABLE(htim);
415
416 /* Change the TIM state*/
417 htim->State = HAL_TIM_STATE_READY;
418
419 /* Return function status */
420 return HAL_OK;
421 }
422
423 /**
424 * @brief Starts the TIM Base generation in interrupt mode.
425 * @param htim TIM Base handle
426 * @retval HAL status
427 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)428 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
429 {
430 uint32_t tmpsmcr;
431
432 /* Check the parameters */
433 assert_param(IS_TIM_INSTANCE(htim->Instance));
434
435 /* Enable the TIM Update interrupt */
436 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
437
438 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
439 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
440 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
441 {
442 __HAL_TIM_ENABLE(htim);
443 }
444
445 /* Return function status */
446 return HAL_OK;
447 }
448
449 /**
450 * @brief Stops the TIM Base generation in interrupt mode.
451 * @param htim TIM Base handle
452 * @retval HAL status
453 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)454 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
455 {
456 /* Check the parameters */
457 assert_param(IS_TIM_INSTANCE(htim->Instance));
458 /* Disable the TIM Update interrupt */
459 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
460
461 /* Disable the Peripheral */
462 __HAL_TIM_DISABLE(htim);
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Starts the TIM Base generation in DMA mode.
470 * @param htim TIM Base handle
471 * @param pData The source Buffer address.
472 * @param Length The length of data to be transferred from memory to peripheral.
473 * @retval HAL status
474 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)475 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
476 {
477 uint32_t tmpsmcr;
478
479 /* Check the parameters */
480 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
481
482 if ((htim->State == HAL_TIM_STATE_BUSY))
483 {
484 return HAL_BUSY;
485 }
486 else if ((htim->State == HAL_TIM_STATE_READY))
487 {
488 if ((pData == NULL) && (Length > 0U))
489 {
490 return HAL_ERROR;
491 }
492 else
493 {
494 htim->State = HAL_TIM_STATE_BUSY;
495 }
496 }
497 else
498 {
499 /* nothing to do */
500 }
501
502 /* Set the DMA Period elapsed callbacks */
503 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
504 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
505
506 /* Set the DMA error callback */
507 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
508
509 /* Enable the DMA stream */
510 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
511 {
512 return HAL_ERROR;
513 }
514
515 /* Enable the TIM Update DMA request */
516 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
517
518 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
519 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
520 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
521 {
522 __HAL_TIM_ENABLE(htim);
523 }
524
525 /* Return function status */
526 return HAL_OK;
527 }
528
529 /**
530 * @brief Stops the TIM Base generation in DMA mode.
531 * @param htim TIM Base handle
532 * @retval HAL status
533 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)534 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
535 {
536 /* Check the parameters */
537 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
538
539 /* Disable the TIM Update DMA request */
540 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
541
542 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
543
544 /* Disable the Peripheral */
545 __HAL_TIM_DISABLE(htim);
546
547 /* Change the htim state */
548 htim->State = HAL_TIM_STATE_READY;
549
550 /* Return function status */
551 return HAL_OK;
552 }
553
554 /**
555 * @}
556 */
557
558 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
559 * @brief TIM Output Compare functions
560 *
561 @verbatim
562 ==============================================================================
563 ##### TIM Output Compare functions #####
564 ==============================================================================
565 [..]
566 This section provides functions allowing to:
567 (+) Initialize and configure the TIM Output Compare.
568 (+) De-initialize the TIM Output Compare.
569 (+) Start the TIM Output Compare.
570 (+) Stop the TIM Output Compare.
571 (+) Start the TIM Output Compare and enable interrupt.
572 (+) Stop the TIM Output Compare and disable interrupt.
573 (+) Start the TIM Output Compare and enable DMA transfer.
574 (+) Stop the TIM Output Compare and disable DMA transfer.
575
576 @endverbatim
577 * @{
578 */
579 /**
580 * @brief Initializes the TIM Output Compare according to the specified
581 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
582 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
583 * requires a timer reset to avoid unexpected direction
584 * due to DIR bit readonly in center aligned mode.
585 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
586 * @param htim TIM Output Compare handle
587 * @retval HAL status
588 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)589 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
590 {
591 /* Check the TIM handle allocation */
592 if (htim == NULL)
593 {
594 return HAL_ERROR;
595 }
596
597 /* Check the parameters */
598 assert_param(IS_TIM_INSTANCE(htim->Instance));
599 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
600 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
601 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
602
603 if (htim->State == HAL_TIM_STATE_RESET)
604 {
605 /* Allocate lock resource and initialize it */
606 htim->Lock = HAL_UNLOCKED;
607
608 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
609 /* Reset interrupt callbacks to legacy weak callbacks */
610 TIM_ResetCallback(htim);
611
612 if (htim->OC_MspInitCallback == NULL)
613 {
614 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
615 }
616 /* Init the low level hardware : GPIO, CLOCK, NVIC */
617 htim->OC_MspInitCallback(htim);
618 #else
619 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
620 HAL_TIM_OC_MspInit(htim);
621 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
622 }
623
624 /* Set the TIM state */
625 htim->State = HAL_TIM_STATE_BUSY;
626
627 /* Init the base time for the Output Compare */
628 TIM_Base_SetConfig(htim->Instance, &htim->Init);
629
630 /* Initialize the TIM state*/
631 htim->State = HAL_TIM_STATE_READY;
632
633 return HAL_OK;
634 }
635
636 /**
637 * @brief DeInitializes the TIM peripheral
638 * @param htim TIM Output Compare handle
639 * @retval HAL status
640 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)641 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
642 {
643 /* Check the parameters */
644 assert_param(IS_TIM_INSTANCE(htim->Instance));
645
646 htim->State = HAL_TIM_STATE_BUSY;
647
648 /* Disable the TIM Peripheral Clock */
649 __HAL_TIM_DISABLE(htim);
650
651 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
652 if (htim->OC_MspDeInitCallback == NULL)
653 {
654 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
655 }
656 /* DeInit the low level hardware */
657 htim->OC_MspDeInitCallback(htim);
658 #else
659 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
660 HAL_TIM_OC_MspDeInit(htim);
661 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
662
663 /* Change TIM state */
664 htim->State = HAL_TIM_STATE_RESET;
665
666 /* Release Lock */
667 __HAL_UNLOCK(htim);
668
669 return HAL_OK;
670 }
671
672 /**
673 * @brief Initializes the TIM Output Compare MSP.
674 * @param htim TIM Output Compare handle
675 * @retval None
676 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)677 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
678 {
679 /* Prevent unused argument(s) compilation warning */
680 UNUSED(htim);
681
682 /* NOTE : This function should not be modified, when the callback is needed,
683 the HAL_TIM_OC_MspInit could be implemented in the user file
684 */
685 }
686
687 /**
688 * @brief DeInitializes TIM Output Compare MSP.
689 * @param htim TIM Output Compare handle
690 * @retval None
691 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)692 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
693 {
694 /* Prevent unused argument(s) compilation warning */
695 UNUSED(htim);
696
697 /* NOTE : This function should not be modified, when the callback is needed,
698 the HAL_TIM_OC_MspDeInit could be implemented in the user file
699 */
700 }
701
702 /**
703 * @brief Starts the TIM Output Compare signal generation.
704 * @param htim TIM Output Compare handle
705 * @param Channel TIM Channel to be enabled
706 * This parameter can be one of the following values:
707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
711 * @retval HAL status
712 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)713 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
714 {
715 uint32_t tmpsmcr;
716
717 /* Check the parameters */
718 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
719
720 /* Enable the Output compare channel */
721 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
722
723 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
724 {
725 /* Enable the main output */
726 __HAL_TIM_MOE_ENABLE(htim);
727 }
728
729 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
730 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
731 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
732 {
733 __HAL_TIM_ENABLE(htim);
734 }
735
736 /* Return function status */
737 return HAL_OK;
738 }
739
740 /**
741 * @brief Stops the TIM Output Compare signal generation.
742 * @param htim TIM Output Compare handle
743 * @param Channel TIM Channel to be disabled
744 * This parameter can be one of the following values:
745 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
746 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
747 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
748 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
749 * @retval HAL status
750 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)751 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
752 {
753 /* Check the parameters */
754 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
755
756 /* Disable the Output compare channel */
757 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
758
759 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
760 {
761 /* Disable the Main Output */
762 __HAL_TIM_MOE_DISABLE(htim);
763 }
764
765 /* Disable the Peripheral */
766 __HAL_TIM_DISABLE(htim);
767
768 /* Return function status */
769 return HAL_OK;
770 }
771
772 /**
773 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
774 * @param htim TIM Output Compare handle
775 * @param Channel TIM Channel to be enabled
776 * This parameter can be one of the following values:
777 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
778 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
779 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
780 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
781 * @retval HAL status
782 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)783 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
784 {
785 uint32_t tmpsmcr;
786
787 /* Check the parameters */
788 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
789
790 switch (Channel)
791 {
792 case TIM_CHANNEL_1:
793 {
794 /* Enable the TIM Capture/Compare 1 interrupt */
795 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
796 break;
797 }
798
799 case TIM_CHANNEL_2:
800 {
801 /* Enable the TIM Capture/Compare 2 interrupt */
802 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
803 break;
804 }
805
806 case TIM_CHANNEL_3:
807 {
808 /* Enable the TIM Capture/Compare 3 interrupt */
809 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
810 break;
811 }
812
813 case TIM_CHANNEL_4:
814 {
815 /* Enable the TIM Capture/Compare 4 interrupt */
816 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
817 break;
818 }
819
820 default:
821 break;
822 }
823
824 /* Enable the Output compare channel */
825 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
826
827 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
828 {
829 /* Enable the main output */
830 __HAL_TIM_MOE_ENABLE(htim);
831 }
832
833 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
834 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
835 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
836 {
837 __HAL_TIM_ENABLE(htim);
838 }
839
840 /* Return function status */
841 return HAL_OK;
842 }
843
844 /**
845 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
846 * @param htim TIM Output Compare handle
847 * @param Channel TIM Channel to be disabled
848 * This parameter can be one of the following values:
849 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
850 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
851 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
852 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
853 * @retval HAL status
854 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)855 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
856 {
857 /* Check the parameters */
858 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
859
860 switch (Channel)
861 {
862 case TIM_CHANNEL_1:
863 {
864 /* Disable the TIM Capture/Compare 1 interrupt */
865 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
866 break;
867 }
868
869 case TIM_CHANNEL_2:
870 {
871 /* Disable the TIM Capture/Compare 2 interrupt */
872 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
873 break;
874 }
875
876 case TIM_CHANNEL_3:
877 {
878 /* Disable the TIM Capture/Compare 3 interrupt */
879 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
880 break;
881 }
882
883 case TIM_CHANNEL_4:
884 {
885 /* Disable the TIM Capture/Compare 4 interrupt */
886 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
887 break;
888 }
889
890 default:
891 break;
892 }
893
894 /* Disable the Output compare channel */
895 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
896
897 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
898 {
899 /* Disable the Main Output */
900 __HAL_TIM_MOE_DISABLE(htim);
901 }
902
903 /* Disable the Peripheral */
904 __HAL_TIM_DISABLE(htim);
905
906 /* Return function status */
907 return HAL_OK;
908 }
909
910 /**
911 * @brief Starts the TIM Output Compare signal generation in DMA mode.
912 * @param htim TIM Output Compare handle
913 * @param Channel TIM Channel to be enabled
914 * This parameter can be one of the following values:
915 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
916 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
917 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
918 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
919 * @param pData The source Buffer address.
920 * @param Length The length of data to be transferred from memory to TIM peripheral
921 * @retval HAL status
922 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)923 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
924 {
925 uint32_t tmpsmcr;
926
927 /* Check the parameters */
928 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
929
930 if ((htim->State == HAL_TIM_STATE_BUSY))
931 {
932 return HAL_BUSY;
933 }
934 else if ((htim->State == HAL_TIM_STATE_READY))
935 {
936 if ((pData == NULL) && (Length > 0U))
937 {
938 return HAL_ERROR;
939 }
940 else
941 {
942 htim->State = HAL_TIM_STATE_BUSY;
943 }
944 }
945 else
946 {
947 /* nothing to do */
948 }
949
950 switch (Channel)
951 {
952 case TIM_CHANNEL_1:
953 {
954 /* Set the DMA compare callbacks */
955 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
956 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
957
958 /* Set the DMA error callback */
959 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
960
961 /* Enable the DMA stream */
962 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
963 {
964 return HAL_ERROR;
965 }
966
967 /* Enable the TIM Capture/Compare 1 DMA request */
968 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
969 break;
970 }
971
972 case TIM_CHANNEL_2:
973 {
974 /* Set the DMA compare callbacks */
975 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
976 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
977
978 /* Set the DMA error callback */
979 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
980
981 /* Enable the DMA stream */
982 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
983 {
984 return HAL_ERROR;
985 }
986
987 /* Enable the TIM Capture/Compare 2 DMA request */
988 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
989 break;
990 }
991
992 case TIM_CHANNEL_3:
993 {
994 /* Set the DMA compare callbacks */
995 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
996 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
997
998 /* Set the DMA error callback */
999 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1000
1001 /* Enable the DMA stream */
1002 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1003 {
1004 return HAL_ERROR;
1005 }
1006 /* Enable the TIM Capture/Compare 3 DMA request */
1007 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1008 break;
1009 }
1010
1011 case TIM_CHANNEL_4:
1012 {
1013 /* Set the DMA compare callbacks */
1014 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1015 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1016
1017 /* Set the DMA error callback */
1018 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1019
1020 /* Enable the DMA stream */
1021 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1022 {
1023 return HAL_ERROR;
1024 }
1025 /* Enable the TIM Capture/Compare 4 DMA request */
1026 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1027 break;
1028 }
1029
1030 default:
1031 break;
1032 }
1033
1034 /* Enable the Output compare channel */
1035 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1036
1037 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1038 {
1039 /* Enable the main output */
1040 __HAL_TIM_MOE_ENABLE(htim);
1041 }
1042
1043 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1044 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1045 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1046 {
1047 __HAL_TIM_ENABLE(htim);
1048 }
1049
1050 /* Return function status */
1051 return HAL_OK;
1052 }
1053
1054 /**
1055 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1056 * @param htim TIM Output Compare handle
1057 * @param Channel TIM Channel to be disabled
1058 * This parameter can be one of the following values:
1059 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1060 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1061 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1062 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1063 * @retval HAL status
1064 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1065 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1066 {
1067 /* Check the parameters */
1068 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1069
1070 switch (Channel)
1071 {
1072 case TIM_CHANNEL_1:
1073 {
1074 /* Disable the TIM Capture/Compare 1 DMA request */
1075 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1076 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1077 break;
1078 }
1079
1080 case TIM_CHANNEL_2:
1081 {
1082 /* Disable the TIM Capture/Compare 2 DMA request */
1083 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1084 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1085 break;
1086 }
1087
1088 case TIM_CHANNEL_3:
1089 {
1090 /* Disable the TIM Capture/Compare 3 DMA request */
1091 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1092 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1093 break;
1094 }
1095
1096 case TIM_CHANNEL_4:
1097 {
1098 /* Disable the TIM Capture/Compare 4 interrupt */
1099 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1100 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1101 break;
1102 }
1103
1104 default:
1105 break;
1106 }
1107
1108 /* Disable the Output compare channel */
1109 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1110
1111 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1112 {
1113 /* Disable the Main Output */
1114 __HAL_TIM_MOE_DISABLE(htim);
1115 }
1116
1117 /* Disable the Peripheral */
1118 __HAL_TIM_DISABLE(htim);
1119
1120 /* Change the htim state */
1121 htim->State = HAL_TIM_STATE_READY;
1122
1123 /* Return function status */
1124 return HAL_OK;
1125 }
1126
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1132 * @brief TIM PWM functions
1133 *
1134 @verbatim
1135 ==============================================================================
1136 ##### TIM PWM functions #####
1137 ==============================================================================
1138 [..]
1139 This section provides functions allowing to:
1140 (+) Initialize and configure the TIM PWM.
1141 (+) De-initialize the TIM PWM.
1142 (+) Start the TIM PWM.
1143 (+) Stop the TIM PWM.
1144 (+) Start the TIM PWM and enable interrupt.
1145 (+) Stop the TIM PWM and disable interrupt.
1146 (+) Start the TIM PWM and enable DMA transfer.
1147 (+) Stop the TIM PWM and disable DMA transfer.
1148
1149 @endverbatim
1150 * @{
1151 */
1152 /**
1153 * @brief Initializes the TIM PWM Time Base according to the specified
1154 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1155 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1156 * requires a timer reset to avoid unexpected direction
1157 * due to DIR bit readonly in center aligned mode.
1158 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1159 * @param htim TIM PWM handle
1160 * @retval HAL status
1161 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1162 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1163 {
1164 /* Check the TIM handle allocation */
1165 if (htim == NULL)
1166 {
1167 return HAL_ERROR;
1168 }
1169
1170 /* Check the parameters */
1171 assert_param(IS_TIM_INSTANCE(htim->Instance));
1172 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1173 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1174 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1175
1176 if (htim->State == HAL_TIM_STATE_RESET)
1177 {
1178 /* Allocate lock resource and initialize it */
1179 htim->Lock = HAL_UNLOCKED;
1180
1181 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1182 /* Reset interrupt callbacks to legacy weak callbacks */
1183 TIM_ResetCallback(htim);
1184
1185 if (htim->PWM_MspInitCallback == NULL)
1186 {
1187 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1188 }
1189 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1190 htim->PWM_MspInitCallback(htim);
1191 #else
1192 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1193 HAL_TIM_PWM_MspInit(htim);
1194 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1195 }
1196
1197 /* Set the TIM state */
1198 htim->State = HAL_TIM_STATE_BUSY;
1199
1200 /* Init the base time for the PWM */
1201 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1202
1203 /* Initialize the TIM state*/
1204 htim->State = HAL_TIM_STATE_READY;
1205
1206 return HAL_OK;
1207 }
1208
1209 /**
1210 * @brief DeInitializes the TIM peripheral
1211 * @param htim TIM PWM handle
1212 * @retval HAL status
1213 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1214 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1215 {
1216 /* Check the parameters */
1217 assert_param(IS_TIM_INSTANCE(htim->Instance));
1218
1219 htim->State = HAL_TIM_STATE_BUSY;
1220
1221 /* Disable the TIM Peripheral Clock */
1222 __HAL_TIM_DISABLE(htim);
1223
1224 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1225 if (htim->PWM_MspDeInitCallback == NULL)
1226 {
1227 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1228 }
1229 /* DeInit the low level hardware */
1230 htim->PWM_MspDeInitCallback(htim);
1231 #else
1232 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1233 HAL_TIM_PWM_MspDeInit(htim);
1234 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1235
1236 /* Change TIM state */
1237 htim->State = HAL_TIM_STATE_RESET;
1238
1239 /* Release Lock */
1240 __HAL_UNLOCK(htim);
1241
1242 return HAL_OK;
1243 }
1244
1245 /**
1246 * @brief Initializes the TIM PWM MSP.
1247 * @param htim TIM PWM handle
1248 * @retval None
1249 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1250 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1251 {
1252 /* Prevent unused argument(s) compilation warning */
1253 UNUSED(htim);
1254
1255 /* NOTE : This function should not be modified, when the callback is needed,
1256 the HAL_TIM_PWM_MspInit could be implemented in the user file
1257 */
1258 }
1259
1260 /**
1261 * @brief DeInitializes TIM PWM MSP.
1262 * @param htim TIM PWM handle
1263 * @retval None
1264 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1265 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1266 {
1267 /* Prevent unused argument(s) compilation warning */
1268 UNUSED(htim);
1269
1270 /* NOTE : This function should not be modified, when the callback is needed,
1271 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1272 */
1273 }
1274
1275 /**
1276 * @brief Starts the PWM signal generation.
1277 * @param htim TIM handle
1278 * @param Channel TIM Channels to be enabled
1279 * This parameter can be one of the following values:
1280 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1281 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1282 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1283 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1284 * @retval HAL status
1285 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1286 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1287 {
1288 uint32_t tmpsmcr;
1289
1290 /* Check the parameters */
1291 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1292
1293 /* Enable the Capture compare channel */
1294 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1295
1296 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1297 {
1298 /* Enable the main output */
1299 __HAL_TIM_MOE_ENABLE(htim);
1300 }
1301
1302 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1303 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1304 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1305 {
1306 __HAL_TIM_ENABLE(htim);
1307 }
1308
1309 /* Return function status */
1310 return HAL_OK;
1311 }
1312
1313 /**
1314 * @brief Stops the PWM signal generation.
1315 * @param htim TIM PWM handle
1316 * @param Channel TIM Channels to be disabled
1317 * This parameter can be one of the following values:
1318 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1319 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1320 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1321 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1322 * @retval HAL status
1323 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1324 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1325 {
1326 /* Check the parameters */
1327 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1328
1329 /* Disable the Capture compare channel */
1330 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1331
1332 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1333 {
1334 /* Disable the Main Output */
1335 __HAL_TIM_MOE_DISABLE(htim);
1336 }
1337
1338 /* Disable the Peripheral */
1339 __HAL_TIM_DISABLE(htim);
1340
1341 /* Change the htim state */
1342 htim->State = HAL_TIM_STATE_READY;
1343
1344 /* Return function status */
1345 return HAL_OK;
1346 }
1347
1348 /**
1349 * @brief Starts the PWM signal generation in interrupt mode.
1350 * @param htim TIM PWM handle
1351 * @param Channel TIM Channel to be enabled
1352 * This parameter can be one of the following values:
1353 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1354 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1355 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1356 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1357 * @retval HAL status
1358 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1359 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1360 {
1361 uint32_t tmpsmcr;
1362 /* Check the parameters */
1363 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1364
1365 switch (Channel)
1366 {
1367 case TIM_CHANNEL_1:
1368 {
1369 /* Enable the TIM Capture/Compare 1 interrupt */
1370 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1371 break;
1372 }
1373
1374 case TIM_CHANNEL_2:
1375 {
1376 /* Enable the TIM Capture/Compare 2 interrupt */
1377 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1378 break;
1379 }
1380
1381 case TIM_CHANNEL_3:
1382 {
1383 /* Enable the TIM Capture/Compare 3 interrupt */
1384 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1385 break;
1386 }
1387
1388 case TIM_CHANNEL_4:
1389 {
1390 /* Enable the TIM Capture/Compare 4 interrupt */
1391 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1392 break;
1393 }
1394
1395 default:
1396 break;
1397 }
1398
1399 /* Enable the Capture compare channel */
1400 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1401
1402 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1403 {
1404 /* Enable the main output */
1405 __HAL_TIM_MOE_ENABLE(htim);
1406 }
1407
1408 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1409 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1410 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1411 {
1412 __HAL_TIM_ENABLE(htim);
1413 }
1414
1415 /* Return function status */
1416 return HAL_OK;
1417 }
1418
1419 /**
1420 * @brief Stops the PWM signal generation in interrupt mode.
1421 * @param htim TIM PWM handle
1422 * @param Channel TIM Channels to be disabled
1423 * This parameter can be one of the following values:
1424 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1425 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1426 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1427 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1428 * @retval HAL status
1429 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1430 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1431 {
1432 /* Check the parameters */
1433 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1434
1435 switch (Channel)
1436 {
1437 case TIM_CHANNEL_1:
1438 {
1439 /* Disable the TIM Capture/Compare 1 interrupt */
1440 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1441 break;
1442 }
1443
1444 case TIM_CHANNEL_2:
1445 {
1446 /* Disable the TIM Capture/Compare 2 interrupt */
1447 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1448 break;
1449 }
1450
1451 case TIM_CHANNEL_3:
1452 {
1453 /* Disable the TIM Capture/Compare 3 interrupt */
1454 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1455 break;
1456 }
1457
1458 case TIM_CHANNEL_4:
1459 {
1460 /* Disable the TIM Capture/Compare 4 interrupt */
1461 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1462 break;
1463 }
1464
1465 default:
1466 break;
1467 }
1468
1469 /* Disable the Capture compare channel */
1470 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1471
1472 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1473 {
1474 /* Disable the Main Output */
1475 __HAL_TIM_MOE_DISABLE(htim);
1476 }
1477
1478 /* Disable the Peripheral */
1479 __HAL_TIM_DISABLE(htim);
1480
1481 /* Return function status */
1482 return HAL_OK;
1483 }
1484
1485 /**
1486 * @brief Starts the TIM PWM signal generation in DMA mode.
1487 * @param htim TIM PWM handle
1488 * @param Channel TIM Channels to be enabled
1489 * This parameter can be one of the following values:
1490 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1491 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1492 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1493 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1494 * @param pData The source Buffer address.
1495 * @param Length The length of data to be transferred from memory to TIM peripheral
1496 * @retval HAL status
1497 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1498 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1499 {
1500 uint32_t tmpsmcr;
1501
1502 /* Check the parameters */
1503 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1504
1505 if ((htim->State == HAL_TIM_STATE_BUSY))
1506 {
1507 return HAL_BUSY;
1508 }
1509 else if ((htim->State == HAL_TIM_STATE_READY))
1510 {
1511 if ((pData == NULL) && (Length > 0U))
1512 {
1513 return HAL_ERROR;
1514 }
1515 else
1516 {
1517 htim->State = HAL_TIM_STATE_BUSY;
1518 }
1519 }
1520 else
1521 {
1522 /* nothing to do */
1523 }
1524
1525 switch (Channel)
1526 {
1527 case TIM_CHANNEL_1:
1528 {
1529 /* Set the DMA compare callbacks */
1530 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1531 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1532
1533 /* Set the DMA error callback */
1534 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1535
1536 /* Enable the DMA stream */
1537 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1538 {
1539 return HAL_ERROR;
1540 }
1541
1542 /* Enable the TIM Capture/Compare 1 DMA request */
1543 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1544 break;
1545 }
1546
1547 case TIM_CHANNEL_2:
1548 {
1549 /* Set the DMA compare callbacks */
1550 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1551 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1552
1553 /* Set the DMA error callback */
1554 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1555
1556 /* Enable the DMA stream */
1557 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1558 {
1559 return HAL_ERROR;
1560 }
1561 /* Enable the TIM Capture/Compare 2 DMA request */
1562 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1563 break;
1564 }
1565
1566 case TIM_CHANNEL_3:
1567 {
1568 /* Set the DMA compare callbacks */
1569 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1570 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1571
1572 /* Set the DMA error callback */
1573 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1574
1575 /* Enable the DMA stream */
1576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1577 {
1578 return HAL_ERROR;
1579 }
1580 /* Enable the TIM Output Capture/Compare 3 request */
1581 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1582 break;
1583 }
1584
1585 case TIM_CHANNEL_4:
1586 {
1587 /* Set the DMA compare callbacks */
1588 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1589 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1590
1591 /* Set the DMA error callback */
1592 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1593
1594 /* Enable the DMA stream */
1595 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1596 {
1597 return HAL_ERROR;
1598 }
1599 /* Enable the TIM Capture/Compare 4 DMA request */
1600 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1601 break;
1602 }
1603
1604 default:
1605 break;
1606 }
1607
1608 /* Enable the Capture compare channel */
1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1610
1611 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1612 {
1613 /* Enable the main output */
1614 __HAL_TIM_MOE_ENABLE(htim);
1615 }
1616
1617 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1618 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1619 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1620 {
1621 __HAL_TIM_ENABLE(htim);
1622 }
1623
1624 /* Return function status */
1625 return HAL_OK;
1626 }
1627
1628 /**
1629 * @brief Stops the TIM PWM signal generation in DMA mode.
1630 * @param htim TIM PWM handle
1631 * @param Channel TIM Channels to be disabled
1632 * This parameter can be one of the following values:
1633 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1634 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1635 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1636 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1637 * @retval HAL status
1638 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1639 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1640 {
1641 /* Check the parameters */
1642 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1643
1644 switch (Channel)
1645 {
1646 case TIM_CHANNEL_1:
1647 {
1648 /* Disable the TIM Capture/Compare 1 DMA request */
1649 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1650 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1651 break;
1652 }
1653
1654 case TIM_CHANNEL_2:
1655 {
1656 /* Disable the TIM Capture/Compare 2 DMA request */
1657 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1658 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1659 break;
1660 }
1661
1662 case TIM_CHANNEL_3:
1663 {
1664 /* Disable the TIM Capture/Compare 3 DMA request */
1665 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1666 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1667 break;
1668 }
1669
1670 case TIM_CHANNEL_4:
1671 {
1672 /* Disable the TIM Capture/Compare 4 interrupt */
1673 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1674 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1675 break;
1676 }
1677
1678 default:
1679 break;
1680 }
1681
1682 /* Disable the Capture compare channel */
1683 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1684
1685 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1686 {
1687 /* Disable the Main Output */
1688 __HAL_TIM_MOE_DISABLE(htim);
1689 }
1690
1691 /* Disable the Peripheral */
1692 __HAL_TIM_DISABLE(htim);
1693
1694 /* Change the htim state */
1695 htim->State = HAL_TIM_STATE_READY;
1696
1697 /* Return function status */
1698 return HAL_OK;
1699 }
1700
1701 /**
1702 * @}
1703 */
1704
1705 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1706 * @brief TIM Input Capture functions
1707 *
1708 @verbatim
1709 ==============================================================================
1710 ##### TIM Input Capture functions #####
1711 ==============================================================================
1712 [..]
1713 This section provides functions allowing to:
1714 (+) Initialize and configure the TIM Input Capture.
1715 (+) De-initialize the TIM Input Capture.
1716 (+) Start the TIM Input Capture.
1717 (+) Stop the TIM Input Capture.
1718 (+) Start the TIM Input Capture and enable interrupt.
1719 (+) Stop the TIM Input Capture and disable interrupt.
1720 (+) Start the TIM Input Capture and enable DMA transfer.
1721 (+) Stop the TIM Input Capture and disable DMA transfer.
1722
1723 @endverbatim
1724 * @{
1725 */
1726 /**
1727 * @brief Initializes the TIM Input Capture Time base according to the specified
1728 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1729 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1730 * requires a timer reset to avoid unexpected direction
1731 * due to DIR bit readonly in center aligned mode.
1732 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1733 * @param htim TIM Input Capture handle
1734 * @retval HAL status
1735 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1736 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1737 {
1738 /* Check the TIM handle allocation */
1739 if (htim == NULL)
1740 {
1741 return HAL_ERROR;
1742 }
1743
1744 /* Check the parameters */
1745 assert_param(IS_TIM_INSTANCE(htim->Instance));
1746 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1747 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1748 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1749
1750 if (htim->State == HAL_TIM_STATE_RESET)
1751 {
1752 /* Allocate lock resource and initialize it */
1753 htim->Lock = HAL_UNLOCKED;
1754
1755 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1756 /* Reset interrupt callbacks to legacy weak callbacks */
1757 TIM_ResetCallback(htim);
1758
1759 if (htim->IC_MspInitCallback == NULL)
1760 {
1761 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1762 }
1763 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1764 htim->IC_MspInitCallback(htim);
1765 #else
1766 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1767 HAL_TIM_IC_MspInit(htim);
1768 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1769 }
1770
1771 /* Set the TIM state */
1772 htim->State = HAL_TIM_STATE_BUSY;
1773
1774 /* Init the base time for the input capture */
1775 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1776
1777 /* Initialize the TIM state*/
1778 htim->State = HAL_TIM_STATE_READY;
1779
1780 return HAL_OK;
1781 }
1782
1783 /**
1784 * @brief DeInitializes the TIM peripheral
1785 * @param htim TIM Input Capture handle
1786 * @retval HAL status
1787 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1788 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1789 {
1790 /* Check the parameters */
1791 assert_param(IS_TIM_INSTANCE(htim->Instance));
1792
1793 htim->State = HAL_TIM_STATE_BUSY;
1794
1795 /* Disable the TIM Peripheral Clock */
1796 __HAL_TIM_DISABLE(htim);
1797
1798 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1799 if (htim->IC_MspDeInitCallback == NULL)
1800 {
1801 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1802 }
1803 /* DeInit the low level hardware */
1804 htim->IC_MspDeInitCallback(htim);
1805 #else
1806 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1807 HAL_TIM_IC_MspDeInit(htim);
1808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1809
1810 /* Change TIM state */
1811 htim->State = HAL_TIM_STATE_RESET;
1812
1813 /* Release Lock */
1814 __HAL_UNLOCK(htim);
1815
1816 return HAL_OK;
1817 }
1818
1819 /**
1820 * @brief Initializes the TIM Input Capture MSP.
1821 * @param htim TIM Input Capture handle
1822 * @retval None
1823 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)1824 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1825 {
1826 /* Prevent unused argument(s) compilation warning */
1827 UNUSED(htim);
1828
1829 /* NOTE : This function should not be modified, when the callback is needed,
1830 the HAL_TIM_IC_MspInit could be implemented in the user file
1831 */
1832 }
1833
1834 /**
1835 * @brief DeInitializes TIM Input Capture MSP.
1836 * @param htim TIM handle
1837 * @retval None
1838 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)1839 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1840 {
1841 /* Prevent unused argument(s) compilation warning */
1842 UNUSED(htim);
1843
1844 /* NOTE : This function should not be modified, when the callback is needed,
1845 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1846 */
1847 }
1848
1849 /**
1850 * @brief Starts the TIM Input Capture measurement.
1851 * @param htim TIM Input Capture handle
1852 * @param Channel TIM Channels to be enabled
1853 * This parameter can be one of the following values:
1854 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1855 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1856 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1857 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1858 * @retval HAL status
1859 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1860 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1861 {
1862 uint32_t tmpsmcr;
1863
1864 /* Check the parameters */
1865 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1866
1867 /* Enable the Input Capture channel */
1868 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1869
1870 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1871 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1872 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1873 {
1874 __HAL_TIM_ENABLE(htim);
1875 }
1876
1877 /* Return function status */
1878 return HAL_OK;
1879 }
1880
1881 /**
1882 * @brief Stops the TIM Input Capture measurement.
1883 * @param htim TIM Input Capture handle
1884 * @param Channel TIM Channels to be disabled
1885 * This parameter can be one of the following values:
1886 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1887 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1888 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1889 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1890 * @retval HAL status
1891 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1892 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1893 {
1894 /* Check the parameters */
1895 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1896
1897 /* Disable the Input Capture channel */
1898 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1899
1900 /* Disable the Peripheral */
1901 __HAL_TIM_DISABLE(htim);
1902
1903 /* Return function status */
1904 return HAL_OK;
1905 }
1906
1907 /**
1908 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1909 * @param htim TIM Input Capture handle
1910 * @param Channel TIM Channels to be enabled
1911 * This parameter can be one of the following values:
1912 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1913 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1914 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1915 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1916 * @retval HAL status
1917 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1918 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1919 {
1920 uint32_t tmpsmcr;
1921
1922 /* Check the parameters */
1923 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1924
1925 switch (Channel)
1926 {
1927 case TIM_CHANNEL_1:
1928 {
1929 /* Enable the TIM Capture/Compare 1 interrupt */
1930 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1931 break;
1932 }
1933
1934 case TIM_CHANNEL_2:
1935 {
1936 /* Enable the TIM Capture/Compare 2 interrupt */
1937 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1938 break;
1939 }
1940
1941 case TIM_CHANNEL_3:
1942 {
1943 /* Enable the TIM Capture/Compare 3 interrupt */
1944 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1945 break;
1946 }
1947
1948 case TIM_CHANNEL_4:
1949 {
1950 /* Enable the TIM Capture/Compare 4 interrupt */
1951 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1952 break;
1953 }
1954
1955 default:
1956 break;
1957 }
1958 /* Enable the Input Capture channel */
1959 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1960
1961 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1962 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1963 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1964 {
1965 __HAL_TIM_ENABLE(htim);
1966 }
1967
1968 /* Return function status */
1969 return HAL_OK;
1970 }
1971
1972 /**
1973 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1974 * @param htim TIM Input Capture handle
1975 * @param Channel TIM Channels to be disabled
1976 * This parameter can be one of the following values:
1977 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1978 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1979 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1980 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1981 * @retval HAL status
1982 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1983 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1984 {
1985 /* Check the parameters */
1986 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1987
1988 switch (Channel)
1989 {
1990 case TIM_CHANNEL_1:
1991 {
1992 /* Disable the TIM Capture/Compare 1 interrupt */
1993 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1994 break;
1995 }
1996
1997 case TIM_CHANNEL_2:
1998 {
1999 /* Disable the TIM Capture/Compare 2 interrupt */
2000 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2001 break;
2002 }
2003
2004 case TIM_CHANNEL_3:
2005 {
2006 /* Disable the TIM Capture/Compare 3 interrupt */
2007 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2008 break;
2009 }
2010
2011 case TIM_CHANNEL_4:
2012 {
2013 /* Disable the TIM Capture/Compare 4 interrupt */
2014 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2015 break;
2016 }
2017
2018 default:
2019 break;
2020 }
2021
2022 /* Disable the Input Capture channel */
2023 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2024
2025 /* Disable the Peripheral */
2026 __HAL_TIM_DISABLE(htim);
2027
2028 /* Return function status */
2029 return HAL_OK;
2030 }
2031
2032 /**
2033 * @brief Starts the TIM Input Capture measurement in DMA mode.
2034 * @param htim TIM Input Capture handle
2035 * @param Channel TIM Channels to be enabled
2036 * This parameter can be one of the following values:
2037 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2038 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2039 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2040 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2041 * @param pData The destination Buffer address.
2042 * @param Length The length of data to be transferred from TIM peripheral to memory.
2043 * @retval HAL status
2044 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2045 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2046 {
2047 uint32_t tmpsmcr;
2048
2049 /* Check the parameters */
2050 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2051 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2052
2053 if ((htim->State == HAL_TIM_STATE_BUSY))
2054 {
2055 return HAL_BUSY;
2056 }
2057 else if ((htim->State == HAL_TIM_STATE_READY))
2058 {
2059 if ((pData == NULL) && (Length > 0U))
2060 {
2061 return HAL_ERROR;
2062 }
2063 else
2064 {
2065 htim->State = HAL_TIM_STATE_BUSY;
2066 }
2067 }
2068 else
2069 {
2070 /* nothing to do */
2071 }
2072
2073 switch (Channel)
2074 {
2075 case TIM_CHANNEL_1:
2076 {
2077 /* Set the DMA capture callbacks */
2078 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2079 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2080
2081 /* Set the DMA error callback */
2082 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2083
2084 /* Enable the DMA stream */
2085 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2086 {
2087 return HAL_ERROR;
2088 }
2089 /* Enable the TIM Capture/Compare 1 DMA request */
2090 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2091 break;
2092 }
2093
2094 case TIM_CHANNEL_2:
2095 {
2096 /* Set the DMA capture callbacks */
2097 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2098 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2099
2100 /* Set the DMA error callback */
2101 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2102
2103 /* Enable the DMA stream */
2104 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2105 {
2106 return HAL_ERROR;
2107 }
2108 /* Enable the TIM Capture/Compare 2 DMA request */
2109 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2110 break;
2111 }
2112
2113 case TIM_CHANNEL_3:
2114 {
2115 /* Set the DMA capture callbacks */
2116 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2117 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2118
2119 /* Set the DMA error callback */
2120 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2121
2122 /* Enable the DMA stream */
2123 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2124 {
2125 return HAL_ERROR;
2126 }
2127 /* Enable the TIM Capture/Compare 3 DMA request */
2128 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2129 break;
2130 }
2131
2132 case TIM_CHANNEL_4:
2133 {
2134 /* Set the DMA capture callbacks */
2135 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2136 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2137
2138 /* Set the DMA error callback */
2139 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2140
2141 /* Enable the DMA stream */
2142 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2143 {
2144 return HAL_ERROR;
2145 }
2146 /* Enable the TIM Capture/Compare 4 DMA request */
2147 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2148 break;
2149 }
2150
2151 default:
2152 break;
2153 }
2154
2155 /* Enable the Input Capture channel */
2156 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2157
2158 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2159 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2160 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2161 {
2162 __HAL_TIM_ENABLE(htim);
2163 }
2164
2165 /* Return function status */
2166 return HAL_OK;
2167 }
2168
2169 /**
2170 * @brief Stops the TIM Input Capture measurement in DMA mode.
2171 * @param htim TIM Input Capture handle
2172 * @param Channel TIM Channels to be disabled
2173 * This parameter can be one of the following values:
2174 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2175 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2176 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2177 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2178 * @retval HAL status
2179 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2180 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2181 {
2182 /* Check the parameters */
2183 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2184 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2185
2186 switch (Channel)
2187 {
2188 case TIM_CHANNEL_1:
2189 {
2190 /* Disable the TIM Capture/Compare 1 DMA request */
2191 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2192 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2193 break;
2194 }
2195
2196 case TIM_CHANNEL_2:
2197 {
2198 /* Disable the TIM Capture/Compare 2 DMA request */
2199 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2200 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2201 break;
2202 }
2203
2204 case TIM_CHANNEL_3:
2205 {
2206 /* Disable the TIM Capture/Compare 3 DMA request */
2207 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2208 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2209 break;
2210 }
2211
2212 case TIM_CHANNEL_4:
2213 {
2214 /* Disable the TIM Capture/Compare 4 DMA request */
2215 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2216 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2217 break;
2218 }
2219
2220 default:
2221 break;
2222 }
2223
2224 /* Disable the Input Capture channel */
2225 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2226
2227 /* Disable the Peripheral */
2228 __HAL_TIM_DISABLE(htim);
2229
2230 /* Change the htim state */
2231 htim->State = HAL_TIM_STATE_READY;
2232
2233 /* Return function status */
2234 return HAL_OK;
2235 }
2236 /**
2237 * @}
2238 */
2239
2240 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2241 * @brief TIM One Pulse functions
2242 *
2243 @verbatim
2244 ==============================================================================
2245 ##### TIM One Pulse functions #####
2246 ==============================================================================
2247 [..]
2248 This section provides functions allowing to:
2249 (+) Initialize and configure the TIM One Pulse.
2250 (+) De-initialize the TIM One Pulse.
2251 (+) Start the TIM One Pulse.
2252 (+) Stop the TIM One Pulse.
2253 (+) Start the TIM One Pulse and enable interrupt.
2254 (+) Stop the TIM One Pulse and disable interrupt.
2255 (+) Start the TIM One Pulse and enable DMA transfer.
2256 (+) Stop the TIM One Pulse and disable DMA transfer.
2257
2258 @endverbatim
2259 * @{
2260 */
2261 /**
2262 * @brief Initializes the TIM One Pulse Time Base according to the specified
2263 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2264 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2265 * requires a timer reset to avoid unexpected direction
2266 * due to DIR bit readonly in center aligned mode.
2267 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2268 * @param htim TIM One Pulse handle
2269 * @param OnePulseMode Select the One pulse mode.
2270 * This parameter can be one of the following values:
2271 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2272 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2273 * @retval HAL status
2274 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2275 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2276 {
2277 /* Check the TIM handle allocation */
2278 if (htim == NULL)
2279 {
2280 return HAL_ERROR;
2281 }
2282
2283 /* Check the parameters */
2284 assert_param(IS_TIM_INSTANCE(htim->Instance));
2285 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2286 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2287 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2288 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2289
2290 if (htim->State == HAL_TIM_STATE_RESET)
2291 {
2292 /* Allocate lock resource and initialize it */
2293 htim->Lock = HAL_UNLOCKED;
2294
2295 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2296 /* Reset interrupt callbacks to legacy weak callbacks */
2297 TIM_ResetCallback(htim);
2298
2299 if (htim->OnePulse_MspInitCallback == NULL)
2300 {
2301 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2302 }
2303 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2304 htim->OnePulse_MspInitCallback(htim);
2305 #else
2306 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2307 HAL_TIM_OnePulse_MspInit(htim);
2308 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2309 }
2310
2311 /* Set the TIM state */
2312 htim->State = HAL_TIM_STATE_BUSY;
2313
2314 /* Configure the Time base in the One Pulse Mode */
2315 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2316
2317 /* Reset the OPM Bit */
2318 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2319
2320 /* Configure the OPM Mode */
2321 htim->Instance->CR1 |= OnePulseMode;
2322
2323 /* Initialize the TIM state*/
2324 htim->State = HAL_TIM_STATE_READY;
2325
2326 return HAL_OK;
2327 }
2328
2329 /**
2330 * @brief DeInitializes the TIM One Pulse
2331 * @param htim TIM One Pulse handle
2332 * @retval HAL status
2333 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2334 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2335 {
2336 /* Check the parameters */
2337 assert_param(IS_TIM_INSTANCE(htim->Instance));
2338
2339 htim->State = HAL_TIM_STATE_BUSY;
2340
2341 /* Disable the TIM Peripheral Clock */
2342 __HAL_TIM_DISABLE(htim);
2343
2344 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2345 if (htim->OnePulse_MspDeInitCallback == NULL)
2346 {
2347 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2348 }
2349 /* DeInit the low level hardware */
2350 htim->OnePulse_MspDeInitCallback(htim);
2351 #else
2352 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2353 HAL_TIM_OnePulse_MspDeInit(htim);
2354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2355
2356 /* Change TIM state */
2357 htim->State = HAL_TIM_STATE_RESET;
2358
2359 /* Release Lock */
2360 __HAL_UNLOCK(htim);
2361
2362 return HAL_OK;
2363 }
2364
2365 /**
2366 * @brief Initializes the TIM One Pulse MSP.
2367 * @param htim TIM One Pulse handle
2368 * @retval None
2369 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2370 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2371 {
2372 /* Prevent unused argument(s) compilation warning */
2373 UNUSED(htim);
2374
2375 /* NOTE : This function should not be modified, when the callback is needed,
2376 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2377 */
2378 }
2379
2380 /**
2381 * @brief DeInitializes TIM One Pulse MSP.
2382 * @param htim TIM One Pulse handle
2383 * @retval None
2384 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2385 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2386 {
2387 /* Prevent unused argument(s) compilation warning */
2388 UNUSED(htim);
2389
2390 /* NOTE : This function should not be modified, when the callback is needed,
2391 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2392 */
2393 }
2394
2395 /**
2396 * @brief Starts the TIM One Pulse signal generation.
2397 * @param htim TIM One Pulse handle
2398 * @param OutputChannel TIM Channels to be enabled
2399 * This parameter can be one of the following values:
2400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2402 * @retval HAL status
2403 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2404 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2405 {
2406 /* Prevent unused argument(s) compilation warning */
2407 UNUSED(OutputChannel);
2408
2409 /* Enable the Capture compare and the Input Capture channels
2410 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2411 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2412 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2413 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2414
2415 No need to enable the counter, it's enabled automatically by hardware
2416 (the counter starts in response to a stimulus and generate a pulse */
2417
2418 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2419 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2420
2421 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2422 {
2423 /* Enable the main output */
2424 __HAL_TIM_MOE_ENABLE(htim);
2425 }
2426
2427 /* Return function status */
2428 return HAL_OK;
2429 }
2430
2431 /**
2432 * @brief Stops the TIM One Pulse signal generation.
2433 * @param htim TIM One Pulse handle
2434 * @param OutputChannel TIM Channels to be disable
2435 * This parameter can be one of the following values:
2436 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2437 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2438 * @retval HAL status
2439 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2440 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2441 {
2442 /* Prevent unused argument(s) compilation warning */
2443 UNUSED(OutputChannel);
2444
2445 /* Disable the Capture compare and the Input Capture channels
2446 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2447 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2448 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2449 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2450
2451 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2453
2454 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2455 {
2456 /* Disable the Main Output */
2457 __HAL_TIM_MOE_DISABLE(htim);
2458 }
2459
2460 /* Disable the Peripheral */
2461 __HAL_TIM_DISABLE(htim);
2462
2463 /* Return function status */
2464 return HAL_OK;
2465 }
2466
2467 /**
2468 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2469 * @param htim TIM One Pulse handle
2470 * @param OutputChannel TIM Channels to be enabled
2471 * This parameter can be one of the following values:
2472 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2473 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2474 * @retval HAL status
2475 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2476 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2477 {
2478 /* Prevent unused argument(s) compilation warning */
2479 UNUSED(OutputChannel);
2480
2481 /* Enable the Capture compare and the Input Capture channels
2482 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2483 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2484 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2485 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2486
2487 No need to enable the counter, it's enabled automatically by hardware
2488 (the counter starts in response to a stimulus and generate a pulse */
2489
2490 /* Enable the TIM Capture/Compare 1 interrupt */
2491 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2492
2493 /* Enable the TIM Capture/Compare 2 interrupt */
2494 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2495
2496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2497 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2498
2499 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2500 {
2501 /* Enable the main output */
2502 __HAL_TIM_MOE_ENABLE(htim);
2503 }
2504
2505 /* Return function status */
2506 return HAL_OK;
2507 }
2508
2509 /**
2510 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2511 * @param htim TIM One Pulse handle
2512 * @param OutputChannel TIM Channels to be enabled
2513 * This parameter can be one of the following values:
2514 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2515 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2516 * @retval HAL status
2517 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2518 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2519 {
2520 /* Prevent unused argument(s) compilation warning */
2521 UNUSED(OutputChannel);
2522
2523 /* Disable the TIM Capture/Compare 1 interrupt */
2524 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2525
2526 /* Disable the TIM Capture/Compare 2 interrupt */
2527 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2528
2529 /* Disable the Capture compare and the Input Capture channels
2530 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2531 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2532 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2533 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2534 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2536
2537 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2538 {
2539 /* Disable the Main Output */
2540 __HAL_TIM_MOE_DISABLE(htim);
2541 }
2542
2543 /* Disable the Peripheral */
2544 __HAL_TIM_DISABLE(htim);
2545
2546 /* Return function status */
2547 return HAL_OK;
2548 }
2549
2550 /**
2551 * @}
2552 */
2553
2554 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2555 * @brief TIM Encoder functions
2556 *
2557 @verbatim
2558 ==============================================================================
2559 ##### TIM Encoder functions #####
2560 ==============================================================================
2561 [..]
2562 This section provides functions allowing to:
2563 (+) Initialize and configure the TIM Encoder.
2564 (+) De-initialize the TIM Encoder.
2565 (+) Start the TIM Encoder.
2566 (+) Stop the TIM Encoder.
2567 (+) Start the TIM Encoder and enable interrupt.
2568 (+) Stop the TIM Encoder and disable interrupt.
2569 (+) Start the TIM Encoder and enable DMA transfer.
2570 (+) Stop the TIM Encoder and disable DMA transfer.
2571
2572 @endverbatim
2573 * @{
2574 */
2575 /**
2576 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2577 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2578 * requires a timer reset to avoid unexpected direction
2579 * due to DIR bit readonly in center aligned mode.
2580 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2581 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2582 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2583 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2584 * @param htim TIM Encoder Interface handle
2585 * @param sConfig TIM Encoder Interface configuration structure
2586 * @retval HAL status
2587 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2588 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2589 {
2590 uint32_t tmpsmcr;
2591 uint32_t tmpccmr1;
2592 uint32_t tmpccer;
2593
2594 /* Check the TIM handle allocation */
2595 if (htim == NULL)
2596 {
2597 return HAL_ERROR;
2598 }
2599
2600 /* Check the parameters */
2601 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2602 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2603 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2604 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2605 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2606 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2607 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2608 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2609 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2610 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2611 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2612 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2613 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2614
2615 if (htim->State == HAL_TIM_STATE_RESET)
2616 {
2617 /* Allocate lock resource and initialize it */
2618 htim->Lock = HAL_UNLOCKED;
2619
2620 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2621 /* Reset interrupt callbacks to legacy weak callbacks */
2622 TIM_ResetCallback(htim);
2623
2624 if (htim->Encoder_MspInitCallback == NULL)
2625 {
2626 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2627 }
2628 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2629 htim->Encoder_MspInitCallback(htim);
2630 #else
2631 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2632 HAL_TIM_Encoder_MspInit(htim);
2633 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2634 }
2635
2636 /* Set the TIM state */
2637 htim->State = HAL_TIM_STATE_BUSY;
2638
2639 /* Reset the SMS and ECE bits */
2640 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2641
2642 /* Configure the Time base in the Encoder Mode */
2643 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2644
2645 /* Get the TIMx SMCR register value */
2646 tmpsmcr = htim->Instance->SMCR;
2647
2648 /* Get the TIMx CCMR1 register value */
2649 tmpccmr1 = htim->Instance->CCMR1;
2650
2651 /* Get the TIMx CCER register value */
2652 tmpccer = htim->Instance->CCER;
2653
2654 /* Set the encoder Mode */
2655 tmpsmcr |= sConfig->EncoderMode;
2656
2657 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2658 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2659 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2660
2661 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2662 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2663 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2664 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2665 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2666
2667 /* Set the TI1 and the TI2 Polarities */
2668 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2669 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2670 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2671
2672 /* Write to TIMx SMCR */
2673 htim->Instance->SMCR = tmpsmcr;
2674
2675 /* Write to TIMx CCMR1 */
2676 htim->Instance->CCMR1 = tmpccmr1;
2677
2678 /* Write to TIMx CCER */
2679 htim->Instance->CCER = tmpccer;
2680
2681 /* Initialize the TIM state*/
2682 htim->State = HAL_TIM_STATE_READY;
2683
2684 return HAL_OK;
2685 }
2686
2687
2688 /**
2689 * @brief DeInitializes the TIM Encoder interface
2690 * @param htim TIM Encoder Interface handle
2691 * @retval HAL status
2692 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2693 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2694 {
2695 /* Check the parameters */
2696 assert_param(IS_TIM_INSTANCE(htim->Instance));
2697
2698 htim->State = HAL_TIM_STATE_BUSY;
2699
2700 /* Disable the TIM Peripheral Clock */
2701 __HAL_TIM_DISABLE(htim);
2702
2703 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2704 if (htim->Encoder_MspDeInitCallback == NULL)
2705 {
2706 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
2707 }
2708 /* DeInit the low level hardware */
2709 htim->Encoder_MspDeInitCallback(htim);
2710 #else
2711 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2712 HAL_TIM_Encoder_MspDeInit(htim);
2713 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2714
2715 /* Change TIM state */
2716 htim->State = HAL_TIM_STATE_RESET;
2717
2718 /* Release Lock */
2719 __HAL_UNLOCK(htim);
2720
2721 return HAL_OK;
2722 }
2723
2724 /**
2725 * @brief Initializes the TIM Encoder Interface MSP.
2726 * @param htim TIM Encoder Interface handle
2727 * @retval None
2728 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)2729 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2730 {
2731 /* Prevent unused argument(s) compilation warning */
2732 UNUSED(htim);
2733
2734 /* NOTE : This function should not be modified, when the callback is needed,
2735 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2736 */
2737 }
2738
2739 /**
2740 * @brief DeInitializes TIM Encoder Interface MSP.
2741 * @param htim TIM Encoder Interface handle
2742 * @retval None
2743 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)2744 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2745 {
2746 /* Prevent unused argument(s) compilation warning */
2747 UNUSED(htim);
2748
2749 /* NOTE : This function should not be modified, when the callback is needed,
2750 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2751 */
2752 }
2753
2754 /**
2755 * @brief Starts the TIM Encoder Interface.
2756 * @param htim TIM Encoder Interface handle
2757 * @param Channel TIM Channels to be enabled
2758 * This parameter can be one of the following values:
2759 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2760 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2761 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2762 * @retval HAL status
2763 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2764 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2765 {
2766 /* Check the parameters */
2767 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2768
2769 /* Enable the encoder interface channels */
2770 switch (Channel)
2771 {
2772 case TIM_CHANNEL_1:
2773 {
2774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2775 break;
2776 }
2777
2778 case TIM_CHANNEL_2:
2779 {
2780 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2781 break;
2782 }
2783
2784 default :
2785 {
2786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2787 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2788 break;
2789 }
2790 }
2791 /* Enable the Peripheral */
2792 __HAL_TIM_ENABLE(htim);
2793
2794 /* Return function status */
2795 return HAL_OK;
2796 }
2797
2798 /**
2799 * @brief Stops the TIM Encoder Interface.
2800 * @param htim TIM Encoder Interface handle
2801 * @param Channel TIM Channels to be disabled
2802 * This parameter can be one of the following values:
2803 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2804 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2805 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2806 * @retval HAL status
2807 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2808 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2809 {
2810 /* Check the parameters */
2811 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2812
2813 /* Disable the Input Capture channels 1 and 2
2814 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2815 switch (Channel)
2816 {
2817 case TIM_CHANNEL_1:
2818 {
2819 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2820 break;
2821 }
2822
2823 case TIM_CHANNEL_2:
2824 {
2825 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2826 break;
2827 }
2828
2829 default :
2830 {
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2832 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2833 break;
2834 }
2835 }
2836
2837 /* Disable the Peripheral */
2838 __HAL_TIM_DISABLE(htim);
2839
2840 /* Return function status */
2841 return HAL_OK;
2842 }
2843
2844 /**
2845 * @brief Starts the TIM Encoder Interface in interrupt mode.
2846 * @param htim TIM Encoder Interface handle
2847 * @param Channel TIM Channels to be enabled
2848 * This parameter can be one of the following values:
2849 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2850 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2851 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2852 * @retval HAL status
2853 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2854 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2855 {
2856 /* Check the parameters */
2857 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2858
2859 /* Enable the encoder interface channels */
2860 /* Enable the capture compare Interrupts 1 and/or 2 */
2861 switch (Channel)
2862 {
2863 case TIM_CHANNEL_1:
2864 {
2865 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2866 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2867 break;
2868 }
2869
2870 case TIM_CHANNEL_2:
2871 {
2872 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2873 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2874 break;
2875 }
2876
2877 default :
2878 {
2879 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2880 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2881 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2882 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2883 break;
2884 }
2885 }
2886
2887 /* Enable the Peripheral */
2888 __HAL_TIM_ENABLE(htim);
2889
2890 /* Return function status */
2891 return HAL_OK;
2892 }
2893
2894 /**
2895 * @brief Stops the TIM Encoder Interface in interrupt mode.
2896 * @param htim TIM Encoder Interface handle
2897 * @param Channel TIM Channels to be disabled
2898 * This parameter can be one of the following values:
2899 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2900 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2901 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2902 * @retval HAL status
2903 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2904 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2905 {
2906 /* Check the parameters */
2907 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2908
2909 /* Disable the Input Capture channels 1 and 2
2910 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2911 if (Channel == TIM_CHANNEL_1)
2912 {
2913 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2914
2915 /* Disable the capture compare Interrupts 1 */
2916 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2917 }
2918 else if (Channel == TIM_CHANNEL_2)
2919 {
2920 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2921
2922 /* Disable the capture compare Interrupts 2 */
2923 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2924 }
2925 else
2926 {
2927 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2928 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2929
2930 /* Disable the capture compare Interrupts 1 and 2 */
2931 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2932 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2933 }
2934
2935 /* Disable the Peripheral */
2936 __HAL_TIM_DISABLE(htim);
2937
2938 /* Change the htim state */
2939 htim->State = HAL_TIM_STATE_READY;
2940
2941 /* Return function status */
2942 return HAL_OK;
2943 }
2944
2945 /**
2946 * @brief Starts the TIM Encoder Interface in DMA mode.
2947 * @param htim TIM Encoder Interface handle
2948 * @param Channel TIM Channels to be enabled
2949 * This parameter can be one of the following values:
2950 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2951 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2952 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2953 * @param pData1 The destination Buffer address for IC1.
2954 * @param pData2 The destination Buffer address for IC2.
2955 * @param Length The length of data to be transferred from TIM peripheral to memory.
2956 * @retval HAL status
2957 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)2958 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2959 {
2960 /* Check the parameters */
2961 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2962
2963 if ((htim->State == HAL_TIM_STATE_BUSY))
2964 {
2965 return HAL_BUSY;
2966 }
2967 else if ((htim->State == HAL_TIM_STATE_READY))
2968 {
2969 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
2970 {
2971 return HAL_ERROR;
2972 }
2973 else
2974 {
2975 htim->State = HAL_TIM_STATE_BUSY;
2976 }
2977 }
2978 else
2979 {
2980 /* nothing to do */
2981 }
2982
2983 switch (Channel)
2984 {
2985 case TIM_CHANNEL_1:
2986 {
2987 /* Set the DMA capture callbacks */
2988 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2989 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2990
2991 /* Set the DMA error callback */
2992 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2993
2994 /* Enable the DMA stream */
2995 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
2996 {
2997 return HAL_ERROR;
2998 }
2999 /* Enable the TIM Input Capture DMA request */
3000 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3001
3002 /* Enable the Peripheral */
3003 __HAL_TIM_ENABLE(htim);
3004
3005 /* Enable the Capture compare channel */
3006 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3007 break;
3008 }
3009
3010 case TIM_CHANNEL_2:
3011 {
3012 /* Set the DMA capture callbacks */
3013 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3014 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3015
3016 /* Set the DMA error callback */
3017 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3018 /* Enable the DMA stream */
3019 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3020 {
3021 return HAL_ERROR;
3022 }
3023 /* Enable the TIM Input Capture DMA request */
3024 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3025
3026 /* Enable the Peripheral */
3027 __HAL_TIM_ENABLE(htim);
3028
3029 /* Enable the Capture compare channel */
3030 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3031 break;
3032 }
3033
3034 case TIM_CHANNEL_ALL:
3035 {
3036 /* Set the DMA capture callbacks */
3037 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3038 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3039
3040 /* Set the DMA error callback */
3041 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3042
3043 /* Enable the DMA stream */
3044 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3045 {
3046 return HAL_ERROR;
3047 }
3048
3049 /* Set the DMA capture callbacks */
3050 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3051 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3052
3053 /* Set the DMA error callback */
3054 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3055
3056 /* Enable the DMA stream */
3057 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3058 {
3059 return HAL_ERROR;
3060 }
3061 /* Enable the Peripheral */
3062 __HAL_TIM_ENABLE(htim);
3063
3064 /* Enable the Capture compare channel */
3065 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3066 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3067
3068 /* Enable the TIM Input Capture DMA request */
3069 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3070 /* Enable the TIM Input Capture DMA request */
3071 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3072 break;
3073 }
3074
3075 default:
3076 break;
3077 }
3078 /* Return function status */
3079 return HAL_OK;
3080 }
3081
3082 /**
3083 * @brief Stops the TIM Encoder Interface in DMA mode.
3084 * @param htim TIM Encoder Interface handle
3085 * @param Channel TIM Channels to be enabled
3086 * This parameter can be one of the following values:
3087 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3088 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3089 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3090 * @retval HAL status
3091 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3092 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3093 {
3094 /* Check the parameters */
3095 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
3096
3097 /* Disable the Input Capture channels 1 and 2
3098 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3099 if (Channel == TIM_CHANNEL_1)
3100 {
3101 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3102
3103 /* Disable the capture compare DMA Request 1 */
3104 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3105 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3106 }
3107 else if (Channel == TIM_CHANNEL_2)
3108 {
3109 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3110
3111 /* Disable the capture compare DMA Request 2 */
3112 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3113 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3114 }
3115 else
3116 {
3117 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3118 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3119
3120 /* Disable the capture compare DMA Request 1 and 2 */
3121 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3122 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3123 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3124 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3125 }
3126
3127 /* Disable the Peripheral */
3128 __HAL_TIM_DISABLE(htim);
3129
3130 /* Change the htim state */
3131 htim->State = HAL_TIM_STATE_READY;
3132
3133 /* Return function status */
3134 return HAL_OK;
3135 }
3136
3137 /**
3138 * @}
3139 */
3140 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3141 * @brief TIM IRQ handler management
3142 *
3143 @verbatim
3144 ==============================================================================
3145 ##### IRQ handler management #####
3146 ==============================================================================
3147 [..]
3148 This section provides Timer IRQ handler function.
3149
3150 @endverbatim
3151 * @{
3152 */
3153 /**
3154 * @brief This function handles TIM interrupts requests.
3155 * @param htim TIM handle
3156 * @retval None
3157 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3158 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3159 {
3160 /* Capture compare 1 event */
3161 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3162 {
3163 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3164 {
3165 {
3166 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3167 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3168
3169 /* Input capture event */
3170 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3171 {
3172 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3173 htim->IC_CaptureCallback(htim);
3174 #else
3175 HAL_TIM_IC_CaptureCallback(htim);
3176 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3177 }
3178 /* Output compare event */
3179 else
3180 {
3181 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3182 htim->OC_DelayElapsedCallback(htim);
3183 htim->PWM_PulseFinishedCallback(htim);
3184 #else
3185 HAL_TIM_OC_DelayElapsedCallback(htim);
3186 HAL_TIM_PWM_PulseFinishedCallback(htim);
3187 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3188 }
3189 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3190 }
3191 }
3192 }
3193 /* Capture compare 2 event */
3194 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3195 {
3196 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3197 {
3198 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3199 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3200 /* Input capture event */
3201 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3202 {
3203 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3204 htim->IC_CaptureCallback(htim);
3205 #else
3206 HAL_TIM_IC_CaptureCallback(htim);
3207 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3208 }
3209 /* Output compare event */
3210 else
3211 {
3212 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3213 htim->OC_DelayElapsedCallback(htim);
3214 htim->PWM_PulseFinishedCallback(htim);
3215 #else
3216 HAL_TIM_OC_DelayElapsedCallback(htim);
3217 HAL_TIM_PWM_PulseFinishedCallback(htim);
3218 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3219 }
3220 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3221 }
3222 }
3223 /* Capture compare 3 event */
3224 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3225 {
3226 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3227 {
3228 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3229 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3230 /* Input capture event */
3231 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3232 {
3233 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3234 htim->IC_CaptureCallback(htim);
3235 #else
3236 HAL_TIM_IC_CaptureCallback(htim);
3237 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3238 }
3239 /* Output compare event */
3240 else
3241 {
3242 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3243 htim->OC_DelayElapsedCallback(htim);
3244 htim->PWM_PulseFinishedCallback(htim);
3245 #else
3246 HAL_TIM_OC_DelayElapsedCallback(htim);
3247 HAL_TIM_PWM_PulseFinishedCallback(htim);
3248 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3249 }
3250 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3251 }
3252 }
3253 /* Capture compare 4 event */
3254 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3255 {
3256 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3257 {
3258 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3259 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3260 /* Input capture event */
3261 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3262 {
3263 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3264 htim->IC_CaptureCallback(htim);
3265 #else
3266 HAL_TIM_IC_CaptureCallback(htim);
3267 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3268 }
3269 /* Output compare event */
3270 else
3271 {
3272 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3273 htim->OC_DelayElapsedCallback(htim);
3274 htim->PWM_PulseFinishedCallback(htim);
3275 #else
3276 HAL_TIM_OC_DelayElapsedCallback(htim);
3277 HAL_TIM_PWM_PulseFinishedCallback(htim);
3278 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3279 }
3280 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3281 }
3282 }
3283 /* TIM Update event */
3284 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3285 {
3286 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3287 {
3288 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3289 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3290 htim->PeriodElapsedCallback(htim);
3291 #else
3292 HAL_TIM_PeriodElapsedCallback(htim);
3293 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3294 }
3295 }
3296 /* TIM Break input event */
3297 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3298 {
3299 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3300 {
3301 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3302 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3303 htim->BreakCallback(htim);
3304 #else
3305 HAL_TIMEx_BreakCallback(htim);
3306 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3307 }
3308 }
3309 /* TIM Trigger detection event */
3310 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3311 {
3312 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3313 {
3314 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3315 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3316 htim->TriggerCallback(htim);
3317 #else
3318 HAL_TIM_TriggerCallback(htim);
3319 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3320 }
3321 }
3322 /* TIM commutation event */
3323 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3324 {
3325 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3326 {
3327 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3328 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3329 htim->CommutationCallback(htim);
3330 #else
3331 HAL_TIMEx_CommutCallback(htim);
3332 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3333 }
3334 }
3335 }
3336
3337 /**
3338 * @}
3339 */
3340
3341 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3342 * @brief TIM Peripheral Control functions
3343 *
3344 @verbatim
3345 ==============================================================================
3346 ##### Peripheral Control functions #####
3347 ==============================================================================
3348 [..]
3349 This section provides functions allowing to:
3350 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3351 (+) Configure External Clock source.
3352 (+) Configure Complementary channels, break features and dead time.
3353 (+) Configure Master and the Slave synchronization.
3354 (+) Configure the DMA Burst Mode.
3355
3356 @endverbatim
3357 * @{
3358 */
3359
3360 /**
3361 * @brief Initializes the TIM Output Compare Channels according to the specified
3362 * parameters in the TIM_OC_InitTypeDef.
3363 * @param htim TIM Output Compare handle
3364 * @param sConfig TIM Output Compare configuration structure
3365 * @param Channel TIM Channels to configure
3366 * This parameter can be one of the following values:
3367 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3368 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3369 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3370 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3371 * @retval HAL status
3372 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3373 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3374 TIM_OC_InitTypeDef *sConfig,
3375 uint32_t Channel)
3376 {
3377 /* Check the parameters */
3378 assert_param(IS_TIM_CHANNELS(Channel));
3379 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3380 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3381
3382 /* Process Locked */
3383 __HAL_LOCK(htim);
3384
3385 htim->State = HAL_TIM_STATE_BUSY;
3386
3387 switch (Channel)
3388 {
3389 case TIM_CHANNEL_1:
3390 {
3391 /* Check the parameters */
3392 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3393
3394 /* Configure the TIM Channel 1 in Output Compare */
3395 TIM_OC1_SetConfig(htim->Instance, sConfig);
3396 break;
3397 }
3398
3399 case TIM_CHANNEL_2:
3400 {
3401 /* Check the parameters */
3402 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3403
3404 /* Configure the TIM Channel 2 in Output Compare */
3405 TIM_OC2_SetConfig(htim->Instance, sConfig);
3406 break;
3407 }
3408
3409 case TIM_CHANNEL_3:
3410 {
3411 /* Check the parameters */
3412 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3413
3414 /* Configure the TIM Channel 3 in Output Compare */
3415 TIM_OC3_SetConfig(htim->Instance, sConfig);
3416 break;
3417 }
3418
3419 case TIM_CHANNEL_4:
3420 {
3421 /* Check the parameters */
3422 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3423
3424 /* Configure the TIM Channel 4 in Output Compare */
3425 TIM_OC4_SetConfig(htim->Instance, sConfig);
3426 break;
3427 }
3428
3429 default:
3430 break;
3431 }
3432
3433 htim->State = HAL_TIM_STATE_READY;
3434
3435 __HAL_UNLOCK(htim);
3436
3437 return HAL_OK;
3438 }
3439
3440 /**
3441 * @brief Initializes the TIM Input Capture Channels according to the specified
3442 * parameters in the TIM_IC_InitTypeDef.
3443 * @param htim TIM IC handle
3444 * @param sConfig TIM Input Capture configuration structure
3445 * @param Channel TIM Channel to configure
3446 * This parameter can be one of the following values:
3447 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3448 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3449 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3450 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3451 * @retval HAL status
3452 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3453 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3454 {
3455 /* Check the parameters */
3456 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3457 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3458 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3459 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3460 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3461
3462 /* Process Locked */
3463 __HAL_LOCK(htim);
3464
3465 htim->State = HAL_TIM_STATE_BUSY;
3466
3467 if (Channel == TIM_CHANNEL_1)
3468 {
3469 /* TI1 Configuration */
3470 TIM_TI1_SetConfig(htim->Instance,
3471 sConfig->ICPolarity,
3472 sConfig->ICSelection,
3473 sConfig->ICFilter);
3474
3475 /* Reset the IC1PSC Bits */
3476 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3477
3478 /* Set the IC1PSC value */
3479 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3480 }
3481 else if (Channel == TIM_CHANNEL_2)
3482 {
3483 /* TI2 Configuration */
3484 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3485
3486 TIM_TI2_SetConfig(htim->Instance,
3487 sConfig->ICPolarity,
3488 sConfig->ICSelection,
3489 sConfig->ICFilter);
3490
3491 /* Reset the IC2PSC Bits */
3492 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3493
3494 /* Set the IC2PSC value */
3495 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3496 }
3497 else if (Channel == TIM_CHANNEL_3)
3498 {
3499 /* TI3 Configuration */
3500 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3501
3502 TIM_TI3_SetConfig(htim->Instance,
3503 sConfig->ICPolarity,
3504 sConfig->ICSelection,
3505 sConfig->ICFilter);
3506
3507 /* Reset the IC3PSC Bits */
3508 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3509
3510 /* Set the IC3PSC value */
3511 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3512 }
3513 else
3514 {
3515 /* TI4 Configuration */
3516 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3517
3518 TIM_TI4_SetConfig(htim->Instance,
3519 sConfig->ICPolarity,
3520 sConfig->ICSelection,
3521 sConfig->ICFilter);
3522
3523 /* Reset the IC4PSC Bits */
3524 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3525
3526 /* Set the IC4PSC value */
3527 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3528 }
3529
3530 htim->State = HAL_TIM_STATE_READY;
3531
3532 __HAL_UNLOCK(htim);
3533
3534 return HAL_OK;
3535 }
3536
3537 /**
3538 * @brief Initializes the TIM PWM channels according to the specified
3539 * parameters in the TIM_OC_InitTypeDef.
3540 * @param htim TIM PWM handle
3541 * @param sConfig TIM PWM configuration structure
3542 * @param Channel TIM Channels to be configured
3543 * This parameter can be one of the following values:
3544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3546 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3547 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3548 * @retval HAL status
3549 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3550 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
3551 TIM_OC_InitTypeDef *sConfig,
3552 uint32_t Channel)
3553 {
3554 /* Check the parameters */
3555 assert_param(IS_TIM_CHANNELS(Channel));
3556 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3557 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3558 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3559
3560 /* Process Locked */
3561 __HAL_LOCK(htim);
3562
3563 htim->State = HAL_TIM_STATE_BUSY;
3564
3565 switch (Channel)
3566 {
3567 case TIM_CHANNEL_1:
3568 {
3569 /* Check the parameters */
3570 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3571
3572 /* Configure the Channel 1 in PWM mode */
3573 TIM_OC1_SetConfig(htim->Instance, sConfig);
3574
3575 /* Set the Preload enable bit for channel1 */
3576 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3577
3578 /* Configure the Output Fast mode */
3579 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3580 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3581 break;
3582 }
3583
3584 case TIM_CHANNEL_2:
3585 {
3586 /* Check the parameters */
3587 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3588
3589 /* Configure the Channel 2 in PWM mode */
3590 TIM_OC2_SetConfig(htim->Instance, sConfig);
3591
3592 /* Set the Preload enable bit for channel2 */
3593 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3594
3595 /* Configure the Output Fast mode */
3596 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3597 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3598 break;
3599 }
3600
3601 case TIM_CHANNEL_3:
3602 {
3603 /* Check the parameters */
3604 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3605
3606 /* Configure the Channel 3 in PWM mode */
3607 TIM_OC3_SetConfig(htim->Instance, sConfig);
3608
3609 /* Set the Preload enable bit for channel3 */
3610 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3611
3612 /* Configure the Output Fast mode */
3613 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3614 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3615 break;
3616 }
3617
3618 case TIM_CHANNEL_4:
3619 {
3620 /* Check the parameters */
3621 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3622
3623 /* Configure the Channel 4 in PWM mode */
3624 TIM_OC4_SetConfig(htim->Instance, sConfig);
3625
3626 /* Set the Preload enable bit for channel4 */
3627 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3628
3629 /* Configure the Output Fast mode */
3630 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3631 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3632 break;
3633 }
3634
3635 default:
3636 break;
3637 }
3638
3639 htim->State = HAL_TIM_STATE_READY;
3640
3641 __HAL_UNLOCK(htim);
3642
3643 return HAL_OK;
3644 }
3645
3646 /**
3647 * @brief Initializes the TIM One Pulse Channels according to the specified
3648 * parameters in the TIM_OnePulse_InitTypeDef.
3649 * @param htim TIM One Pulse handle
3650 * @param sConfig TIM One Pulse configuration structure
3651 * @param OutputChannel TIM output channel to configure
3652 * This parameter can be one of the following values:
3653 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3654 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3655 * @param InputChannel TIM input Channel to configure
3656 * This parameter can be one of the following values:
3657 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3658 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3659 * @retval HAL status
3660 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)3661 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3662 {
3663 TIM_OC_InitTypeDef temp1;
3664
3665 /* Check the parameters */
3666 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3667 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3668
3669 if (OutputChannel != InputChannel)
3670 {
3671 /* Process Locked */
3672 __HAL_LOCK(htim);
3673
3674 htim->State = HAL_TIM_STATE_BUSY;
3675
3676 /* Extract the Output compare configuration from sConfig structure */
3677 temp1.OCMode = sConfig->OCMode;
3678 temp1.Pulse = sConfig->Pulse;
3679 temp1.OCPolarity = sConfig->OCPolarity;
3680 temp1.OCNPolarity = sConfig->OCNPolarity;
3681 temp1.OCIdleState = sConfig->OCIdleState;
3682 temp1.OCNIdleState = sConfig->OCNIdleState;
3683
3684 switch (OutputChannel)
3685 {
3686 case TIM_CHANNEL_1:
3687 {
3688 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3689
3690 TIM_OC1_SetConfig(htim->Instance, &temp1);
3691 break;
3692 }
3693 case TIM_CHANNEL_2:
3694 {
3695 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3696
3697 TIM_OC2_SetConfig(htim->Instance, &temp1);
3698 break;
3699 }
3700 default:
3701 break;
3702 }
3703
3704 switch (InputChannel)
3705 {
3706 case TIM_CHANNEL_1:
3707 {
3708 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3709
3710 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3711 sConfig->ICSelection, sConfig->ICFilter);
3712
3713 /* Reset the IC1PSC Bits */
3714 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3715
3716 /* Select the Trigger source */
3717 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3718 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3719
3720 /* Select the Slave Mode */
3721 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3722 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3723 break;
3724 }
3725 case TIM_CHANNEL_2:
3726 {
3727 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3728
3729 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3730 sConfig->ICSelection, sConfig->ICFilter);
3731
3732 /* Reset the IC2PSC Bits */
3733 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3734
3735 /* Select the Trigger source */
3736 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3737 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3738
3739 /* Select the Slave Mode */
3740 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3741 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3742 break;
3743 }
3744
3745 default:
3746 break;
3747 }
3748
3749 htim->State = HAL_TIM_STATE_READY;
3750
3751 __HAL_UNLOCK(htim);
3752
3753 return HAL_OK;
3754 }
3755 else
3756 {
3757 return HAL_ERROR;
3758 }
3759 }
3760
3761 /**
3762 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3763 * @param htim TIM handle
3764 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3765 * This parameter can be one of the following values:
3766 * @arg TIM_DMABASE_CR1
3767 * @arg TIM_DMABASE_CR2
3768 * @arg TIM_DMABASE_SMCR
3769 * @arg TIM_DMABASE_DIER
3770 * @arg TIM_DMABASE_SR
3771 * @arg TIM_DMABASE_EGR
3772 * @arg TIM_DMABASE_CCMR1
3773 * @arg TIM_DMABASE_CCMR2
3774 * @arg TIM_DMABASE_CCER
3775 * @arg TIM_DMABASE_CNT
3776 * @arg TIM_DMABASE_PSC
3777 * @arg TIM_DMABASE_ARR
3778 * @arg TIM_DMABASE_RCR
3779 * @arg TIM_DMABASE_CCR1
3780 * @arg TIM_DMABASE_CCR2
3781 * @arg TIM_DMABASE_CCR3
3782 * @arg TIM_DMABASE_CCR4
3783 * @arg TIM_DMABASE_BDTR
3784 * @param BurstRequestSrc TIM DMA Request sources
3785 * This parameter can be one of the following values:
3786 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3787 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3788 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3789 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3790 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3791 * @arg TIM_DMA_COM: TIM Commutation DMA source
3792 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3793 * @param BurstBuffer The Buffer address.
3794 * @param BurstLength DMA Burst length. This parameter can be one value
3795 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3796 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
3797 * @retval HAL status
3798 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3799 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3800 uint32_t *BurstBuffer, uint32_t BurstLength)
3801 {
3802 /* Check the parameters */
3803 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3804 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3805 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3806 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3807
3808 if ((htim->State == HAL_TIM_STATE_BUSY))
3809 {
3810 return HAL_BUSY;
3811 }
3812 else if ((htim->State == HAL_TIM_STATE_READY))
3813 {
3814 if ((BurstBuffer == NULL) && (BurstLength > 0U))
3815 {
3816 return HAL_ERROR;
3817 }
3818 else
3819 {
3820 htim->State = HAL_TIM_STATE_BUSY;
3821 }
3822 }
3823 else
3824 {
3825 /* nothing to do */
3826 }
3827 switch (BurstRequestSrc)
3828 {
3829 case TIM_DMA_UPDATE:
3830 {
3831 /* Set the DMA Period elapsed callbacks */
3832 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3833 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
3834
3835 /* Set the DMA error callback */
3836 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3837
3838 /* Enable the DMA stream */
3839 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3840 {
3841 return HAL_ERROR;
3842 }
3843 break;
3844 }
3845 case TIM_DMA_CC1:
3846 {
3847 /* Set the DMA compare callbacks */
3848 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3849 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3850
3851 /* Set the DMA error callback */
3852 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3853
3854 /* Enable the DMA stream */
3855 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3856 {
3857 return HAL_ERROR;
3858 }
3859 break;
3860 }
3861 case TIM_DMA_CC2:
3862 {
3863 /* Set the DMA compare callbacks */
3864 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3865 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3866
3867 /* Set the DMA error callback */
3868 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3869
3870 /* Enable the DMA stream */
3871 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3872 {
3873 return HAL_ERROR;
3874 }
3875 break;
3876 }
3877 case TIM_DMA_CC3:
3878 {
3879 /* Set the DMA compare callbacks */
3880 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3881 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3882
3883 /* Set the DMA error callback */
3884 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3885
3886 /* Enable the DMA stream */
3887 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3888 {
3889 return HAL_ERROR;
3890 }
3891 break;
3892 }
3893 case TIM_DMA_CC4:
3894 {
3895 /* Set the DMA compare callbacks */
3896 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3897 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3898
3899 /* Set the DMA error callback */
3900 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3901
3902 /* Enable the DMA stream */
3903 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3904 {
3905 return HAL_ERROR;
3906 }
3907 break;
3908 }
3909 case TIM_DMA_COM:
3910 {
3911 /* Set the DMA commutation callbacks */
3912 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3913 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
3914
3915 /* Set the DMA error callback */
3916 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3917
3918 /* Enable the DMA stream */
3919 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3920 {
3921 return HAL_ERROR;
3922 }
3923 break;
3924 }
3925 case TIM_DMA_TRIGGER:
3926 {
3927 /* Set the DMA trigger callbacks */
3928 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3929 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
3930
3931 /* Set the DMA error callback */
3932 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3933
3934 /* Enable the DMA stream */
3935 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3936 {
3937 return HAL_ERROR;
3938 }
3939 break;
3940 }
3941 default:
3942 break;
3943 }
3944 /* configure the DMA Burst Mode */
3945 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
3946
3947 /* Enable the TIM DMA Request */
3948 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3949
3950 htim->State = HAL_TIM_STATE_READY;
3951
3952 /* Return function status */
3953 return HAL_OK;
3954 }
3955
3956 /**
3957 * @brief Stops the TIM DMA Burst mode
3958 * @param htim TIM handle
3959 * @param BurstRequestSrc TIM DMA Request sources to disable
3960 * @retval HAL status
3961 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)3962 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3963 {
3964 HAL_StatusTypeDef status = HAL_OK;
3965 /* Check the parameters */
3966 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3967
3968 /* Abort the DMA transfer (at least disable the DMA stream) */
3969 switch (BurstRequestSrc)
3970 {
3971 case TIM_DMA_UPDATE:
3972 {
3973 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
3974 break;
3975 }
3976 case TIM_DMA_CC1:
3977 {
3978 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3979 break;
3980 }
3981 case TIM_DMA_CC2:
3982 {
3983 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3984 break;
3985 }
3986 case TIM_DMA_CC3:
3987 {
3988 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
3989 break;
3990 }
3991 case TIM_DMA_CC4:
3992 {
3993 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
3994 break;
3995 }
3996 case TIM_DMA_COM:
3997 {
3998 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3999 break;
4000 }
4001 case TIM_DMA_TRIGGER:
4002 {
4003 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4004 break;
4005 }
4006 default:
4007 break;
4008 }
4009
4010 if (HAL_OK == status)
4011 {
4012 /* Disable the TIM Update DMA request */
4013 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4014 }
4015
4016 /* Return function status */
4017 return status;
4018 }
4019
4020 /**
4021 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4022 * @param htim TIM handle
4023 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4024 * This parameter can be one of the following values:
4025 * @arg TIM_DMABASE_CR1
4026 * @arg TIM_DMABASE_CR2
4027 * @arg TIM_DMABASE_SMCR
4028 * @arg TIM_DMABASE_DIER
4029 * @arg TIM_DMABASE_SR
4030 * @arg TIM_DMABASE_EGR
4031 * @arg TIM_DMABASE_CCMR1
4032 * @arg TIM_DMABASE_CCMR2
4033 * @arg TIM_DMABASE_CCER
4034 * @arg TIM_DMABASE_CNT
4035 * @arg TIM_DMABASE_PSC
4036 * @arg TIM_DMABASE_ARR
4037 * @arg TIM_DMABASE_RCR
4038 * @arg TIM_DMABASE_CCR1
4039 * @arg TIM_DMABASE_CCR2
4040 * @arg TIM_DMABASE_CCR3
4041 * @arg TIM_DMABASE_CCR4
4042 * @arg TIM_DMABASE_BDTR
4043 * @param BurstRequestSrc TIM DMA Request sources
4044 * This parameter can be one of the following values:
4045 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4046 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4047 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4048 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4049 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4050 * @arg TIM_DMA_COM: TIM Commutation DMA source
4051 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4052 * @param BurstBuffer The Buffer address.
4053 * @param BurstLength DMA Burst length. This parameter can be one value
4054 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4055 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4056 * @retval HAL status
4057 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4058 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
4059 uint32_t *BurstBuffer, uint32_t BurstLength)
4060 {
4061 /* Check the parameters */
4062 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4063 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4064 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4065 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4066
4067 if ((htim->State == HAL_TIM_STATE_BUSY))
4068 {
4069 return HAL_BUSY;
4070 }
4071 else if ((htim->State == HAL_TIM_STATE_READY))
4072 {
4073 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4074 {
4075 return HAL_ERROR;
4076 }
4077 else
4078 {
4079 htim->State = HAL_TIM_STATE_BUSY;
4080 }
4081 }
4082 else
4083 {
4084 /* nothing to do */
4085 }
4086 switch (BurstRequestSrc)
4087 {
4088 case TIM_DMA_UPDATE:
4089 {
4090 /* Set the DMA Period elapsed callbacks */
4091 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4092 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4093
4094 /* Set the DMA error callback */
4095 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4096
4097 /* Enable the DMA stream */
4098 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4099 {
4100 return HAL_ERROR;
4101 }
4102 break;
4103 }
4104 case TIM_DMA_CC1:
4105 {
4106 /* Set the DMA capture callbacks */
4107 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4108 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4109
4110 /* Set the DMA error callback */
4111 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4112
4113 /* Enable the DMA stream */
4114 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4115 {
4116 return HAL_ERROR;
4117 }
4118 break;
4119 }
4120 case TIM_DMA_CC2:
4121 {
4122 /* Set the DMA capture/compare callbacks */
4123 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4124 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4125
4126 /* Set the DMA error callback */
4127 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4128
4129 /* Enable the DMA stream */
4130 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4131 {
4132 return HAL_ERROR;
4133 }
4134 break;
4135 }
4136 case TIM_DMA_CC3:
4137 {
4138 /* Set the DMA capture callbacks */
4139 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4140 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4141
4142 /* Set the DMA error callback */
4143 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4144
4145 /* Enable the DMA stream */
4146 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4147 {
4148 return HAL_ERROR;
4149 }
4150 break;
4151 }
4152 case TIM_DMA_CC4:
4153 {
4154 /* Set the DMA capture callbacks */
4155 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4156 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4157
4158 /* Set the DMA error callback */
4159 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4160
4161 /* Enable the DMA stream */
4162 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4163 {
4164 return HAL_ERROR;
4165 }
4166 break;
4167 }
4168 case TIM_DMA_COM:
4169 {
4170 /* Set the DMA commutation callbacks */
4171 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4172 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4173
4174 /* Set the DMA error callback */
4175 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4176
4177 /* Enable the DMA stream */
4178 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4179 {
4180 return HAL_ERROR;
4181 }
4182 break;
4183 }
4184 case TIM_DMA_TRIGGER:
4185 {
4186 /* Set the DMA trigger callbacks */
4187 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4188 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4189
4190 /* Set the DMA error callback */
4191 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4192
4193 /* Enable the DMA stream */
4194 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4195 {
4196 return HAL_ERROR;
4197 }
4198 break;
4199 }
4200 default:
4201 break;
4202 }
4203
4204 /* configure the DMA Burst Mode */
4205 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4206
4207 /* Enable the TIM DMA Request */
4208 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4209
4210 htim->State = HAL_TIM_STATE_READY;
4211
4212 /* Return function status */
4213 return HAL_OK;
4214 }
4215
4216 /**
4217 * @brief Stop the DMA burst reading
4218 * @param htim TIM handle
4219 * @param BurstRequestSrc TIM DMA Request sources to disable.
4220 * @retval HAL status
4221 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4222 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4223 {
4224 HAL_StatusTypeDef status = HAL_OK;
4225 /* Check the parameters */
4226 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4227
4228 /* Abort the DMA transfer (at least disable the DMA stream) */
4229 switch (BurstRequestSrc)
4230 {
4231 case TIM_DMA_UPDATE:
4232 {
4233 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4234 break;
4235 }
4236 case TIM_DMA_CC1:
4237 {
4238 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4239 break;
4240 }
4241 case TIM_DMA_CC2:
4242 {
4243 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4244 break;
4245 }
4246 case TIM_DMA_CC3:
4247 {
4248 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4249 break;
4250 }
4251 case TIM_DMA_CC4:
4252 {
4253 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4254 break;
4255 }
4256 case TIM_DMA_COM:
4257 {
4258 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4259 break;
4260 }
4261 case TIM_DMA_TRIGGER:
4262 {
4263 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4264 break;
4265 }
4266 default:
4267 break;
4268 }
4269
4270 if (HAL_OK == status)
4271 {
4272 /* Disable the TIM Update DMA request */
4273 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4274 }
4275
4276 /* Return function status */
4277 return status;
4278 }
4279
4280 /**
4281 * @brief Generate a software event
4282 * @param htim TIM handle
4283 * @param EventSource specifies the event source.
4284 * This parameter can be one of the following values:
4285 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4286 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4287 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4288 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4289 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4290 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4291 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4292 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4293 * @note Basic timers can only generate an update event.
4294 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4295 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
4296 * supporting a break input.
4297 * @retval HAL status
4298 */
4299
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4300 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4301 {
4302 /* Check the parameters */
4303 assert_param(IS_TIM_INSTANCE(htim->Instance));
4304 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4305
4306 /* Process Locked */
4307 __HAL_LOCK(htim);
4308
4309 /* Change the TIM state */
4310 htim->State = HAL_TIM_STATE_BUSY;
4311
4312 /* Set the event sources */
4313 htim->Instance->EGR = EventSource;
4314
4315 /* Change the TIM state */
4316 htim->State = HAL_TIM_STATE_READY;
4317
4318 __HAL_UNLOCK(htim);
4319
4320 /* Return function status */
4321 return HAL_OK;
4322 }
4323
4324 /**
4325 * @brief Configures the OCRef clear feature
4326 * @param htim TIM handle
4327 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4328 * contains the OCREF clear feature and parameters for the TIM peripheral.
4329 * @param Channel specifies the TIM Channel
4330 * This parameter can be one of the following values:
4331 * @arg TIM_CHANNEL_1: TIM Channel 1
4332 * @arg TIM_CHANNEL_2: TIM Channel 2
4333 * @arg TIM_CHANNEL_3: TIM Channel 3
4334 * @arg TIM_CHANNEL_4: TIM Channel 4
4335 * @retval HAL status
4336 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4337 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4338 TIM_ClearInputConfigTypeDef *sClearInputConfig,
4339 uint32_t Channel)
4340 {
4341 /* Check the parameters */
4342 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4343 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4344
4345 /* Process Locked */
4346 __HAL_LOCK(htim);
4347
4348 htim->State = HAL_TIM_STATE_BUSY;
4349
4350 switch (sClearInputConfig->ClearInputSource)
4351 {
4352 case TIM_CLEARINPUTSOURCE_NONE:
4353 {
4354 /* Clear the OCREF clear selection bit and the the ETR Bits */
4355 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4356 break;
4357 }
4358
4359 case TIM_CLEARINPUTSOURCE_ETR:
4360 {
4361 /* Check the parameters */
4362 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4363 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4364 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4365
4366 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
4367 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
4368 {
4369 htim->State = HAL_TIM_STATE_READY;
4370 __HAL_UNLOCK(htim);
4371 return HAL_ERROR;
4372 }
4373
4374 TIM_ETR_SetConfig(htim->Instance,
4375 sClearInputConfig->ClearInputPrescaler,
4376 sClearInputConfig->ClearInputPolarity,
4377 sClearInputConfig->ClearInputFilter);
4378 break;
4379 }
4380
4381 default:
4382 break;
4383 }
4384
4385 switch (Channel)
4386 {
4387 case TIM_CHANNEL_1:
4388 {
4389 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4390 {
4391 /* Enable the OCREF clear feature for Channel 1 */
4392 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4393 }
4394 else
4395 {
4396 /* Disable the OCREF clear feature for Channel 1 */
4397 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4398 }
4399 break;
4400 }
4401 case TIM_CHANNEL_2:
4402 {
4403 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4404 {
4405 /* Enable the OCREF clear feature for Channel 2 */
4406 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4407 }
4408 else
4409 {
4410 /* Disable the OCREF clear feature for Channel 2 */
4411 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4412 }
4413 break;
4414 }
4415 case TIM_CHANNEL_3:
4416 {
4417 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4418 {
4419 /* Enable the OCREF clear feature for Channel 3 */
4420 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4421 }
4422 else
4423 {
4424 /* Disable the OCREF clear feature for Channel 3 */
4425 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4426 }
4427 break;
4428 }
4429 case TIM_CHANNEL_4:
4430 {
4431 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4432 {
4433 /* Enable the OCREF clear feature for Channel 4 */
4434 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4435 }
4436 else
4437 {
4438 /* Disable the OCREF clear feature for Channel 4 */
4439 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4440 }
4441 break;
4442 }
4443 default:
4444 break;
4445 }
4446
4447 htim->State = HAL_TIM_STATE_READY;
4448
4449 __HAL_UNLOCK(htim);
4450
4451 return HAL_OK;
4452 }
4453
4454 /**
4455 * @brief Configures the clock source to be used
4456 * @param htim TIM handle
4457 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
4458 * contains the clock source information for the TIM peripheral.
4459 * @retval HAL status
4460 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)4461 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
4462 {
4463 uint32_t tmpsmcr;
4464
4465 /* Process Locked */
4466 __HAL_LOCK(htim);
4467
4468 htim->State = HAL_TIM_STATE_BUSY;
4469
4470 /* Check the parameters */
4471 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4472
4473 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4474 tmpsmcr = htim->Instance->SMCR;
4475 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4476 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4477 htim->Instance->SMCR = tmpsmcr;
4478
4479 switch (sClockSourceConfig->ClockSource)
4480 {
4481 case TIM_CLOCKSOURCE_INTERNAL:
4482 {
4483 assert_param(IS_TIM_INSTANCE(htim->Instance));
4484 break;
4485 }
4486
4487 case TIM_CLOCKSOURCE_ETRMODE1:
4488 {
4489 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
4490 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4491
4492 /* Check ETR input conditioning related parameters */
4493 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4494 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4495 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4496
4497 /* Configure the ETR Clock source */
4498 TIM_ETR_SetConfig(htim->Instance,
4499 sClockSourceConfig->ClockPrescaler,
4500 sClockSourceConfig->ClockPolarity,
4501 sClockSourceConfig->ClockFilter);
4502
4503 /* Select the External clock mode1 and the ETRF trigger */
4504 tmpsmcr = htim->Instance->SMCR;
4505 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
4506 /* Write to TIMx SMCR */
4507 htim->Instance->SMCR = tmpsmcr;
4508 break;
4509 }
4510
4511 case TIM_CLOCKSOURCE_ETRMODE2:
4512 {
4513 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
4514 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
4515
4516 /* Check ETR input conditioning related parameters */
4517 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4518 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4519 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4520
4521 /* Configure the ETR Clock source */
4522 TIM_ETR_SetConfig(htim->Instance,
4523 sClockSourceConfig->ClockPrescaler,
4524 sClockSourceConfig->ClockPolarity,
4525 sClockSourceConfig->ClockFilter);
4526 /* Enable the External clock mode2 */
4527 htim->Instance->SMCR |= TIM_SMCR_ECE;
4528 break;
4529 }
4530
4531 case TIM_CLOCKSOURCE_TI1:
4532 {
4533 /* Check whether or not the timer instance supports external clock mode 1 */
4534 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4535
4536 /* Check TI1 input conditioning related parameters */
4537 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4538 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4539
4540 TIM_TI1_ConfigInputStage(htim->Instance,
4541 sClockSourceConfig->ClockPolarity,
4542 sClockSourceConfig->ClockFilter);
4543 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4544 break;
4545 }
4546
4547 case TIM_CLOCKSOURCE_TI2:
4548 {
4549 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4550 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4551
4552 /* Check TI2 input conditioning related parameters */
4553 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4554 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4555
4556 TIM_TI2_ConfigInputStage(htim->Instance,
4557 sClockSourceConfig->ClockPolarity,
4558 sClockSourceConfig->ClockFilter);
4559 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4560 break;
4561 }
4562
4563 case TIM_CLOCKSOURCE_TI1ED:
4564 {
4565 /* Check whether or not the timer instance supports external clock mode 1 */
4566 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4567
4568 /* Check TI1 input conditioning related parameters */
4569 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4570 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4571
4572 TIM_TI1_ConfigInputStage(htim->Instance,
4573 sClockSourceConfig->ClockPolarity,
4574 sClockSourceConfig->ClockFilter);
4575 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4576 break;
4577 }
4578
4579 case TIM_CLOCKSOURCE_ITR0:
4580 case TIM_CLOCKSOURCE_ITR1:
4581 case TIM_CLOCKSOURCE_ITR2:
4582 case TIM_CLOCKSOURCE_ITR3:
4583 {
4584 /* Check whether or not the timer instance supports internal trigger input */
4585 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4586
4587 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
4588 break;
4589 }
4590
4591 default:
4592 break;
4593 }
4594 htim->State = HAL_TIM_STATE_READY;
4595
4596 __HAL_UNLOCK(htim);
4597
4598 return HAL_OK;
4599 }
4600
4601 /**
4602 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4603 * or a XOR combination between CH1_input, CH2_input & CH3_input
4604 * @param htim TIM handle.
4605 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
4606 * output of a XOR gate.
4607 * This parameter can be one of the following values:
4608 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4609 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4610 * pins are connected to the TI1 input (XOR combination)
4611 * @retval HAL status
4612 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)4613 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4614 {
4615 uint32_t tmpcr2;
4616
4617 /* Check the parameters */
4618 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4619 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4620
4621 /* Get the TIMx CR2 register value */
4622 tmpcr2 = htim->Instance->CR2;
4623
4624 /* Reset the TI1 selection */
4625 tmpcr2 &= ~TIM_CR2_TI1S;
4626
4627 /* Set the TI1 selection */
4628 tmpcr2 |= TI1_Selection;
4629
4630 /* Write to TIMxCR2 */
4631 htim->Instance->CR2 = tmpcr2;
4632
4633 return HAL_OK;
4634 }
4635
4636 /**
4637 * @brief Configures the TIM in Slave mode
4638 * @param htim TIM handle.
4639 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4640 * contains the selected trigger (internal trigger input, filtered
4641 * timer input or external trigger input) and the Slave mode
4642 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4643 * @retval HAL status
4644 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4645 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
4646 {
4647 /* Check the parameters */
4648 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4649 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4650 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4651
4652 __HAL_LOCK(htim);
4653
4654 htim->State = HAL_TIM_STATE_BUSY;
4655
4656 if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4657 {
4658 htim->State = HAL_TIM_STATE_READY;
4659 __HAL_UNLOCK(htim);
4660 return HAL_ERROR;
4661 }
4662
4663 /* Disable Trigger Interrupt */
4664 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4665
4666 /* Disable Trigger DMA request */
4667 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4668
4669 htim->State = HAL_TIM_STATE_READY;
4670
4671 __HAL_UNLOCK(htim);
4672
4673 return HAL_OK;
4674 }
4675
4676 /**
4677 * @brief Configures the TIM in Slave mode in interrupt mode
4678 * @param htim TIM handle.
4679 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4680 * contains the selected trigger (internal trigger input, filtered
4681 * timer input or external trigger input) and the Slave mode
4682 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4683 * @retval HAL status
4684 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4685 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
4686 TIM_SlaveConfigTypeDef *sSlaveConfig)
4687 {
4688 /* Check the parameters */
4689 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4690 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4691 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4692
4693 __HAL_LOCK(htim);
4694
4695 htim->State = HAL_TIM_STATE_BUSY;
4696
4697 if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4698 {
4699 htim->State = HAL_TIM_STATE_READY;
4700 __HAL_UNLOCK(htim);
4701 return HAL_ERROR;
4702 }
4703
4704 /* Enable Trigger Interrupt */
4705 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4706
4707 /* Disable Trigger DMA request */
4708 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4709
4710 htim->State = HAL_TIM_STATE_READY;
4711
4712 __HAL_UNLOCK(htim);
4713
4714 return HAL_OK;
4715 }
4716
4717 /**
4718 * @brief Read the captured value from Capture Compare unit
4719 * @param htim TIM handle.
4720 * @param Channel TIM Channels to be enabled
4721 * This parameter can be one of the following values:
4722 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4723 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4724 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4725 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4726 * @retval Captured value
4727 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)4728 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4729 {
4730 uint32_t tmpreg = 0U;
4731
4732 switch (Channel)
4733 {
4734 case TIM_CHANNEL_1:
4735 {
4736 /* Check the parameters */
4737 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4738
4739 /* Return the capture 1 value */
4740 tmpreg = htim->Instance->CCR1;
4741
4742 break;
4743 }
4744 case TIM_CHANNEL_2:
4745 {
4746 /* Check the parameters */
4747 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4748
4749 /* Return the capture 2 value */
4750 tmpreg = htim->Instance->CCR2;
4751
4752 break;
4753 }
4754
4755 case TIM_CHANNEL_3:
4756 {
4757 /* Check the parameters */
4758 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4759
4760 /* Return the capture 3 value */
4761 tmpreg = htim->Instance->CCR3;
4762
4763 break;
4764 }
4765
4766 case TIM_CHANNEL_4:
4767 {
4768 /* Check the parameters */
4769 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4770
4771 /* Return the capture 4 value */
4772 tmpreg = htim->Instance->CCR4;
4773
4774 break;
4775 }
4776
4777 default:
4778 break;
4779 }
4780
4781 return tmpreg;
4782 }
4783
4784 /**
4785 * @}
4786 */
4787
4788 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4789 * @brief TIM Callbacks functions
4790 *
4791 @verbatim
4792 ==============================================================================
4793 ##### TIM Callbacks functions #####
4794 ==============================================================================
4795 [..]
4796 This section provides TIM callback functions:
4797 (+) TIM Period elapsed callback
4798 (+) TIM Output Compare callback
4799 (+) TIM Input capture callback
4800 (+) TIM Trigger callback
4801 (+) TIM Error callback
4802
4803 @endverbatim
4804 * @{
4805 */
4806
4807 /**
4808 * @brief Period elapsed callback in non-blocking mode
4809 * @param htim TIM handle
4810 * @retval None
4811 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)4812 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4813 {
4814 /* Prevent unused argument(s) compilation warning */
4815 UNUSED(htim);
4816
4817 /* NOTE : This function should not be modified, when the callback is needed,
4818 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4819 */
4820 }
4821
4822 /**
4823 * @brief Period elapsed half complete callback in non-blocking mode
4824 * @param htim TIM handle
4825 * @retval None
4826 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)4827 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
4828 {
4829 /* Prevent unused argument(s) compilation warning */
4830 UNUSED(htim);
4831
4832 /* NOTE : This function should not be modified, when the callback is needed,
4833 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
4834 */
4835 }
4836
4837 /**
4838 * @brief Output Compare callback in non-blocking mode
4839 * @param htim TIM OC handle
4840 * @retval None
4841 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)4842 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4843 {
4844 /* Prevent unused argument(s) compilation warning */
4845 UNUSED(htim);
4846
4847 /* NOTE : This function should not be modified, when the callback is needed,
4848 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4849 */
4850 }
4851
4852 /**
4853 * @brief Input Capture callback in non-blocking mode
4854 * @param htim TIM IC handle
4855 * @retval None
4856 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)4857 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4858 {
4859 /* Prevent unused argument(s) compilation warning */
4860 UNUSED(htim);
4861
4862 /* NOTE : This function should not be modified, when the callback is needed,
4863 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
4864 */
4865 }
4866
4867 /**
4868 * @brief Input Capture half complete callback in non-blocking mode
4869 * @param htim TIM IC handle
4870 * @retval None
4871 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)4872 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
4873 {
4874 /* Prevent unused argument(s) compilation warning */
4875 UNUSED(htim);
4876
4877 /* NOTE : This function should not be modified, when the callback is needed,
4878 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
4879 */
4880 }
4881
4882 /**
4883 * @brief PWM Pulse finished callback in non-blocking mode
4884 * @param htim TIM handle
4885 * @retval None
4886 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)4887 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4888 {
4889 /* Prevent unused argument(s) compilation warning */
4890 UNUSED(htim);
4891
4892 /* NOTE : This function should not be modified, when the callback is needed,
4893 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4894 */
4895 }
4896
4897 /**
4898 * @brief PWM Pulse finished half complete callback in non-blocking mode
4899 * @param htim TIM handle
4900 * @retval None
4901 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)4902 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
4903 {
4904 /* Prevent unused argument(s) compilation warning */
4905 UNUSED(htim);
4906
4907 /* NOTE : This function should not be modified, when the callback is needed,
4908 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
4909 */
4910 }
4911
4912 /**
4913 * @brief Hall Trigger detection callback in non-blocking mode
4914 * @param htim TIM handle
4915 * @retval None
4916 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)4917 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4918 {
4919 /* Prevent unused argument(s) compilation warning */
4920 UNUSED(htim);
4921
4922 /* NOTE : This function should not be modified, when the callback is needed,
4923 the HAL_TIM_TriggerCallback could be implemented in the user file
4924 */
4925 }
4926
4927 /**
4928 * @brief Hall Trigger detection half complete callback in non-blocking mode
4929 * @param htim TIM handle
4930 * @retval None
4931 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)4932 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
4933 {
4934 /* Prevent unused argument(s) compilation warning */
4935 UNUSED(htim);
4936
4937 /* NOTE : This function should not be modified, when the callback is needed,
4938 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
4939 */
4940 }
4941
4942 /**
4943 * @brief Timer error callback in non-blocking mode
4944 * @param htim TIM handle
4945 * @retval None
4946 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)4947 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4948 {
4949 /* Prevent unused argument(s) compilation warning */
4950 UNUSED(htim);
4951
4952 /* NOTE : This function should not be modified, when the callback is needed,
4953 the HAL_TIM_ErrorCallback could be implemented in the user file
4954 */
4955 }
4956
4957 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4958 /**
4959 * @brief Register a User TIM callback to be used instead of the weak predefined callback
4960 * @param htim tim handle
4961 * @param CallbackID ID of the callback to be registered
4962 * This parameter can be one of the following values:
4963 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
4964 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
4965 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
4966 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
4967 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
4968 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
4969 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
4970 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
4971 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
4972 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
4973 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
4974 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
4975 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
4976 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
4977 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
4978 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
4979 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
4980 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
4981 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
4982 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
4983 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
4984 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
4985 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
4986 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
4987 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
4988 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
4989 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
4990 * @param pCallback pointer to the callback function
4991 * @retval status
4992 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)4993 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
4994 {
4995 HAL_StatusTypeDef status = HAL_OK;
4996
4997 if (pCallback == NULL)
4998 {
4999 return HAL_ERROR;
5000 }
5001 /* Process locked */
5002 __HAL_LOCK(htim);
5003
5004 if (htim->State == HAL_TIM_STATE_READY)
5005 {
5006 switch (CallbackID)
5007 {
5008 case HAL_TIM_BASE_MSPINIT_CB_ID :
5009 htim->Base_MspInitCallback = pCallback;
5010 break;
5011
5012 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5013 htim->Base_MspDeInitCallback = pCallback;
5014 break;
5015
5016 case HAL_TIM_IC_MSPINIT_CB_ID :
5017 htim->IC_MspInitCallback = pCallback;
5018 break;
5019
5020 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5021 htim->IC_MspDeInitCallback = pCallback;
5022 break;
5023
5024 case HAL_TIM_OC_MSPINIT_CB_ID :
5025 htim->OC_MspInitCallback = pCallback;
5026 break;
5027
5028 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5029 htim->OC_MspDeInitCallback = pCallback;
5030 break;
5031
5032 case HAL_TIM_PWM_MSPINIT_CB_ID :
5033 htim->PWM_MspInitCallback = pCallback;
5034 break;
5035
5036 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5037 htim->PWM_MspDeInitCallback = pCallback;
5038 break;
5039
5040 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5041 htim->OnePulse_MspInitCallback = pCallback;
5042 break;
5043
5044 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5045 htim->OnePulse_MspDeInitCallback = pCallback;
5046 break;
5047
5048 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5049 htim->Encoder_MspInitCallback = pCallback;
5050 break;
5051
5052 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5053 htim->Encoder_MspDeInitCallback = pCallback;
5054 break;
5055
5056 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5057 htim->HallSensor_MspInitCallback = pCallback;
5058 break;
5059
5060 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5061 htim->HallSensor_MspDeInitCallback = pCallback;
5062 break;
5063
5064 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5065 htim->PeriodElapsedCallback = pCallback;
5066 break;
5067
5068 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5069 htim->PeriodElapsedHalfCpltCallback = pCallback;
5070 break;
5071
5072 case HAL_TIM_TRIGGER_CB_ID :
5073 htim->TriggerCallback = pCallback;
5074 break;
5075
5076 case HAL_TIM_TRIGGER_HALF_CB_ID :
5077 htim->TriggerHalfCpltCallback = pCallback;
5078 break;
5079
5080 case HAL_TIM_IC_CAPTURE_CB_ID :
5081 htim->IC_CaptureCallback = pCallback;
5082 break;
5083
5084 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5085 htim->IC_CaptureHalfCpltCallback = pCallback;
5086 break;
5087
5088 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5089 htim->OC_DelayElapsedCallback = pCallback;
5090 break;
5091
5092 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5093 htim->PWM_PulseFinishedCallback = pCallback;
5094 break;
5095
5096 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5097 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5098 break;
5099
5100 case HAL_TIM_ERROR_CB_ID :
5101 htim->ErrorCallback = pCallback;
5102 break;
5103
5104 case HAL_TIM_COMMUTATION_CB_ID :
5105 htim->CommutationCallback = pCallback;
5106 break;
5107
5108 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5109 htim->CommutationHalfCpltCallback = pCallback;
5110 break;
5111
5112 case HAL_TIM_BREAK_CB_ID :
5113 htim->BreakCallback = pCallback;
5114 break;
5115
5116 default :
5117 /* Return error status */
5118 status = HAL_ERROR;
5119 break;
5120 }
5121 }
5122 else if (htim->State == HAL_TIM_STATE_RESET)
5123 {
5124 switch (CallbackID)
5125 {
5126 case HAL_TIM_BASE_MSPINIT_CB_ID :
5127 htim->Base_MspInitCallback = pCallback;
5128 break;
5129
5130 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5131 htim->Base_MspDeInitCallback = pCallback;
5132 break;
5133
5134 case HAL_TIM_IC_MSPINIT_CB_ID :
5135 htim->IC_MspInitCallback = pCallback;
5136 break;
5137
5138 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5139 htim->IC_MspDeInitCallback = pCallback;
5140 break;
5141
5142 case HAL_TIM_OC_MSPINIT_CB_ID :
5143 htim->OC_MspInitCallback = pCallback;
5144 break;
5145
5146 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5147 htim->OC_MspDeInitCallback = pCallback;
5148 break;
5149
5150 case HAL_TIM_PWM_MSPINIT_CB_ID :
5151 htim->PWM_MspInitCallback = pCallback;
5152 break;
5153
5154 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5155 htim->PWM_MspDeInitCallback = pCallback;
5156 break;
5157
5158 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5159 htim->OnePulse_MspInitCallback = pCallback;
5160 break;
5161
5162 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5163 htim->OnePulse_MspDeInitCallback = pCallback;
5164 break;
5165
5166 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5167 htim->Encoder_MspInitCallback = pCallback;
5168 break;
5169
5170 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5171 htim->Encoder_MspDeInitCallback = pCallback;
5172 break;
5173
5174 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5175 htim->HallSensor_MspInitCallback = pCallback;
5176 break;
5177
5178 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5179 htim->HallSensor_MspDeInitCallback = pCallback;
5180 break;
5181
5182 default :
5183 /* Return error status */
5184 status = HAL_ERROR;
5185 break;
5186 }
5187 }
5188 else
5189 {
5190 /* Return error status */
5191 status = HAL_ERROR;
5192 }
5193
5194 /* Release Lock */
5195 __HAL_UNLOCK(htim);
5196
5197 return status;
5198 }
5199
5200 /**
5201 * @brief Unregister a TIM callback
5202 * TIM callback is redirected to the weak predefined callback
5203 * @param htim tim handle
5204 * @param CallbackID ID of the callback to be unregistered
5205 * This parameter can be one of the following values:
5206 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5207 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5208 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5209 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5210 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5211 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5212 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5213 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5214 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5215 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5216 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5217 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5218 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5219 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5220 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5221 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5222 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5223 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5224 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5225 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5226 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5227 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5228 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5229 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5230 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5231 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5232 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5233 * @retval status
5234 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5235 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5236 {
5237 HAL_StatusTypeDef status = HAL_OK;
5238
5239 /* Process locked */
5240 __HAL_LOCK(htim);
5241
5242 if (htim->State == HAL_TIM_STATE_READY)
5243 {
5244 switch (CallbackID)
5245 {
5246 case HAL_TIM_BASE_MSPINIT_CB_ID :
5247 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5248 break;
5249
5250 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5251 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5252 break;
5253
5254 case HAL_TIM_IC_MSPINIT_CB_ID :
5255 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5256 break;
5257
5258 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5259 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5260 break;
5261
5262 case HAL_TIM_OC_MSPINIT_CB_ID :
5263 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5264 break;
5265
5266 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5267 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5268 break;
5269
5270 case HAL_TIM_PWM_MSPINIT_CB_ID :
5271 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5272 break;
5273
5274 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5275 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5276 break;
5277
5278 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5279 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5280 break;
5281
5282 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5283 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5284 break;
5285
5286 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5287 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5288 break;
5289
5290 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5291 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5292 break;
5293
5294 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5295 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5296 break;
5297
5298 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5299 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5300 break;
5301
5302 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5303 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
5304 break;
5305
5306 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5307 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
5308 break;
5309
5310 case HAL_TIM_TRIGGER_CB_ID :
5311 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
5312 break;
5313
5314 case HAL_TIM_TRIGGER_HALF_CB_ID :
5315 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
5316 break;
5317
5318 case HAL_TIM_IC_CAPTURE_CB_ID :
5319 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
5320 break;
5321
5322 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5323 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
5324 break;
5325
5326 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5327 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
5328 break;
5329
5330 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5331 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
5332 break;
5333
5334 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5335 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
5336 break;
5337
5338 case HAL_TIM_ERROR_CB_ID :
5339 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
5340 break;
5341
5342 case HAL_TIM_COMMUTATION_CB_ID :
5343 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
5344 break;
5345
5346 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5347 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
5348 break;
5349
5350 case HAL_TIM_BREAK_CB_ID :
5351 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
5352 break;
5353
5354 default :
5355 /* Return error status */
5356 status = HAL_ERROR;
5357 break;
5358 }
5359 }
5360 else if (htim->State == HAL_TIM_STATE_RESET)
5361 {
5362 switch (CallbackID)
5363 {
5364 case HAL_TIM_BASE_MSPINIT_CB_ID :
5365 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5366 break;
5367
5368 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5369 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5370 break;
5371
5372 case HAL_TIM_IC_MSPINIT_CB_ID :
5373 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5374 break;
5375
5376 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5377 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5378 break;
5379
5380 case HAL_TIM_OC_MSPINIT_CB_ID :
5381 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5382 break;
5383
5384 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5385 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5386 break;
5387
5388 case HAL_TIM_PWM_MSPINIT_CB_ID :
5389 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5390 break;
5391
5392 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5393 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5394 break;
5395
5396 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5397 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5398 break;
5399
5400 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5401 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5402 break;
5403
5404 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5405 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5406 break;
5407
5408 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5409 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5410 break;
5411
5412 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5413 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5414 break;
5415
5416 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5417 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5418 break;
5419
5420 default :
5421 /* Return error status */
5422 status = HAL_ERROR;
5423 break;
5424 }
5425 }
5426 else
5427 {
5428 /* Return error status */
5429 status = HAL_ERROR;
5430 }
5431
5432 /* Release Lock */
5433 __HAL_UNLOCK(htim);
5434
5435 return status;
5436 }
5437 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5438
5439 /**
5440 * @}
5441 */
5442
5443 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
5444 * @brief TIM Peripheral State functions
5445 *
5446 @verbatim
5447 ==============================================================================
5448 ##### Peripheral State functions #####
5449 ==============================================================================
5450 [..]
5451 This subsection permits to get in run-time the status of the peripheral
5452 and the data flow.
5453
5454 @endverbatim
5455 * @{
5456 */
5457
5458 /**
5459 * @brief Return the TIM Base handle state.
5460 * @param htim TIM Base handle
5461 * @retval HAL state
5462 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)5463 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
5464 {
5465 return htim->State;
5466 }
5467
5468 /**
5469 * @brief Return the TIM OC handle state.
5470 * @param htim TIM Output Compare handle
5471 * @retval HAL state
5472 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)5473 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
5474 {
5475 return htim->State;
5476 }
5477
5478 /**
5479 * @brief Return the TIM PWM handle state.
5480 * @param htim TIM handle
5481 * @retval HAL state
5482 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)5483 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
5484 {
5485 return htim->State;
5486 }
5487
5488 /**
5489 * @brief Return the TIM Input Capture handle state.
5490 * @param htim TIM IC handle
5491 * @retval HAL state
5492 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)5493 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
5494 {
5495 return htim->State;
5496 }
5497
5498 /**
5499 * @brief Return the TIM One Pulse Mode handle state.
5500 * @param htim TIM OPM handle
5501 * @retval HAL state
5502 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)5503 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
5504 {
5505 return htim->State;
5506 }
5507
5508 /**
5509 * @brief Return the TIM Encoder Mode handle state.
5510 * @param htim TIM Encoder Interface handle
5511 * @retval HAL state
5512 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)5513 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
5514 {
5515 return htim->State;
5516 }
5517
5518 /**
5519 * @}
5520 */
5521
5522 /**
5523 * @}
5524 */
5525
5526 /** @defgroup TIM_Private_Functions TIM Private Functions
5527 * @{
5528 */
5529
5530 /**
5531 * @brief TIM DMA error callback
5532 * @param hdma pointer to DMA handle.
5533 * @retval None
5534 */
TIM_DMAError(DMA_HandleTypeDef * hdma)5535 void TIM_DMAError(DMA_HandleTypeDef *hdma)
5536 {
5537 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5538
5539 htim->State = HAL_TIM_STATE_READY;
5540
5541 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5542 htim->ErrorCallback(htim);
5543 #else
5544 HAL_TIM_ErrorCallback(htim);
5545 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5546 }
5547
5548 /**
5549 * @brief TIM DMA Delay Pulse complete callback.
5550 * @param hdma pointer to DMA handle.
5551 * @retval None
5552 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)5553 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
5554 {
5555 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5556
5557 htim->State = HAL_TIM_STATE_READY;
5558
5559 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5560 {
5561 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5562 }
5563 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5564 {
5565 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5566 }
5567 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5568 {
5569 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5570 }
5571 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5572 {
5573 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5574 }
5575 else
5576 {
5577 /* nothing to do */
5578 }
5579
5580 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5581 htim->PWM_PulseFinishedCallback(htim);
5582 #else
5583 HAL_TIM_PWM_PulseFinishedCallback(htim);
5584 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5585
5586 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5587 }
5588
5589 /**
5590 * @brief TIM DMA Delay Pulse half complete callback.
5591 * @param hdma pointer to DMA handle.
5592 * @retval None
5593 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)5594 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
5595 {
5596 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5597
5598 htim->State = HAL_TIM_STATE_READY;
5599
5600 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5601 {
5602 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5603 }
5604 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5605 {
5606 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5607 }
5608 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5609 {
5610 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5611 }
5612 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5613 {
5614 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5615 }
5616 else
5617 {
5618 /* nothing to do */
5619 }
5620
5621 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5622 htim->PWM_PulseFinishedHalfCpltCallback(htim);
5623 #else
5624 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
5625 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5626
5627 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5628 }
5629
5630 /**
5631 * @brief TIM DMA Capture complete callback.
5632 * @param hdma pointer to DMA handle.
5633 * @retval None
5634 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)5635 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
5636 {
5637 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5638
5639 htim->State = HAL_TIM_STATE_READY;
5640
5641 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5642 {
5643 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5644 }
5645 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5646 {
5647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5648 }
5649 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5650 {
5651 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5652 }
5653 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5654 {
5655 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5656 }
5657 else
5658 {
5659 /* nothing to do */
5660 }
5661
5662 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5663 htim->IC_CaptureCallback(htim);
5664 #else
5665 HAL_TIM_IC_CaptureCallback(htim);
5666 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5667
5668 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5669 }
5670
5671 /**
5672 * @brief TIM DMA Capture half complete callback.
5673 * @param hdma pointer to DMA handle.
5674 * @retval None
5675 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)5676 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
5677 {
5678 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5679
5680 htim->State = HAL_TIM_STATE_READY;
5681
5682 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5683 {
5684 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5685 }
5686 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5687 {
5688 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5689 }
5690 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5691 {
5692 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5693 }
5694 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5695 {
5696 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5697 }
5698 else
5699 {
5700 /* nothing to do */
5701 }
5702
5703 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5704 htim->IC_CaptureHalfCpltCallback(htim);
5705 #else
5706 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
5707 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5708
5709 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5710 }
5711
5712 /**
5713 * @brief TIM DMA Period Elapse complete callback.
5714 * @param hdma pointer to DMA handle.
5715 * @retval None
5716 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)5717 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
5718 {
5719 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5720
5721 htim->State = HAL_TIM_STATE_READY;
5722
5723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5724 htim->PeriodElapsedCallback(htim);
5725 #else
5726 HAL_TIM_PeriodElapsedCallback(htim);
5727 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5728 }
5729
5730 /**
5731 * @brief TIM DMA Period Elapse half complete callback.
5732 * @param hdma pointer to DMA handle.
5733 * @retval None
5734 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)5735 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
5736 {
5737 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5738
5739 htim->State = HAL_TIM_STATE_READY;
5740
5741 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5742 htim->PeriodElapsedHalfCpltCallback(htim);
5743 #else
5744 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
5745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5746 }
5747
5748 /**
5749 * @brief TIM DMA Trigger callback.
5750 * @param hdma pointer to DMA handle.
5751 * @retval None
5752 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)5753 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
5754 {
5755 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5756
5757 htim->State = HAL_TIM_STATE_READY;
5758
5759 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5760 htim->TriggerCallback(htim);
5761 #else
5762 HAL_TIM_TriggerCallback(htim);
5763 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5764 }
5765
5766 /**
5767 * @brief TIM DMA Trigger half complete callback.
5768 * @param hdma pointer to DMA handle.
5769 * @retval None
5770 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)5771 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
5772 {
5773 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5774
5775 htim->State = HAL_TIM_STATE_READY;
5776
5777 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5778 htim->TriggerHalfCpltCallback(htim);
5779 #else
5780 HAL_TIM_TriggerHalfCpltCallback(htim);
5781 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5782 }
5783
5784 /**
5785 * @brief Time Base configuration
5786 * @param TIMx TIM peripheral
5787 * @param Structure TIM Base configuration structure
5788 * @retval None
5789 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)5790 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
5791 {
5792 uint32_t tmpcr1;
5793 tmpcr1 = TIMx->CR1;
5794
5795 /* Set TIM Time Base Unit parameters ---------------------------------------*/
5796 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
5797 {
5798 /* Select the Counter Mode */
5799 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
5800 tmpcr1 |= Structure->CounterMode;
5801 }
5802
5803 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
5804 {
5805 /* Set the clock division */
5806 tmpcr1 &= ~TIM_CR1_CKD;
5807 tmpcr1 |= (uint32_t)Structure->ClockDivision;
5808 }
5809
5810 /* Set the auto-reload preload */
5811 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
5812
5813 TIMx->CR1 = tmpcr1;
5814
5815 /* Set the Autoreload value */
5816 TIMx->ARR = (uint32_t)Structure->Period ;
5817
5818 /* Set the Prescaler value */
5819 TIMx->PSC = Structure->Prescaler;
5820
5821 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
5822 {
5823 /* Set the Repetition Counter value */
5824 TIMx->RCR = Structure->RepetitionCounter;
5825 }
5826
5827 /* Generate an update event to reload the Prescaler
5828 and the repetition counter (only for advanced timer) value immediately */
5829 TIMx->EGR = TIM_EGR_UG;
5830 }
5831
5832 /**
5833 * @brief Timer Output Compare 1 configuration
5834 * @param TIMx to select the TIM peripheral
5835 * @param OC_Config The ouput configuration structure
5836 * @retval None
5837 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5838 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5839 {
5840 uint32_t tmpccmrx;
5841 uint32_t tmpccer;
5842 uint32_t tmpcr2;
5843
5844 /* Disable the Channel 1: Reset the CC1E Bit */
5845 TIMx->CCER &= ~TIM_CCER_CC1E;
5846
5847 /* Get the TIMx CCER register value */
5848 tmpccer = TIMx->CCER;
5849 /* Get the TIMx CR2 register value */
5850 tmpcr2 = TIMx->CR2;
5851
5852 /* Get the TIMx CCMR1 register value */
5853 tmpccmrx = TIMx->CCMR1;
5854
5855 /* Reset the Output Compare Mode Bits */
5856 tmpccmrx &= ~TIM_CCMR1_OC1M;
5857 tmpccmrx &= ~TIM_CCMR1_CC1S;
5858 /* Select the Output Compare Mode */
5859 tmpccmrx |= OC_Config->OCMode;
5860
5861 /* Reset the Output Polarity level */
5862 tmpccer &= ~TIM_CCER_CC1P;
5863 /* Set the Output Compare Polarity */
5864 tmpccer |= OC_Config->OCPolarity;
5865
5866 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
5867 {
5868 /* Check parameters */
5869 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
5870
5871 /* Reset the Output N Polarity level */
5872 tmpccer &= ~TIM_CCER_CC1NP;
5873 /* Set the Output N Polarity */
5874 tmpccer |= OC_Config->OCNPolarity;
5875 /* Reset the Output N State */
5876 tmpccer &= ~TIM_CCER_CC1NE;
5877 }
5878
5879 if (IS_TIM_BREAK_INSTANCE(TIMx))
5880 {
5881 /* Check parameters */
5882 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
5883 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
5884
5885 /* Reset the Output Compare and Output Compare N IDLE State */
5886 tmpcr2 &= ~TIM_CR2_OIS1;
5887 tmpcr2 &= ~TIM_CR2_OIS1N;
5888 /* Set the Output Idle state */
5889 tmpcr2 |= OC_Config->OCIdleState;
5890 /* Set the Output N Idle state */
5891 tmpcr2 |= OC_Config->OCNIdleState;
5892 }
5893
5894 /* Write to TIMx CR2 */
5895 TIMx->CR2 = tmpcr2;
5896
5897 /* Write to TIMx CCMR1 */
5898 TIMx->CCMR1 = tmpccmrx;
5899
5900 /* Set the Capture Compare Register value */
5901 TIMx->CCR1 = OC_Config->Pulse;
5902
5903 /* Write to TIMx CCER */
5904 TIMx->CCER = tmpccer;
5905 }
5906
5907 /**
5908 * @brief Timer Output Compare 2 configuration
5909 * @param TIMx to select the TIM peripheral
5910 * @param OC_Config The ouput configuration structure
5911 * @retval None
5912 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5913 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5914 {
5915 uint32_t tmpccmrx;
5916 uint32_t tmpccer;
5917 uint32_t tmpcr2;
5918
5919 /* Disable the Channel 2: Reset the CC2E Bit */
5920 TIMx->CCER &= ~TIM_CCER_CC2E;
5921
5922 /* Get the TIMx CCER register value */
5923 tmpccer = TIMx->CCER;
5924 /* Get the TIMx CR2 register value */
5925 tmpcr2 = TIMx->CR2;
5926
5927 /* Get the TIMx CCMR1 register value */
5928 tmpccmrx = TIMx->CCMR1;
5929
5930 /* Reset the Output Compare mode and Capture/Compare selection Bits */
5931 tmpccmrx &= ~TIM_CCMR1_OC2M;
5932 tmpccmrx &= ~TIM_CCMR1_CC2S;
5933
5934 /* Select the Output Compare Mode */
5935 tmpccmrx |= (OC_Config->OCMode << 8U);
5936
5937 /* Reset the Output Polarity level */
5938 tmpccer &= ~TIM_CCER_CC2P;
5939 /* Set the Output Compare Polarity */
5940 tmpccer |= (OC_Config->OCPolarity << 4U);
5941
5942 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
5943 {
5944 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
5945
5946 /* Reset the Output N Polarity level */
5947 tmpccer &= ~TIM_CCER_CC2NP;
5948 /* Set the Output N Polarity */
5949 tmpccer |= (OC_Config->OCNPolarity << 4U);
5950 /* Reset the Output N State */
5951 tmpccer &= ~TIM_CCER_CC2NE;
5952
5953 }
5954
5955 if (IS_TIM_BREAK_INSTANCE(TIMx))
5956 {
5957 /* Check parameters */
5958 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
5959 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
5960
5961 /* Reset the Output Compare and Output Compare N IDLE State */
5962 tmpcr2 &= ~TIM_CR2_OIS2;
5963 tmpcr2 &= ~TIM_CR2_OIS2N;
5964 /* Set the Output Idle state */
5965 tmpcr2 |= (OC_Config->OCIdleState << 2U);
5966 /* Set the Output N Idle state */
5967 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
5968 }
5969
5970 /* Write to TIMx CR2 */
5971 TIMx->CR2 = tmpcr2;
5972
5973 /* Write to TIMx CCMR1 */
5974 TIMx->CCMR1 = tmpccmrx;
5975
5976 /* Set the Capture Compare Register value */
5977 TIMx->CCR2 = OC_Config->Pulse;
5978
5979 /* Write to TIMx CCER */
5980 TIMx->CCER = tmpccer;
5981 }
5982
5983 /**
5984 * @brief Timer Output Compare 3 configuration
5985 * @param TIMx to select the TIM peripheral
5986 * @param OC_Config The ouput configuration structure
5987 * @retval None
5988 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5989 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5990 {
5991 uint32_t tmpccmrx;
5992 uint32_t tmpccer;
5993 uint32_t tmpcr2;
5994
5995 /* Disable the Channel 3: Reset the CC2E Bit */
5996 TIMx->CCER &= ~TIM_CCER_CC3E;
5997
5998 /* Get the TIMx CCER register value */
5999 tmpccer = TIMx->CCER;
6000 /* Get the TIMx CR2 register value */
6001 tmpcr2 = TIMx->CR2;
6002
6003 /* Get the TIMx CCMR2 register value */
6004 tmpccmrx = TIMx->CCMR2;
6005
6006 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6007 tmpccmrx &= ~TIM_CCMR2_OC3M;
6008 tmpccmrx &= ~TIM_CCMR2_CC3S;
6009 /* Select the Output Compare Mode */
6010 tmpccmrx |= OC_Config->OCMode;
6011
6012 /* Reset the Output Polarity level */
6013 tmpccer &= ~TIM_CCER_CC3P;
6014 /* Set the Output Compare Polarity */
6015 tmpccer |= (OC_Config->OCPolarity << 8U);
6016
6017 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6018 {
6019 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6020
6021 /* Reset the Output N Polarity level */
6022 tmpccer &= ~TIM_CCER_CC3NP;
6023 /* Set the Output N Polarity */
6024 tmpccer |= (OC_Config->OCNPolarity << 8U);
6025 /* Reset the Output N State */
6026 tmpccer &= ~TIM_CCER_CC3NE;
6027 }
6028
6029 if (IS_TIM_BREAK_INSTANCE(TIMx))
6030 {
6031 /* Check parameters */
6032 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6033 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6034
6035 /* Reset the Output Compare and Output Compare N IDLE State */
6036 tmpcr2 &= ~TIM_CR2_OIS3;
6037 tmpcr2 &= ~TIM_CR2_OIS3N;
6038 /* Set the Output Idle state */
6039 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6040 /* Set the Output N Idle state */
6041 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6042 }
6043
6044 /* Write to TIMx CR2 */
6045 TIMx->CR2 = tmpcr2;
6046
6047 /* Write to TIMx CCMR2 */
6048 TIMx->CCMR2 = tmpccmrx;
6049
6050 /* Set the Capture Compare Register value */
6051 TIMx->CCR3 = OC_Config->Pulse;
6052
6053 /* Write to TIMx CCER */
6054 TIMx->CCER = tmpccer;
6055 }
6056
6057 /**
6058 * @brief Timer Output Compare 4 configuration
6059 * @param TIMx to select the TIM peripheral
6060 * @param OC_Config The ouput configuration structure
6061 * @retval None
6062 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6063 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6064 {
6065 uint32_t tmpccmrx;
6066 uint32_t tmpccer;
6067 uint32_t tmpcr2;
6068
6069 /* Disable the Channel 4: Reset the CC4E Bit */
6070 TIMx->CCER &= ~TIM_CCER_CC4E;
6071
6072 /* Get the TIMx CCER register value */
6073 tmpccer = TIMx->CCER;
6074 /* Get the TIMx CR2 register value */
6075 tmpcr2 = TIMx->CR2;
6076
6077 /* Get the TIMx CCMR2 register value */
6078 tmpccmrx = TIMx->CCMR2;
6079
6080 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6081 tmpccmrx &= ~TIM_CCMR2_OC4M;
6082 tmpccmrx &= ~TIM_CCMR2_CC4S;
6083
6084 /* Select the Output Compare Mode */
6085 tmpccmrx |= (OC_Config->OCMode << 8U);
6086
6087 /* Reset the Output Polarity level */
6088 tmpccer &= ~TIM_CCER_CC4P;
6089 /* Set the Output Compare Polarity */
6090 tmpccer |= (OC_Config->OCPolarity << 12U);
6091
6092 if (IS_TIM_BREAK_INSTANCE(TIMx))
6093 {
6094 /* Check parameters */
6095 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6096
6097 /* Reset the Output Compare IDLE State */
6098 tmpcr2 &= ~TIM_CR2_OIS4;
6099
6100 /* Set the Output Idle state */
6101 tmpcr2 |= (OC_Config->OCIdleState << 6U);
6102 }
6103
6104 /* Write to TIMx CR2 */
6105 TIMx->CR2 = tmpcr2;
6106
6107 /* Write to TIMx CCMR2 */
6108 TIMx->CCMR2 = tmpccmrx;
6109
6110 /* Set the Capture Compare Register value */
6111 TIMx->CCR4 = OC_Config->Pulse;
6112
6113 /* Write to TIMx CCER */
6114 TIMx->CCER = tmpccer;
6115 }
6116
6117 /**
6118 * @brief Slave Timer configuration function
6119 * @param htim TIM handle
6120 * @param sSlaveConfig Slave timer configuration
6121 * @retval None
6122 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)6123 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6124 TIM_SlaveConfigTypeDef *sSlaveConfig)
6125 {
6126 uint32_t tmpsmcr;
6127 uint32_t tmpccmr1;
6128 uint32_t tmpccer;
6129
6130 /* Get the TIMx SMCR register value */
6131 tmpsmcr = htim->Instance->SMCR;
6132
6133 /* Reset the Trigger Selection Bits */
6134 tmpsmcr &= ~TIM_SMCR_TS;
6135 /* Set the Input Trigger source */
6136 tmpsmcr |= sSlaveConfig->InputTrigger;
6137
6138 /* Reset the slave mode Bits */
6139 tmpsmcr &= ~TIM_SMCR_SMS;
6140 /* Set the slave mode */
6141 tmpsmcr |= sSlaveConfig->SlaveMode;
6142
6143 /* Write to TIMx SMCR */
6144 htim->Instance->SMCR = tmpsmcr;
6145
6146 /* Configure the trigger prescaler, filter, and polarity */
6147 switch (sSlaveConfig->InputTrigger)
6148 {
6149 case TIM_TS_ETRF:
6150 {
6151 /* Check the parameters */
6152 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6153 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6154 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6155 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6156 /* Configure the ETR Trigger source */
6157 TIM_ETR_SetConfig(htim->Instance,
6158 sSlaveConfig->TriggerPrescaler,
6159 sSlaveConfig->TriggerPolarity,
6160 sSlaveConfig->TriggerFilter);
6161 break;
6162 }
6163
6164 case TIM_TS_TI1F_ED:
6165 {
6166 /* Check the parameters */
6167 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6168 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6169
6170 if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6171 {
6172 return HAL_ERROR;
6173 }
6174
6175 /* Disable the Channel 1: Reset the CC1E Bit */
6176 tmpccer = htim->Instance->CCER;
6177 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6178 tmpccmr1 = htim->Instance->CCMR1;
6179
6180 /* Set the filter */
6181 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6182 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6183
6184 /* Write to TIMx CCMR1 and CCER registers */
6185 htim->Instance->CCMR1 = tmpccmr1;
6186 htim->Instance->CCER = tmpccer;
6187 break;
6188 }
6189
6190 case TIM_TS_TI1FP1:
6191 {
6192 /* Check the parameters */
6193 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6194 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6195 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6196
6197 /* Configure TI1 Filter and Polarity */
6198 TIM_TI1_ConfigInputStage(htim->Instance,
6199 sSlaveConfig->TriggerPolarity,
6200 sSlaveConfig->TriggerFilter);
6201 break;
6202 }
6203
6204 case TIM_TS_TI2FP2:
6205 {
6206 /* Check the parameters */
6207 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6208 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6209 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6210
6211 /* Configure TI2 Filter and Polarity */
6212 TIM_TI2_ConfigInputStage(htim->Instance,
6213 sSlaveConfig->TriggerPolarity,
6214 sSlaveConfig->TriggerFilter);
6215 break;
6216 }
6217
6218 case TIM_TS_ITR0:
6219 case TIM_TS_ITR1:
6220 case TIM_TS_ITR2:
6221 case TIM_TS_ITR3:
6222 {
6223 /* Check the parameter */
6224 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6225 break;
6226 }
6227
6228 default:
6229 break;
6230 }
6231 return HAL_OK;
6232 }
6233
6234 /**
6235 * @brief Configure the TI1 as Input.
6236 * @param TIMx to select the TIM peripheral.
6237 * @param TIM_ICPolarity The Input Polarity.
6238 * This parameter can be one of the following values:
6239 * @arg TIM_ICPOLARITY_RISING
6240 * @arg TIM_ICPOLARITY_FALLING
6241 * @arg TIM_ICPOLARITY_BOTHEDGE
6242 * @param TIM_ICSelection specifies the input to be used.
6243 * This parameter can be one of the following values:
6244 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6245 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6246 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6247 * @param TIM_ICFilter Specifies the Input Capture Filter.
6248 * This parameter must be a value between 0x00 and 0x0F.
6249 * @retval None
6250 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6251 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6252 * protected against un-initialized filter and polarity values.
6253 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6254 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6255 uint32_t TIM_ICFilter)
6256 {
6257 uint32_t tmpccmr1;
6258 uint32_t tmpccer;
6259
6260 /* Disable the Channel 1: Reset the CC1E Bit */
6261 TIMx->CCER &= ~TIM_CCER_CC1E;
6262 tmpccmr1 = TIMx->CCMR1;
6263 tmpccer = TIMx->CCER;
6264
6265 /* Select the Input */
6266 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6267 {
6268 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6269 tmpccmr1 |= TIM_ICSelection;
6270 }
6271 else
6272 {
6273 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6274 }
6275
6276 /* Set the filter */
6277 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6278 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6279
6280 /* Select the Polarity and set the CC1E Bit */
6281 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6282 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6283
6284 /* Write to TIMx CCMR1 and CCER registers */
6285 TIMx->CCMR1 = tmpccmr1;
6286 TIMx->CCER = tmpccer;
6287 }
6288
6289 /**
6290 * @brief Configure the Polarity and Filter for TI1.
6291 * @param TIMx to select the TIM peripheral.
6292 * @param TIM_ICPolarity The Input Polarity.
6293 * This parameter can be one of the following values:
6294 * @arg TIM_ICPOLARITY_RISING
6295 * @arg TIM_ICPOLARITY_FALLING
6296 * @arg TIM_ICPOLARITY_BOTHEDGE
6297 * @param TIM_ICFilter Specifies the Input Capture Filter.
6298 * This parameter must be a value between 0x00 and 0x0F.
6299 * @retval None
6300 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6301 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6302 {
6303 uint32_t tmpccmr1;
6304 uint32_t tmpccer;
6305
6306 /* Disable the Channel 1: Reset the CC1E Bit */
6307 tmpccer = TIMx->CCER;
6308 TIMx->CCER &= ~TIM_CCER_CC1E;
6309 tmpccmr1 = TIMx->CCMR1;
6310
6311 /* Set the filter */
6312 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6313 tmpccmr1 |= (TIM_ICFilter << 4U);
6314
6315 /* Select the Polarity and set the CC1E Bit */
6316 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6317 tmpccer |= TIM_ICPolarity;
6318
6319 /* Write to TIMx CCMR1 and CCER registers */
6320 TIMx->CCMR1 = tmpccmr1;
6321 TIMx->CCER = tmpccer;
6322 }
6323
6324 /**
6325 * @brief Configure the TI2 as Input.
6326 * @param TIMx to select the TIM peripheral
6327 * @param TIM_ICPolarity The Input Polarity.
6328 * This parameter can be one of the following values:
6329 * @arg TIM_ICPOLARITY_RISING
6330 * @arg TIM_ICPOLARITY_FALLING
6331 * @arg TIM_ICPOLARITY_BOTHEDGE
6332 * @param TIM_ICSelection specifies the input to be used.
6333 * This parameter can be one of the following values:
6334 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6335 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6336 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6337 * @param TIM_ICFilter Specifies the Input Capture Filter.
6338 * This parameter must be a value between 0x00 and 0x0F.
6339 * @retval None
6340 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6341 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6342 * protected against un-initialized filter and polarity values.
6343 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6344 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6345 uint32_t TIM_ICFilter)
6346 {
6347 uint32_t tmpccmr1;
6348 uint32_t tmpccer;
6349
6350 /* Disable the Channel 2: Reset the CC2E Bit */
6351 TIMx->CCER &= ~TIM_CCER_CC2E;
6352 tmpccmr1 = TIMx->CCMR1;
6353 tmpccer = TIMx->CCER;
6354
6355 /* Select the Input */
6356 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6357 tmpccmr1 |= (TIM_ICSelection << 8U);
6358
6359 /* Set the filter */
6360 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6361 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6362
6363 /* Select the Polarity and set the CC2E Bit */
6364 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6365 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6366
6367 /* Write to TIMx CCMR1 and CCER registers */
6368 TIMx->CCMR1 = tmpccmr1 ;
6369 TIMx->CCER = tmpccer;
6370 }
6371
6372 /**
6373 * @brief Configure the Polarity and Filter for TI2.
6374 * @param TIMx to select the TIM peripheral.
6375 * @param TIM_ICPolarity The Input Polarity.
6376 * This parameter can be one of the following values:
6377 * @arg TIM_ICPOLARITY_RISING
6378 * @arg TIM_ICPOLARITY_FALLING
6379 * @arg TIM_ICPOLARITY_BOTHEDGE
6380 * @param TIM_ICFilter Specifies the Input Capture Filter.
6381 * This parameter must be a value between 0x00 and 0x0F.
6382 * @retval None
6383 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6384 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6385 {
6386 uint32_t tmpccmr1;
6387 uint32_t tmpccer;
6388
6389 /* Disable the Channel 2: Reset the CC2E Bit */
6390 TIMx->CCER &= ~TIM_CCER_CC2E;
6391 tmpccmr1 = TIMx->CCMR1;
6392 tmpccer = TIMx->CCER;
6393
6394 /* Set the filter */
6395 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6396 tmpccmr1 |= (TIM_ICFilter << 12U);
6397
6398 /* Select the Polarity and set the CC2E Bit */
6399 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6400 tmpccer |= (TIM_ICPolarity << 4U);
6401
6402 /* Write to TIMx CCMR1 and CCER registers */
6403 TIMx->CCMR1 = tmpccmr1 ;
6404 TIMx->CCER = tmpccer;
6405 }
6406
6407 /**
6408 * @brief Configure the TI3 as Input.
6409 * @param TIMx to select the TIM peripheral
6410 * @param TIM_ICPolarity The Input Polarity.
6411 * This parameter can be one of the following values:
6412 * @arg TIM_ICPOLARITY_RISING
6413 * @arg TIM_ICPOLARITY_FALLING
6414 * @arg TIM_ICPOLARITY_BOTHEDGE
6415 * @param TIM_ICSelection specifies the input to be used.
6416 * This parameter can be one of the following values:
6417 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6418 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6419 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6420 * @param TIM_ICFilter Specifies the Input Capture Filter.
6421 * This parameter must be a value between 0x00 and 0x0F.
6422 * @retval None
6423 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6424 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6425 * protected against un-initialized filter and polarity values.
6426 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6427 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6428 uint32_t TIM_ICFilter)
6429 {
6430 uint32_t tmpccmr2;
6431 uint32_t tmpccer;
6432
6433 /* Disable the Channel 3: Reset the CC3E Bit */
6434 TIMx->CCER &= ~TIM_CCER_CC3E;
6435 tmpccmr2 = TIMx->CCMR2;
6436 tmpccer = TIMx->CCER;
6437
6438 /* Select the Input */
6439 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6440 tmpccmr2 |= TIM_ICSelection;
6441
6442 /* Set the filter */
6443 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6444 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6445
6446 /* Select the Polarity and set the CC3E Bit */
6447 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6448 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
6449
6450 /* Write to TIMx CCMR2 and CCER registers */
6451 TIMx->CCMR2 = tmpccmr2;
6452 TIMx->CCER = tmpccer;
6453 }
6454
6455 /**
6456 * @brief Configure the TI4 as Input.
6457 * @param TIMx to select the TIM peripheral
6458 * @param TIM_ICPolarity The Input Polarity.
6459 * This parameter can be one of the following values:
6460 * @arg TIM_ICPOLARITY_RISING
6461 * @arg TIM_ICPOLARITY_FALLING
6462 * @arg TIM_ICPOLARITY_BOTHEDGE
6463 * @param TIM_ICSelection specifies the input to be used.
6464 * This parameter can be one of the following values:
6465 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
6466 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
6467 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
6468 * @param TIM_ICFilter Specifies the Input Capture Filter.
6469 * This parameter must be a value between 0x00 and 0x0F.
6470 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
6471 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6472 * protected against un-initialized filter and polarity values.
6473 * @retval None
6474 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6475 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6476 uint32_t TIM_ICFilter)
6477 {
6478 uint32_t tmpccmr2;
6479 uint32_t tmpccer;
6480
6481 /* Disable the Channel 4: Reset the CC4E Bit */
6482 TIMx->CCER &= ~TIM_CCER_CC4E;
6483 tmpccmr2 = TIMx->CCMR2;
6484 tmpccer = TIMx->CCER;
6485
6486 /* Select the Input */
6487 tmpccmr2 &= ~TIM_CCMR2_CC4S;
6488 tmpccmr2 |= (TIM_ICSelection << 8U);
6489
6490 /* Set the filter */
6491 tmpccmr2 &= ~TIM_CCMR2_IC4F;
6492 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
6493
6494 /* Select the Polarity and set the CC4E Bit */
6495 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
6496 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
6497
6498 /* Write to TIMx CCMR2 and CCER registers */
6499 TIMx->CCMR2 = tmpccmr2;
6500 TIMx->CCER = tmpccer ;
6501 }
6502
6503 /**
6504 * @brief Selects the Input Trigger source
6505 * @param TIMx to select the TIM peripheral
6506 * @param InputTriggerSource The Input Trigger source.
6507 * This parameter can be one of the following values:
6508 * @arg TIM_TS_ITR0: Internal Trigger 0
6509 * @arg TIM_TS_ITR1: Internal Trigger 1
6510 * @arg TIM_TS_ITR2: Internal Trigger 2
6511 * @arg TIM_TS_ITR3: Internal Trigger 3
6512 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
6513 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
6514 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
6515 * @arg TIM_TS_ETRF: External Trigger input
6516 * @retval None
6517 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)6518 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
6519 {
6520 uint32_t tmpsmcr;
6521
6522 /* Get the TIMx SMCR register value */
6523 tmpsmcr = TIMx->SMCR;
6524 /* Reset the TS Bits */
6525 tmpsmcr &= ~TIM_SMCR_TS;
6526 /* Set the Input Trigger source and the slave mode*/
6527 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
6528 /* Write to TIMx SMCR */
6529 TIMx->SMCR = tmpsmcr;
6530 }
6531 /**
6532 * @brief Configures the TIMx External Trigger (ETR).
6533 * @param TIMx to select the TIM peripheral
6534 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
6535 * This parameter can be one of the following values:
6536 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
6537 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
6538 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
6539 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
6540 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
6541 * This parameter can be one of the following values:
6542 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
6543 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
6544 * @param ExtTRGFilter External Trigger Filter.
6545 * This parameter must be a value between 0x00 and 0x0F
6546 * @retval None
6547 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)6548 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
6549 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
6550 {
6551 uint32_t tmpsmcr;
6552
6553 tmpsmcr = TIMx->SMCR;
6554
6555 /* Reset the ETR Bits */
6556 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
6557
6558 /* Set the Prescaler, the Filter value and the Polarity */
6559 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
6560
6561 /* Write to TIMx SMCR */
6562 TIMx->SMCR = tmpsmcr;
6563 }
6564
6565 /**
6566 * @brief Enables or disables the TIM Capture Compare Channel x.
6567 * @param TIMx to select the TIM peripheral
6568 * @param Channel specifies the TIM Channel
6569 * This parameter can be one of the following values:
6570 * @arg TIM_CHANNEL_1: TIM Channel 1
6571 * @arg TIM_CHANNEL_2: TIM Channel 2
6572 * @arg TIM_CHANNEL_3: TIM Channel 3
6573 * @arg TIM_CHANNEL_4: TIM Channel 4
6574 * @param ChannelState specifies the TIM Channel CCxE bit new state.
6575 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
6576 * @retval None
6577 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)6578 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
6579 {
6580 uint32_t tmp;
6581
6582 /* Check the parameters */
6583 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
6584 assert_param(IS_TIM_CHANNELS(Channel));
6585
6586 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
6587
6588 /* Reset the CCxE Bit */
6589 TIMx->CCER &= ~tmp;
6590
6591 /* Set or reset the CCxE Bit */
6592 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
6593 }
6594
6595 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6596 /**
6597 * @brief Reset interrupt callbacks to the legacy weak callbacks.
6598 * @param htim pointer to a TIM_HandleTypeDef structure that contains
6599 * the configuration information for TIM module.
6600 * @retval None
6601 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)6602 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
6603 {
6604 /* Reset the TIM callback to the legacy weak callbacks */
6605 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
6606 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
6607 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
6608 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
6609 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
6610 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
6611 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
6612 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
6613 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
6614 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
6615 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
6616 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
6617 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
6618 }
6619 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6620
6621 /**
6622 * @}
6623 */
6624
6625 #endif /* HAL_TIM_MODULE_ENABLED */
6626 /**
6627 * @}
6628 */
6629
6630 /**
6631 * @}
6632 */
6633 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6634