1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (+) TxCpltCallback : SPI Tx Completed callback
69 (+) RxCpltCallback : SPI Rx Completed callback
70 (+) TxRxCpltCallback : SPI TxRx Completed callback
71 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (+) ErrorCallback : SPI Error callback
75 (+) AbortCpltCallback : SPI Abort callback
76 (+) MspInitCallback : SPI Msp Init callback
77 (+) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (+) TxCpltCallback : SPI Tx Completed callback
88 (+) RxCpltCallback : SPI Rx Completed callback
89 (+) TxRxCpltCallback : SPI TxRx Completed callback
90 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (+) ErrorCallback : SPI Error callback
94 (+) AbortCpltCallback : SPI Abort callback
95 (+) MspInitCallback : SPI Msp Init callback
96 (+) MspDeInitCallback : SPI Msp DeInit callback
97
98 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
99 all callbacks are set to the corresponding weak functions:
100 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
101 Exception done for MspInit and MspDeInit functions that are
102 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
103 these callbacks are null (not registered beforehand).
104 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
105 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
106
107 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
108 Exception done MspInit/MspDeInit functions that can be registered/unregistered
109 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
110 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
111 Then, the user first registers the MspInit/MspDeInit user callbacks
112 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
113 or HAL_SPI_Init() function.
114
115 When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
116 not defined, the callback registering feature is not available
117 and weak (surcharged) callbacks are used.
118
119 [..]
120 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
121 the following table resume the max SPI frequency reached with data size 8bits/16bits,
122 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
123
124 @endverbatim
125
126 Additional table :
127
128 DataSize = SPI_DATASIZE_8BIT:
129 +----------------------------------------------------------------------------------------------+
130 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
131 | Process | Tranfert mode |---------------------|----------------------|----------------------|
132 | | | Master | Slave | Master | Slave | Master | Slave |
133 |==============================================================================================|
134 | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
135 | X |----------------|----------|----------|-----------|----------|-----------|----------|
136 | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
137 | R |----------------|----------|----------|-----------|----------|-----------|----------|
138 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
139 |=========|================|==========|==========|===========|==========|===========|==========|
140 | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
141 | |----------------|----------|----------|-----------|----------|-----------|----------|
142 | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
143 | X |----------------|----------|----------|-----------|----------|-----------|----------|
144 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
145 |=========|================|==========|==========|===========|==========|===========|==========|
146 | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
147 | |----------------|----------|----------|-----------|----------|-----------|----------|
148 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
149 | X |----------------|----------|----------|-----------|----------|-----------|----------|
150 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
151 +----------------------------------------------------------------------------------------------+
152
153 DataSize = SPI_DATASIZE_16BIT:
154 +----------------------------------------------------------------------------------------------+
155 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
156 | Process | Tranfert mode |---------------------|----------------------|----------------------|
157 | | | Master | Slave | Master | Slave | Master | Slave |
158 |==============================================================================================|
159 | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
160 | X |----------------|----------|----------|-----------|----------|-----------|----------|
161 | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
162 | R |----------------|----------|----------|-----------|----------|-----------|----------|
163 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
164 |=========|================|==========|==========|===========|==========|===========|==========|
165 | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
166 | |----------------|----------|----------|-----------|----------|-----------|----------|
167 | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
168 | X |----------------|----------|----------|-----------|----------|-----------|----------|
169 | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
170 |=========|================|==========|==========|===========|==========|===========|==========|
171 | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
172 | |----------------|----------|----------|-----------|----------|-----------|----------|
173 | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
174 | X |----------------|----------|----------|-----------|----------|-----------|----------|
175 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
176 +----------------------------------------------------------------------------------------------+
177 @note The max SPI frequency depend on SPI data size (8bits, 16bits),
178 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
179 @note
180 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
181 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
182 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
183
184 ******************************************************************************
185 * @attention
186 *
187 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
188 * All rights reserved.</center></h2>
189 *
190 * This software component is licensed by ST under BSD 3-Clause license,
191 * the "License"; You may not use this file except in compliance with the
192 * License. You may obtain a copy of the License at:
193 * opensource.org/licenses/BSD-3-Clause
194 *
195 ******************************************************************************
196 */
197
198 /* Includes ------------------------------------------------------------------*/
199 #include "stm32f4xx_hal.h"
200
201 /** @addtogroup STM32F4xx_HAL_Driver
202 * @{
203 */
204
205 /** @defgroup SPI SPI
206 * @brief SPI HAL module driver
207 * @{
208 */
209 #ifdef HAL_SPI_MODULE_ENABLED
210
211 /* Private typedef -----------------------------------------------------------*/
212 /* Private defines -----------------------------------------------------------*/
213 /** @defgroup SPI_Private_Constants SPI Private Constants
214 * @{
215 */
216 #define SPI_DEFAULT_TIMEOUT 100U
217 /**
218 * @}
219 */
220
221 /* Private macros ------------------------------------------------------------*/
222 /* Private variables ---------------------------------------------------------*/
223 /* Private function prototypes -----------------------------------------------*/
224 /** @defgroup SPI_Private_Functions SPI Private Functions
225 * @{
226 */
227 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
228 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
236 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
237 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
238 uint32_t Timeout, uint32_t Tickstart);
239 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
240 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
241 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
242 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
247 #if (USE_SPI_CRC != 0U)
248 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
251 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
252 #endif /* USE_SPI_CRC */
253 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
254 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
255 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
256 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
258 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
259 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
260 /**
261 * @}
262 */
263
264 /* Exported functions --------------------------------------------------------*/
265 /** @defgroup SPI_Exported_Functions SPI Exported Functions
266 * @{
267 */
268
269 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
270 * @brief Initialization and Configuration functions
271 *
272 @verbatim
273 ===============================================================================
274 ##### Initialization and de-initialization functions #####
275 ===============================================================================
276 [..] This subsection provides a set of functions allowing to initialize and
277 de-initialize the SPIx peripheral:
278
279 (+) User must implement HAL_SPI_MspInit() function in which he configures
280 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
281
282 (+) Call the function HAL_SPI_Init() to configure the selected device with
283 the selected configuration:
284 (++) Mode
285 (++) Direction
286 (++) Data Size
287 (++) Clock Polarity and Phase
288 (++) NSS Management
289 (++) BaudRate Prescaler
290 (++) FirstBit
291 (++) TIMode
292 (++) CRC Calculation
293 (++) CRC Polynomial if CRC enabled
294
295 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
296 of the selected SPIx peripheral.
297
298 @endverbatim
299 * @{
300 */
301
302 /**
303 * @brief Initialize the SPI according to the specified parameters
304 * in the SPI_InitTypeDef and initialize the associated handle.
305 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
306 * the configuration information for SPI module.
307 * @retval HAL status
308 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)309 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
310 {
311 /* Check the SPI handle allocation */
312 if (hspi == NULL)
313 {
314 return HAL_ERROR;
315 }
316
317 /* Check the parameters */
318 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
319 assert_param(IS_SPI_MODE(hspi->Init.Mode));
320 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
321 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
322 assert_param(IS_SPI_NSS(hspi->Init.NSS));
323 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
324 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
325 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
326 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
327 {
328 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
329 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
330 }
331 #if (USE_SPI_CRC != 0U)
332 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
333 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
334 {
335 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
336 }
337 #else
338 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
339 #endif /* USE_SPI_CRC */
340
341 if (hspi->State == HAL_SPI_STATE_RESET)
342 {
343 /* Allocate lock resource and initialize it */
344 hspi->Lock = HAL_UNLOCKED;
345
346 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
347 /* Init the SPI Callback settings */
348 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
349 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
350 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
351 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
352 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
353 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
354 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
355 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
356
357 if (hspi->MspInitCallback == NULL)
358 {
359 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
360 }
361
362 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
363 hspi->MspInitCallback(hspi);
364 #else
365 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
366 HAL_SPI_MspInit(hspi);
367 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
368 }
369
370 hspi->State = HAL_SPI_STATE_BUSY;
371
372 /* Disable the selected SPI peripheral */
373 __HAL_SPI_DISABLE(hspi);
374
375 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
376 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
377 Communication speed, First bit and CRC calculation state */
378 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
379 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
380 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
381
382 /* Configure : NSS management, TI Mode */
383 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
384
385 #if (USE_SPI_CRC != 0U)
386 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
387 /* Configure : CRC Polynomial */
388 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
389 {
390 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
391 }
392 #endif /* USE_SPI_CRC */
393
394 #if defined(SPI_I2SCFGR_I2SMOD)
395 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
396 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
397 #endif /* SPI_I2SCFGR_I2SMOD */
398
399 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
400 hspi->State = HAL_SPI_STATE_READY;
401
402 return HAL_OK;
403 }
404
405 /**
406 * @brief De-Initialize the SPI peripheral.
407 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
408 * the configuration information for SPI module.
409 * @retval HAL status
410 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)411 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
412 {
413 /* Check the SPI handle allocation */
414 if (hspi == NULL)
415 {
416 return HAL_ERROR;
417 }
418
419 /* Check SPI Instance parameter */
420 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
421
422 hspi->State = HAL_SPI_STATE_BUSY;
423
424 /* Disable the SPI Peripheral Clock */
425 __HAL_SPI_DISABLE(hspi);
426
427 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
428 if (hspi->MspDeInitCallback == NULL)
429 {
430 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
431 }
432
433 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
434 hspi->MspDeInitCallback(hspi);
435 #else
436 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
437 HAL_SPI_MspDeInit(hspi);
438 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
439
440 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
441 hspi->State = HAL_SPI_STATE_RESET;
442
443 /* Release Lock */
444 __HAL_UNLOCK(hspi);
445
446 return HAL_OK;
447 }
448
449 /**
450 * @brief Initialize the SPI MSP.
451 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
452 * the configuration information for SPI module.
453 * @retval None
454 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)455 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
456 {
457 /* Prevent unused argument(s) compilation warning */
458 UNUSED(hspi);
459
460 /* NOTE : This function should not be modified, when the callback is needed,
461 the HAL_SPI_MspInit should be implemented in the user file
462 */
463 }
464
465 /**
466 * @brief De-Initialize the SPI MSP.
467 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
468 * the configuration information for SPI module.
469 * @retval None
470 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)471 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
472 {
473 /* Prevent unused argument(s) compilation warning */
474 UNUSED(hspi);
475
476 /* NOTE : This function should not be modified, when the callback is needed,
477 the HAL_SPI_MspDeInit should be implemented in the user file
478 */
479 }
480
481 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
482 /**
483 * @brief Register a User SPI Callback
484 * To be used instead of the weak predefined callback
485 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
486 * the configuration information for the specified SPI.
487 * @param CallbackID ID of the callback to be registered
488 * @param pCallback pointer to the Callback function
489 * @retval HAL status
490 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)491 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
492 {
493 HAL_StatusTypeDef status = HAL_OK;
494
495 if (pCallback == NULL)
496 {
497 /* Update the error code */
498 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
499
500 return HAL_ERROR;
501 }
502 /* Process locked */
503 __HAL_LOCK(hspi);
504
505 if (HAL_SPI_STATE_READY == hspi->State)
506 {
507 switch (CallbackID)
508 {
509 case HAL_SPI_TX_COMPLETE_CB_ID :
510 hspi->TxCpltCallback = pCallback;
511 break;
512
513 case HAL_SPI_RX_COMPLETE_CB_ID :
514 hspi->RxCpltCallback = pCallback;
515 break;
516
517 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
518 hspi->TxRxCpltCallback = pCallback;
519 break;
520
521 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
522 hspi->TxHalfCpltCallback = pCallback;
523 break;
524
525 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
526 hspi->RxHalfCpltCallback = pCallback;
527 break;
528
529 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
530 hspi->TxRxHalfCpltCallback = pCallback;
531 break;
532
533 case HAL_SPI_ERROR_CB_ID :
534 hspi->ErrorCallback = pCallback;
535 break;
536
537 case HAL_SPI_ABORT_CB_ID :
538 hspi->AbortCpltCallback = pCallback;
539 break;
540
541 case HAL_SPI_MSPINIT_CB_ID :
542 hspi->MspInitCallback = pCallback;
543 break;
544
545 case HAL_SPI_MSPDEINIT_CB_ID :
546 hspi->MspDeInitCallback = pCallback;
547 break;
548
549 default :
550 /* Update the error code */
551 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
552
553 /* Return error status */
554 status = HAL_ERROR;
555 break;
556 }
557 }
558 else if (HAL_SPI_STATE_RESET == hspi->State)
559 {
560 switch (CallbackID)
561 {
562 case HAL_SPI_MSPINIT_CB_ID :
563 hspi->MspInitCallback = pCallback;
564 break;
565
566 case HAL_SPI_MSPDEINIT_CB_ID :
567 hspi->MspDeInitCallback = pCallback;
568 break;
569
570 default :
571 /* Update the error code */
572 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
573
574 /* Return error status */
575 status = HAL_ERROR;
576 break;
577 }
578 }
579 else
580 {
581 /* Update the error code */
582 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
583
584 /* Return error status */
585 status = HAL_ERROR;
586 }
587
588 /* Release Lock */
589 __HAL_UNLOCK(hspi);
590 return status;
591 }
592
593 /**
594 * @brief Unregister an SPI Callback
595 * SPI callback is redirected to the weak predefined callback
596 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
597 * the configuration information for the specified SPI.
598 * @param CallbackID ID of the callback to be unregistered
599 * @retval HAL status
600 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)601 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
602 {
603 HAL_StatusTypeDef status = HAL_OK;
604
605 /* Process locked */
606 __HAL_LOCK(hspi);
607
608 if (HAL_SPI_STATE_READY == hspi->State)
609 {
610 switch (CallbackID)
611 {
612 case HAL_SPI_TX_COMPLETE_CB_ID :
613 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
614 break;
615
616 case HAL_SPI_RX_COMPLETE_CB_ID :
617 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
618 break;
619
620 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
621 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
622 break;
623
624 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
625 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
626 break;
627
628 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
629 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
630 break;
631
632 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
633 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
634 break;
635
636 case HAL_SPI_ERROR_CB_ID :
637 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
638 break;
639
640 case HAL_SPI_ABORT_CB_ID :
641 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
642 break;
643
644 case HAL_SPI_MSPINIT_CB_ID :
645 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
646 break;
647
648 case HAL_SPI_MSPDEINIT_CB_ID :
649 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
650 break;
651
652 default :
653 /* Update the error code */
654 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
655
656 /* Return error status */
657 status = HAL_ERROR;
658 break;
659 }
660 }
661 else if (HAL_SPI_STATE_RESET == hspi->State)
662 {
663 switch (CallbackID)
664 {
665 case HAL_SPI_MSPINIT_CB_ID :
666 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
667 break;
668
669 case HAL_SPI_MSPDEINIT_CB_ID :
670 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
671 break;
672
673 default :
674 /* Update the error code */
675 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
676
677 /* Return error status */
678 status = HAL_ERROR;
679 break;
680 }
681 }
682 else
683 {
684 /* Update the error code */
685 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
686
687 /* Return error status */
688 status = HAL_ERROR;
689 }
690
691 /* Release Lock */
692 __HAL_UNLOCK(hspi);
693 return status;
694 }
695 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
696 /**
697 * @}
698 */
699
700 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
701 * @brief Data transfers functions
702 *
703 @verbatim
704 ==============================================================================
705 ##### IO operation functions #####
706 ===============================================================================
707 [..]
708 This subsection provides a set of functions allowing to manage the SPI
709 data transfers.
710
711 [..] The SPI supports master and slave mode :
712
713 (#) There are two modes of transfer:
714 (++) Blocking mode: The communication is performed in polling mode.
715 The HAL status of all data processing is returned by the same function
716 after finishing transfer.
717 (++) No-Blocking mode: The communication is performed using Interrupts
718 or DMA, These APIs return the HAL status.
719 The end of the data processing will be indicated through the
720 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
721 using DMA mode.
722 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
723 will be executed respectively at the end of the transmit or Receive process
724 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
725
726 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
727 exist for 1Line (simplex) and 2Lines (full duplex) modes.
728
729 @endverbatim
730 * @{
731 */
732
733 /**
734 * @brief Transmit an amount of data in blocking mode.
735 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
736 * the configuration information for SPI module.
737 * @param pData pointer to data buffer
738 * @param Size amount of data to be sent
739 * @param Timeout Timeout duration
740 * @retval HAL status
741 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)742 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
743 {
744 uint32_t tickstart;
745 HAL_StatusTypeDef errorcode = HAL_OK;
746 uint16_t initial_TxXferCount;
747
748 /* Check Direction parameter */
749 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
750
751 /* Process Locked */
752 __HAL_LOCK(hspi);
753
754 /* Init tickstart for timeout management*/
755 tickstart = HAL_GetTick();
756 initial_TxXferCount = Size;
757
758 if (hspi->State != HAL_SPI_STATE_READY)
759 {
760 errorcode = HAL_BUSY;
761 goto error;
762 }
763
764 if ((pData == NULL) || (Size == 0U))
765 {
766 errorcode = HAL_ERROR;
767 goto error;
768 }
769
770 /* Set the transaction information */
771 hspi->State = HAL_SPI_STATE_BUSY_TX;
772 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
773 hspi->pTxBuffPtr = (uint8_t *)pData;
774 hspi->TxXferSize = Size;
775 hspi->TxXferCount = Size;
776
777 /*Init field not used in handle to zero */
778 hspi->pRxBuffPtr = (uint8_t *)NULL;
779 hspi->RxXferSize = 0U;
780 hspi->RxXferCount = 0U;
781 hspi->TxISR = NULL;
782 hspi->RxISR = NULL;
783
784 /* Configure communication direction : 1Line */
785 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
786 {
787 SPI_1LINE_TX(hspi);
788 }
789
790 #if (USE_SPI_CRC != 0U)
791 /* Reset CRC Calculation */
792 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
793 {
794 SPI_RESET_CRC(hspi);
795 }
796 #endif /* USE_SPI_CRC */
797
798 /* Check if the SPI is already enabled */
799 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
800 {
801 /* Enable SPI peripheral */
802 __HAL_SPI_ENABLE(hspi);
803 }
804
805 /* Transmit data in 16 Bit mode */
806 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
807 {
808 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
809 {
810 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
811 hspi->pTxBuffPtr += sizeof(uint16_t);
812 hspi->TxXferCount--;
813 }
814 /* Transmit data in 16 Bit mode */
815 while (hspi->TxXferCount > 0U)
816 {
817 /* Wait until TXE flag is set to send data */
818 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
819 {
820 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
821 hspi->pTxBuffPtr += sizeof(uint16_t);
822 hspi->TxXferCount--;
823 }
824 else
825 {
826 /* Timeout management */
827 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
828 {
829 errorcode = HAL_TIMEOUT;
830 goto error;
831 }
832 }
833 }
834 }
835 /* Transmit data in 8 Bit mode */
836 else
837 {
838 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
839 {
840 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
841 hspi->pTxBuffPtr += sizeof(uint8_t);
842 hspi->TxXferCount--;
843 }
844 while (hspi->TxXferCount > 0U)
845 {
846 /* Wait until TXE flag is set to send data */
847 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
848 {
849 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
850 hspi->pTxBuffPtr += sizeof(uint8_t);
851 hspi->TxXferCount--;
852 }
853 else
854 {
855 /* Timeout management */
856 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
857 {
858 errorcode = HAL_TIMEOUT;
859 goto error;
860 }
861 }
862 }
863 }
864 #if (USE_SPI_CRC != 0U)
865 /* Enable CRC Transmission */
866 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
867 {
868 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
869 }
870 #endif /* USE_SPI_CRC */
871
872 /* Check the end of the transaction */
873 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
874 {
875 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
876 }
877
878 /* Clear overrun flag in 2 Lines communication mode because received is not read */
879 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
880 {
881 __HAL_SPI_CLEAR_OVRFLAG(hspi);
882 }
883
884 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
885 {
886 errorcode = HAL_ERROR;
887 }
888
889 error:
890 hspi->State = HAL_SPI_STATE_READY;
891 /* Process Unlocked */
892 __HAL_UNLOCK(hspi);
893 return errorcode;
894 }
895
896 /**
897 * @brief Receive an amount of data in blocking mode.
898 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
899 * the configuration information for SPI module.
900 * @param pData pointer to data buffer
901 * @param Size amount of data to be received
902 * @param Timeout Timeout duration
903 * @retval HAL status
904 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)905 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
906 {
907 uint32_t tickstart;
908 HAL_StatusTypeDef errorcode = HAL_OK;
909
910 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
911 {
912 hspi->State = HAL_SPI_STATE_BUSY_RX;
913 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
914 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
915 }
916
917 /* Process Locked */
918 __HAL_LOCK(hspi);
919
920 /* Init tickstart for timeout management*/
921 tickstart = HAL_GetTick();
922
923 if (hspi->State != HAL_SPI_STATE_READY)
924 {
925 errorcode = HAL_BUSY;
926 goto error;
927 }
928
929 if ((pData == NULL) || (Size == 0U))
930 {
931 errorcode = HAL_ERROR;
932 goto error;
933 }
934
935 /* Set the transaction information */
936 hspi->State = HAL_SPI_STATE_BUSY_RX;
937 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
938 hspi->pRxBuffPtr = (uint8_t *)pData;
939 hspi->RxXferSize = Size;
940 hspi->RxXferCount = Size;
941
942 /*Init field not used in handle to zero */
943 hspi->pTxBuffPtr = (uint8_t *)NULL;
944 hspi->TxXferSize = 0U;
945 hspi->TxXferCount = 0U;
946 hspi->RxISR = NULL;
947 hspi->TxISR = NULL;
948
949 #if (USE_SPI_CRC != 0U)
950 /* Reset CRC Calculation */
951 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
952 {
953 SPI_RESET_CRC(hspi);
954 /* this is done to handle the CRCNEXT before the latest data */
955 hspi->RxXferCount--;
956 }
957 #endif /* USE_SPI_CRC */
958
959 /* Configure communication direction: 1Line */
960 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
961 {
962 SPI_1LINE_RX(hspi);
963 }
964
965 /* Check if the SPI is already enabled */
966 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
967 {
968 /* Enable SPI peripheral */
969 __HAL_SPI_ENABLE(hspi);
970 }
971
972 /* Receive data in 8 Bit mode */
973 if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
974 {
975 /* Transfer loop */
976 while (hspi->RxXferCount > 0U)
977 {
978 /* Check the RXNE flag */
979 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
980 {
981 /* read the received data */
982 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
983 hspi->pRxBuffPtr += sizeof(uint8_t);
984 hspi->RxXferCount--;
985 }
986 else
987 {
988 /* Timeout management */
989 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
990 {
991 errorcode = HAL_TIMEOUT;
992 goto error;
993 }
994 }
995 }
996 }
997 else
998 {
999 /* Transfer loop */
1000 while (hspi->RxXferCount > 0U)
1001 {
1002 /* Check the RXNE flag */
1003 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1004 {
1005 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1006 hspi->pRxBuffPtr += sizeof(uint16_t);
1007 hspi->RxXferCount--;
1008 }
1009 else
1010 {
1011 /* Timeout management */
1012 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1013 {
1014 errorcode = HAL_TIMEOUT;
1015 goto error;
1016 }
1017 }
1018 }
1019 }
1020
1021 #if (USE_SPI_CRC != 0U)
1022 /* Handle the CRC Transmission */
1023 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1024 {
1025 /* freeze the CRC before the latest data */
1026 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1027
1028 /* Read the latest data */
1029 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1030 {
1031 /* the latest data has not been received */
1032 errorcode = HAL_TIMEOUT;
1033 goto error;
1034 }
1035
1036 /* Receive last data in 16 Bit mode */
1037 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1038 {
1039 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1040 }
1041 /* Receive last data in 8 Bit mode */
1042 else
1043 {
1044 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1045 }
1046
1047 /* Wait the CRC data */
1048 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1049 {
1050 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1051 errorcode = HAL_TIMEOUT;
1052 goto error;
1053 }
1054
1055 /* Read CRC to Flush DR and RXNE flag */
1056 READ_REG(hspi->Instance->DR);
1057 }
1058 #endif /* USE_SPI_CRC */
1059
1060 /* Check the end of the transaction */
1061 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1062 {
1063 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1064 }
1065
1066 #if (USE_SPI_CRC != 0U)
1067 /* Check if CRC error occurred */
1068 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1069 {
1070 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1071 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1072 }
1073 #endif /* USE_SPI_CRC */
1074
1075 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1076 {
1077 errorcode = HAL_ERROR;
1078 }
1079
1080 error :
1081 hspi->State = HAL_SPI_STATE_READY;
1082 __HAL_UNLOCK(hspi);
1083 return errorcode;
1084 }
1085
1086 /**
1087 * @brief Transmit and Receive an amount of data in blocking mode.
1088 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1089 * the configuration information for SPI module.
1090 * @param pTxData pointer to transmission data buffer
1091 * @param pRxData pointer to reception data buffer
1092 * @param Size amount of data to be sent and received
1093 * @param Timeout Timeout duration
1094 * @retval HAL status
1095 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1096 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1097 uint32_t Timeout)
1098 {
1099 uint16_t initial_TxXferCount;
1100 uint32_t tmp_mode;
1101 HAL_SPI_StateTypeDef tmp_state;
1102 uint32_t tickstart;
1103
1104 /* Variable used to alternate Rx and Tx during transfer */
1105 uint32_t txallowed = 1U;
1106 HAL_StatusTypeDef errorcode = HAL_OK;
1107
1108 /* Check Direction parameter */
1109 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1110
1111 /* Process Locked */
1112 __HAL_LOCK(hspi);
1113
1114 /* Init tickstart for timeout management*/
1115 tickstart = HAL_GetTick();
1116
1117 /* Init temporary variables */
1118 tmp_state = hspi->State;
1119 tmp_mode = hspi->Init.Mode;
1120 initial_TxXferCount = Size;
1121
1122 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1123 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1124 {
1125 errorcode = HAL_BUSY;
1126 goto error;
1127 }
1128
1129 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1130 {
1131 errorcode = HAL_ERROR;
1132 goto error;
1133 }
1134
1135 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1136 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1137 {
1138 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1139 }
1140
1141 /* Set the transaction information */
1142 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1143 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1144 hspi->RxXferCount = Size;
1145 hspi->RxXferSize = Size;
1146 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1147 hspi->TxXferCount = Size;
1148 hspi->TxXferSize = Size;
1149
1150 /*Init field not used in handle to zero */
1151 hspi->RxISR = NULL;
1152 hspi->TxISR = NULL;
1153
1154 #if (USE_SPI_CRC != 0U)
1155 /* Reset CRC Calculation */
1156 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1157 {
1158 SPI_RESET_CRC(hspi);
1159 }
1160 #endif /* USE_SPI_CRC */
1161
1162 /* Check if the SPI is already enabled */
1163 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1164 {
1165 /* Enable SPI peripheral */
1166 __HAL_SPI_ENABLE(hspi);
1167 }
1168
1169 /* Transmit and Receive data in 16 Bit mode */
1170 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1171 {
1172 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1173 {
1174 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1175 hspi->pTxBuffPtr += sizeof(uint16_t);
1176 hspi->TxXferCount--;
1177 }
1178 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1179 {
1180 /* Check TXE flag */
1181 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1182 {
1183 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1184 hspi->pTxBuffPtr += sizeof(uint16_t);
1185 hspi->TxXferCount--;
1186 /* Next Data is a reception (Rx). Tx not allowed */
1187 txallowed = 0U;
1188
1189 #if (USE_SPI_CRC != 0U)
1190 /* Enable CRC Transmission */
1191 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1192 {
1193 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1194 }
1195 #endif /* USE_SPI_CRC */
1196 }
1197
1198 /* Check RXNE flag */
1199 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1200 {
1201 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1202 hspi->pRxBuffPtr += sizeof(uint16_t);
1203 hspi->RxXferCount--;
1204 /* Next Data is a Transmission (Tx). Tx is allowed */
1205 txallowed = 1U;
1206 }
1207 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1208 {
1209 errorcode = HAL_TIMEOUT;
1210 goto error;
1211 }
1212 }
1213 }
1214 /* Transmit and Receive data in 8 Bit mode */
1215 else
1216 {
1217 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1218 {
1219 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1220 hspi->pTxBuffPtr += sizeof(uint8_t);
1221 hspi->TxXferCount--;
1222 }
1223 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1224 {
1225 /* Check TXE flag */
1226 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1227 {
1228 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1229 hspi->pTxBuffPtr++;
1230 hspi->TxXferCount--;
1231 /* Next Data is a reception (Rx). Tx not allowed */
1232 txallowed = 0U;
1233
1234 #if (USE_SPI_CRC != 0U)
1235 /* Enable CRC Transmission */
1236 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1237 {
1238 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1239 }
1240 #endif /* USE_SPI_CRC */
1241 }
1242
1243 /* Wait until RXNE flag is reset */
1244 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1245 {
1246 (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
1247 hspi->pRxBuffPtr++;
1248 hspi->RxXferCount--;
1249 /* Next Data is a Transmission (Tx). Tx is allowed */
1250 txallowed = 1U;
1251 }
1252 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1253 {
1254 errorcode = HAL_TIMEOUT;
1255 goto error;
1256 }
1257 }
1258 }
1259
1260 #if (USE_SPI_CRC != 0U)
1261 /* Read CRC from DR to close CRC calculation process */
1262 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1263 {
1264 /* Wait until TXE flag */
1265 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1266 {
1267 /* Error on the CRC reception */
1268 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1269 errorcode = HAL_TIMEOUT;
1270 goto error;
1271 }
1272 /* Read CRC */
1273 READ_REG(hspi->Instance->DR);
1274 }
1275
1276 /* Check if CRC error occurred */
1277 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1278 {
1279 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1280 /* Clear CRC Flag */
1281 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1282
1283 errorcode = HAL_ERROR;
1284 }
1285 #endif /* USE_SPI_CRC */
1286
1287 /* Check the end of the transaction */
1288 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1289 {
1290 errorcode = HAL_ERROR;
1291 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1292 goto error;
1293 }
1294
1295 /* Clear overrun flag in 2 Lines communication mode because received is not read */
1296 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
1297 {
1298 __HAL_SPI_CLEAR_OVRFLAG(hspi);
1299 }
1300
1301 error :
1302 hspi->State = HAL_SPI_STATE_READY;
1303 __HAL_UNLOCK(hspi);
1304 return errorcode;
1305 }
1306
1307 /**
1308 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1309 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1310 * the configuration information for SPI module.
1311 * @param pData pointer to data buffer
1312 * @param Size amount of data to be sent
1313 * @retval HAL status
1314 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1315 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1316 {
1317 HAL_StatusTypeDef errorcode = HAL_OK;
1318
1319 /* Check Direction parameter */
1320 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1321
1322 /* Process Locked */
1323 __HAL_LOCK(hspi);
1324
1325 if ((pData == NULL) || (Size == 0U))
1326 {
1327 errorcode = HAL_ERROR;
1328 goto error;
1329 }
1330
1331 if (hspi->State != HAL_SPI_STATE_READY)
1332 {
1333 errorcode = HAL_BUSY;
1334 goto error;
1335 }
1336
1337 /* Set the transaction information */
1338 hspi->State = HAL_SPI_STATE_BUSY_TX;
1339 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1340 hspi->pTxBuffPtr = (uint8_t *)pData;
1341 hspi->TxXferSize = Size;
1342 hspi->TxXferCount = Size;
1343
1344 /* Init field not used in handle to zero */
1345 hspi->pRxBuffPtr = (uint8_t *)NULL;
1346 hspi->RxXferSize = 0U;
1347 hspi->RxXferCount = 0U;
1348 hspi->RxISR = NULL;
1349
1350 /* Set the function for IT treatment */
1351 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1352 {
1353 hspi->TxISR = SPI_TxISR_16BIT;
1354 }
1355 else
1356 {
1357 hspi->TxISR = SPI_TxISR_8BIT;
1358 }
1359
1360 /* Configure communication direction : 1Line */
1361 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1362 {
1363 SPI_1LINE_TX(hspi);
1364 }
1365
1366 #if (USE_SPI_CRC != 0U)
1367 /* Reset CRC Calculation */
1368 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1369 {
1370 SPI_RESET_CRC(hspi);
1371 }
1372 #endif /* USE_SPI_CRC */
1373
1374 /* Enable TXE and ERR interrupt */
1375 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1376
1377
1378 /* Check if the SPI is already enabled */
1379 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1380 {
1381 /* Enable SPI peripheral */
1382 __HAL_SPI_ENABLE(hspi);
1383 }
1384
1385 error :
1386 __HAL_UNLOCK(hspi);
1387 return errorcode;
1388 }
1389
1390 /**
1391 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1392 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1393 * the configuration information for SPI module.
1394 * @param pData pointer to data buffer
1395 * @param Size amount of data to be sent
1396 * @retval HAL status
1397 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1398 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1399 {
1400 HAL_StatusTypeDef errorcode = HAL_OK;
1401
1402 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1403 {
1404 hspi->State = HAL_SPI_STATE_BUSY_RX;
1405 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1406 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1407 }
1408
1409 /* Process Locked */
1410 __HAL_LOCK(hspi);
1411
1412 if (hspi->State != HAL_SPI_STATE_READY)
1413 {
1414 errorcode = HAL_BUSY;
1415 goto error;
1416 }
1417
1418 if ((pData == NULL) || (Size == 0U))
1419 {
1420 errorcode = HAL_ERROR;
1421 goto error;
1422 }
1423
1424 /* Set the transaction information */
1425 hspi->State = HAL_SPI_STATE_BUSY_RX;
1426 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1427 hspi->pRxBuffPtr = (uint8_t *)pData;
1428 hspi->RxXferSize = Size;
1429 hspi->RxXferCount = Size;
1430
1431 /* Init field not used in handle to zero */
1432 hspi->pTxBuffPtr = (uint8_t *)NULL;
1433 hspi->TxXferSize = 0U;
1434 hspi->TxXferCount = 0U;
1435 hspi->TxISR = NULL;
1436
1437 /* Set the function for IT treatment */
1438 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1439 {
1440 hspi->RxISR = SPI_RxISR_16BIT;
1441 }
1442 else
1443 {
1444 hspi->RxISR = SPI_RxISR_8BIT;
1445 }
1446
1447 /* Configure communication direction : 1Line */
1448 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1449 {
1450 SPI_1LINE_RX(hspi);
1451 }
1452
1453 #if (USE_SPI_CRC != 0U)
1454 /* Reset CRC Calculation */
1455 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1456 {
1457 SPI_RESET_CRC(hspi);
1458 }
1459 #endif /* USE_SPI_CRC */
1460
1461 /* Enable TXE and ERR interrupt */
1462 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1463
1464 /* Note : The SPI must be enabled after unlocking current process
1465 to avoid the risk of SPI interrupt handle execution before current
1466 process unlock */
1467
1468 /* Check if the SPI is already enabled */
1469 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1470 {
1471 /* Enable SPI peripheral */
1472 __HAL_SPI_ENABLE(hspi);
1473 }
1474
1475 error :
1476 /* Process Unlocked */
1477 __HAL_UNLOCK(hspi);
1478 return errorcode;
1479 }
1480
1481 /**
1482 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1483 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1484 * the configuration information for SPI module.
1485 * @param pTxData pointer to transmission data buffer
1486 * @param pRxData pointer to reception data buffer
1487 * @param Size amount of data to be sent and received
1488 * @retval HAL status
1489 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1490 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1491 {
1492 uint32_t tmp_mode;
1493 HAL_SPI_StateTypeDef tmp_state;
1494 HAL_StatusTypeDef errorcode = HAL_OK;
1495
1496 /* Check Direction parameter */
1497 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1498
1499 /* Process locked */
1500 __HAL_LOCK(hspi);
1501
1502 /* Init temporary variables */
1503 tmp_state = hspi->State;
1504 tmp_mode = hspi->Init.Mode;
1505
1506 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1507 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1508 {
1509 errorcode = HAL_BUSY;
1510 goto error;
1511 }
1512
1513 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1514 {
1515 errorcode = HAL_ERROR;
1516 goto error;
1517 }
1518
1519 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1520 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1521 {
1522 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1523 }
1524
1525 /* Set the transaction information */
1526 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1527 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1528 hspi->TxXferSize = Size;
1529 hspi->TxXferCount = Size;
1530 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1531 hspi->RxXferSize = Size;
1532 hspi->RxXferCount = Size;
1533
1534 /* Set the function for IT treatment */
1535 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1536 {
1537 hspi->RxISR = SPI_2linesRxISR_16BIT;
1538 hspi->TxISR = SPI_2linesTxISR_16BIT;
1539 }
1540 else
1541 {
1542 hspi->RxISR = SPI_2linesRxISR_8BIT;
1543 hspi->TxISR = SPI_2linesTxISR_8BIT;
1544 }
1545
1546 #if (USE_SPI_CRC != 0U)
1547 /* Reset CRC Calculation */
1548 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1549 {
1550 SPI_RESET_CRC(hspi);
1551 }
1552 #endif /* USE_SPI_CRC */
1553
1554 /* Enable TXE, RXNE and ERR interrupt */
1555 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1556
1557 /* Check if the SPI is already enabled */
1558 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1559 {
1560 /* Enable SPI peripheral */
1561 __HAL_SPI_ENABLE(hspi);
1562 }
1563
1564 error :
1565 /* Process Unlocked */
1566 __HAL_UNLOCK(hspi);
1567 return errorcode;
1568 }
1569
1570 /**
1571 * @brief Transmit an amount of data in non-blocking mode with DMA.
1572 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1573 * the configuration information for SPI module.
1574 * @param pData pointer to data buffer
1575 * @param Size amount of data to be sent
1576 * @retval HAL status
1577 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1578 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1579 {
1580 HAL_StatusTypeDef errorcode = HAL_OK;
1581
1582 /* Check tx dma handle */
1583 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1584
1585 /* Check Direction parameter */
1586 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1587
1588 /* Process Locked */
1589 __HAL_LOCK(hspi);
1590
1591 if (hspi->State != HAL_SPI_STATE_READY)
1592 {
1593 errorcode = HAL_BUSY;
1594 goto error;
1595 }
1596
1597 if ((pData == NULL) || (Size == 0U))
1598 {
1599 errorcode = HAL_ERROR;
1600 goto error;
1601 }
1602
1603 /* Set the transaction information */
1604 hspi->State = HAL_SPI_STATE_BUSY_TX;
1605 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1606 hspi->pTxBuffPtr = (uint8_t *)pData;
1607 hspi->TxXferSize = Size;
1608 hspi->TxXferCount = Size;
1609
1610 /* Init field not used in handle to zero */
1611 hspi->pRxBuffPtr = (uint8_t *)NULL;
1612 hspi->TxISR = NULL;
1613 hspi->RxISR = NULL;
1614 hspi->RxXferSize = 0U;
1615 hspi->RxXferCount = 0U;
1616
1617 /* Configure communication direction : 1Line */
1618 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1619 {
1620 SPI_1LINE_TX(hspi);
1621 }
1622
1623 #if (USE_SPI_CRC != 0U)
1624 /* Reset CRC Calculation */
1625 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1626 {
1627 SPI_RESET_CRC(hspi);
1628 }
1629 #endif /* USE_SPI_CRC */
1630
1631 /* Set the SPI TxDMA Half transfer complete callback */
1632 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1633
1634 /* Set the SPI TxDMA transfer complete callback */
1635 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1636
1637 /* Set the DMA error callback */
1638 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1639
1640 /* Set the DMA AbortCpltCallback */
1641 hspi->hdmatx->XferAbortCallback = NULL;
1642
1643 /* Enable the Tx DMA Stream/Channel */
1644 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
1645 {
1646 /* Update SPI error code */
1647 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1648 errorcode = HAL_ERROR;
1649
1650 hspi->State = HAL_SPI_STATE_READY;
1651 goto error;
1652 }
1653
1654 /* Check if the SPI is already enabled */
1655 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1656 {
1657 /* Enable SPI peripheral */
1658 __HAL_SPI_ENABLE(hspi);
1659 }
1660
1661 /* Enable the SPI Error Interrupt Bit */
1662 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1663
1664 /* Enable Tx DMA Request */
1665 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1666
1667 error :
1668 /* Process Unlocked */
1669 __HAL_UNLOCK(hspi);
1670 return errorcode;
1671 }
1672
1673 /**
1674 * @brief Receive an amount of data in non-blocking mode with DMA.
1675 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1676 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1677 * the configuration information for SPI module.
1678 * @param pData pointer to data buffer
1679 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1680 * @param Size amount of data to be sent
1681 * @retval HAL status
1682 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1683 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1684 {
1685 HAL_StatusTypeDef errorcode = HAL_OK;
1686
1687 /* Check rx dma handle */
1688 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1689
1690 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1691 {
1692 hspi->State = HAL_SPI_STATE_BUSY_RX;
1693
1694 /* Check tx dma handle */
1695 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1696
1697 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1698 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1699 }
1700
1701 /* Process Locked */
1702 __HAL_LOCK(hspi);
1703
1704 if (hspi->State != HAL_SPI_STATE_READY)
1705 {
1706 errorcode = HAL_BUSY;
1707 goto error;
1708 }
1709
1710 if ((pData == NULL) || (Size == 0U))
1711 {
1712 errorcode = HAL_ERROR;
1713 goto error;
1714 }
1715
1716 /* Set the transaction information */
1717 hspi->State = HAL_SPI_STATE_BUSY_RX;
1718 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1719 hspi->pRxBuffPtr = (uint8_t *)pData;
1720 hspi->RxXferSize = Size;
1721 hspi->RxXferCount = Size;
1722
1723 /*Init field not used in handle to zero */
1724 hspi->RxISR = NULL;
1725 hspi->TxISR = NULL;
1726 hspi->TxXferSize = 0U;
1727 hspi->TxXferCount = 0U;
1728
1729 /* Configure communication direction : 1Line */
1730 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1731 {
1732 SPI_1LINE_RX(hspi);
1733 }
1734
1735 #if (USE_SPI_CRC != 0U)
1736 /* Reset CRC Calculation */
1737 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1738 {
1739 SPI_RESET_CRC(hspi);
1740 }
1741 #endif /* USE_SPI_CRC */
1742
1743 /* Set the SPI RxDMA Half transfer complete callback */
1744 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1745
1746 /* Set the SPI Rx DMA transfer complete callback */
1747 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1748
1749 /* Set the DMA error callback */
1750 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1751
1752 /* Set the DMA AbortCpltCallback */
1753 hspi->hdmarx->XferAbortCallback = NULL;
1754
1755 /* Enable the Rx DMA Stream/Channel */
1756 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
1757 {
1758 /* Update SPI error code */
1759 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1760 errorcode = HAL_ERROR;
1761
1762 hspi->State = HAL_SPI_STATE_READY;
1763 goto error;
1764 }
1765
1766 /* Check if the SPI is already enabled */
1767 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1768 {
1769 /* Enable SPI peripheral */
1770 __HAL_SPI_ENABLE(hspi);
1771 }
1772
1773 /* Enable the SPI Error Interrupt Bit */
1774 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1775
1776 /* Enable Rx DMA Request */
1777 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1778
1779 error:
1780 /* Process Unlocked */
1781 __HAL_UNLOCK(hspi);
1782 return errorcode;
1783 }
1784
1785 /**
1786 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
1787 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1788 * the configuration information for SPI module.
1789 * @param pTxData pointer to transmission data buffer
1790 * @param pRxData pointer to reception data buffer
1791 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
1792 * @param Size amount of data to be sent
1793 * @retval HAL status
1794 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1795 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
1796 uint16_t Size)
1797 {
1798 uint32_t tmp_mode;
1799 HAL_SPI_StateTypeDef tmp_state;
1800 HAL_StatusTypeDef errorcode = HAL_OK;
1801
1802 /* Check rx & tx dma handles */
1803 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1804 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1805
1806 /* Check Direction parameter */
1807 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1808
1809 /* Process locked */
1810 __HAL_LOCK(hspi);
1811
1812 /* Init temporary variables */
1813 tmp_state = hspi->State;
1814 tmp_mode = hspi->Init.Mode;
1815
1816 if (!((tmp_state == HAL_SPI_STATE_READY) ||
1817 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1818 {
1819 errorcode = HAL_BUSY;
1820 goto error;
1821 }
1822
1823 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1824 {
1825 errorcode = HAL_ERROR;
1826 goto error;
1827 }
1828
1829 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1830 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1831 {
1832 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1833 }
1834
1835 /* Set the transaction information */
1836 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1837 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1838 hspi->TxXferSize = Size;
1839 hspi->TxXferCount = Size;
1840 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1841 hspi->RxXferSize = Size;
1842 hspi->RxXferCount = Size;
1843
1844 /* Init field not used in handle to zero */
1845 hspi->RxISR = NULL;
1846 hspi->TxISR = NULL;
1847
1848 #if (USE_SPI_CRC != 0U)
1849 /* Reset CRC Calculation */
1850 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1851 {
1852 SPI_RESET_CRC(hspi);
1853 }
1854 #endif /* USE_SPI_CRC */
1855
1856 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
1857 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
1858 {
1859 /* Set the SPI Rx DMA Half transfer complete callback */
1860 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1861 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1862 }
1863 else
1864 {
1865 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
1866 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1867 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
1868 }
1869
1870 /* Set the DMA error callback */
1871 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1872
1873 /* Set the DMA AbortCpltCallback */
1874 hspi->hdmarx->XferAbortCallback = NULL;
1875
1876 /* Enable the Rx DMA Stream/Channel */
1877 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
1878 {
1879 /* Update SPI error code */
1880 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1881 errorcode = HAL_ERROR;
1882
1883 hspi->State = HAL_SPI_STATE_READY;
1884 goto error;
1885 }
1886
1887 /* Enable Rx DMA Request */
1888 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1889
1890 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1891 is performed in DMA reception complete callback */
1892 hspi->hdmatx->XferHalfCpltCallback = NULL;
1893 hspi->hdmatx->XferCpltCallback = NULL;
1894 hspi->hdmatx->XferErrorCallback = NULL;
1895 hspi->hdmatx->XferAbortCallback = NULL;
1896
1897 /* Enable the Tx DMA Stream/Channel */
1898 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
1899 {
1900 /* Update SPI error code */
1901 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1902 errorcode = HAL_ERROR;
1903
1904 hspi->State = HAL_SPI_STATE_READY;
1905 goto error;
1906 }
1907
1908 /* Check if the SPI is already enabled */
1909 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1910 {
1911 /* Enable SPI peripheral */
1912 __HAL_SPI_ENABLE(hspi);
1913 }
1914 /* Enable the SPI Error Interrupt Bit */
1915 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1916
1917 /* Enable Tx DMA Request */
1918 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1919
1920 error :
1921 /* Process Unlocked */
1922 __HAL_UNLOCK(hspi);
1923 return errorcode;
1924 }
1925
1926 /**
1927 * @brief Abort ongoing transfer (blocking mode).
1928 * @param hspi SPI handle.
1929 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
1930 * started in Interrupt or DMA mode.
1931 * This procedure performs following operations :
1932 * - Disable SPI Interrupts (depending of transfer direction)
1933 * - Disable the DMA transfer in the peripheral register (if enabled)
1934 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
1935 * - Set handle State to READY
1936 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
1937 * @retval HAL status
1938 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)1939 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
1940 {
1941 HAL_StatusTypeDef errorcode;
1942 __IO uint32_t count, resetcount;
1943
1944 /* Initialized local variable */
1945 errorcode = HAL_OK;
1946 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
1947 count = resetcount;
1948
1949 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
1950 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
1951
1952 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
1953 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
1954 {
1955 hspi->TxISR = SPI_AbortTx_ISR;
1956 /* Wait HAL_SPI_STATE_ABORT state */
1957 do
1958 {
1959 if (count == 0U)
1960 {
1961 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
1962 break;
1963 }
1964 count--;
1965 }
1966 while (hspi->State != HAL_SPI_STATE_ABORT);
1967 /* Reset Timeout Counter */
1968 count = resetcount;
1969 }
1970
1971 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
1972 {
1973 hspi->RxISR = SPI_AbortRx_ISR;
1974 /* Wait HAL_SPI_STATE_ABORT state */
1975 do
1976 {
1977 if (count == 0U)
1978 {
1979 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
1980 break;
1981 }
1982 count--;
1983 }
1984 while (hspi->State != HAL_SPI_STATE_ABORT);
1985 /* Reset Timeout Counter */
1986 count = resetcount;
1987 }
1988
1989 /* Disable the SPI DMA Tx request if enabled */
1990 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
1991 {
1992 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
1993 if (hspi->hdmatx != NULL)
1994 {
1995 /* Set the SPI DMA Abort callback :
1996 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
1997 hspi->hdmatx->XferAbortCallback = NULL;
1998
1999 /* Abort DMA Tx Handle linked to SPI Peripheral */
2000 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2001 {
2002 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2003 }
2004
2005 /* Disable Tx DMA Request */
2006 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2007
2008 /* Wait until TXE flag is set */
2009 do
2010 {
2011 if (count == 0U)
2012 {
2013 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2014 break;
2015 }
2016 count--;
2017 }
2018 while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2019 }
2020 }
2021
2022 /* Disable the SPI DMA Rx request if enabled */
2023 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2024 {
2025 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2026 if (hspi->hdmarx != NULL)
2027 {
2028 /* Set the SPI DMA Abort callback :
2029 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2030 hspi->hdmarx->XferAbortCallback = NULL;
2031
2032 /* Abort DMA Rx Handle linked to SPI Peripheral */
2033 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2034 {
2035 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2036 }
2037
2038 /* Disable peripheral */
2039 __HAL_SPI_DISABLE(hspi);
2040
2041 /* Disable Rx DMA Request */
2042 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2043 }
2044 }
2045 /* Reset Tx and Rx transfer counters */
2046 hspi->RxXferCount = 0U;
2047 hspi->TxXferCount = 0U;
2048
2049 /* Check error during Abort procedure */
2050 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2051 {
2052 /* return HAL_Error in case of error during Abort procedure */
2053 errorcode = HAL_ERROR;
2054 }
2055 else
2056 {
2057 /* Reset errorCode */
2058 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2059 }
2060
2061 /* Clear the Error flags in the SR register */
2062 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2063 __HAL_SPI_CLEAR_FREFLAG(hspi);
2064
2065 /* Restore hspi->state to ready */
2066 hspi->State = HAL_SPI_STATE_READY;
2067
2068 return errorcode;
2069 }
2070
2071 /**
2072 * @brief Abort ongoing transfer (Interrupt mode).
2073 * @param hspi SPI handle.
2074 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2075 * started in Interrupt or DMA mode.
2076 * This procedure performs following operations :
2077 * - Disable SPI Interrupts (depending of transfer direction)
2078 * - Disable the DMA transfer in the peripheral register (if enabled)
2079 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2080 * - Set handle State to READY
2081 * - At abort completion, call user abort complete callback
2082 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2083 * considered as completed only when user abort complete callback is executed (not when exiting function).
2084 * @retval HAL status
2085 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2086 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2087 {
2088 HAL_StatusTypeDef errorcode;
2089 uint32_t abortcplt ;
2090 __IO uint32_t count, resetcount;
2091
2092 /* Initialized local variable */
2093 errorcode = HAL_OK;
2094 abortcplt = 1U;
2095 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2096 count = resetcount;
2097
2098 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2099 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2100
2101 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2102 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2103 {
2104 hspi->TxISR = SPI_AbortTx_ISR;
2105 /* Wait HAL_SPI_STATE_ABORT state */
2106 do
2107 {
2108 if (count == 0U)
2109 {
2110 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2111 break;
2112 }
2113 count--;
2114 }
2115 while (hspi->State != HAL_SPI_STATE_ABORT);
2116 /* Reset Timeout Counter */
2117 count = resetcount;
2118 }
2119
2120 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2121 {
2122 hspi->RxISR = SPI_AbortRx_ISR;
2123 /* Wait HAL_SPI_STATE_ABORT state */
2124 do
2125 {
2126 if (count == 0U)
2127 {
2128 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2129 break;
2130 }
2131 count--;
2132 }
2133 while (hspi->State != HAL_SPI_STATE_ABORT);
2134 /* Reset Timeout Counter */
2135 count = resetcount;
2136 }
2137
2138 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2139 before any call to DMA Abort functions */
2140 /* DMA Tx Handle is valid */
2141 if (hspi->hdmatx != NULL)
2142 {
2143 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2144 Otherwise, set it to NULL */
2145 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2146 {
2147 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2148 }
2149 else
2150 {
2151 hspi->hdmatx->XferAbortCallback = NULL;
2152 }
2153 }
2154 /* DMA Rx Handle is valid */
2155 if (hspi->hdmarx != NULL)
2156 {
2157 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2158 Otherwise, set it to NULL */
2159 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2160 {
2161 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2162 }
2163 else
2164 {
2165 hspi->hdmarx->XferAbortCallback = NULL;
2166 }
2167 }
2168
2169 /* Disable the SPI DMA Tx request if enabled */
2170 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2171 {
2172 /* Abort the SPI DMA Tx Stream/Channel */
2173 if (hspi->hdmatx != NULL)
2174 {
2175 /* Abort DMA Tx Handle linked to SPI Peripheral */
2176 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2177 {
2178 hspi->hdmatx->XferAbortCallback = NULL;
2179 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2180 }
2181 else
2182 {
2183 abortcplt = 0U;
2184 }
2185 }
2186 }
2187 /* Disable the SPI DMA Rx request if enabled */
2188 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2189 {
2190 /* Abort the SPI DMA Rx Stream/Channel */
2191 if (hspi->hdmarx != NULL)
2192 {
2193 /* Abort DMA Rx Handle linked to SPI Peripheral */
2194 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2195 {
2196 hspi->hdmarx->XferAbortCallback = NULL;
2197 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2198 }
2199 else
2200 {
2201 abortcplt = 0U;
2202 }
2203 }
2204 }
2205
2206 if (abortcplt == 1U)
2207 {
2208 /* Reset Tx and Rx transfer counters */
2209 hspi->RxXferCount = 0U;
2210 hspi->TxXferCount = 0U;
2211
2212 /* Check error during Abort procedure */
2213 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2214 {
2215 /* return HAL_Error in case of error during Abort procedure */
2216 errorcode = HAL_ERROR;
2217 }
2218 else
2219 {
2220 /* Reset errorCode */
2221 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2222 }
2223
2224 /* Clear the Error flags in the SR register */
2225 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2226 __HAL_SPI_CLEAR_FREFLAG(hspi);
2227
2228 /* Restore hspi->State to Ready */
2229 hspi->State = HAL_SPI_STATE_READY;
2230
2231 /* As no DMA to be aborted, call directly user Abort complete callback */
2232 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2233 hspi->AbortCpltCallback(hspi);
2234 #else
2235 HAL_SPI_AbortCpltCallback(hspi);
2236 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2237 }
2238
2239 return errorcode;
2240 }
2241
2242 /**
2243 * @brief Pause the DMA Transfer.
2244 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2245 * the configuration information for the specified SPI module.
2246 * @retval HAL status
2247 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2248 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2249 {
2250 /* Process Locked */
2251 __HAL_LOCK(hspi);
2252
2253 /* Disable the SPI DMA Tx & Rx requests */
2254 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2255
2256 /* Process Unlocked */
2257 __HAL_UNLOCK(hspi);
2258
2259 return HAL_OK;
2260 }
2261
2262 /**
2263 * @brief Resume the DMA Transfer.
2264 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2265 * the configuration information for the specified SPI module.
2266 * @retval HAL status
2267 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2268 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2269 {
2270 /* Process Locked */
2271 __HAL_LOCK(hspi);
2272
2273 /* Enable the SPI DMA Tx & Rx requests */
2274 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2275
2276 /* Process Unlocked */
2277 __HAL_UNLOCK(hspi);
2278
2279 return HAL_OK;
2280 }
2281
2282 /**
2283 * @brief Stop the DMA Transfer.
2284 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2285 * the configuration information for the specified SPI module.
2286 * @retval HAL status
2287 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2288 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2289 {
2290 HAL_StatusTypeDef errorcode = HAL_OK;
2291 /* The Lock is not implemented on this API to allow the user application
2292 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2293 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2294 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2295 */
2296
2297 /* Abort the SPI DMA tx Stream/Channel */
2298 if (hspi->hdmatx != NULL)
2299 {
2300 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2301 {
2302 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2303 errorcode = HAL_ERROR;
2304 }
2305 }
2306 /* Abort the SPI DMA rx Stream/Channel */
2307 if (hspi->hdmarx != NULL)
2308 {
2309 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2310 {
2311 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2312 errorcode = HAL_ERROR;
2313 }
2314 }
2315
2316 /* Disable the SPI DMA Tx & Rx requests */
2317 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2318 hspi->State = HAL_SPI_STATE_READY;
2319 return errorcode;
2320 }
2321
2322 /**
2323 * @brief Handle SPI interrupt request.
2324 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2325 * the configuration information for the specified SPI module.
2326 * @retval None
2327 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2328 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2329 {
2330 uint32_t itsource = hspi->Instance->CR2;
2331 uint32_t itflag = hspi->Instance->SR;
2332
2333 /* SPI in mode Receiver ----------------------------------------------------*/
2334 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2335 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2336 {
2337 hspi->RxISR(hspi);
2338 return;
2339 }
2340
2341 /* SPI in mode Transmitter -------------------------------------------------*/
2342 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2343 {
2344 hspi->TxISR(hspi);
2345 return;
2346 }
2347
2348 /* SPI in Error Treatment --------------------------------------------------*/
2349 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2350 {
2351 /* SPI Overrun error interrupt occurred ----------------------------------*/
2352 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2353 {
2354 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2355 {
2356 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2357 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2358 }
2359 else
2360 {
2361 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2362 return;
2363 }
2364 }
2365
2366 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2367 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2368 {
2369 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2370 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2371 }
2372
2373 /* SPI Frame error interrupt occurred ------------------------------------*/
2374 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2375 {
2376 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2377 __HAL_SPI_CLEAR_FREFLAG(hspi);
2378 }
2379
2380 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2381 {
2382 /* Disable all interrupts */
2383 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2384
2385 hspi->State = HAL_SPI_STATE_READY;
2386 /* Disable the SPI DMA requests if enabled */
2387 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2388 {
2389 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2390
2391 /* Abort the SPI DMA Rx channel */
2392 if (hspi->hdmarx != NULL)
2393 {
2394 /* Set the SPI DMA Abort callback :
2395 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2396 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2397 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2398 {
2399 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2400 }
2401 }
2402 /* Abort the SPI DMA Tx channel */
2403 if (hspi->hdmatx != NULL)
2404 {
2405 /* Set the SPI DMA Abort callback :
2406 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2407 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2408 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2409 {
2410 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2411 }
2412 }
2413 }
2414 else
2415 {
2416 /* Call user error callback */
2417 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2418 hspi->ErrorCallback(hspi);
2419 #else
2420 HAL_SPI_ErrorCallback(hspi);
2421 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2422 }
2423 }
2424 return;
2425 }
2426 }
2427
2428 /**
2429 * @brief Tx Transfer completed callback.
2430 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2431 * the configuration information for SPI module.
2432 * @retval None
2433 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2434 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2435 {
2436 /* Prevent unused argument(s) compilation warning */
2437 UNUSED(hspi);
2438
2439 /* NOTE : This function should not be modified, when the callback is needed,
2440 the HAL_SPI_TxCpltCallback should be implemented in the user file
2441 */
2442 }
2443
2444 /**
2445 * @brief Rx Transfer completed callback.
2446 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2447 * the configuration information for SPI module.
2448 * @retval None
2449 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2450 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2451 {
2452 /* Prevent unused argument(s) compilation warning */
2453 UNUSED(hspi);
2454
2455 /* NOTE : This function should not be modified, when the callback is needed,
2456 the HAL_SPI_RxCpltCallback should be implemented in the user file
2457 */
2458 }
2459
2460 /**
2461 * @brief Tx and Rx Transfer completed callback.
2462 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2463 * the configuration information for SPI module.
2464 * @retval None
2465 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2466 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2467 {
2468 /* Prevent unused argument(s) compilation warning */
2469 UNUSED(hspi);
2470
2471 /* NOTE : This function should not be modified, when the callback is needed,
2472 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2473 */
2474 }
2475
2476 /**
2477 * @brief Tx Half Transfer completed callback.
2478 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2479 * the configuration information for SPI module.
2480 * @retval None
2481 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2482 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2483 {
2484 /* Prevent unused argument(s) compilation warning */
2485 UNUSED(hspi);
2486
2487 /* NOTE : This function should not be modified, when the callback is needed,
2488 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2489 */
2490 }
2491
2492 /**
2493 * @brief Rx Half Transfer completed callback.
2494 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2495 * the configuration information for SPI module.
2496 * @retval None
2497 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2498 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2499 {
2500 /* Prevent unused argument(s) compilation warning */
2501 UNUSED(hspi);
2502
2503 /* NOTE : This function should not be modified, when the callback is needed,
2504 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2505 */
2506 }
2507
2508 /**
2509 * @brief Tx and Rx Half Transfer callback.
2510 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2511 * the configuration information for SPI module.
2512 * @retval None
2513 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2514 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2515 {
2516 /* Prevent unused argument(s) compilation warning */
2517 UNUSED(hspi);
2518
2519 /* NOTE : This function should not be modified, when the callback is needed,
2520 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2521 */
2522 }
2523
2524 /**
2525 * @brief SPI error callback.
2526 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2527 * the configuration information for SPI module.
2528 * @retval None
2529 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2530 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2531 {
2532 /* Prevent unused argument(s) compilation warning */
2533 UNUSED(hspi);
2534
2535 /* NOTE : This function should not be modified, when the callback is needed,
2536 the HAL_SPI_ErrorCallback should be implemented in the user file
2537 */
2538 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2539 and user can use HAL_SPI_GetError() API to check the latest error occurred
2540 */
2541 }
2542
2543 /**
2544 * @brief SPI Abort Complete callback.
2545 * @param hspi SPI handle.
2546 * @retval None
2547 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2548 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2549 {
2550 /* Prevent unused argument(s) compilation warning */
2551 UNUSED(hspi);
2552
2553 /* NOTE : This function should not be modified, when the callback is needed,
2554 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2555 */
2556 }
2557
2558 /**
2559 * @}
2560 */
2561
2562 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2563 * @brief SPI control functions
2564 *
2565 @verbatim
2566 ===============================================================================
2567 ##### Peripheral State and Errors functions #####
2568 ===============================================================================
2569 [..]
2570 This subsection provides a set of functions allowing to control the SPI.
2571 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2572 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2573 @endverbatim
2574 * @{
2575 */
2576
2577 /**
2578 * @brief Return the SPI handle state.
2579 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2580 * the configuration information for SPI module.
2581 * @retval SPI state
2582 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2583 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2584 {
2585 /* Return SPI handle state */
2586 return hspi->State;
2587 }
2588
2589 /**
2590 * @brief Return the SPI error code.
2591 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2592 * the configuration information for SPI module.
2593 * @retval SPI error code in bitmap format
2594 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2595 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2596 {
2597 /* Return SPI ErrorCode */
2598 return hspi->ErrorCode;
2599 }
2600
2601 /**
2602 * @}
2603 */
2604
2605 /**
2606 * @}
2607 */
2608
2609 /** @addtogroup SPI_Private_Functions
2610 * @brief Private functions
2611 * @{
2612 */
2613
2614 /**
2615 * @brief DMA SPI transmit process complete callback.
2616 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2617 * the configuration information for the specified DMA module.
2618 * @retval None
2619 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2620 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2621 {
2622 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2623 uint32_t tickstart;
2624
2625 /* Init tickstart for timeout management*/
2626 tickstart = HAL_GetTick();
2627
2628 /* DMA Normal Mode */
2629 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
2630 {
2631 /* Disable ERR interrupt */
2632 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2633
2634 /* Disable Tx DMA Request */
2635 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2636
2637 /* Check the end of the transaction */
2638 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2639 {
2640 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2641 }
2642
2643 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2644 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2645 {
2646 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2647 }
2648
2649 hspi->TxXferCount = 0U;
2650 hspi->State = HAL_SPI_STATE_READY;
2651
2652 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2653 {
2654 /* Call user error callback */
2655 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2656 hspi->ErrorCallback(hspi);
2657 #else
2658 HAL_SPI_ErrorCallback(hspi);
2659 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2660 return;
2661 }
2662 }
2663 /* Call user Tx complete callback */
2664 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2665 hspi->TxCpltCallback(hspi);
2666 #else
2667 HAL_SPI_TxCpltCallback(hspi);
2668 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2669 }
2670
2671 /**
2672 * @brief DMA SPI receive process complete callback.
2673 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2674 * the configuration information for the specified DMA module.
2675 * @retval None
2676 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)2677 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2678 {
2679 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2680 uint32_t tickstart;
2681
2682 /* Init tickstart for timeout management*/
2683 tickstart = HAL_GetTick();
2684
2685 /* DMA Normal Mode */
2686 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
2687 {
2688 /* Disable ERR interrupt */
2689 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2690
2691 #if (USE_SPI_CRC != 0U)
2692 /* CRC handling */
2693 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2694 {
2695 /* Wait until RXNE flag */
2696 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2697 {
2698 /* Error on the CRC reception */
2699 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2700 }
2701 /* Read CRC */
2702 READ_REG(hspi->Instance->DR);
2703 }
2704 #endif /* USE_SPI_CRC */
2705
2706 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
2707 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2708
2709 /* Check the end of the transaction */
2710 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2711 {
2712 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
2713 }
2714
2715 hspi->RxXferCount = 0U;
2716 hspi->State = HAL_SPI_STATE_READY;
2717
2718 #if (USE_SPI_CRC != 0U)
2719 /* Check if CRC error occurred */
2720 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
2721 {
2722 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2723 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2724 }
2725 #endif /* USE_SPI_CRC */
2726
2727 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2728 {
2729 /* Call user error callback */
2730 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2731 hspi->ErrorCallback(hspi);
2732 #else
2733 HAL_SPI_ErrorCallback(hspi);
2734 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2735 return;
2736 }
2737 }
2738 /* Call user Rx complete callback */
2739 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2740 hspi->RxCpltCallback(hspi);
2741 #else
2742 HAL_SPI_RxCpltCallback(hspi);
2743 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2744 }
2745
2746 /**
2747 * @brief DMA SPI transmit receive process complete callback.
2748 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2749 * the configuration information for the specified DMA module.
2750 * @retval None
2751 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)2752 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2753 {
2754 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2755 uint32_t tickstart;
2756
2757 /* Init tickstart for timeout management*/
2758 tickstart = HAL_GetTick();
2759
2760 /* DMA Normal Mode */
2761 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
2762 {
2763 /* Disable ERR interrupt */
2764 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2765
2766 #if (USE_SPI_CRC != 0U)
2767 /* CRC handling */
2768 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2769 {
2770 /* Wait the CRC data */
2771 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2772 {
2773 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2774 }
2775 /* Read CRC to Flush DR and RXNE flag */
2776 READ_REG(hspi->Instance->DR);
2777 }
2778 #endif /* USE_SPI_CRC */
2779
2780 /* Check the end of the transaction */
2781 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2782 {
2783 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2784 }
2785
2786 /* Disable Rx/Tx DMA Request */
2787 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2788
2789 hspi->TxXferCount = 0U;
2790 hspi->RxXferCount = 0U;
2791 hspi->State = HAL_SPI_STATE_READY;
2792
2793 #if (USE_SPI_CRC != 0U)
2794 /* Check if CRC error occurred */
2795 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
2796 {
2797 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2798 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2799 }
2800 #endif /* USE_SPI_CRC */
2801
2802 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2803 {
2804 /* Call user error callback */
2805 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2806 hspi->ErrorCallback(hspi);
2807 #else
2808 HAL_SPI_ErrorCallback(hspi);
2809 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2810 return;
2811 }
2812 }
2813 /* Call user TxRx complete callback */
2814 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2815 hspi->TxRxCpltCallback(hspi);
2816 #else
2817 HAL_SPI_TxRxCpltCallback(hspi);
2818 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2819 }
2820
2821 /**
2822 * @brief DMA SPI half transmit process complete callback.
2823 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2824 * the configuration information for the specified DMA module.
2825 * @retval None
2826 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)2827 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2828 {
2829 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2830
2831 /* Call user Tx half complete callback */
2832 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2833 hspi->TxHalfCpltCallback(hspi);
2834 #else
2835 HAL_SPI_TxHalfCpltCallback(hspi);
2836 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2837 }
2838
2839 /**
2840 * @brief DMA SPI half receive process complete callback
2841 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2842 * the configuration information for the specified DMA module.
2843 * @retval None
2844 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)2845 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2846 {
2847 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2848
2849 /* Call user Rx half complete callback */
2850 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2851 hspi->RxHalfCpltCallback(hspi);
2852 #else
2853 HAL_SPI_RxHalfCpltCallback(hspi);
2854 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2855 }
2856
2857 /**
2858 * @brief DMA SPI half transmit receive process complete callback.
2859 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2860 * the configuration information for the specified DMA module.
2861 * @retval None
2862 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)2863 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2864 {
2865 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2866
2867 /* Call user TxRx half complete callback */
2868 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2869 hspi->TxRxHalfCpltCallback(hspi);
2870 #else
2871 HAL_SPI_TxRxHalfCpltCallback(hspi);
2872 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2873 }
2874
2875 /**
2876 * @brief DMA SPI communication error callback.
2877 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2878 * the configuration information for the specified DMA module.
2879 * @retval None
2880 */
SPI_DMAError(DMA_HandleTypeDef * hdma)2881 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2882 {
2883 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2884
2885 /* Stop the disable DMA transfer on SPI side */
2886 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2887
2888 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2889 hspi->State = HAL_SPI_STATE_READY;
2890 /* Call user error callback */
2891 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2892 hspi->ErrorCallback(hspi);
2893 #else
2894 HAL_SPI_ErrorCallback(hspi);
2895 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2896 }
2897
2898 /**
2899 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
2900 * (To be called at end of DMA Abort procedure following error occurrence).
2901 * @param hdma DMA handle.
2902 * @retval None
2903 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)2904 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
2905 {
2906 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2907 hspi->RxXferCount = 0U;
2908 hspi->TxXferCount = 0U;
2909
2910 /* Call user error callback */
2911 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2912 hspi->ErrorCallback(hspi);
2913 #else
2914 HAL_SPI_ErrorCallback(hspi);
2915 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2916 }
2917
2918 /**
2919 * @brief DMA SPI Tx communication abort callback, when initiated by user
2920 * (To be called at end of DMA Tx Abort procedure following user abort request).
2921 * @note When this callback is executed, User Abort complete call back is called only if no
2922 * Abort still ongoing for Rx DMA Handle.
2923 * @param hdma DMA handle.
2924 * @retval None
2925 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)2926 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
2927 {
2928 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2929 __IO uint32_t count;
2930
2931 hspi->hdmatx->XferAbortCallback = NULL;
2932 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2933
2934 /* Disable Tx DMA Request */
2935 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2936
2937 /* Wait until TXE flag is set */
2938 do
2939 {
2940 if (count == 0U)
2941 {
2942 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2943 break;
2944 }
2945 count--;
2946 }
2947 while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2948
2949 /* Check if an Abort process is still ongoing */
2950 if (hspi->hdmarx != NULL)
2951 {
2952 if (hspi->hdmarx->XferAbortCallback != NULL)
2953 {
2954 return;
2955 }
2956 }
2957
2958 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
2959 hspi->RxXferCount = 0U;
2960 hspi->TxXferCount = 0U;
2961
2962 /* Check no error during Abort procedure */
2963 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
2964 {
2965 /* Reset errorCode */
2966 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2967 }
2968
2969 /* Clear the Error flags in the SR register */
2970 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2971 __HAL_SPI_CLEAR_FREFLAG(hspi);
2972
2973 /* Restore hspi->State to Ready */
2974 hspi->State = HAL_SPI_STATE_READY;
2975
2976 /* Call user Abort complete callback */
2977 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2978 hspi->AbortCpltCallback(hspi);
2979 #else
2980 HAL_SPI_AbortCpltCallback(hspi);
2981 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2982 }
2983
2984 /**
2985 * @brief DMA SPI Rx communication abort callback, when initiated by user
2986 * (To be called at end of DMA Rx Abort procedure following user abort request).
2987 * @note When this callback is executed, User Abort complete call back is called only if no
2988 * Abort still ongoing for Tx DMA Handle.
2989 * @param hdma DMA handle.
2990 * @retval None
2991 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)2992 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
2993 {
2994 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2995
2996 /* Disable SPI Peripheral */
2997 __HAL_SPI_DISABLE(hspi);
2998
2999 hspi->hdmarx->XferAbortCallback = NULL;
3000
3001 /* Disable Rx DMA Request */
3002 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3003
3004 /* Check Busy flag */
3005 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3006 {
3007 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3008 }
3009
3010 /* Check if an Abort process is still ongoing */
3011 if (hspi->hdmatx != NULL)
3012 {
3013 if (hspi->hdmatx->XferAbortCallback != NULL)
3014 {
3015 return;
3016 }
3017 }
3018
3019 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3020 hspi->RxXferCount = 0U;
3021 hspi->TxXferCount = 0U;
3022
3023 /* Check no error during Abort procedure */
3024 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3025 {
3026 /* Reset errorCode */
3027 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3028 }
3029
3030 /* Clear the Error flags in the SR register */
3031 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3032 __HAL_SPI_CLEAR_FREFLAG(hspi);
3033
3034 /* Restore hspi->State to Ready */
3035 hspi->State = HAL_SPI_STATE_READY;
3036
3037 /* Call user Abort complete callback */
3038 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3039 hspi->AbortCpltCallback(hspi);
3040 #else
3041 HAL_SPI_AbortCpltCallback(hspi);
3042 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3043 }
3044
3045 /**
3046 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3047 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3048 * the configuration information for SPI module.
3049 * @retval None
3050 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3051 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3052 {
3053 /* Receive data in 8bit mode */
3054 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3055 hspi->pRxBuffPtr++;
3056 hspi->RxXferCount--;
3057
3058 /* Check end of the reception */
3059 if (hspi->RxXferCount == 0U)
3060 {
3061 #if (USE_SPI_CRC != 0U)
3062 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3063 {
3064 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3065 return;
3066 }
3067 #endif /* USE_SPI_CRC */
3068
3069 /* Disable RXNE and ERR interrupt */
3070 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3071
3072 if (hspi->TxXferCount == 0U)
3073 {
3074 SPI_CloseRxTx_ISR(hspi);
3075 }
3076 }
3077 }
3078
3079 #if (USE_SPI_CRC != 0U)
3080 /**
3081 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3082 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3083 * the configuration information for SPI module.
3084 * @retval None
3085 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3086 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3087 {
3088 /* Read 8bit CRC to flush Data Regsiter */
3089 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3090
3091 /* Disable RXNE and ERR interrupt */
3092 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3093
3094 if (hspi->TxXferCount == 0U)
3095 {
3096 SPI_CloseRxTx_ISR(hspi);
3097 }
3098 }
3099 #endif /* USE_SPI_CRC */
3100
3101 /**
3102 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3103 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3104 * the configuration information for SPI module.
3105 * @retval None
3106 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3107 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3108 {
3109 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3110 hspi->pTxBuffPtr++;
3111 hspi->TxXferCount--;
3112
3113 /* Check the end of the transmission */
3114 if (hspi->TxXferCount == 0U)
3115 {
3116 #if (USE_SPI_CRC != 0U)
3117 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3118 {
3119 /* Set CRC Next Bit to send CRC */
3120 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3121 /* Disable TXE interrupt */
3122 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3123 return;
3124 }
3125 #endif /* USE_SPI_CRC */
3126
3127 /* Disable TXE interrupt */
3128 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3129
3130 if (hspi->RxXferCount == 0U)
3131 {
3132 SPI_CloseRxTx_ISR(hspi);
3133 }
3134 }
3135 }
3136
3137 /**
3138 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3139 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3140 * the configuration information for SPI module.
3141 * @retval None
3142 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3143 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3144 {
3145 /* Receive data in 16 Bit mode */
3146 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3147 hspi->pRxBuffPtr += sizeof(uint16_t);
3148 hspi->RxXferCount--;
3149
3150 if (hspi->RxXferCount == 0U)
3151 {
3152 #if (USE_SPI_CRC != 0U)
3153 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3154 {
3155 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3156 return;
3157 }
3158 #endif /* USE_SPI_CRC */
3159
3160 /* Disable RXNE interrupt */
3161 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3162
3163 if (hspi->TxXferCount == 0U)
3164 {
3165 SPI_CloseRxTx_ISR(hspi);
3166 }
3167 }
3168 }
3169
3170 #if (USE_SPI_CRC != 0U)
3171 /**
3172 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3173 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3174 * the configuration information for SPI module.
3175 * @retval None
3176 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3177 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3178 {
3179 /* Read 16bit CRC to flush Data Regsiter */
3180 READ_REG(hspi->Instance->DR);
3181
3182 /* Disable RXNE interrupt */
3183 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3184
3185 SPI_CloseRxTx_ISR(hspi);
3186 }
3187 #endif /* USE_SPI_CRC */
3188
3189 /**
3190 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3191 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3192 * the configuration information for SPI module.
3193 * @retval None
3194 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3195 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3196 {
3197 /* Transmit data in 16 Bit mode */
3198 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3199 hspi->pTxBuffPtr += sizeof(uint16_t);
3200 hspi->TxXferCount--;
3201
3202 /* Enable CRC Transmission */
3203 if (hspi->TxXferCount == 0U)
3204 {
3205 #if (USE_SPI_CRC != 0U)
3206 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3207 {
3208 /* Set CRC Next Bit to send CRC */
3209 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3210 /* Disable TXE interrupt */
3211 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3212 return;
3213 }
3214 #endif /* USE_SPI_CRC */
3215
3216 /* Disable TXE interrupt */
3217 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3218
3219 if (hspi->RxXferCount == 0U)
3220 {
3221 SPI_CloseRxTx_ISR(hspi);
3222 }
3223 }
3224 }
3225
3226 #if (USE_SPI_CRC != 0U)
3227 /**
3228 * @brief Manage the CRC 8-bit receive in Interrupt context.
3229 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3230 * the configuration information for SPI module.
3231 * @retval None
3232 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3233 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3234 {
3235 /* Read 8bit CRC to flush Data Register */
3236 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3237
3238 SPI_CloseRx_ISR(hspi);
3239 }
3240 #endif /* USE_SPI_CRC */
3241
3242 /**
3243 * @brief Manage the receive 8-bit in Interrupt context.
3244 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3245 * the configuration information for SPI module.
3246 * @retval None
3247 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3248 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3249 {
3250 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3251 hspi->pRxBuffPtr++;
3252 hspi->RxXferCount--;
3253
3254 #if (USE_SPI_CRC != 0U)
3255 /* Enable CRC Transmission */
3256 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3257 {
3258 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3259 }
3260 #endif /* USE_SPI_CRC */
3261
3262 if (hspi->RxXferCount == 0U)
3263 {
3264 #if (USE_SPI_CRC != 0U)
3265 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3266 {
3267 hspi->RxISR = SPI_RxISR_8BITCRC;
3268 return;
3269 }
3270 #endif /* USE_SPI_CRC */
3271 SPI_CloseRx_ISR(hspi);
3272 }
3273 }
3274
3275 #if (USE_SPI_CRC != 0U)
3276 /**
3277 * @brief Manage the CRC 16-bit receive in Interrupt context.
3278 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3279 * the configuration information for SPI module.
3280 * @retval None
3281 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3282 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3283 {
3284 /* Read 16bit CRC to flush Data Register */
3285 READ_REG(hspi->Instance->DR);
3286
3287 /* Disable RXNE and ERR interrupt */
3288 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3289
3290 SPI_CloseRx_ISR(hspi);
3291 }
3292 #endif /* USE_SPI_CRC */
3293
3294 /**
3295 * @brief Manage the 16-bit receive in Interrupt context.
3296 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3297 * the configuration information for SPI module.
3298 * @retval None
3299 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3300 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3301 {
3302 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3303 hspi->pRxBuffPtr += sizeof(uint16_t);
3304 hspi->RxXferCount--;
3305
3306 #if (USE_SPI_CRC != 0U)
3307 /* Enable CRC Transmission */
3308 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3309 {
3310 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3311 }
3312 #endif /* USE_SPI_CRC */
3313
3314 if (hspi->RxXferCount == 0U)
3315 {
3316 #if (USE_SPI_CRC != 0U)
3317 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3318 {
3319 hspi->RxISR = SPI_RxISR_16BITCRC;
3320 return;
3321 }
3322 #endif /* USE_SPI_CRC */
3323 SPI_CloseRx_ISR(hspi);
3324 }
3325 }
3326
3327 /**
3328 * @brief Handle the data 8-bit transmit in Interrupt mode.
3329 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3330 * the configuration information for SPI module.
3331 * @retval None
3332 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3333 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3334 {
3335 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3336 hspi->pTxBuffPtr++;
3337 hspi->TxXferCount--;
3338
3339 if (hspi->TxXferCount == 0U)
3340 {
3341 #if (USE_SPI_CRC != 0U)
3342 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3343 {
3344 /* Enable CRC Transmission */
3345 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3346 }
3347 #endif /* USE_SPI_CRC */
3348 SPI_CloseTx_ISR(hspi);
3349 }
3350 }
3351
3352 /**
3353 * @brief Handle the data 16-bit transmit in Interrupt mode.
3354 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3355 * the configuration information for SPI module.
3356 * @retval None
3357 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3358 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3359 {
3360 /* Transmit data in 16 Bit mode */
3361 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3362 hspi->pTxBuffPtr += sizeof(uint16_t);
3363 hspi->TxXferCount--;
3364
3365 if (hspi->TxXferCount == 0U)
3366 {
3367 #if (USE_SPI_CRC != 0U)
3368 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3369 {
3370 /* Enable CRC Transmission */
3371 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3372 }
3373 #endif /* USE_SPI_CRC */
3374 SPI_CloseTx_ISR(hspi);
3375 }
3376 }
3377
3378 /**
3379 * @brief Handle SPI Communication Timeout.
3380 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3381 * the configuration information for SPI module.
3382 * @param Flag SPI flag to check
3383 * @param State flag state to check
3384 * @param Timeout Timeout duration
3385 * @param Tickstart tick start value
3386 * @retval HAL status
3387 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3388 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3389 uint32_t Timeout, uint32_t Tickstart)
3390 {
3391 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3392 {
3393 if (Timeout != HAL_MAX_DELAY)
3394 {
3395 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3396 {
3397 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3398 on both master and slave sides in order to resynchronize the master
3399 and slave for their respective CRC calculation */
3400
3401 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3402 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3403
3404 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3405 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3406 {
3407 /* Disable SPI peripheral */
3408 __HAL_SPI_DISABLE(hspi);
3409 }
3410
3411 /* Reset CRC Calculation */
3412 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3413 {
3414 SPI_RESET_CRC(hspi);
3415 }
3416
3417 hspi->State = HAL_SPI_STATE_READY;
3418
3419 /* Process Unlocked */
3420 __HAL_UNLOCK(hspi);
3421
3422 return HAL_TIMEOUT;
3423 }
3424 }
3425 }
3426
3427 return HAL_OK;
3428 }
3429
3430 /**
3431 * @brief Handle the check of the RX transaction complete.
3432 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3433 * the configuration information for SPI module.
3434 * @param Timeout Timeout duration
3435 * @param Tickstart tick start value
3436 * @retval HAL status
3437 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3438 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3439 {
3440 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3441 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3442 {
3443 /* Disable SPI peripheral */
3444 __HAL_SPI_DISABLE(hspi);
3445 }
3446
3447 /* Control the BSY flag */
3448 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3449 {
3450 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3451 return HAL_TIMEOUT;
3452 }
3453 return HAL_OK;
3454 }
3455
3456 /**
3457 * @brief Handle the check of the RXTX or TX transaction complete.
3458 * @param hspi SPI handle
3459 * @param Timeout Timeout duration
3460 * @param Tickstart tick start value
3461 * @retval HAL status
3462 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3463 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3464 {
3465 /* Control the BSY flag */
3466 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3467 {
3468 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3469 return HAL_TIMEOUT;
3470 }
3471 return HAL_OK;
3472 }
3473
3474 /**
3475 * @brief Handle the end of the RXTX transaction.
3476 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3477 * the configuration information for SPI module.
3478 * @retval None
3479 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)3480 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3481 {
3482 uint32_t tickstart;
3483 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3484
3485 /* Init tickstart for timeout managment*/
3486 tickstart = HAL_GetTick();
3487
3488 /* Disable ERR interrupt */
3489 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3490
3491 /* Wait until TXE flag is set */
3492 do
3493 {
3494 if (count == 0U)
3495 {
3496 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3497 break;
3498 }
3499 count--;
3500 }
3501 while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3502
3503 /* Check the end of the transaction */
3504 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3505 {
3506 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3507 }
3508
3509 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3510 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3511 {
3512 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3513 }
3514
3515 #if (USE_SPI_CRC != 0U)
3516 /* Check if CRC error occurred */
3517 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3518 {
3519 hspi->State = HAL_SPI_STATE_READY;
3520 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3521 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3522 /* Call user error callback */
3523 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3524 hspi->ErrorCallback(hspi);
3525 #else
3526 HAL_SPI_ErrorCallback(hspi);
3527 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3528 }
3529 else
3530 {
3531 #endif /* USE_SPI_CRC */
3532 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3533 {
3534 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
3535 {
3536 hspi->State = HAL_SPI_STATE_READY;
3537 /* Call user Rx complete callback */
3538 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3539 hspi->RxCpltCallback(hspi);
3540 #else
3541 HAL_SPI_RxCpltCallback(hspi);
3542 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3543 }
3544 else
3545 {
3546 hspi->State = HAL_SPI_STATE_READY;
3547 /* Call user TxRx complete callback */
3548 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3549 hspi->TxRxCpltCallback(hspi);
3550 #else
3551 HAL_SPI_TxRxCpltCallback(hspi);
3552 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3553 }
3554 }
3555 else
3556 {
3557 hspi->State = HAL_SPI_STATE_READY;
3558 /* Call user error callback */
3559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3560 hspi->ErrorCallback(hspi);
3561 #else
3562 HAL_SPI_ErrorCallback(hspi);
3563 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3564 }
3565 #if (USE_SPI_CRC != 0U)
3566 }
3567 #endif /* USE_SPI_CRC */
3568 }
3569
3570 /**
3571 * @brief Handle the end of the RX transaction.
3572 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3573 * the configuration information for SPI module.
3574 * @retval None
3575 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)3576 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
3577 {
3578 /* Disable RXNE and ERR interrupt */
3579 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3580
3581 /* Check the end of the transaction */
3582 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3583 {
3584 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3585 }
3586
3587 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3588 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3589 {
3590 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3591 }
3592 hspi->State = HAL_SPI_STATE_READY;
3593
3594 #if (USE_SPI_CRC != 0U)
3595 /* Check if CRC error occurred */
3596 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3597 {
3598 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3599 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3600 /* Call user error callback */
3601 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3602 hspi->ErrorCallback(hspi);
3603 #else
3604 HAL_SPI_ErrorCallback(hspi);
3605 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3606 }
3607 else
3608 {
3609 #endif /* USE_SPI_CRC */
3610 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3611 {
3612 /* Call user Rx complete callback */
3613 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3614 hspi->RxCpltCallback(hspi);
3615 #else
3616 HAL_SPI_RxCpltCallback(hspi);
3617 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3618 }
3619 else
3620 {
3621 /* Call user error callback */
3622 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3623 hspi->ErrorCallback(hspi);
3624 #else
3625 HAL_SPI_ErrorCallback(hspi);
3626 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3627 }
3628 #if (USE_SPI_CRC != 0U)
3629 }
3630 #endif /* USE_SPI_CRC */
3631 }
3632
3633 /**
3634 * @brief Handle the end of the TX transaction.
3635 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3636 * the configuration information for SPI module.
3637 * @retval None
3638 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)3639 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
3640 {
3641 uint32_t tickstart;
3642 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3643
3644 /* Init tickstart for timeout management*/
3645 tickstart = HAL_GetTick();
3646
3647 /* Wait until TXE flag is set */
3648 do
3649 {
3650 if (count == 0U)
3651 {
3652 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3653 break;
3654 }
3655 count--;
3656 }
3657 while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3658
3659 /* Disable TXE and ERR interrupt */
3660 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
3661
3662 /* Check the end of the transaction */
3663 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3664 {
3665 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3666 }
3667
3668 /* Clear overrun flag in 2 Lines communication mode because received is not read */
3669 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3670 {
3671 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3672 }
3673
3674 hspi->State = HAL_SPI_STATE_READY;
3675 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3676 {
3677 /* Call user error callback */
3678 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3679 hspi->ErrorCallback(hspi);
3680 #else
3681 HAL_SPI_ErrorCallback(hspi);
3682 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3683 }
3684 else
3685 {
3686 /* Call user Rx complete callback */
3687 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3688 hspi->TxCpltCallback(hspi);
3689 #else
3690 HAL_SPI_TxCpltCallback(hspi);
3691 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3692 }
3693 }
3694
3695 /**
3696 * @brief Handle abort a Rx transaction.
3697 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3698 * the configuration information for SPI module.
3699 * @retval None
3700 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)3701 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
3702 {
3703 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3704
3705 /* Wait until TXE flag is set */
3706 do
3707 {
3708 if (count == 0U)
3709 {
3710 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3711 break;
3712 }
3713 count--;
3714 }
3715 while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3716
3717 /* Disable SPI Peripheral */
3718 __HAL_SPI_DISABLE(hspi);
3719
3720 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3721 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3722
3723 /* Read CRC to flush Data Register */
3724 READ_REG(hspi->Instance->DR);
3725
3726 hspi->State = HAL_SPI_STATE_ABORT;
3727 }
3728
3729 /**
3730 * @brief Handle abort a Tx or Rx/Tx transaction.
3731 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3732 * the configuration information for SPI module.
3733 * @retval None
3734 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)3735 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
3736 {
3737 /* Disable TXEIE interrupt */
3738 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
3739
3740 /* Disable SPI Peripheral */
3741 __HAL_SPI_DISABLE(hspi);
3742
3743 hspi->State = HAL_SPI_STATE_ABORT;
3744 }
3745
3746 /**
3747 * @}
3748 */
3749
3750 #endif /* HAL_SPI_MODULE_ENABLED */
3751
3752 /**
3753 * @}
3754 */
3755
3756 /**
3757 * @}
3758 */
3759
3760 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3761