1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F4xx_HAL_TIM_H 22 #define STM32F4xx_HAL_TIM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TIM_Exported_Types TIM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TIM Time base Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 58 59 uint32_t ClockDivision; /*!< Specifies the clock division. 60 This parameter can be a value of @ref TIM_ClockDivision */ 61 62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 63 reaches zero, an update event is generated and counting restarts 64 from the RCR value (N). 65 This means in PWM mode that (N+1) corresponds to: 66 - the number of PWM periods in edge-aligned mode 67 - the number of half PWM period in center-aligned mode 68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 70 71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 72 This parameter can be a value of @ref TIM_AutoReloadPreload */ 73 } TIM_Base_InitTypeDef; 74 75 /** 76 * @brief TIM Output Compare Configuration Structure definition 77 */ 78 typedef struct 79 { 80 uint32_t OCMode; /*!< Specifies the TIM mode. 81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 82 83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 85 86 uint32_t OCPolarity; /*!< Specifies the output polarity. 87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 88 89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 91 @note This parameter is valid only for timer instances supporting break feature. */ 92 93 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 94 This parameter can be a value of @ref TIM_Output_Fast_State 95 @note This parameter is valid only in PWM1 and PWM2 mode. */ 96 97 98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 100 @note This parameter is valid only for timer instances supporting break feature. */ 101 102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 104 @note This parameter is valid only for timer instances supporting break feature. */ 105 } TIM_OC_InitTypeDef; 106 107 /** 108 * @brief TIM One Pulse Mode Configuration Structure definition 109 */ 110 typedef struct 111 { 112 uint32_t OCMode; /*!< Specifies the TIM mode. 113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 114 115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 117 118 uint32_t OCPolarity; /*!< Specifies the output polarity. 119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 120 121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 123 @note This parameter is valid only for timer instances supporting break feature. */ 124 125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 127 @note This parameter is valid only for timer instances supporting break feature. */ 128 129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 131 @note This parameter is valid only for timer instances supporting break feature. */ 132 133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 135 136 uint32_t ICSelection; /*!< Specifies the input. 137 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 138 139 uint32_t ICFilter; /*!< Specifies the input capture filter. 140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 141 } TIM_OnePulse_InitTypeDef; 142 143 /** 144 * @brief TIM Input Capture Configuration Structure definition 145 */ 146 typedef struct 147 { 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 150 151 uint32_t ICSelection; /*!< Specifies the input. 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 153 154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 156 157 uint32_t ICFilter; /*!< Specifies the input capture filter. 158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 159 } TIM_IC_InitTypeDef; 160 161 /** 162 * @brief TIM Encoder Configuration Structure definition 163 */ 164 typedef struct 165 { 166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 167 This parameter can be a value of @ref TIM_Encoder_Mode */ 168 169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 170 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 171 172 uint32_t IC1Selection; /*!< Specifies the input. 173 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 174 175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 177 178 uint32_t IC1Filter; /*!< Specifies the input capture filter. 179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 180 181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 182 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 183 184 uint32_t IC2Selection; /*!< Specifies the input. 185 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 186 187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 189 190 uint32_t IC2Filter; /*!< Specifies the input capture filter. 191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 192 } TIM_Encoder_InitTypeDef; 193 194 /** 195 * @brief Clock Configuration Handle Structure definition 196 */ 197 typedef struct 198 { 199 uint32_t ClockSource; /*!< TIM clock sources 200 This parameter can be a value of @ref TIM_Clock_Source */ 201 uint32_t ClockPolarity; /*!< TIM clock polarity 202 This parameter can be a value of @ref TIM_Clock_Polarity */ 203 uint32_t ClockPrescaler; /*!< TIM clock prescaler 204 This parameter can be a value of @ref TIM_Clock_Prescaler */ 205 uint32_t ClockFilter; /*!< TIM clock filter 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 207 } TIM_ClockConfigTypeDef; 208 209 /** 210 * @brief TIM Clear Input Configuration Handle Structure definition 211 */ 212 typedef struct 213 { 214 uint32_t ClearInputState; /*!< TIM clear Input state 215 This parameter can be ENABLE or DISABLE */ 216 uint32_t ClearInputSource; /*!< TIM clear Input sources 217 This parameter can be a value of @ref TIM_ClearInput_Source */ 218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 219 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 224 } TIM_ClearInputConfigTypeDef; 225 226 /** 227 * @brief TIM Master configuration Structure definition 228 */ 229 typedef struct 230 { 231 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 232 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 233 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 234 This parameter can be a value of @ref TIM_Master_Slave_Mode */ 235 } TIM_MasterConfigTypeDef; 236 237 /** 238 * @brief TIM Slave configuration Structure definition 239 */ 240 typedef struct 241 { 242 uint32_t SlaveMode; /*!< Slave mode selection 243 This parameter can be a value of @ref TIM_Slave_Mode */ 244 uint32_t InputTrigger; /*!< Input Trigger source 245 This parameter can be a value of @ref TIM_Trigger_Selection */ 246 uint32_t TriggerPolarity; /*!< Input Trigger polarity 247 This parameter can be a value of @ref TIM_Trigger_Polarity */ 248 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 249 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 250 uint32_t TriggerFilter; /*!< Input trigger filter 251 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 252 253 } TIM_SlaveConfigTypeDef; 254 255 /** 256 * @brief TIM Break input(s) and Dead time configuration Structure definition 257 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 258 * filter and polarity. 259 */ 260 typedef struct 261 { 262 uint32_t OffStateRunMode; /*!< TIM off state in run mode 263 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 264 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 265 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 266 uint32_t LockLevel; /*!< TIM Lock level 267 This parameter can be a value of @ref TIM_Lock_level */ 268 uint32_t DeadTime; /*!< TIM dead Time 269 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 270 uint32_t BreakState; /*!< TIM Break State 271 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 272 uint32_t BreakPolarity; /*!< TIM Break input polarity 273 This parameter can be a value of @ref TIM_Break_Polarity */ 274 uint32_t BreakFilter; /*!< Specifies the break input filter. 275 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 276 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 277 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 278 } TIM_BreakDeadTimeConfigTypeDef; 279 280 /** 281 * @brief HAL State structures definition 282 */ 283 typedef enum 284 { 285 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 286 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 287 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 288 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 289 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 290 } HAL_TIM_StateTypeDef; 291 292 /** 293 * @brief HAL Active channel structures definition 294 */ 295 typedef enum 296 { 297 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 298 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 299 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 300 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 301 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 302 } HAL_TIM_ActiveChannel; 303 304 /** 305 * @brief TIM Time Base Handle Structure definition 306 */ 307 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 308 typedef struct __TIM_HandleTypeDef 309 #else 310 typedef struct 311 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 312 { 313 TIM_TypeDef *Instance; /*!< Register base address */ 314 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 315 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 316 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 317 This array is accessed by a @ref DMA_Handle_index */ 318 HAL_LockTypeDef Lock; /*!< Locking object */ 319 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 320 321 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 322 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 323 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 324 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 325 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 326 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 327 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 328 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 329 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 330 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 331 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 332 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 333 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 334 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 335 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 336 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 337 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 338 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 339 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 340 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 341 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 342 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 343 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 344 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 345 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 346 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 347 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 348 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 349 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 350 } TIM_HandleTypeDef; 351 352 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 353 /** 354 * @brief HAL TIM Callback ID enumeration definition 355 */ 356 typedef enum 357 { 358 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 359 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 360 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 361 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 362 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 363 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 364 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 365 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 366 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 367 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 368 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 369 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 370 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 371 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 372 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 373 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 374 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 375 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 376 377 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 378 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 379 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 380 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 381 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 382 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 383 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 384 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 385 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 386 } HAL_TIM_CallbackIDTypeDef; 387 388 /** 389 * @brief HAL TIM Callback pointer definition 390 */ 391 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 392 393 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 394 395 /** 396 * @} 397 */ 398 /* End of exported types -----------------------------------------------------*/ 399 400 /* Exported constants --------------------------------------------------------*/ 401 /** @defgroup TIM_Exported_Constants TIM Exported Constants 402 * @{ 403 */ 404 405 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 406 * @{ 407 */ 408 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 409 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 415 * @{ 416 */ 417 #define TIM_DMABASE_CR1 0x00000000U 418 #define TIM_DMABASE_CR2 0x00000001U 419 #define TIM_DMABASE_SMCR 0x00000002U 420 #define TIM_DMABASE_DIER 0x00000003U 421 #define TIM_DMABASE_SR 0x00000004U 422 #define TIM_DMABASE_EGR 0x00000005U 423 #define TIM_DMABASE_CCMR1 0x00000006U 424 #define TIM_DMABASE_CCMR2 0x00000007U 425 #define TIM_DMABASE_CCER 0x00000008U 426 #define TIM_DMABASE_CNT 0x00000009U 427 #define TIM_DMABASE_PSC 0x0000000AU 428 #define TIM_DMABASE_ARR 0x0000000BU 429 #define TIM_DMABASE_RCR 0x0000000CU 430 #define TIM_DMABASE_CCR1 0x0000000DU 431 #define TIM_DMABASE_CCR2 0x0000000EU 432 #define TIM_DMABASE_CCR3 0x0000000FU 433 #define TIM_DMABASE_CCR4 0x00000010U 434 #define TIM_DMABASE_BDTR 0x00000011U 435 #define TIM_DMABASE_DCR 0x00000012U 436 #define TIM_DMABASE_DMAR 0x00000013U 437 /** 438 * @} 439 */ 440 441 /** @defgroup TIM_Event_Source TIM Event Source 442 * @{ 443 */ 444 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 445 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 446 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 447 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 448 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 449 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 450 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 451 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 452 /** 453 * @} 454 */ 455 456 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 457 * @{ 458 */ 459 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 460 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 461 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 467 * @{ 468 */ 469 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 470 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 471 /** 472 * @} 473 */ 474 475 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 476 * @{ 477 */ 478 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 479 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 480 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 481 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup TIM_Counter_Mode TIM Counter Mode 487 * @{ 488 */ 489 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 490 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 491 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 492 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 493 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup TIM_ClockDivision TIM Clock Division 499 * @{ 500 */ 501 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 502 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 503 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 504 /** 505 * @} 506 */ 507 508 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 509 * @{ 510 */ 511 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 512 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 518 * @{ 519 */ 520 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 521 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 522 523 /** 524 * @} 525 */ 526 527 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 528 * @{ 529 */ 530 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 531 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 537 * @{ 538 */ 539 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 540 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 546 * @{ 547 */ 548 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 549 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 555 * @{ 556 */ 557 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 558 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 564 * @{ 565 */ 566 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 567 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 573 * @{ 574 */ 575 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 576 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 582 * @{ 583 */ 584 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 585 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 586 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 587 /** 588 * @} 589 */ 590 591 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 592 * @{ 593 */ 594 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 595 connected to IC1, IC2, IC3 or IC4, respectively */ 596 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 597 connected to IC2, IC1, IC4 or IC3, respectively */ 598 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 604 * @{ 605 */ 606 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 607 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 608 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 609 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 610 /** 611 * @} 612 */ 613 614 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 615 * @{ 616 */ 617 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 618 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 624 * @{ 625 */ 626 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 627 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 628 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 634 * @{ 635 */ 636 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 637 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 638 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 639 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 640 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 641 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 642 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 643 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 644 /** 645 * @} 646 */ 647 648 /** @defgroup TIM_Commutation_Source TIM Commutation Source 649 * @{ 650 */ 651 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 652 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 653 /** 654 * @} 655 */ 656 657 /** @defgroup TIM_DMA_sources TIM DMA Sources 658 * @{ 659 */ 660 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 661 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 662 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 663 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 664 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 665 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 666 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 667 /** 668 * @} 669 */ 670 671 /** @defgroup TIM_Flag_definition TIM Flag Definition 672 * @{ 673 */ 674 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 675 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 676 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 677 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 678 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 679 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 680 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 681 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 682 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 683 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 684 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 685 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 686 /** 687 * @} 688 */ 689 690 /** @defgroup TIM_Channel TIM Channel 691 * @{ 692 */ 693 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 694 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 695 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 696 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 697 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup TIM_Clock_Source TIM Clock Source 703 * @{ 704 */ 705 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 706 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 707 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 708 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 709 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 710 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 711 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 712 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 713 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 714 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 715 /** 716 * @} 717 */ 718 719 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 720 * @{ 721 */ 722 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 723 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 724 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 725 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 726 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 727 /** 728 * @} 729 */ 730 731 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 732 * @{ 733 */ 734 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 735 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 736 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 737 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 738 /** 739 * @} 740 */ 741 742 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 743 * @{ 744 */ 745 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 746 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 747 /** 748 * @} 749 */ 750 751 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 752 * @{ 753 */ 754 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 755 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 756 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 757 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 758 /** 759 * @} 760 */ 761 762 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 763 * @{ 764 */ 765 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 766 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 767 /** 768 * @} 769 */ 770 771 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 772 * @{ 773 */ 774 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 775 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 776 /** 777 * @} 778 */ 779 /** @defgroup TIM_Lock_level TIM Lock level 780 * @{ 781 */ 782 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 783 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 784 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 785 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 786 /** 787 * @} 788 */ 789 790 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 791 * @{ 792 */ 793 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 794 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 800 * @{ 801 */ 802 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 803 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 804 /** 805 * @} 806 */ 807 808 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 809 * @{ 810 */ 811 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 812 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 813 (if none of the break inputs BRK and BRK2 is active) */ 814 /** 815 * @} 816 */ 817 818 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 819 * @{ 820 */ 821 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 822 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 823 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 824 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 825 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 826 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 827 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 828 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 829 /** 830 * @} 831 */ 832 833 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 834 * @{ 835 */ 836 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 837 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 838 /** 839 * @} 840 */ 841 842 /** @defgroup TIM_Slave_Mode TIM Slave mode 843 * @{ 844 */ 845 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 846 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 847 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 848 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 849 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 850 /** 851 * @} 852 */ 853 854 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 855 * @{ 856 */ 857 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 858 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 859 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 860 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 861 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 862 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 863 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 864 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 865 /** 866 * @} 867 */ 868 869 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 870 * @{ 871 */ 872 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 873 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 874 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 875 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 876 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 877 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 878 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 879 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 880 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 881 /** 882 * @} 883 */ 884 885 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 886 * @{ 887 */ 888 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 889 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 890 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 891 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 892 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 893 /** 894 * @} 895 */ 896 897 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 898 * @{ 899 */ 900 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 901 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 902 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 903 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 904 /** 905 * @} 906 */ 907 908 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 909 * @{ 910 */ 911 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 912 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 913 /** 914 * @} 915 */ 916 917 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 918 * @{ 919 */ 920 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 921 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 922 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 923 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 924 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 925 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 926 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 927 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 928 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 929 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 930 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 931 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 932 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 933 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 934 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 935 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 936 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 937 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 938 /** 939 * @} 940 */ 941 942 /** @defgroup DMA_Handle_index TIM DMA Handle Index 943 * @{ 944 */ 945 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 946 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 947 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 948 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 949 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 950 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 951 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 952 /** 953 * @} 954 */ 955 956 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 957 * @{ 958 */ 959 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 960 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 961 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 962 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 963 /** 964 * @} 965 */ 966 967 /** 968 * @} 969 */ 970 /* End of exported constants -------------------------------------------------*/ 971 972 /* Exported macros -----------------------------------------------------------*/ 973 /** @defgroup TIM_Exported_Macros TIM Exported Macros 974 * @{ 975 */ 976 977 /** @brief Reset TIM handle state. 978 * @param __HANDLE__ TIM handle. 979 * @retval None 980 */ 981 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 982 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 983 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 984 (__HANDLE__)->Base_MspInitCallback = NULL; \ 985 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 986 (__HANDLE__)->IC_MspInitCallback = NULL; \ 987 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 988 (__HANDLE__)->OC_MspInitCallback = NULL; \ 989 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 990 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 991 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 992 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 993 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 994 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 995 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 996 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 997 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 998 } while(0) 999 #else 1000 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1001 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1002 1003 /** 1004 * @brief Enable the TIM peripheral. 1005 * @param __HANDLE__ TIM handle 1006 * @retval None 1007 */ 1008 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1009 1010 /** 1011 * @brief Enable the TIM main Output. 1012 * @param __HANDLE__ TIM handle 1013 * @retval None 1014 */ 1015 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1016 1017 /** 1018 * @brief Disable the TIM peripheral. 1019 * @param __HANDLE__ TIM handle 1020 * @retval None 1021 */ 1022 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1023 do { \ 1024 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1025 { \ 1026 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1027 { \ 1028 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1029 } \ 1030 } \ 1031 } while(0) 1032 1033 /** 1034 * @brief Disable the TIM main Output. 1035 * @param __HANDLE__ TIM handle 1036 * @retval None 1037 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1038 */ 1039 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1040 do { \ 1041 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1042 { \ 1043 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1044 { \ 1045 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1046 } \ 1047 } \ 1048 } while(0) 1049 1050 /** 1051 * @brief Disable the TIM main Output. 1052 * @param __HANDLE__ TIM handle 1053 * @retval None 1054 * @note The Main Output Enable of a timer instance is disabled unconditionally 1055 */ 1056 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1057 1058 /** @brief Enable the specified TIM interrupt. 1059 * @param __HANDLE__ specifies the TIM Handle. 1060 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1061 * This parameter can be one of the following values: 1062 * @arg TIM_IT_UPDATE: Update interrupt 1063 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1064 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1065 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1066 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1067 * @arg TIM_IT_COM: Commutation interrupt 1068 * @arg TIM_IT_TRIGGER: Trigger interrupt 1069 * @arg TIM_IT_BREAK: Break interrupt 1070 * @retval None 1071 */ 1072 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1073 1074 /** @brief Disable the specified TIM interrupt. 1075 * @param __HANDLE__ specifies the TIM Handle. 1076 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1077 * This parameter can be one of the following values: 1078 * @arg TIM_IT_UPDATE: Update interrupt 1079 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1080 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1081 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1082 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1083 * @arg TIM_IT_COM: Commutation interrupt 1084 * @arg TIM_IT_TRIGGER: Trigger interrupt 1085 * @arg TIM_IT_BREAK: Break interrupt 1086 * @retval None 1087 */ 1088 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1089 1090 /** @brief Enable the specified DMA request. 1091 * @param __HANDLE__ specifies the TIM Handle. 1092 * @param __DMA__ specifies the TIM DMA request to enable. 1093 * This parameter can be one of the following values: 1094 * @arg TIM_DMA_UPDATE: Update DMA request 1095 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1096 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1097 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1098 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1099 * @arg TIM_DMA_COM: Commutation DMA request 1100 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1101 * @retval None 1102 */ 1103 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1104 1105 /** @brief Disable the specified DMA request. 1106 * @param __HANDLE__ specifies the TIM Handle. 1107 * @param __DMA__ specifies the TIM DMA request to disable. 1108 * This parameter can be one of the following values: 1109 * @arg TIM_DMA_UPDATE: Update DMA request 1110 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1111 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1112 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1113 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1114 * @arg TIM_DMA_COM: Commutation DMA request 1115 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1116 * @retval None 1117 */ 1118 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1119 1120 /** @brief Check whether the specified TIM interrupt flag is set or not. 1121 * @param __HANDLE__ specifies the TIM Handle. 1122 * @param __FLAG__ specifies the TIM interrupt flag to check. 1123 * This parameter can be one of the following values: 1124 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1125 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1126 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1127 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1128 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1129 * @arg TIM_FLAG_COM: Commutation interrupt flag 1130 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1131 * @arg TIM_FLAG_BREAK: Break interrupt flag 1132 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1133 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1134 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1135 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1136 * @retval The new state of __FLAG__ (TRUE or FALSE). 1137 */ 1138 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1139 1140 /** @brief Clear the specified TIM interrupt flag. 1141 * @param __HANDLE__ specifies the TIM Handle. 1142 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1143 * This parameter can be one of the following values: 1144 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1145 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1146 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1147 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1148 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1149 * @arg TIM_FLAG_COM: Commutation interrupt flag 1150 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1151 * @arg TIM_FLAG_BREAK: Break interrupt flag 1152 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1153 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1154 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1155 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1156 * @retval The new state of __FLAG__ (TRUE or FALSE). 1157 */ 1158 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1159 1160 /** 1161 * @brief Check whether the specified TIM interrupt source is enabled or not. 1162 * @param __HANDLE__ TIM handle 1163 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1164 * This parameter can be one of the following values: 1165 * @arg TIM_IT_UPDATE: Update interrupt 1166 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1167 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1168 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1169 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1170 * @arg TIM_IT_COM: Commutation interrupt 1171 * @arg TIM_IT_TRIGGER: Trigger interrupt 1172 * @arg TIM_IT_BREAK: Break interrupt 1173 * @retval The state of TIM_IT (SET or RESET). 1174 */ 1175 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 1176 1177 /** @brief Clear the TIM interrupt pending bits. 1178 * @param __HANDLE__ TIM handle 1179 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1180 * This parameter can be one of the following values: 1181 * @arg TIM_IT_UPDATE: Update interrupt 1182 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1183 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1184 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1185 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1186 * @arg TIM_IT_COM: Commutation interrupt 1187 * @arg TIM_IT_TRIGGER: Trigger interrupt 1188 * @arg TIM_IT_BREAK: Break interrupt 1189 * @retval None 1190 */ 1191 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1192 1193 /** 1194 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1195 * @param __HANDLE__ TIM handle. 1196 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1197 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1198 mode. 1199 */ 1200 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1201 1202 /** 1203 * @brief Set the TIM Prescaler on runtime. 1204 * @param __HANDLE__ TIM handle. 1205 * @param __PRESC__ specifies the Prescaler new value. 1206 * @retval None 1207 */ 1208 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1209 1210 /** 1211 * @brief Set the TIM Counter Register value on runtime. 1212 * @param __HANDLE__ TIM handle. 1213 * @param __COUNTER__ specifies the Counter register new value. 1214 * @retval None 1215 */ 1216 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1217 1218 /** 1219 * @brief Get the TIM Counter Register value on runtime. 1220 * @param __HANDLE__ TIM handle. 1221 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1222 */ 1223 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ 1224 ((__HANDLE__)->Instance->CNT) 1225 1226 /** 1227 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1228 * @param __HANDLE__ TIM handle. 1229 * @param __AUTORELOAD__ specifies the Counter register new value. 1230 * @retval None 1231 */ 1232 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1233 do{ \ 1234 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1235 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1236 } while(0) 1237 1238 /** 1239 * @brief Get the TIM Autoreload Register value on runtime. 1240 * @param __HANDLE__ TIM handle. 1241 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1242 */ 1243 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ 1244 ((__HANDLE__)->Instance->ARR) 1245 1246 /** 1247 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1248 * @param __HANDLE__ TIM handle. 1249 * @param __CKD__ specifies the clock division value. 1250 * This parameter can be one of the following value: 1251 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1252 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1253 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1254 * @retval None 1255 */ 1256 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1257 do{ \ 1258 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1259 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1260 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1261 } while(0) 1262 1263 /** 1264 * @brief Get the TIM Clock Division value on runtime. 1265 * @param __HANDLE__ TIM handle. 1266 * @retval The clock division can be one of the following values: 1267 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1268 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1269 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1270 */ 1271 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ 1272 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1273 1274 /** 1275 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1276 * @param __HANDLE__ TIM handle. 1277 * @param __CHANNEL__ TIM Channels to be configured. 1278 * This parameter can be one of the following values: 1279 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1280 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1281 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1282 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1283 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1284 * This parameter can be one of the following values: 1285 * @arg TIM_ICPSC_DIV1: no prescaler 1286 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1287 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1288 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1289 * @retval None 1290 */ 1291 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1292 do{ \ 1293 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1294 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1295 } while(0) 1296 1297 /** 1298 * @brief Get the TIM Input Capture prescaler on runtime. 1299 * @param __HANDLE__ TIM handle. 1300 * @param __CHANNEL__ TIM Channels to be configured. 1301 * This parameter can be one of the following values: 1302 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1303 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1304 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1305 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1306 * @retval The input capture prescaler can be one of the following values: 1307 * @arg TIM_ICPSC_DIV1: no prescaler 1308 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1309 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1310 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1311 */ 1312 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1313 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1314 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1315 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1316 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1317 1318 /** 1319 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1320 * @param __HANDLE__ TIM handle. 1321 * @param __CHANNEL__ TIM Channels to be configured. 1322 * This parameter can be one of the following values: 1323 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1324 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1325 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1326 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1327 * @param __COMPARE__ specifies the Capture Compare register new value. 1328 * @retval None 1329 */ 1330 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1331 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1332 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1333 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1334 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) 1335 1336 /** 1337 * @brief Get the TIM Capture Compare Register value on runtime. 1338 * @param __HANDLE__ TIM handle. 1339 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1340 * This parameter can be one of the following values: 1341 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1342 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1343 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1344 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1345 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1346 */ 1347 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1348 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1349 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1350 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1351 ((__HANDLE__)->Instance->CCR4)) 1352 1353 /** 1354 * @brief Set the TIM Output compare preload. 1355 * @param __HANDLE__ TIM handle. 1356 * @param __CHANNEL__ TIM Channels to be configured. 1357 * This parameter can be one of the following values: 1358 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1359 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1360 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1361 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1362 * @retval None 1363 */ 1364 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1365 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1366 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1367 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1368 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) 1369 1370 /** 1371 * @brief Reset the TIM Output compare preload. 1372 * @param __HANDLE__ TIM handle. 1373 * @param __CHANNEL__ TIM Channels to be configured. 1374 * This parameter can be one of the following values: 1375 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1376 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1377 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1378 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1379 * @retval None 1380 */ 1381 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1382 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ 1383 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ 1384 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ 1385 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) 1386 1387 /** 1388 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1389 * @param __HANDLE__ TIM handle. 1390 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1391 * overflow/underflow generates an update interrupt or DMA request (if 1392 * enabled) 1393 * @retval None 1394 */ 1395 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ 1396 ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1397 1398 /** 1399 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1400 * @param __HANDLE__ TIM handle. 1401 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1402 * following events generate an update interrupt or DMA request (if 1403 * enabled): 1404 * _ Counter overflow underflow 1405 * _ Setting the UG bit 1406 * _ Update generation through the slave mode controller 1407 * @retval None 1408 */ 1409 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ 1410 ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1411 1412 /** 1413 * @brief Set the TIM Capture x input polarity on runtime. 1414 * @param __HANDLE__ TIM handle. 1415 * @param __CHANNEL__ TIM Channels to be configured. 1416 * This parameter can be one of the following values: 1417 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1418 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1419 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1420 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1421 * @param __POLARITY__ Polarity for TIx source 1422 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1423 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1424 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1425 * @retval None 1426 */ 1427 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1428 do{ \ 1429 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1430 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1431 }while(0) 1432 1433 /** 1434 * @} 1435 */ 1436 /* End of exported macros ----------------------------------------------------*/ 1437 1438 /* Private constants ---------------------------------------------------------*/ 1439 /** @defgroup TIM_Private_Constants TIM Private Constants 1440 * @{ 1441 */ 1442 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1443 channels have been disabled */ 1444 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1445 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1446 /** 1447 * @} 1448 */ 1449 /* End of private constants --------------------------------------------------*/ 1450 1451 /* Private macros ------------------------------------------------------------*/ 1452 /** @defgroup TIM_Private_Macros TIM Private Macros 1453 * @{ 1454 */ 1455 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1456 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1457 1458 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1459 ((__BASE__) == TIM_DMABASE_CR2) || \ 1460 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1461 ((__BASE__) == TIM_DMABASE_DIER) || \ 1462 ((__BASE__) == TIM_DMABASE_SR) || \ 1463 ((__BASE__) == TIM_DMABASE_EGR) || \ 1464 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1465 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1466 ((__BASE__) == TIM_DMABASE_CCER) || \ 1467 ((__BASE__) == TIM_DMABASE_CNT) || \ 1468 ((__BASE__) == TIM_DMABASE_PSC) || \ 1469 ((__BASE__) == TIM_DMABASE_ARR) || \ 1470 ((__BASE__) == TIM_DMABASE_RCR) || \ 1471 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1472 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1473 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1474 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1475 ((__BASE__) == TIM_DMABASE_BDTR)) 1476 1477 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1478 1479 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1480 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1481 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1482 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1483 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1484 1485 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1486 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1487 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1488 1489 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1490 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1491 1492 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1493 ((__STATE__) == TIM_OCFAST_ENABLE)) 1494 1495 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1496 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1497 1498 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1499 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1500 1501 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1502 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1503 1504 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1505 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1506 1507 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1508 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1509 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1510 1511 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1512 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1513 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1514 1515 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1516 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1517 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1518 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1519 1520 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1521 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1522 1523 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1524 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1525 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1526 1527 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1528 1529 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1530 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1531 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1532 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1533 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1534 1535 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1536 ((__CHANNEL__) == TIM_CHANNEL_2)) 1537 1538 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1539 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1540 ((__CHANNEL__) == TIM_CHANNEL_3)) 1541 1542 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1543 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1544 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1545 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1546 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1547 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1548 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1549 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1550 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1551 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1552 1553 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1554 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1555 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1556 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1557 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1558 1559 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1560 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1561 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1562 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1563 1564 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1565 1566 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1567 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1568 1569 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1570 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1571 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1572 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1573 1574 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1575 1576 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1577 ((__STATE__) == TIM_OSSR_DISABLE)) 1578 1579 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1580 ((__STATE__) == TIM_OSSI_DISABLE)) 1581 1582 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1583 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1584 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1585 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1586 1587 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1588 1589 1590 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1591 ((__STATE__) == TIM_BREAK_DISABLE)) 1592 1593 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1594 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1595 1596 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1597 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1598 1599 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1600 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1601 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1602 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1603 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1604 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1605 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1606 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1607 1608 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1609 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1610 1611 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1612 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1613 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1614 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1615 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) 1616 1617 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1618 ((__MODE__) == TIM_OCMODE_PWM2)) 1619 1620 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1621 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1622 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1623 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1624 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1625 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) 1626 1627 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1628 ((__SELECTION__) == TIM_TS_ITR1) || \ 1629 ((__SELECTION__) == TIM_TS_ITR2) || \ 1630 ((__SELECTION__) == TIM_TS_ITR3) || \ 1631 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1632 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1633 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1634 ((__SELECTION__) == TIM_TS_ETRF)) 1635 1636 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1637 ((__SELECTION__) == TIM_TS_ITR1) || \ 1638 ((__SELECTION__) == TIM_TS_ITR2) || \ 1639 ((__SELECTION__) == TIM_TS_ITR3) || \ 1640 ((__SELECTION__) == TIM_TS_NONE)) 1641 1642 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1643 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1644 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1645 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1646 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1647 1648 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1649 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1650 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1651 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1652 1653 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1654 1655 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1656 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1657 1658 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1659 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1660 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1661 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1662 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1663 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1664 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1665 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1666 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1667 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1668 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1669 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1670 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1671 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1672 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1673 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1674 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1675 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1676 1677 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1678 1679 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1680 1681 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) 1682 1683 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1684 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1685 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1686 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1687 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1688 1689 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1690 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ 1691 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ 1692 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ 1693 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) 1694 1695 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1696 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1697 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1698 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1699 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1700 1701 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1702 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1703 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1704 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1705 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1706 1707 /** 1708 * @} 1709 */ 1710 /* End of private macros -----------------------------------------------------*/ 1711 1712 /* Include TIM HAL Extended module */ 1713 #include "stm32f4xx_hal_tim_ex.h" 1714 1715 /* Exported functions --------------------------------------------------------*/ 1716 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1717 * @{ 1718 */ 1719 1720 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1721 * @brief Time Base functions 1722 * @{ 1723 */ 1724 /* Time Base functions ********************************************************/ 1725 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1726 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1727 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1728 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1729 /* Blocking mode: Polling */ 1730 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1731 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1732 /* Non-Blocking mode: Interrupt */ 1733 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1734 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1735 /* Non-Blocking mode: DMA */ 1736 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1737 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1738 /** 1739 * @} 1740 */ 1741 1742 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 1743 * @brief TIM Output Compare functions 1744 * @{ 1745 */ 1746 /* Timer Output Compare functions *********************************************/ 1747 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1748 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1749 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1750 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1751 /* Blocking mode: Polling */ 1752 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1753 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1754 /* Non-Blocking mode: Interrupt */ 1755 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1756 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1757 /* Non-Blocking mode: DMA */ 1758 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1759 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1760 /** 1761 * @} 1762 */ 1763 1764 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 1765 * @brief TIM PWM functions 1766 * @{ 1767 */ 1768 /* Timer PWM functions ********************************************************/ 1769 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 1770 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 1771 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 1772 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 1773 /* Blocking mode: Polling */ 1774 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1775 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1776 /* Non-Blocking mode: Interrupt */ 1777 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1778 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1779 /* Non-Blocking mode: DMA */ 1780 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1781 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1782 /** 1783 * @} 1784 */ 1785 1786 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 1787 * @brief TIM Input Capture functions 1788 * @{ 1789 */ 1790 /* Timer Input Capture functions **********************************************/ 1791 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 1792 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 1793 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 1794 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 1795 /* Blocking mode: Polling */ 1796 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1797 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1798 /* Non-Blocking mode: Interrupt */ 1799 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1800 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1801 /* Non-Blocking mode: DMA */ 1802 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1803 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1804 /** 1805 * @} 1806 */ 1807 1808 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 1809 * @brief TIM One Pulse functions 1810 * @{ 1811 */ 1812 /* Timer One Pulse functions **************************************************/ 1813 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 1814 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 1815 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 1816 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 1817 /* Blocking mode: Polling */ 1818 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1819 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1820 /* Non-Blocking mode: Interrupt */ 1821 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1822 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1823 /** 1824 * @} 1825 */ 1826 1827 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 1828 * @brief TIM Encoder functions 1829 * @{ 1830 */ 1831 /* Timer Encoder functions ****************************************************/ 1832 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 1833 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 1834 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 1835 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 1836 /* Blocking mode: Polling */ 1837 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1838 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1839 /* Non-Blocking mode: Interrupt */ 1840 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1841 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1842 /* Non-Blocking mode: DMA */ 1843 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 1844 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1845 /** 1846 * @} 1847 */ 1848 1849 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 1850 * @brief IRQ handler management 1851 * @{ 1852 */ 1853 /* Interrupt Handler functions ***********************************************/ 1854 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 1855 /** 1856 * @} 1857 */ 1858 1859 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 1860 * @brief Peripheral Control functions 1861 * @{ 1862 */ 1863 /* Control functions *********************************************************/ 1864 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 1865 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 1866 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 1867 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); 1868 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); 1869 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 1870 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 1871 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 1872 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 1873 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 1874 uint32_t *BurstBuffer, uint32_t BurstLength); 1875 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 1876 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 1877 uint32_t *BurstBuffer, uint32_t BurstLength); 1878 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 1879 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 1880 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 1881 /** 1882 * @} 1883 */ 1884 1885 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 1886 * @brief TIM Callbacks functions 1887 * @{ 1888 */ 1889 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 1890 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 1891 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 1892 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 1893 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 1894 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 1895 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 1896 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 1897 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 1898 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 1899 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 1900 1901 /* Callbacks Register/UnRegister functions ***********************************/ 1902 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1903 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); 1904 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 1905 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1906 1907 /** 1908 * @} 1909 */ 1910 1911 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 1912 * @brief Peripheral State functions 1913 * @{ 1914 */ 1915 /* Peripheral State functions ************************************************/ 1916 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 1917 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 1918 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 1919 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 1920 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 1921 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 1922 /** 1923 * @} 1924 */ 1925 1926 /** 1927 * @} 1928 */ 1929 /* End of exported functions -------------------------------------------------*/ 1930 1931 /* Private functions----------------------------------------------------------*/ 1932 /** @defgroup TIM_Private_Functions TIM Private Functions 1933 * @{ 1934 */ 1935 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 1936 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 1937 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 1938 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 1939 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 1940 1941 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 1942 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 1943 void TIM_DMAError(DMA_HandleTypeDef *hdma); 1944 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 1945 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 1946 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 1947 1948 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1949 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 1950 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1951 1952 /** 1953 * @} 1954 */ 1955 /* End of private functions --------------------------------------------------*/ 1956 1957 /** 1958 * @} 1959 */ 1960 1961 /** 1962 * @} 1963 */ 1964 1965 #ifdef __cplusplus 1966 } 1967 #endif 1968 1969 #endif /* STM32F4xx_HAL_TIM_H */ 1970 1971 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1972