1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71Q20_ 46 #define _SAMV71Q20_ 47 48 /** \addtogroup SAMV71Q20_definitions SAMV71Q20 definitions 49 This file defines all structures and symbols for SAMV71Q20: 50 - registers and bitfields 51 - peripheral base address 52 - peripheral ID 53 - PIO definitions 54 */ 55 /*@{*/ 56 57 #ifdef __cplusplus 58 extern "C" { 59 #endif 60 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 #include <stdint.h> 63 #endif 64 65 /* ************************************************************************** */ 66 /* CMSIS DEFINITIONS FOR SAMV71Q20 */ 67 /* ************************************************************************** */ 68 /** \addtogroup SAMV71Q20_cmsis CMSIS Definitions */ 69 /*@{*/ 70 71 /**< Interrupt Number Definition */ 72 typedef enum IRQn 73 { 74 /****** Cortex-M7 Processor Exceptions Numbers ******************************/ 75 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 76 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ 77 MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ 78 BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ 79 UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ 80 SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ 81 DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ 82 PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ 83 SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ 84 /****** SAMV71Q20 specific Interrupt Numbers *********************************/ 85 86 SUPC_IRQn = 0, /**< 0 SAMV71Q20 Supply Controller (SUPC) */ 87 RSTC_IRQn = 1, /**< 1 SAMV71Q20 Reset Controller (RSTC) */ 88 RTC_IRQn = 2, /**< 2 SAMV71Q20 Real Time Clock (RTC) */ 89 RTT_IRQn = 3, /**< 3 SAMV71Q20 Real Time Timer (RTT) */ 90 WDT_IRQn = 4, /**< 4 SAMV71Q20 Watchdog Timer (WDT) */ 91 PMC_IRQn = 5, /**< 5 SAMV71Q20 Power Management Controller (PMC) */ 92 EFC_IRQn = 6, /**< 6 SAMV71Q20 Enhanced Embedded Flash Controller (EFC) */ 93 UART0_IRQn = 7, /**< 7 SAMV71Q20 UART 0 (UART0) */ 94 UART1_IRQn = 8, /**< 8 SAMV71Q20 UART 1 (UART1) */ 95 PIOA_IRQn = 10, /**< 10 SAMV71Q20 Parallel I/O Controller A (PIOA) */ 96 PIOB_IRQn = 11, /**< 11 SAMV71Q20 Parallel I/O Controller B (PIOB) */ 97 PIOC_IRQn = 12, /**< 12 SAMV71Q20 Parallel I/O Controller C (PIOC) */ 98 USART0_IRQn = 13, /**< 13 SAMV71Q20 USART 0 (USART0) */ 99 USART1_IRQn = 14, /**< 14 SAMV71Q20 USART 1 (USART1) */ 100 USART2_IRQn = 15, /**< 15 SAMV71Q20 USART 2 (USART2) */ 101 PIOD_IRQn = 16, /**< 16 SAMV71Q20 Parallel I/O Controller D (PIOD) */ 102 PIOE_IRQn = 17, /**< 17 SAMV71Q20 Parallel I/O Controller E (PIOE) */ 103 HSMCI_IRQn = 18, /**< 18 SAMV71Q20 Multimedia Card Interface (HSMCI) */ 104 TWIHS0_IRQn = 19, /**< 19 SAMV71Q20 Two Wire Interface 0 HS (TWIHS0) */ 105 TWIHS1_IRQn = 20, /**< 20 SAMV71Q20 Two Wire Interface 1 HS (TWIHS1) */ 106 SPI0_IRQn = 21, /**< 21 SAMV71Q20 Serial Peripheral Interface 0 (SPI0) */ 107 SSC_IRQn = 22, /**< 22 SAMV71Q20 Synchronous Serial Controller (SSC) */ 108 TC0_IRQn = 23, /**< 23 SAMV71Q20 Timer/Counter 0 (TC0) */ 109 TC1_IRQn = 24, /**< 24 SAMV71Q20 Timer/Counter 1 (TC1) */ 110 TC2_IRQn = 25, /**< 25 SAMV71Q20 Timer/Counter 2 (TC2) */ 111 TC3_IRQn = 26, /**< 26 SAMV71Q20 Timer/Counter 3 (TC3) */ 112 TC4_IRQn = 27, /**< 27 SAMV71Q20 Timer/Counter 4 (TC4) */ 113 TC5_IRQn = 28, /**< 28 SAMV71Q20 Timer/Counter 5 (TC5) */ 114 AFEC0_IRQn = 29, /**< 29 SAMV71Q20 Analog Front End 0 (AFEC0) */ 115 DACC_IRQn = 30, /**< 30 SAMV71Q20 Digital To Analog Converter (DACC) */ 116 PWM0_IRQn = 31, /**< 31 SAMV71Q20 Pulse Width Modulation 0 (PWM0) */ 117 ICM_IRQn = 32, /**< 32 SAMV71Q20 Integrity Check Monitor (ICM) */ 118 ACC_IRQn = 33, /**< 33 SAMV71Q20 Analog Comparator (ACC) */ 119 USBHS_IRQn = 34, /**< 34 SAMV71Q20 USB Host / Device Controller (USBHS) */ 120 MCAN0_IRQn = 35, /**< 35 SAMV71Q20 MCAN Controller 0 (MCAN0) */ 121 MCAN1_IRQn = 37, /**< 37 SAMV71Q20 MCAN Controller 1 (MCAN1) */ 122 GMAC_IRQn = 39, /**< 39 SAMV71Q20 Ethernet MAC (GMAC) */ 123 AFEC1_IRQn = 40, /**< 40 SAMV71Q20 Analog Front End 1 (AFEC1) */ 124 TWIHS2_IRQn = 41, /**< 41 SAMV71Q20 Two Wire Interface 2 HS (TWIHS2) */ 125 SPI1_IRQn = 42, /**< 42 SAMV71Q20 Serial Peripheral Interface 1 (SPI1) */ 126 QSPI_IRQn = 43, /**< 43 SAMV71Q20 Quad I/O Serial Peripheral Interface (QSPI) */ 127 UART2_IRQn = 44, /**< 44 SAMV71Q20 UART 2 (UART2) */ 128 UART3_IRQn = 45, /**< 45 SAMV71Q20 UART 3 (UART3) */ 129 UART4_IRQn = 46, /**< 46 SAMV71Q20 UART 4 (UART4) */ 130 TC6_IRQn = 47, /**< 47 SAMV71Q20 Timer/Counter 6 (TC6) */ 131 TC7_IRQn = 48, /**< 48 SAMV71Q20 Timer/Counter 7 (TC7) */ 132 TC8_IRQn = 49, /**< 49 SAMV71Q20 Timer/Counter 8 (TC8) */ 133 TC9_IRQn = 50, /**< 50 SAMV71Q20 Timer/Counter 9 (TC9) */ 134 TC10_IRQn = 51, /**< 51 SAMV71Q20 Timer/Counter 10 (TC10) */ 135 TC11_IRQn = 52, /**< 52 SAMV71Q20 Timer/Counter 11 (TC11) */ 136 MLB_IRQn = 53, /**< 53 SAMV71Q20 MediaLB (MLB) */ 137 AES_IRQn = 56, /**< 56 SAMV71Q20 AES (AES) */ 138 TRNG_IRQn = 57, /**< 57 SAMV71Q20 True Random Generator (TRNG) */ 139 XDMAC_IRQn = 58, /**< 58 SAMV71Q20 DMA (XDMAC) */ 140 ISI_IRQn = 59, /**< 59 SAMV71Q20 Camera Interface (ISI) */ 141 PWM1_IRQn = 60, /**< 60 SAMV71Q20 Pulse Width Modulation 1 (PWM1) */ 142 SDRAMC_IRQn = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */ 143 RSWDT_IRQn = 63, /**< 63 SAMV71Q20 Reinforced Secure Watchdog Timer (RSWDT) */ 144 145 PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ 146 } IRQn_Type; 147 148 typedef struct _DeviceVectors 149 { 150 /* Stack pointer */ 151 void* pvStack; 152 153 /* Cortex-M handlers */ 154 void* pfnReset_Handler; 155 void* pfnNMI_Handler; 156 void* pfnHardFault_Handler; 157 void* pfnMemManage_Handler; 158 void* pfnBusFault_Handler; 159 void* pfnUsageFault_Handler; 160 void* pfnReserved1_Handler; 161 void* pfnReserved2_Handler; 162 void* pfnReserved3_Handler; 163 void* pfnReserved4_Handler; 164 void* pfnSVC_Handler; 165 void* pfnDebugMon_Handler; 166 void* pfnReserved5_Handler; 167 void* pfnPendSV_Handler; 168 void* pfnSysTick_Handler; 169 170 /* Peripheral handlers */ 171 void* pfnSUPC_Handler; /* 0 Supply Controller */ 172 void* pfnRSTC_Handler; /* 1 Reset Controller */ 173 void* pfnRTC_Handler; /* 2 Real Time Clock */ 174 void* pfnRTT_Handler; /* 3 Real Time Timer */ 175 void* pfnWDT_Handler; /* 4 Watchdog Timer */ 176 void* pfnPMC_Handler; /* 5 Power Management Controller */ 177 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ 178 void* pfnUART0_Handler; /* 7 UART 0 */ 179 void* pfnUART1_Handler; /* 8 UART 1 */ 180 void* pvReserved9; 181 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ 182 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ 183 void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ 184 void* pfnUSART0_Handler; /* 13 USART 0 */ 185 void* pfnUSART1_Handler; /* 14 USART 1 */ 186 void* pfnUSART2_Handler; /* 15 USART 2 */ 187 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ 188 void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ 189 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ 190 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ 191 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ 192 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ 193 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ 194 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ 195 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ 196 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ 197 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ 198 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ 199 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ 200 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ 201 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ 202 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ 203 void* pfnICM_Handler; /* 32 Integrity Check Monitor */ 204 void* pfnACC_Handler; /* 33 Analog Comparator */ 205 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ 206 void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ 207 void* pvReserved36; 208 void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ 209 void* pvReserved38; 210 void* pfnGMAC_Handler; /* 39 Ethernet MAC */ 211 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ 212 void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ 213 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ 214 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ 215 void* pfnUART2_Handler; /* 44 UART 2 */ 216 void* pfnUART3_Handler; /* 45 UART 3 */ 217 void* pfnUART4_Handler; /* 46 UART 4 */ 218 void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ 219 void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ 220 void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ 221 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ 222 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ 223 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ 224 void* pfnMLB_Handler; /* 53 MediaLB */ 225 void* pvReserved54; 226 void* pvReserved55; 227 void* pfnAES_Handler; /* 56 AES */ 228 void* pfnTRNG_Handler; /* 57 True Random Generator */ 229 void* pfnXDMAC_Handler; /* 58 DMA */ 230 void* pfnISI_Handler; /* 59 Camera Interface */ 231 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ 232 void* pvReserved61; 233 void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ 234 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ 235 } DeviceVectors; 236 237 /* Cortex-M7 core handlers */ 238 void Reset_Handler ( void ); 239 void NMI_Handler ( void ); 240 void HardFault_Handler ( void ); 241 void MemManage_Handler ( void ); 242 void BusFault_Handler ( void ); 243 void UsageFault_Handler ( void ); 244 void SVC_Handler ( void ); 245 void DebugMon_Handler ( void ); 246 void PendSV_Handler ( void ); 247 void SysTick_Handler ( void ); 248 249 /* Peripherals handlers */ 250 void ACC_Handler ( void ); 251 void AES_Handler ( void ); 252 void AFEC0_Handler ( void ); 253 void AFEC1_Handler ( void ); 254 void DACC_Handler ( void ); 255 void EFC_Handler ( void ); 256 void GMAC_Handler ( void ); 257 void HSMCI_Handler ( void ); 258 void ICM_Handler ( void ); 259 void ISI_Handler ( void ); 260 void MCAN0_Handler ( void ); 261 void MCAN1_Handler ( void ); 262 void MLB_Handler ( void ); 263 void PIOA_Handler ( void ); 264 void PIOB_Handler ( void ); 265 void PIOC_Handler ( void ); 266 void PIOD_Handler ( void ); 267 void PIOE_Handler ( void ); 268 void PMC_Handler ( void ); 269 void PWM0_Handler ( void ); 270 void PWM1_Handler ( void ); 271 void QSPI_Handler ( void ); 272 void RSTC_Handler ( void ); 273 void RSWDT_Handler ( void ); 274 void RTC_Handler ( void ); 275 void RTT_Handler ( void ); 276 void SDRAMC_Handler ( void ); 277 void SPI0_Handler ( void ); 278 void SPI1_Handler ( void ); 279 void SSC_Handler ( void ); 280 void SUPC_Handler ( void ); 281 void TC0_Handler ( void ); 282 void TC1_Handler ( void ); 283 void TC2_Handler ( void ); 284 void TC3_Handler ( void ); 285 void TC4_Handler ( void ); 286 void TC5_Handler ( void ); 287 void TC6_Handler ( void ); 288 void TC7_Handler ( void ); 289 void TC8_Handler ( void ); 290 void TC9_Handler ( void ); 291 void TC10_Handler ( void ); 292 void TC11_Handler ( void ); 293 void TRNG_Handler ( void ); 294 void TWIHS0_Handler ( void ); 295 void TWIHS1_Handler ( void ); 296 void TWIHS2_Handler ( void ); 297 void UART0_Handler ( void ); 298 void UART1_Handler ( void ); 299 void UART2_Handler ( void ); 300 void UART3_Handler ( void ); 301 void UART4_Handler ( void ); 302 void USART0_Handler ( void ); 303 void USART1_Handler ( void ); 304 void USART2_Handler ( void ); 305 void USBHS_Handler ( void ); 306 void WDT_Handler ( void ); 307 void XDMAC_Handler ( void ); 308 309 /** 310 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals 311 */ 312 313 #define __CM7_REV 0x0000 /**< SAMV71Q20 core revision number ([15:8] revision number, [7:0] patch number) */ 314 #define __MPU_PRESENT 1 /**< SAMV71Q20 does provide a MPU */ 315 #define __NVIC_PRIO_BITS 3 /**< SAMV71Q20 uses 3 Bits for the Priority Levels */ 316 #define __FPU_PRESENT 1 /**< SAMV71Q20 does provide a FPU */ 317 #define __FPU_DP 1 /**< SAMV71Q20 Double precision FPU */ 318 #define __ICACHE_PRESENT 1 /**< SAMV71Q20 does provide an Instruction Cache */ 319 #define __DCACHE_PRESENT 1 /**< SAMV71Q20 does provide a Data Cache */ 320 #define __DTCM_PRESENT 1 /**< SAMV71Q20 does provide a Data TCM */ 321 #define __ITCM_PRESENT 1 /**< SAMV71Q20 does provide an Instruction TCM */ 322 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 323 324 /* 325 * \brief CMSIS includes 326 */ 327 328 #include <core_cm7.h> 329 #if !defined DONT_USE_CMSIS_INIT 330 #include "system_samv71.h" 331 #endif /* DONT_USE_CMSIS_INIT */ 332 333 /*@}*/ 334 335 /* ************************************************************************** */ 336 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q20 */ 337 /* ************************************************************************** */ 338 /** \addtogroup SAMV71Q20_api Peripheral Software API */ 339 /*@{*/ 340 341 #include "component/acc.h" 342 #include "component/aes.h" 343 #include "component/afec.h" 344 #include "component/chipid.h" 345 #include "component/dacc.h" 346 #include "component/efc.h" 347 #include "component/gmac.h" 348 #include "component/gpbr.h" 349 #include "component/hsmci.h" 350 #include "component/icm.h" 351 #include "component/isi.h" 352 #include "component/matrix.h" 353 #include "component/mcan.h" 354 #include "component/mlb.h" 355 #include "component/pio.h" 356 #include "component/pmc.h" 357 #include "component/pwm.h" 358 #include "component/qspi.h" 359 #include "component/rstc.h" 360 #include "component/rswdt.h" 361 #include "component/rtc.h" 362 #include "component/rtt.h" 363 #include "component/sdramc.h" 364 #include "component/smc.h" 365 #include "component/spi.h" 366 #include "component/ssc.h" 367 #include "component/supc.h" 368 #include "component/tc.h" 369 #include "component/trng.h" 370 #include "component/twihs.h" 371 #include "component/uart.h" 372 #include "component/usart.h" 373 #include "component/usbhs.h" 374 #include "component/utmi.h" 375 #include "component/wdt.h" 376 #include "component/xdmac.h" 377 /*@}*/ 378 379 /* ************************************************************************** */ 380 /* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */ 381 /* ************************************************************************** */ 382 /** \addtogroup SAMV71Q20_reg Registers Access Definitions */ 383 /*@{*/ 384 385 #include "instance/hsmci.h" 386 #include "instance/ssc.h" 387 #include "instance/spi0.h" 388 #include "instance/tc0.h" 389 #include "instance/tc1.h" 390 #include "instance/tc2.h" 391 #include "instance/twihs0.h" 392 #include "instance/twihs1.h" 393 #include "instance/pwm0.h" 394 #include "instance/usart0.h" 395 #include "instance/usart1.h" 396 #include "instance/usart2.h" 397 #include "instance/mcan0.h" 398 #include "instance/mcan1.h" 399 #include "instance/usbhs.h" 400 #include "instance/afec0.h" 401 #include "instance/dacc.h" 402 #include "instance/acc.h" 403 #include "instance/icm.h" 404 #include "instance/isi.h" 405 #include "instance/gmac.h" 406 #include "instance/tc3.h" 407 #include "instance/spi1.h" 408 #include "instance/pwm1.h" 409 #include "instance/twihs2.h" 410 #include "instance/afec1.h" 411 #include "instance/mlb.h" 412 #include "instance/aes.h" 413 #include "instance/trng.h" 414 #include "instance/xdmac.h" 415 #include "instance/qspi.h" 416 #include "instance/smc.h" 417 #include "instance/sdramc.h" 418 #include "instance/matrix.h" 419 #include "instance/utmi.h" 420 #include "instance/pmc.h" 421 #include "instance/uart0.h" 422 #include "instance/chipid.h" 423 #include "instance/uart1.h" 424 #include "instance/efc.h" 425 #include "instance/pioa.h" 426 #include "instance/piob.h" 427 #include "instance/pioc.h" 428 #include "instance/piod.h" 429 #include "instance/pioe.h" 430 #include "instance/rstc.h" 431 #include "instance/supc.h" 432 #include "instance/rtt.h" 433 #include "instance/wdt.h" 434 #include "instance/rtc.h" 435 #include "instance/gpbr.h" 436 #include "instance/rswdt.h" 437 #include "instance/uart2.h" 438 #include "instance/uart3.h" 439 #include "instance/uart4.h" 440 /*@}*/ 441 442 /* ************************************************************************** */ 443 /* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */ 444 /* ************************************************************************** */ 445 /** \addtogroup SAMV71Q20_id Peripheral Ids Definitions */ 446 /*@{*/ 447 448 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 449 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 450 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 451 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 452 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 453 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 454 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ 455 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ 456 #define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ 457 #define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ 458 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ 459 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ 460 #define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ 461 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */ 462 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */ 463 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */ 464 #define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ 465 #define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ 466 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ 467 #define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ 468 #define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ 469 #define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ 470 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ 471 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ 472 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ 473 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ 474 #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ 475 #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ 476 #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ 477 #define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ 478 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ 479 #define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ 480 #define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ 481 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ 482 #define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ 483 #define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ 484 #define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ 485 #define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ 486 #define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ 487 #define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ 488 #define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ 489 #define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ 490 #define ID_UART2 (44) /**< \brief UART 2 (UART2) */ 491 #define ID_UART3 (45) /**< \brief UART 3 (UART3) */ 492 #define ID_UART4 (46) /**< \brief UART 4 (UART4) */ 493 #define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ 494 #define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ 495 #define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ 496 #define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ 497 #define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ 498 #define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ 499 #define ID_MLB (53) /**< \brief MediaLB (MLB) */ 500 #define ID_AES (56) /**< \brief AES (AES) */ 501 #define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ 502 #define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ 503 #define ID_ISI (59) /**< \brief Camera Interface (ISI) */ 504 #define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ 505 #define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ 506 #define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ 507 508 #define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ 509 /*@}*/ 510 511 /* ************************************************************************** */ 512 /* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */ 513 /* ************************************************************************** */ 514 /** \addtogroup SAMV71Q20_base Peripheral Base Address Definitions */ 515 /*@{*/ 516 517 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 518 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ 519 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ 520 #define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ 521 #define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ 522 #define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ 523 #define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ 524 #define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ 525 #define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ 526 #define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ 527 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ 528 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ 529 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ 530 #define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ 531 #define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ 532 #define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ 533 #define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ 534 #define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ 535 #define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ 536 #define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ 537 #define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ 538 #define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ 539 #define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ 540 #define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ 541 #define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ 542 #define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ 543 #define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ 544 #define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ 545 #define AES (0x4006C000U) /**< \brief (AES ) Base Address */ 546 #define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ 547 #define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ 548 #define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ 549 #define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ 550 #define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ 551 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ 552 #define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ 553 #define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ 554 #define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ 555 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ 556 #define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ 557 #define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ 558 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 559 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 560 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ 561 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ 562 #define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ 563 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ 564 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ 565 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ 566 #define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ 567 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ 568 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ 569 #define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ 570 #define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ 571 #define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ 572 #define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ 573 #else 574 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ 575 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 576 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ 577 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ 578 #define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ 579 #define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ 580 #define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ 581 #define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ 582 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ 583 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ 584 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ 585 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ 586 #define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ 587 #define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ 588 #define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ 589 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ 590 #define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ 591 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ 592 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ 593 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ 594 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ 595 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ 596 #define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ 597 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ 598 #define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ 599 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ 600 #define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ 601 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ 602 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ 603 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ 604 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ 605 #define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ 606 #define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ 607 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ 608 #define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ 609 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ 610 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ 611 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ 612 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ 613 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ 614 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 615 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 616 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ 617 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ 618 #define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ 619 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ 620 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ 621 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ 622 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ 623 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ 624 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ 625 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ 626 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ 627 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ 628 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ 629 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 630 /*@}*/ 631 632 /* ************************************************************************** */ 633 /* PIO DEFINITIONS FOR SAMV71Q20 */ 634 /* ************************************************************************** */ 635 /** \addtogroup SAMV71Q20_pio Peripheral Pio Definitions */ 636 /*@{*/ 637 638 #include "pio/samv71q20.h" 639 /*@}*/ 640 641 /* ************************************************************************** */ 642 /* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */ 643 /* ************************************************************************** */ 644 645 #define IFLASH_SIZE (0x100000u) 646 #define IFLASH_PAGE_SIZE (512u) 647 #define IFLASH_LOCK_REGION_SIZE (8192u) 648 #define IFLASH_NB_OF_PAGES (2048u) 649 #define IFLASH_NB_OF_LOCK_BITS (64u) 650 #define IRAM_SIZE (0x60000u) 651 652 #define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ 653 #define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ 654 #define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ 655 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ 656 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 657 #define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ 658 #define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ 659 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ 660 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ 661 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ 662 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ 663 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ 664 665 /* ************************************************************************** */ 666 /* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */ 667 /* ************************************************************************** */ 668 669 #define CHIP_JTAGID (0x05B3D03FUL) 670 #define CHIP_CIDR (0xA1220C00UL) 671 #define CHIP_EXID (0x00000002UL) 672 673 /* ************************************************************************** */ 674 /* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */ 675 /* ************************************************************************** */ 676 677 /* %ATMEL_ELECTRICAL% */ 678 679 /* Device characteristics */ 680 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 681 #define CHIP_FREQ_SLCK_RC (32000UL) 682 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 683 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 684 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 685 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 686 #define CHIP_FREQ_CPU_MAX (300000000UL) 687 #define CHIP_FREQ_XTAL_32K (32768UL) 688 #define CHIP_FREQ_XTAL_12M (12000000UL) 689 690 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ 691 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 692 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 693 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 694 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 695 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 696 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ 697 698 #ifdef __cplusplus 699 } 700 #endif 701 702 /*@}*/ 703 704 #endif /* _SAMV71Q20_ */ 705