1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71J19_ 46 #define _SAMV71J19_ 47 48 /** \addtogroup SAMV71J19_definitions SAMV71J19 definitions 49 This file defines all structures and symbols for SAMV71J19: 50 - registers and bitfields 51 - peripheral base address 52 - peripheral ID 53 - PIO definitions 54 */ 55 /*@{*/ 56 57 #ifdef __cplusplus 58 extern "C" { 59 #endif 60 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 #include <stdint.h> 63 #endif 64 65 /* ************************************************************************** */ 66 /* CMSIS DEFINITIONS FOR SAMV71J19 */ 67 /* ************************************************************************** */ 68 /** \addtogroup SAMV71J19_cmsis CMSIS Definitions */ 69 /*@{*/ 70 71 /**< Interrupt Number Definition */ 72 typedef enum IRQn 73 { 74 /****** Cortex-M7 Processor Exceptions Numbers ******************************/ 75 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 76 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ 77 MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ 78 BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ 79 UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ 80 SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ 81 DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ 82 PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ 83 SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ 84 /****** SAMV71J19 specific Interrupt Numbers *********************************/ 85 86 SUPC_IRQn = 0, /**< 0 SAMV71J19 Supply Controller (SUPC) */ 87 RSTC_IRQn = 1, /**< 1 SAMV71J19 Reset Controller (RSTC) */ 88 RTC_IRQn = 2, /**< 2 SAMV71J19 Real Time Clock (RTC) */ 89 RTT_IRQn = 3, /**< 3 SAMV71J19 Real Time Timer (RTT) */ 90 WDT_IRQn = 4, /**< 4 SAMV71J19 Watchdog Timer (WDT) */ 91 PMC_IRQn = 5, /**< 5 SAMV71J19 Power Management Controller (PMC) */ 92 EFC_IRQn = 6, /**< 6 SAMV71J19 Enhanced Embedded Flash Controller (EFC) */ 93 UART0_IRQn = 7, /**< 7 SAMV71J19 UART 0 (UART0) */ 94 UART1_IRQn = 8, /**< 8 SAMV71J19 UART 1 (UART1) */ 95 PIOA_IRQn = 10, /**< 10 SAMV71J19 Parallel I/O Controller A (PIOA) */ 96 PIOB_IRQn = 11, /**< 11 SAMV71J19 Parallel I/O Controller B (PIOB) */ 97 USART0_IRQn = 13, /**< 13 SAMV71J19 USART 0 (USART0) */ 98 USART1_IRQn = 14, /**< 14 SAMV71J19 USART 1 (USART1) */ 99 USART2_IRQn = 15, /**< 15 SAMV71J19 USART 2 (USART2) */ 100 PIOD_IRQn = 16, /**< 16 SAMV71J19 Parallel I/O Controller D (PIOD) */ 101 HSMCI_IRQn = 18, /**< 18 SAMV71J19 Multimedia Card Interface (HSMCI) */ 102 TWIHS0_IRQn = 19, /**< 19 SAMV71J19 Two Wire Interface 0 HS (TWIHS0) */ 103 TWIHS1_IRQn = 20, /**< 20 SAMV71J19 Two Wire Interface 1 HS (TWIHS1) */ 104 SPI0_IRQn = 21, /**< 21 SAMV71J19 Serial Peripheral Interface 0 (SPI0) */ 105 SSC_IRQn = 22, /**< 22 SAMV71J19 Synchronous Serial Controller (SSC) */ 106 TC0_IRQn = 23, /**< 23 SAMV71J19 Timer/Counter 0 (TC0) */ 107 TC1_IRQn = 24, /**< 24 SAMV71J19 Timer/Counter 1 (TC1) */ 108 TC2_IRQn = 25, /**< 25 SAMV71J19 Timer/Counter 2 (TC2) */ 109 AFEC0_IRQn = 29, /**< 29 SAMV71J19 Analog Front End 0 (AFEC0) */ 110 PWM0_IRQn = 31, /**< 31 SAMV71J19 Pulse Width Modulation 0 (PWM0) */ 111 ICM_IRQn = 32, /**< 32 SAMV71J19 Integrity Check Monitor (ICM) */ 112 ACC_IRQn = 33, /**< 33 SAMV71J19 Analog Comparator (ACC) */ 113 USBHS_IRQn = 34, /**< 34 SAMV71J19 USB Host / Device Controller (USBHS) */ 114 MCAN0_IRQn = 35, /**< 35 SAMV71J19 MCAN Controller 0 (MCAN0) */ 115 MCAN1_IRQn = 37, /**< 37 SAMV71J19 MCAN Controller 1 (MCAN1) */ 116 GMAC_IRQn = 39, /**< 39 SAMV71J19 Ethernet MAC (GMAC) */ 117 AFEC1_IRQn = 40, /**< 40 SAMV71J19 Analog Front End 1 (AFEC1) */ 118 SPI1_IRQn = 42, /**< 42 SAMV71J19 Serial Peripheral Interface 1 (SPI1) */ 119 QSPI_IRQn = 43, /**< 43 SAMV71J19 Quad I/O Serial Peripheral Interface (QSPI) */ 120 UART2_IRQn = 44, /**< 44 SAMV71J19 UART 2 (UART2) */ 121 UART3_IRQn = 45, /**< 45 SAMV71J19 UART 3 (UART3) */ 122 UART4_IRQn = 46, /**< 46 SAMV71J19 UART 4 (UART4) */ 123 TC9_IRQn = 50, /**< 50 SAMV71J19 Timer/Counter 9 (TC9) */ 124 TC10_IRQn = 51, /**< 51 SAMV71J19 Timer/Counter 10 (TC10) */ 125 TC11_IRQn = 52, /**< 52 SAMV71J19 Timer/Counter 11 (TC11) */ 126 MLB_IRQn = 53, /**< 53 SAMV71J19 MediaLB (MLB) */ 127 AES_IRQn = 56, /**< 56 SAMV71J19 AES (AES) */ 128 TRNG_IRQn = 57, /**< 57 SAMV71J19 True Random Generator (TRNG) */ 129 XDMAC_IRQn = 58, /**< 58 SAMV71J19 DMA (XDMAC) */ 130 ISI_IRQn = 59, /**< 59 SAMV71J19 Camera Interface (ISI) */ 131 PWM1_IRQn = 60, /**< 60 SAMV71J19 Pulse Width Modulation 1 (PWM1) */ 132 RSWDT_IRQn = 63, /**< 63 SAMV71J19 Reinforced Secure Watchdog Timer (RSWDT) */ 133 134 PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ 135 } IRQn_Type; 136 137 typedef struct _DeviceVectors 138 { 139 /* Stack pointer */ 140 void* pvStack; 141 142 /* Cortex-M handlers */ 143 void* pfnReset_Handler; 144 void* pfnNMI_Handler; 145 void* pfnHardFault_Handler; 146 void* pfnMemManage_Handler; 147 void* pfnBusFault_Handler; 148 void* pfnUsageFault_Handler; 149 void* pfnReserved1_Handler; 150 void* pfnReserved2_Handler; 151 void* pfnReserved3_Handler; 152 void* pfnReserved4_Handler; 153 void* pfnSVC_Handler; 154 void* pfnDebugMon_Handler; 155 void* pfnReserved5_Handler; 156 void* pfnPendSV_Handler; 157 void* pfnSysTick_Handler; 158 159 /* Peripheral handlers */ 160 void* pfnSUPC_Handler; /* 0 Supply Controller */ 161 void* pfnRSTC_Handler; /* 1 Reset Controller */ 162 void* pfnRTC_Handler; /* 2 Real Time Clock */ 163 void* pfnRTT_Handler; /* 3 Real Time Timer */ 164 void* pfnWDT_Handler; /* 4 Watchdog Timer */ 165 void* pfnPMC_Handler; /* 5 Power Management Controller */ 166 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ 167 void* pfnUART0_Handler; /* 7 UART 0 */ 168 void* pfnUART1_Handler; /* 8 UART 1 */ 169 void* pvReserved9; 170 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ 171 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ 172 void* pvReserved12; 173 void* pfnUSART0_Handler; /* 13 USART 0 */ 174 void* pfnUSART1_Handler; /* 14 USART 1 */ 175 void* pfnUSART2_Handler; /* 15 USART 2 */ 176 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ 177 void* pvReserved17; 178 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ 179 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ 180 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ 181 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ 182 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ 183 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ 184 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ 185 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ 186 void* pvReserved26; 187 void* pvReserved27; 188 void* pvReserved28; 189 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ 190 void* pvReserved30; 191 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ 192 void* pfnICM_Handler; /* 32 Integrity Check Monitor */ 193 void* pfnACC_Handler; /* 33 Analog Comparator */ 194 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ 195 void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ 196 void* pvReserved36; 197 void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ 198 void* pvReserved38; 199 void* pfnGMAC_Handler; /* 39 Ethernet MAC */ 200 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ 201 void* pvReserved41; 202 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ 203 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ 204 void* pfnUART2_Handler; /* 44 UART 2 */ 205 void* pfnUART3_Handler; /* 45 UART 3 */ 206 void* pfnUART4_Handler; /* 46 UART 4 */ 207 void* pvReserved47; 208 void* pvReserved48; 209 void* pvReserved49; 210 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ 211 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ 212 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ 213 void* pfnMLB_Handler; /* 53 MediaLB */ 214 void* pvReserved54; 215 void* pvReserved55; 216 void* pfnAES_Handler; /* 56 AES */ 217 void* pfnTRNG_Handler; /* 57 True Random Generator */ 218 void* pfnXDMAC_Handler; /* 58 DMA */ 219 void* pfnISI_Handler; /* 59 Camera Interface */ 220 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ 221 void* pvReserved61; 222 void* pvReserved62; 223 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ 224 } DeviceVectors; 225 226 /* Cortex-M7 core handlers */ 227 void Reset_Handler ( void ); 228 void NMI_Handler ( void ); 229 void HardFault_Handler ( void ); 230 void MemManage_Handler ( void ); 231 void BusFault_Handler ( void ); 232 void UsageFault_Handler ( void ); 233 void SVC_Handler ( void ); 234 void DebugMon_Handler ( void ); 235 void PendSV_Handler ( void ); 236 void SysTick_Handler ( void ); 237 238 /* Peripherals handlers */ 239 void ACC_Handler ( void ); 240 void AES_Handler ( void ); 241 void AFEC0_Handler ( void ); 242 void AFEC1_Handler ( void ); 243 void EFC_Handler ( void ); 244 void GMAC_Handler ( void ); 245 void HSMCI_Handler ( void ); 246 void ICM_Handler ( void ); 247 void ISI_Handler ( void ); 248 void MCAN0_Handler ( void ); 249 void MCAN1_Handler ( void ); 250 void MLB_Handler ( void ); 251 void PIOA_Handler ( void ); 252 void PIOB_Handler ( void ); 253 void PIOD_Handler ( void ); 254 void PMC_Handler ( void ); 255 void PWM0_Handler ( void ); 256 void PWM1_Handler ( void ); 257 void QSPI_Handler ( void ); 258 void RSTC_Handler ( void ); 259 void RSWDT_Handler ( void ); 260 void RTC_Handler ( void ); 261 void RTT_Handler ( void ); 262 void SPI0_Handler ( void ); 263 void SPI1_Handler ( void ); 264 void SSC_Handler ( void ); 265 void SUPC_Handler ( void ); 266 void TC0_Handler ( void ); 267 void TC1_Handler ( void ); 268 void TC2_Handler ( void ); 269 void TC9_Handler ( void ); 270 void TC10_Handler ( void ); 271 void TC11_Handler ( void ); 272 void TRNG_Handler ( void ); 273 void TWIHS0_Handler ( void ); 274 void TWIHS1_Handler ( void ); 275 void UART0_Handler ( void ); 276 void UART1_Handler ( void ); 277 void UART2_Handler ( void ); 278 void UART3_Handler ( void ); 279 void UART4_Handler ( void ); 280 void USART0_Handler ( void ); 281 void USART1_Handler ( void ); 282 void USART2_Handler ( void ); 283 void USBHS_Handler ( void ); 284 void WDT_Handler ( void ); 285 void XDMAC_Handler ( void ); 286 287 /** 288 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals 289 */ 290 291 #define __CM7_REV 0x0000 /**< SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number) */ 292 #define __MPU_PRESENT 1 /**< SAMV71J19 does provide a MPU */ 293 #define __NVIC_PRIO_BITS 3 /**< SAMV71J19 uses 3 Bits for the Priority Levels */ 294 #define __FPU_PRESENT 1 /**< SAMV71J19 does provide a FPU */ 295 #define __FPU_DP 1 /**< SAMV71J19 Double precision FPU */ 296 #define __ICACHE_PRESENT 1 /**< SAMV71J19 does provide an Instruction Cache */ 297 #define __DCACHE_PRESENT 1 /**< SAMV71J19 does provide a Data Cache */ 298 #define __DTCM_PRESENT 1 /**< SAMV71J19 does provide a Data TCM */ 299 #define __ITCM_PRESENT 1 /**< SAMV71J19 does provide an Instruction TCM */ 300 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 301 302 /* 303 * \brief CMSIS includes 304 */ 305 306 #include <core_cm7.h> 307 #if !defined DONT_USE_CMSIS_INIT 308 #include "system_samv71.h" 309 #endif /* DONT_USE_CMSIS_INIT */ 310 311 /*@}*/ 312 313 /* ************************************************************************** */ 314 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J19 */ 315 /* ************************************************************************** */ 316 /** \addtogroup SAMV71J19_api Peripheral Software API */ 317 /*@{*/ 318 319 #include "component/acc.h" 320 #include "component/aes.h" 321 #include "component/afec.h" 322 #include "component/chipid.h" 323 #include "component/efc.h" 324 #include "component/gmac.h" 325 #include "component/gpbr.h" 326 #include "component/hsmci.h" 327 #include "component/icm.h" 328 #include "component/isi.h" 329 #include "component/matrix.h" 330 #include "component/mcan.h" 331 #include "component/mlb.h" 332 #include "component/pio.h" 333 #include "component/pmc.h" 334 #include "component/pwm.h" 335 #include "component/qspi.h" 336 #include "component/rstc.h" 337 #include "component/rswdt.h" 338 #include "component/rtc.h" 339 #include "component/rtt.h" 340 #include "component/spi.h" 341 #include "component/ssc.h" 342 #include "component/supc.h" 343 #include "component/tc.h" 344 #include "component/trng.h" 345 #include "component/twihs.h" 346 #include "component/uart.h" 347 #include "component/usart.h" 348 #include "component/usbhs.h" 349 #include "component/utmi.h" 350 #include "component/wdt.h" 351 #include "component/xdmac.h" 352 /*@}*/ 353 354 /* ************************************************************************** */ 355 /* REGISTER ACCESS DEFINITIONS FOR SAMV71J19 */ 356 /* ************************************************************************** */ 357 /** \addtogroup SAMV71J19_reg Registers Access Definitions */ 358 /*@{*/ 359 360 #include "instance/hsmci.h" 361 #include "instance/ssc.h" 362 #include "instance/spi0.h" 363 #include "instance/tc0.h" 364 #include "instance/twihs0.h" 365 #include "instance/twihs1.h" 366 #include "instance/pwm0.h" 367 #include "instance/usart0.h" 368 #include "instance/usart1.h" 369 #include "instance/usart2.h" 370 #include "instance/mcan0.h" 371 #include "instance/mcan1.h" 372 #include "instance/usbhs.h" 373 #include "instance/afec0.h" 374 #include "instance/acc.h" 375 #include "instance/icm.h" 376 #include "instance/isi.h" 377 #include "instance/gmac.h" 378 #include "instance/tc3.h" 379 #include "instance/spi1.h" 380 #include "instance/pwm1.h" 381 #include "instance/afec1.h" 382 #include "instance/mlb.h" 383 #include "instance/aes.h" 384 #include "instance/trng.h" 385 #include "instance/xdmac.h" 386 #include "instance/qspi.h" 387 #include "instance/matrix.h" 388 #include "instance/utmi.h" 389 #include "instance/pmc.h" 390 #include "instance/uart0.h" 391 #include "instance/chipid.h" 392 #include "instance/uart1.h" 393 #include "instance/efc.h" 394 #include "instance/pioa.h" 395 #include "instance/piob.h" 396 #include "instance/piod.h" 397 #include "instance/rstc.h" 398 #include "instance/supc.h" 399 #include "instance/rtt.h" 400 #include "instance/wdt.h" 401 #include "instance/rtc.h" 402 #include "instance/gpbr.h" 403 #include "instance/rswdt.h" 404 #include "instance/uart2.h" 405 #include "instance/uart3.h" 406 #include "instance/uart4.h" 407 /*@}*/ 408 409 /* ************************************************************************** */ 410 /* PERIPHERAL ID DEFINITIONS FOR SAMV71J19 */ 411 /* ************************************************************************** */ 412 /** \addtogroup SAMV71J19_id Peripheral Ids Definitions */ 413 /*@{*/ 414 415 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 416 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 417 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 418 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 419 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 420 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 421 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ 422 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ 423 #define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ 424 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ 425 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ 426 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */ 427 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */ 428 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */ 429 #define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ 430 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ 431 #define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ 432 #define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ 433 #define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ 434 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ 435 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ 436 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ 437 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ 438 #define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ 439 #define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ 440 #define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ 441 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ 442 #define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ 443 #define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ 444 #define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ 445 #define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ 446 #define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ 447 #define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ 448 #define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ 449 #define ID_UART2 (44) /**< \brief UART 2 (UART2) */ 450 #define ID_UART3 (45) /**< \brief UART 3 (UART3) */ 451 #define ID_UART4 (46) /**< \brief UART 4 (UART4) */ 452 #define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ 453 #define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ 454 #define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ 455 #define ID_MLB (53) /**< \brief MediaLB (MLB) */ 456 #define ID_AES (56) /**< \brief AES (AES) */ 457 #define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ 458 #define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ 459 #define ID_ISI (59) /**< \brief Camera Interface (ISI) */ 460 #define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ 461 #define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ 462 463 #define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ 464 /*@}*/ 465 466 /* ************************************************************************** */ 467 /* BASE ADDRESS DEFINITIONS FOR SAMV71J19 */ 468 /* ************************************************************************** */ 469 /** \addtogroup SAMV71J19_base Peripheral Base Address Definitions */ 470 /*@{*/ 471 472 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 473 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ 474 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ 475 #define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ 476 #define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ 477 #define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ 478 #define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ 479 #define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ 480 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ 481 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ 482 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ 483 #define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ 484 #define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ 485 #define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ 486 #define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ 487 #define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ 488 #define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ 489 #define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ 490 #define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ 491 #define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ 492 #define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ 493 #define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ 494 #define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ 495 #define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ 496 #define AES (0x4006C000U) /**< \brief (AES ) Base Address */ 497 #define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ 498 #define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ 499 #define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ 500 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ 501 #define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ 502 #define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ 503 #define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ 504 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ 505 #define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ 506 #define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ 507 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 508 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 509 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ 510 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ 511 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ 512 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ 513 #define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ 514 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ 515 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ 516 #define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ 517 #define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ 518 #define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ 519 #define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ 520 #else 521 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ 522 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 523 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ 524 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ 525 #define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ 526 #define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ 527 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ 528 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ 529 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ 530 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ 531 #define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ 532 #define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ 533 #define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ 534 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ 535 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ 536 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ 537 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ 538 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ 539 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ 540 #define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ 541 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ 542 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ 543 #define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ 544 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ 545 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ 546 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ 547 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ 548 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ 549 #define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ 550 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ 551 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ 552 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ 553 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ 554 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ 555 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 556 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 557 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ 558 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ 559 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ 560 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ 561 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ 562 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ 563 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ 564 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ 565 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ 566 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ 567 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ 568 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 569 /*@}*/ 570 571 /* ************************************************************************** */ 572 /* PIO DEFINITIONS FOR SAMV71J19 */ 573 /* ************************************************************************** */ 574 /** \addtogroup SAMV71J19_pio Peripheral Pio Definitions */ 575 /*@{*/ 576 577 #include "pio/samv71j19.h" 578 /*@}*/ 579 580 /* ************************************************************************** */ 581 /* MEMORY MAPPING DEFINITIONS FOR SAMV71J19 */ 582 /* ************************************************************************** */ 583 584 #define IFLASH_SIZE (0x80000u) 585 #define IFLASH_PAGE_SIZE (512u) 586 #define IFLASH_LOCK_REGION_SIZE (8192u) 587 #define IFLASH_NB_OF_PAGES (1024u) 588 #define IFLASH_NB_OF_LOCK_BITS (32u) 589 #define IRAM_SIZE (0x40000u) 590 591 #define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ 592 #define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ 593 #define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ 594 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ 595 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 596 #define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ 597 #define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ 598 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ 599 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ 600 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ 601 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ 602 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ 603 604 /* ************************************************************************** */ 605 /* MISCELLANEOUS DEFINITIONS FOR SAMV71J19 */ 606 /* ************************************************************************** */ 607 608 #define CHIP_JTAGID (0x05B3D03FUL) 609 #define CHIP_CIDR (0xA12D0A00UL) 610 #define CHIP_EXID (0x00000000UL) 611 612 /* ************************************************************************** */ 613 /* ELECTRICAL DEFINITIONS FOR SAMV71J19 */ 614 /* ************************************************************************** */ 615 616 /* %ATMEL_ELECTRICAL% */ 617 618 /* Device characteristics */ 619 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 620 #define CHIP_FREQ_SLCK_RC (32000UL) 621 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 622 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 623 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 624 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 625 #define CHIP_FREQ_CPU_MAX (300000000UL) 626 #define CHIP_FREQ_XTAL_32K (32768UL) 627 #define CHIP_FREQ_XTAL_12M (12000000UL) 628 629 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ 630 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 631 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 632 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 633 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 634 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 635 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ 636 637 #ifdef __cplusplus 638 } 639 #endif 640 641 /*@}*/ 642 643 #endif /* _SAMV71J19_ */ 644