1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_USART0_INSTANCE_ 46 #define _SAMV71_USART0_INSTANCE_ 47 48 /* ========== Register definition for USART0 peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ 51 #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ 52 #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ 53 #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ 54 #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ 55 #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ 56 #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */ 57 #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ 58 #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ 59 #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ 60 #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ 61 #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ 62 #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */ 63 #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */ 64 #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ 65 #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */ 66 #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */ 67 #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */ 68 #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ 69 #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */ 70 #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ 71 #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ 72 #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */ 73 #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ 74 #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ 75 #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */ 76 #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ 77 #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ 78 #else 79 #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ 80 #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ 81 #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ 82 #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ 83 #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ 84 #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ 85 #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */ 86 #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ 87 #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ 88 #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ 89 #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ 90 #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ 91 #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */ 92 #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */ 93 #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ 94 #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */ 95 #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */ 96 #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */ 97 #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ 98 #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */ 99 #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ 100 #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ 101 #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */ 102 #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ 103 #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ 104 #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */ 105 #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ 106 #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ 107 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 108 109 #endif /* _SAMV71_USART0_INSTANCE_ */ 110