1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_SDRAMC_INSTANCE_ 46 #define _SAMV71_SDRAMC_INSTANCE_ 47 48 /* ========== Register definition for SDRAMC peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ 51 #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ 52 #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ 53 #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ 54 #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ 55 #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ 56 #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ 57 #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ 58 #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ 59 #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ 60 #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ 61 #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ 62 #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ 63 #else 64 #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ 65 #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ 66 #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ 67 #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ 68 #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ 69 #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ 70 #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ 71 #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ 72 #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ 73 #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ 74 #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ 75 #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ 76 #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ 77 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 #endif /* _SAMV71_SDRAMC_INSTANCE_ */ 80