1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_PWM0_INSTANCE_ 46 #define _SAMV71_PWM0_INSTANCE_ 47 48 /* ========== Register definition for PWM0 peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */ 51 #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */ 52 #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */ 53 #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */ 54 #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ 55 #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ 56 #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ 57 #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ 58 #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ 59 #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */ 60 #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ 61 #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ 62 #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ 63 #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ 64 #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ 65 #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ 66 #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ 67 #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ 68 #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ 69 #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ 70 #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ 71 #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ 72 #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ 73 #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ 74 #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ 75 #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ 76 #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ 77 #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ 78 #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ 79 #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ 80 #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ 81 #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ 82 #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ 83 #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ 84 #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ 85 #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ 86 #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ 87 #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ 88 #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ 89 #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ 90 #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ 91 #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ 92 #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ 93 #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ 94 #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ 95 #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ 96 #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ 97 #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ 98 #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ 99 #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ 100 #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ 101 #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ 102 #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ 103 #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ 104 #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ 105 #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ 106 #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ 107 #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ 108 #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ 109 #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ 110 #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ 111 #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ 112 #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ 113 #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ 114 #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ 115 #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ 116 #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ 117 #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ 118 #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ 119 #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ 120 #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ 121 #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ 122 #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ 123 #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ 124 #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ 125 #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ 126 #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ 127 #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ 128 #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ 129 #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ 130 #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ 131 #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ 132 #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ 133 #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ 134 #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ 135 #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ 136 #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ 137 #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ 138 #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ 139 #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ 140 #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ 141 #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ 142 #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ 143 #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ 144 #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ 145 #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ 146 #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ 147 #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ 148 #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ 149 #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ 150 #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ 151 #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ 152 #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ 153 #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ 154 #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ 155 #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ 156 #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ 157 #define REG_PWM0_ETRG3 (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */ 158 #define REG_PWM0_LEBR3 (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */ 159 #define REG_PWM0_ETRG4 (0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */ 160 #define REG_PWM0_LEBR4 (0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */ 161 #else 162 #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */ 163 #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */ 164 #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */ 165 #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */ 166 #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ 167 #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ 168 #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ 169 #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ 170 #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ 171 #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */ 172 #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ 173 #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ 174 #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ 175 #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ 176 #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ 177 #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ 178 #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ 179 #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ 180 #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ 181 #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ 182 #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ 183 #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ 184 #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ 185 #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ 186 #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ 187 #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ 188 #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ 189 #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ 190 #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ 191 #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ 192 #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ 193 #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ 194 #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ 195 #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ 196 #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ 197 #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ 198 #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ 199 #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ 200 #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ 201 #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ 202 #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ 203 #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ 204 #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ 205 #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ 206 #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ 207 #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ 208 #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ 209 #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ 210 #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ 211 #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ 212 #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ 213 #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ 214 #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ 215 #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ 216 #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ 217 #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ 218 #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ 219 #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ 220 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ 221 #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ 222 #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ 223 #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ 224 #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ 225 #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ 226 #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ 227 #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ 228 #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ 229 #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ 230 #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ 231 #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ 232 #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ 233 #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ 234 #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ 235 #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ 236 #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ 237 #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ 238 #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ 239 #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ 240 #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ 241 #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ 242 #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ 243 #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ 244 #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ 245 #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ 246 #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ 247 #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ 248 #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ 249 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ 250 #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ 251 #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ 252 #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ 253 #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ 254 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ 255 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ 256 #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ 257 #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ 258 #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ 259 #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ 260 #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ 261 #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ 262 #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ 263 #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ 264 #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ 265 #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ 266 #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ 267 #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ 268 #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ 269 #define REG_PWM0_ETRG3 (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */ 270 #define REG_PWM0_LEBR3 (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */ 271 #define REG_PWM0_ETRG4 (*(__IO uint32_t*)0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */ 272 #define REG_PWM0_LEBR4 (*(__IO uint32_t*)0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */ 273 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 #endif /* _SAMV71_PWM0_INSTANCE_ */ 276