1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_PIOA_INSTANCE_ 46 #define _SAMV71_PIOA_INSTANCE_ 47 48 /* ========== Register definition for PIOA peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ 51 #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ 52 #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ 53 #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ 54 #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ 55 #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ 56 #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ 57 #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ 58 #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ 59 #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ 60 #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ 61 #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ 62 #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ 63 #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ 64 #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ 65 #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ 66 #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ 67 #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ 68 #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ 69 #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ 70 #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ 71 #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ 72 #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ 73 #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ 74 #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ 75 #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ 76 #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ 77 #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ 78 #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ 79 #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ 80 #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ 81 #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ 82 #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ 83 #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ 84 #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ 85 #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ 86 #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ 87 #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ 88 #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ 89 #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ 90 #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ 91 #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ 92 #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ 93 #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ 94 #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ 95 #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ 96 #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ 97 #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ 98 #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ 99 #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ 100 #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ 101 #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ 102 #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ 103 #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ 104 #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ 105 #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ 106 #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ 107 #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ 108 #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ 109 #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ 110 #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ 111 #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ 112 #else 113 #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ 114 #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ 115 #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ 116 #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ 117 #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ 118 #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ 119 #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ 120 #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ 121 #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ 122 #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ 123 #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ 124 #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ 125 #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ 126 #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ 127 #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ 128 #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ 129 #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ 130 #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ 131 #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ 132 #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ 133 #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ 134 #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ 135 #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ 136 #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ 137 #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ 138 #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ 139 #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ 140 #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ 141 #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ 142 #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ 143 #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ 144 #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ 145 #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ 146 #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ 147 #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ 148 #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ 149 #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ 150 #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ 151 #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ 152 #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ 153 #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ 154 #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ 155 #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ 156 #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ 157 #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ 158 #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ 159 #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ 160 #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ 161 #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ 162 #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ 163 #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ 164 #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ 165 #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ 166 #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ 167 #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ 168 #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ 169 #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ 170 #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ 171 #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ 172 #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ 173 #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ 174 #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ 175 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #endif /* _SAMV71_PIOA_INSTANCE_ */ 178