1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_MLB_INSTANCE_ 46 #define _SAMV71_MLB_INSTANCE_ 47 48 /* ========== Register definition for MLB peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_MLB_MLBC0 (0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ 51 #define REG_MLB_MS0 (0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ 52 #define REG_MLB_MS1 (0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ 53 #define REG_MLB_MSS (0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ 54 #define REG_MLB_MSD (0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ 55 #define REG_MLB_MIEN (0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ 56 #define REG_MLB_MLBC1 (0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ 57 #define REG_MLB_HCTL (0x40068080U) /**< \brief (MLB) HBI Control Register */ 58 #define REG_MLB_HCMR (0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ 59 #define REG_MLB_HCER (0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ 60 #define REG_MLB_HCBR (0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ 61 #define REG_MLB_MDAT (0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ 62 #define REG_MLB_MDWE (0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ 63 #define REG_MLB_MCTL (0x400680E0U) /**< \brief (MLB) MIF Control Register */ 64 #define REG_MLB_MADR (0x400680E4U) /**< \brief (MLB) MIF Address Register */ 65 #define REG_MLB_ACTL (0x400683C0U) /**< \brief (MLB) AHB Control Register */ 66 #define REG_MLB_ACSR (0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ 67 #define REG_MLB_ACMR (0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ 68 #else 69 #define REG_MLB_MLBC0 (*(__IO uint32_t*)0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ 70 #define REG_MLB_MS0 (*(__IO uint32_t*)0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ 71 #define REG_MLB_MS1 (*(__IO uint32_t*)0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ 72 #define REG_MLB_MSS (*(__IO uint32_t*)0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ 73 #define REG_MLB_MSD (*(__I uint32_t*)0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ 74 #define REG_MLB_MIEN (*(__IO uint32_t*)0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ 75 #define REG_MLB_MLBC1 (*(__IO uint32_t*)0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ 76 #define REG_MLB_HCTL (*(__IO uint32_t*)0x40068080U) /**< \brief (MLB) HBI Control Register */ 77 #define REG_MLB_HCMR (*(__IO uint32_t*)0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ 78 #define REG_MLB_HCER (*(__I uint32_t*)0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ 79 #define REG_MLB_HCBR (*(__I uint32_t*)0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ 80 #define REG_MLB_MDAT (*(__IO uint32_t*)0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ 81 #define REG_MLB_MDWE (*(__IO uint32_t*)0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ 82 #define REG_MLB_MCTL (*(__IO uint32_t*)0x400680E0U) /**< \brief (MLB) MIF Control Register */ 83 #define REG_MLB_MADR (*(__IO uint32_t*)0x400680E4U) /**< \brief (MLB) MIF Address Register */ 84 #define REG_MLB_ACTL (*(__IO uint32_t*)0x400683C0U) /**< \brief (MLB) AHB Control Register */ 85 #define REG_MLB_ACSR (*(__IO uint32_t*)0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ 86 #define REG_MLB_ACMR (*(__IO uint32_t*)0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ 87 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 89 #endif /* _SAMV71_MLB_INSTANCE_ */ 90