1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_MCAN1_INSTANCE_ 46 #define _SAMV71_MCAN1_INSTANCE_ 47 48 /* ========== Register definition for MCAN1 peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_MCAN1_CUST (0x40034008U) /**< \brief (MCAN1) Customer Register */ 51 #define REG_MCAN1_FBTP (0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ 52 #define REG_MCAN1_TEST (0x40034010U) /**< \brief (MCAN1) Test Register */ 53 #define REG_MCAN1_RWD (0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ 54 #define REG_MCAN1_CCCR (0x40034018U) /**< \brief (MCAN1) CC Control Register */ 55 #define REG_MCAN1_BTP (0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ 56 #define REG_MCAN1_TSCC (0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ 57 #define REG_MCAN1_TSCV (0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ 58 #define REG_MCAN1_TOCC (0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ 59 #define REG_MCAN1_TOCV (0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ 60 #define REG_MCAN1_ECR (0x40034040U) /**< \brief (MCAN1) Error Counter Register */ 61 #define REG_MCAN1_PSR (0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ 62 #define REG_MCAN1_IR (0x40034050U) /**< \brief (MCAN1) Interrupt Register */ 63 #define REG_MCAN1_IE (0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ 64 #define REG_MCAN1_ILS (0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ 65 #define REG_MCAN1_ILE (0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ 66 #define REG_MCAN1_GFC (0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ 67 #define REG_MCAN1_SIDFC (0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ 68 #define REG_MCAN1_XIDFC (0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ 69 #define REG_MCAN1_XIDAM (0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ 70 #define REG_MCAN1_HPMS (0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ 71 #define REG_MCAN1_NDAT1 (0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ 72 #define REG_MCAN1_NDAT2 (0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ 73 #define REG_MCAN1_RXF0C (0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ 74 #define REG_MCAN1_RXF0S (0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ 75 #define REG_MCAN1_RXF0A (0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ 76 #define REG_MCAN1_RXBC (0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ 77 #define REG_MCAN1_RXF1C (0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ 78 #define REG_MCAN1_RXF1S (0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ 79 #define REG_MCAN1_RXF1A (0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ 80 #define REG_MCAN1_RXESC (0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ 81 #define REG_MCAN1_TXBC (0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ 82 #define REG_MCAN1_TXFQS (0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ 83 #define REG_MCAN1_TXESC (0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ 84 #define REG_MCAN1_TXBRP (0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ 85 #define REG_MCAN1_TXBAR (0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ 86 #define REG_MCAN1_TXBCR (0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ 87 #define REG_MCAN1_TXBTO (0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ 88 #define REG_MCAN1_TXBCF (0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ 89 #define REG_MCAN1_TXBTIE (0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ 90 #define REG_MCAN1_TXBCIE (0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 91 #define REG_MCAN1_TXEFC (0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ 92 #define REG_MCAN1_TXEFS (0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ 93 #define REG_MCAN1_TXEFA (0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ 94 #else 95 #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< \brief (MCAN1) Customer Register */ 96 #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ 97 #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< \brief (MCAN1) Test Register */ 98 #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ 99 #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< \brief (MCAN1) CC Control Register */ 100 #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ 101 #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ 102 #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ 103 #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ 104 #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ 105 #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< \brief (MCAN1) Error Counter Register */ 106 #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ 107 #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< \brief (MCAN1) Interrupt Register */ 108 #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ 109 #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ 110 #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ 111 #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ 112 #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ 113 #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ 114 #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ 115 #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ 116 #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ 117 #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ 118 #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ 119 #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ 120 #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ 121 #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ 122 #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ 123 #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ 124 #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ 125 #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ 126 #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ 127 #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ 128 #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ 129 #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ 130 #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ 131 #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ 132 #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ 133 #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ 134 #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ 135 #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 136 #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ 137 #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ 138 #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ 139 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #endif /* _SAMV71_MCAN1_INSTANCE_ */ 142