1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_MATRIX_INSTANCE_ 46 #define _SAMV71_MATRIX_INSTANCE_ 47 48 /* ========== Register definition for MATRIX peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_MATRIX_MCFG (0x40088000U) /**< \brief (MATRIX) Master Configuration Register */ 51 #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ 52 #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ 53 #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ 54 #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ 55 #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ 56 #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ 57 #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ 58 #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ 59 #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ 60 #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ 61 #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ 62 #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ 63 #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ 64 #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ 65 #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ 66 #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ 67 #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ 68 #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ 69 #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ 70 #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ 71 #define REG_CCFG_CAN0 (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ 72 #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ 73 #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ 74 #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ 75 #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ 76 #else 77 #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register */ 78 #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ 79 #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ 80 #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ 81 #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ 82 #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ 83 #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ 84 #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ 85 #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ 86 #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ 87 #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ 88 #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ 89 #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ 90 #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ 91 #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ 92 #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ 93 #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ 94 #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ 95 #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ 96 #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ 97 #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ 98 #define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ 99 #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ 100 #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ 101 #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ 102 #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ 103 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #endif /* _SAMV71_MATRIX_INSTANCE_ */ 106