1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_HSMCI_INSTANCE_ 46 #define _SAMV71_HSMCI_INSTANCE_ 47 48 /* ========== Register definition for HSMCI peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ 51 #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ 52 #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ 53 #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ 54 #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ 55 #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ 56 #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ 57 #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ 58 #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ 59 #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ 60 #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ 61 #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ 62 #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ 63 #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ 64 #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ 65 #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ 66 #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ 67 #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ 68 #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ 69 #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ 70 #else 71 #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ 72 #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ 73 #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ 74 #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ 75 #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ 76 #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ 77 #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ 78 #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ 79 #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ 80 #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ 81 #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ 82 #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ 83 #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ 84 #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ 85 #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ 86 #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ 87 #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ 88 #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ 89 #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ 90 #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ 91 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 92 93 #endif /* _SAMV71_HSMCI_INSTANCE_ */ 94