1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_AFEC1_INSTANCE_ 46 #define _SAMV71_AFEC1_INSTANCE_ 47 48 /* ========== Register definition for AFEC1 peripheral ========== */ 49 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ 51 #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ 52 #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ 53 #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ 54 #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ 55 #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ 56 #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ 57 #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ 58 #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ 59 #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ 60 #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ 61 #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ 62 #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ 63 #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ 64 #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ 65 #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ 66 #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ 67 #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ 68 #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ 69 #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ 70 #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ 71 #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ 72 #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ 73 #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ 74 #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ 75 #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ 76 #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ 77 #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ 78 #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ 79 #else 80 #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ 81 #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ 82 #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ 83 #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ 84 #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ 85 #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ 86 #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ 87 #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ 88 #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ 89 #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ 90 #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ 91 #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ 92 #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ 93 #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ 94 #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ 95 #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ 96 #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ 97 #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ 98 #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ 99 #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ 100 #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ 101 #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ 102 #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ 103 #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ 104 #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ 105 #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ 106 #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ 107 #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ 108 #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ 109 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 111 #endif /* _SAMV71_AFEC1_INSTANCE_ */ 112