1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_MLB_COMPONENT_ 46 #define _SAMV71_MLB_COMPONENT_ 47 48 /* ============================================================================= */ 49 /** SOFTWARE API DEFINITION FOR Media LB */ 50 /* ============================================================================= */ 51 /** \addtogroup SAMV71_MLB Media LB */ 52 /*@{*/ 53 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 /** \brief Mlb hardware registers */ 56 typedef struct { 57 __IO uint32_t MLB_MLBC0; /**< \brief (Mlb Offset: 0x000) MediaLB Control 0 Register */ 58 __I uint32_t Reserved1[2]; 59 __IO uint32_t MLB_MS0; /**< \brief (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register */ 60 __I uint32_t Reserved2[1]; 61 __IO uint32_t MLB_MS1; /**< \brief (Mlb Offset: 0x014) MediaLB Channel Status1 Register */ 62 __I uint32_t Reserved3[2]; 63 __IO uint32_t MLB_MSS; /**< \brief (Mlb Offset: 0x020) MediaLB System Status Register */ 64 __I uint32_t MLB_MSD; /**< \brief (Mlb Offset: 0x024) MediaLB System Data Register */ 65 __I uint32_t Reserved4[1]; 66 __IO uint32_t MLB_MIEN; /**< \brief (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register */ 67 __I uint32_t Reserved5[3]; 68 __IO uint32_t MLB_MLBC1; /**< \brief (Mlb Offset: 0x03C) MediaLB Control 1 Register */ 69 __I uint32_t Reserved6[1]; 70 __I uint32_t Reserved7[15]; 71 __IO uint32_t MLB_HCTL; /**< \brief (Mlb Offset: 0x080) HBI Control Register */ 72 __I uint32_t Reserved8[1]; 73 __IO uint32_t MLB_HCMR[2]; /**< \brief (Mlb Offset: 0x088) HBI Channel Mask 0 Register */ 74 __I uint32_t MLB_HCER[2]; /**< \brief (Mlb Offset: 0x090) HBI Channel Error 0 Register */ 75 __I uint32_t MLB_HCBR[2]; /**< \brief (Mlb Offset: 0x098) HBI Channel Busy 0 Register */ 76 __I uint32_t Reserved9[8]; 77 __IO uint32_t MLB_MDAT[4]; /**< \brief (Mlb Offset: 0x0C0) MIF Data 0 Register */ 78 __IO uint32_t MLB_MDWE[4]; /**< \brief (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register */ 79 __IO uint32_t MLB_MCTL; /**< \brief (Mlb Offset: 0x0E0) MIF Control Register */ 80 __IO uint32_t MLB_MADR; /**< \brief (Mlb Offset: 0x0E4) MIF Address Register */ 81 __I uint32_t Reserved10[182]; 82 __IO uint32_t MLB_ACTL; /**< \brief (Mlb Offset: 0x3C0) AHB Control Register */ 83 __I uint32_t Reserved11[3]; 84 __IO uint32_t MLB_ACSR[2]; /**< \brief (Mlb Offset: 0x3D0) AHB Channel Status 0 Register */ 85 __IO uint32_t MLB_ACMR[2]; /**< \brief (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register */ 86 } Mlb; 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 /* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */ 89 #define MLB_MLBC0_MLBEN (0x1u << 0) /**< \brief (MLB_MLBC0) MediaLB Enable */ 90 #define MLB_MLBC0_MLBCLK_Pos 2 91 #define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos) /**< \brief (MLB_MLBC0) MLB_CLK (MediaLB clock) speed select */ 92 #define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos))) 93 #define MLB_MLBC0_MLBCLK_256_FS (0x0u << 2) /**< \brief (MLB_MLBC0) 256xFs (for MLBPEN = 0) */ 94 #define MLB_MLBC0_MLBCLK_512_FS (0x1u << 2) /**< \brief (MLB_MLBC0) 512xFs (for MLBPEN = 0) */ 95 #define MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2) /**< \brief (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */ 96 #define MLB_MLBC0_ZERO (0x1u << 5) /**< \brief (MLB_MLBC0) Must be Written to 0 */ 97 #define MLB_MLBC0_MLBLK (0x1u << 7) /**< \brief (MLB_MLBC0) MediaLB Lock Status (read-only) */ 98 #define MLB_MLBC0_ASYRETRY (0x1u << 12) /**< \brief (MLB_MLBC0) Asynchronous Tx Packet Retry */ 99 #define MLB_MLBC0_CTLRETRY (0x1u << 14) /**< \brief (MLB_MLBC0) Control Tx Packet Retry */ 100 #define MLB_MLBC0_FCNT_Pos 15 101 #define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos) /**< \brief (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels */ 102 #define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos))) 103 #define MLB_MLBC0_FCNT_1_FRAME (0x0u << 15) /**< \brief (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */ 104 #define MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15) /**< \brief (MLB_MLBC0) 2 frames per sub-buffer */ 105 #define MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15) /**< \brief (MLB_MLBC0) 4 frames per sub-buffer */ 106 #define MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15) /**< \brief (MLB_MLBC0) 8 frames per sub-buffer */ 107 #define MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15) /**< \brief (MLB_MLBC0) 16 frames per sub-buffer */ 108 #define MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15) /**< \brief (MLB_MLBC0) 32 frames per sub-buffer */ 109 #define MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15) /**< \brief (MLB_MLBC0) 64 frames per sub-buffer */ 110 /* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */ 111 #define MLB_MS0_MCS_Pos 0 112 #define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos) /**< \brief (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) */ 113 #define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos))) 114 /* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */ 115 #define MLB_MS1_MCS_Pos 0 116 #define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos) /**< \brief (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) */ 117 #define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos))) 118 /* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */ 119 #define MLB_MSS_RSTSYSCMD (0x1u << 0) /**< \brief (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) */ 120 #define MLB_MSS_LKSYSCMD (0x1u << 1) /**< \brief (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */ 121 #define MLB_MSS_ULKSYSCMD (0x1u << 2) /**< \brief (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */ 122 #define MLB_MSS_CSSYSCMD (0x1u << 3) /**< \brief (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */ 123 #define MLB_MSS_SWSYSCMD (0x1u << 4) /**< \brief (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) */ 124 #define MLB_MSS_SERVREQ (0x1u << 5) /**< \brief (MLB_MSS) Service Request Enabled */ 125 /* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */ 126 #define MLB_MSD_SD0_Pos 0 127 #define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos) /**< \brief (MLB_MSD) System Data (Byte 0) */ 128 #define MLB_MSD_SD1_Pos 8 129 #define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos) /**< \brief (MLB_MSD) System Data (Byte 1) */ 130 #define MLB_MSD_SD2_Pos 16 131 #define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos) /**< \brief (MLB_MSD) System Data (Byte 2) */ 132 #define MLB_MSD_SD3_Pos 24 133 #define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos) /**< \brief (MLB_MSD) System Data (Byte 3) */ 134 /* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */ 135 #define MLB_MIEN_ISOC_PE (0x1u << 0) /**< \brief (MLB_MIEN) Isochronous Rx Protocol Error Enable */ 136 #define MLB_MIEN_ISOC_BUFO (0x1u << 1) /**< \brief (MLB_MIEN) Isochronous Rx Buffer Overflow Enable */ 137 #define MLB_MIEN_SYNC_PE (0x1u << 16) /**< \brief (MLB_MIEN) Synchronous Protocol Error Enable */ 138 #define MLB_MIEN_ARX_DONE (0x1u << 17) /**< \brief (MLB_MIEN) Asynchronous Rx Done Enable */ 139 #define MLB_MIEN_ARX_PE (0x1u << 18) /**< \brief (MLB_MIEN) Asynchronous Rx Protocol Error Enable */ 140 #define MLB_MIEN_ARX_BREAK (0x1u << 19) /**< \brief (MLB_MIEN) Asynchronous Rx Break Enable */ 141 #define MLB_MIEN_ATX_DONE (0x1u << 20) /**< \brief (MLB_MIEN) Asynchronous Tx Packet Done Enable */ 142 #define MLB_MIEN_ATX_PE (0x1u << 21) /**< \brief (MLB_MIEN) Asynchronous Tx Protocol Error Enable */ 143 #define MLB_MIEN_ATX_BREAK (0x1u << 22) /**< \brief (MLB_MIEN) Asynchronous Tx Break Enable */ 144 #define MLB_MIEN_CRX_DONE (0x1u << 24) /**< \brief (MLB_MIEN) Control Rx Packet Done Enable */ 145 #define MLB_MIEN_CRX_PE (0x1u << 25) /**< \brief (MLB_MIEN) Control Rx Protocol Error Enable */ 146 #define MLB_MIEN_CRX_BREAK (0x1u << 26) /**< \brief (MLB_MIEN) Control Rx Break Enable */ 147 #define MLB_MIEN_CTX_DONE (0x1u << 27) /**< \brief (MLB_MIEN) Control Tx Packet Done Enable */ 148 #define MLB_MIEN_CTX_PE (0x1u << 28) /**< \brief (MLB_MIEN) Control Tx Protocol Error Enable */ 149 #define MLB_MIEN_CTX_BREAK (0x1u << 29) /**< \brief (MLB_MIEN) Control Tx Break Enable */ 150 /* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */ 151 #define MLB_MLBC1_LOCK (0x1u << 6) /**< \brief (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) */ 152 #define MLB_MLBC1_CLKM (0x1u << 7) /**< \brief (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) */ 153 #define MLB_MLBC1_NDA_Pos 8 154 #define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos) /**< \brief (MLB_MLBC1) Node Device Address */ 155 #define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos))) 156 /* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */ 157 #define MLB_HCTL_RST0 (0x1u << 0) /**< \brief (MLB_HCTL) Address Generation Unit 0 Software Reset */ 158 #define MLB_HCTL_RST1 (0x1u << 1) /**< \brief (MLB_HCTL) Address Generation Unit 1 Software Reset */ 159 #define MLB_HCTL_EN (0x1u << 15) /**< \brief (MLB_HCTL) HBI Enable */ 160 /* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */ 161 #define MLB_HCMR_CHM_Pos 0 162 #define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos) /**< \brief (MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0] */ 163 #define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos))) 164 /* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */ 165 #define MLB_HCER_CERR_Pos 0 166 #define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos) /**< \brief (MLB_HCER[2]) Bitwise Channel Error Bit [31:0] */ 167 /* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */ 168 #define MLB_HCBR_CHB_Pos 0 169 #define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos) /**< \brief (MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0] */ 170 /* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */ 171 #define MLB_MDAT_DATA_Pos 0 172 #define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos) /**< \brief (MLB_MDAT[4]) CRT or DBR Data */ 173 #define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos))) 174 /* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */ 175 #define MLB_MDWE_MASK_Pos 0 176 #define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos) /**< \brief (MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0] */ 177 #define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos))) 178 /* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */ 179 #define MLB_MCTL_XCMP (0x1u << 0) /**< \brief (MLB_MCTL) Transfer Complete (Write 0 to Clear) */ 180 /* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */ 181 #define MLB_MADR_ADDR_Pos 0 182 #define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos) /**< \brief (MLB_MADR) CTR or DBR Address */ 183 #define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos))) 184 #define MLB_MADR_TB (0x1u << 30) /**< \brief (MLB_MADR) Target Location Bit */ 185 #define MLB_MADR_TB_CTR (0x0u << 30) /**< \brief (MLB_MADR) Selects CTR */ 186 #define MLB_MADR_TB_DBR (0x1u << 30) /**< \brief (MLB_MADR) Selects DBR */ 187 #define MLB_MADR_WNR (0x1u << 31) /**< \brief (MLB_MADR) Write-Not-Read Selection */ 188 /* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */ 189 #define MLB_ACTL_SCE (0x1u << 0) /**< \brief (MLB_ACTL) Software Clear Enable */ 190 #define MLB_ACTL_SMX (0x1u << 1) /**< \brief (MLB_ACTL) AHB Interrupt Mux Enable */ 191 #define MLB_ACTL_DMA_MODE (0x1u << 2) /**< \brief (MLB_ACTL) DMA Mode */ 192 #define MLB_ACTL_MPB (0x1u << 4) /**< \brief (MLB_ACTL) DMA Packet Buffering Mode */ 193 #define MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4) /**< \brief (MLB_ACTL) Single-packet mode */ 194 #define MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4) /**< \brief (MLB_ACTL) Multiple-packet mode */ 195 /* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */ 196 #define MLB_ACSR_CHS_Pos 0 197 #define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos) /**< \brief (MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */ 198 #define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos))) 199 /* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */ 200 #define MLB_ACMR_CHM_Pos 0 201 #define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos) /**< \brief (MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0 */ 202 #define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos))) 203 204 /*@}*/ 205 206 207 #endif /* _SAMV71_MLB_COMPONENT_ */ 208