1 /* 2 * Copyright (C) 2009-2012 by Matthias Ringwald 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY MATTHIAS RINGWALD AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS 24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at [email protected] 34 * 35 */ 36 37 /* 38 * btstack_chipset_cc256x.c 39 * 40 * Adapter to use cc256x-based chipsets with BTstack 41 * 42 * Handles init script (a.k.a. Service Patch) 43 * Allows for non-standard UART baud rate 44 * Allows to configure transmit power 45 * Allows to activate eHCILL deep sleep mode 46 * 47 * Issues with mspgcc LTS: 48 * - 20 bit support is not there yet -> .text cannot get bigger than 48 kb 49 * - arrays cannot have more than 32k entries 50 * 51 * workarounds: 52 * - store init script in .fartext and use assembly code to read from there 53 * - split into two arrays 54 * 55 * Issues with AVR 56 * - Harvard architecture doesn't allow to store init script directly -> use avr-libc helpers 57 * 58 * Documentation for TI VS CC256x commands: http://processors.wiki.ti.com/index.php/CC256x_VS_HCI_Commands 59 * 60 */ 61 62 #include "btstack_config.h" 63 #include "btstack_chipset_cc256x.h" 64 65 #include <stddef.h> /* NULL */ 66 #include <stdio.h> 67 #include <string.h> /* memcpy */ 68 69 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 70 #include "hal_compat.h" 71 #endif 72 73 #ifdef __AVR__ 74 #include <avr/pgmspace.h> 75 #endif 76 77 #include "btstack_control.h" 78 79 80 // actual init script provided by seperate .c file 81 extern const uint8_t cc256x_init_script[]; 82 extern const uint32_t cc256x_init_script_size; 83 84 // init script 85 static uint32_t init_script_offset = 0; 86 static int16_t init_power_in_dB = 13; // 13 dBm 87 88 // support for SCO over HCI 89 #ifdef ENABLE_SCO_OVER_HCI 90 static int init_send_route_sco_over_hci = 0; 91 static const uint8_t hci_route_sco_over_hci[] = { 92 #if 1 93 // Follow recommendation from https://e2e.ti.com/support/wireless_connectivity/bluetooth_cc256x/f/660/t/397004 94 // route SCO over HCI (connection type=1, tx buffer size = 120, tx buffer max latency= 720, accept packets with CRC Error 95 0x10, 0xfe, 0x05, 0x01, 0x78, 0xd0, 0x02, 0x01, 96 #else 97 // Configure SCO via I2S interface - 256 kbps 98 // Send_HCI_VS_Write_CODEC_Config 0xFD06, 99 0x06, 0xfd, 100 // len 101 34, 102 //3072, - clock rate 3072000 hz 103 0x00, 0x01, 104 // 0x00 - clock direction: output = master 105 0x00, 106 // 8000, framesync frequency in hz 107 0x40, 0x1f, 0x00, 0x00, 108 // 0x0001, framesync duty cycle 109 0x01, 0x00, 110 // 1, framesync edge 111 1, 112 // 0x00, framesync polarity 113 0x00, 114 // 0x00, RESERVED 115 0x00, 116 // 16, channel 1 out size 117 8, 0, 118 // 0x0001, channel 1 out offset 119 0x01, 0x00, 120 // 1, channel 1 out edge 121 1, 122 // 16, channel 1 in size 123 8, 0, 124 // 0x0001, channel 1 in offset 125 0x01, 0x00, 126 // 0, channel 1 in edge 127 0, 128 // 0x00, RESERVED 129 0x00, 130 // 16, channel 2 out size 131 8, 0, 132 // 17, channel 2 out offset 133 9, 0, 134 // 0x01, channel 2 out edge 135 0x01, 136 // 16, channel 2 in size 137 8, 0, 138 // 17, channel 2 in offset 139 9, 0, 140 // 0x00, channel 2 in edge 141 0x00, 142 // 0x0001, RESERVED 143 0x00 144 #endif 145 }; 146 #endif 147 148 static void chipset_init(const void * config){ 149 init_script_offset = 0; 150 #ifdef ENABLE_SCO_OVER_HCI 151 init_send_route_sco_over_hci = 1; 152 #endif 153 } 154 155 static void chipset_set_baudrate_command(uint32_t baudrate, uint8_t *hci_cmd_buffer){ 156 hci_cmd_buffer[0] = 0x36; 157 hci_cmd_buffer[1] = 0xFF; 158 hci_cmd_buffer[2] = 0x04; 159 hci_cmd_buffer[3] = baudrate & 0xff; 160 hci_cmd_buffer[4] = (baudrate >> 8) & 0xff; 161 hci_cmd_buffer[5] = (baudrate >> 16) & 0xff; 162 hci_cmd_buffer[6] = 0; 163 } 164 165 static void chipset_set_bd_addr_command(bd_addr_t addr, uint8_t *hci_cmd_buffer){ 166 hci_cmd_buffer[0] = 0x06; 167 hci_cmd_buffer[1] = 0xFC; 168 hci_cmd_buffer[2] = 0x06; 169 reverse_bd_addr(addr, &hci_cmd_buffer[3]); 170 } 171 172 // Output Power control from: http://e2e.ti.com/support/low_power_rf/f/660/p/134853/484767.aspx 173 #define NUM_POWER_LEVELS 16 174 #define DB_MIN_LEVEL -35 175 #define DB_PER_LEVEL 5 176 #define DB_DYNAMIC_RANGE 30 177 178 static int get_max_power_for_modulation_type(int type){ 179 // a) limit max output power 180 int power_db; 181 switch (type){ 182 case 0: // GFSK 183 power_db = 12; 184 break; 185 default: // EDRx 186 power_db = 10; 187 break; 188 } 189 if (power_db > init_power_in_dB) { 190 power_db = init_power_in_dB; 191 } 192 return power_db; 193 } 194 195 static int get_highest_level_for_given_power(int power_db, int recommended_db){ 196 int i = NUM_POWER_LEVELS-1; 197 while (i) { 198 if (power_db <= recommended_db) { 199 return i; 200 } 201 power_db -= DB_PER_LEVEL; 202 i--; 203 } 204 return 0; 205 } 206 207 static void update_set_power_vector(uint8_t *hci_cmd_buffer){ 208 int i; 209 int modulation_type = hci_cmd_buffer[3]; 210 int power_db = get_max_power_for_modulation_type(modulation_type); 211 int dynamic_range = 0; 212 213 // f) don't touch level 0 214 for ( i = (NUM_POWER_LEVELS-1) ; i >= 1 ; i--){ 215 216 #ifdef ENABLE_BLE 217 // level 1 is BLE transmit power for GFSK 218 if (i == 1 && modulation_type == 0) { 219 hci_cmd_buffer[4+1] = 2 * get_max_power_for_modulation_type(modulation_type); 220 // as level 0 isn't set, we're done 221 continue; 222 } 223 #endif 224 hci_cmd_buffer[4+i] = 2 * power_db; 225 226 if (dynamic_range + DB_PER_LEVEL > DB_DYNAMIC_RANGE) continue; // e) 227 228 power_db -= DB_PER_LEVEL; // d) 229 dynamic_range += DB_PER_LEVEL; 230 231 if (power_db > DB_MIN_LEVEL) continue; 232 233 power_db = DB_MIN_LEVEL; // b) 234 } 235 } 236 237 // max permitted power for class 2 devices: 4 dBm 238 static void update_set_class2_single_power(uint8_t * hci_cmd_buffer){ 239 const int max_power_class_2 = 4; 240 int i = 0; 241 for (i=0;i<3;i++){ 242 hci_cmd_buffer[3+i] = get_highest_level_for_given_power(get_max_power_for_modulation_type(i), max_power_class_2); 243 } 244 } 245 246 // eHCILL activate from http://e2e.ti.com/support/low_power_rf/f/660/p/134855/484776.aspx 247 static void update_sleep_mode_configurations(uint8_t * hci_cmd_buffer){ 248 #ifdef ENABLE_EHCILL 249 hci_cmd_buffer[4] = 1; 250 #else 251 hci_cmd_buffer[4] = 0; 252 #endif 253 } 254 255 static void update_init_script_command(uint8_t *hci_cmd_buffer){ 256 257 uint16_t opcode = hci_cmd_buffer[0] | (hci_cmd_buffer[1] << 8); 258 259 switch (opcode){ 260 case 0xFD87: 261 update_set_class2_single_power(hci_cmd_buffer); 262 break; 263 case 0xFD82: 264 update_set_power_vector(hci_cmd_buffer); 265 break; 266 case 0xFD0C: 267 update_sleep_mode_configurations(hci_cmd_buffer); 268 break; 269 default: 270 break; 271 } 272 } 273 274 static btstack_chipset_result_t chipset_next_command(uint8_t * hci_cmd_buffer){ 275 if (init_script_offset >= cc256x_init_script_size) { 276 277 #ifdef ENABLE_SCO_OVER_HCI 278 // append send route SCO over HCI if requested 279 if (init_send_route_sco_over_hci){ 280 init_send_route_sco_over_hci = 0; 281 memcpy(hci_cmd_buffer, hci_route_sco_over_hci, sizeof(hci_route_sco_over_hci)); 282 return BTSTACK_CHIPSET_VALID_COMMAND; 283 } 284 #endif 285 286 return BTSTACK_CHIPSET_DONE; 287 } 288 289 // extracted init script has 0x01 cmd packet type, but BTstack expects them without 290 init_script_offset++; 291 292 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 293 294 // workaround: use FlashReadBlock with 32-bit integer and assume init script starts at 0x10000 295 uint32_t init_script_addr = 0x10000; 296 FlashReadBlock(&hci_cmd_buffer[0], init_script_addr + init_script_offset, 3); // cmd header 297 init_script_offset += 3; 298 int payload_len = hci_cmd_buffer[2]; 299 FlashReadBlock(&hci_cmd_buffer[3], init_script_addr + init_script_offset, payload_len); // cmd payload 300 301 #elif defined (__AVR__) 302 303 // workaround: use memcpy_P to access init script in lower 64 kB of flash 304 memcpy_P(&hci_cmd_buffer[0], &cc256x_init_script[init_script_offset], 3); 305 init_script_offset += 3; 306 int payload_len = hci_cmd_buffer[2]; 307 memcpy_P(&hci_cmd_buffer[3], &cc256x_init_script[init_script_offset], payload_len); 308 309 #else 310 311 // use memcpy with pointer 312 uint8_t * init_script_ptr = (uint8_t*) &cc256x_init_script[0]; 313 memcpy(&hci_cmd_buffer[0], init_script_ptr + init_script_offset, 3); // cmd header 314 init_script_offset += 3; 315 int payload_len = hci_cmd_buffer[2]; 316 memcpy(&hci_cmd_buffer[3], init_script_ptr + init_script_offset, payload_len); // cmd payload 317 318 #endif 319 320 init_script_offset += payload_len; 321 322 // control power commands and ehcill 323 update_init_script_command(hci_cmd_buffer); 324 325 return BTSTACK_CHIPSET_VALID_COMMAND; 326 } 327 328 329 // MARK: public API 330 void btstack_chipset_cc256x_set_power(int16_t power_in_dB){ 331 init_power_in_dB = power_in_dB; 332 } 333 334 static const btstack_chipset_t btstack_chipset_cc256x = { 335 "CC256x", 336 chipset_init, 337 chipset_next_command, 338 chipset_set_baudrate_command, 339 chipset_set_bd_addr_command, 340 }; 341 342 const btstack_chipset_t * btstack_chipset_cc256x_instance(void){ 343 return &btstack_chipset_cc256x; 344 } 345 346