1 /*
2 * Copyright (C) 2009-2012 by Matthias Ringwald
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the copyright holders nor the names of
14 * contributors may be used to endorse or promote products derived
15 * from this software without specific prior written permission.
16 * 4. Any redistribution, use, or modification is done solely for
17 * personal benefit and not for any commercial purpose or for
18 * monetary gain.
19 *
20 * THIS SOFTWARE IS PROVIDED BY MATTHIAS RINGWALD AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS
24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * Please inquire about commercial licensing options at [email protected]
34 *
35 */
36
37 #define BTSTACK_FILE__ "btstack_chipset_cc256x.c"
38
39 /*
40 * btstack_chipset_cc256x.c
41 *
42 * Adapter to use cc256x-based chipsets with BTstack
43 *
44 * Handles init script (a.k.a. Service Patch)
45 * Allows for non-standard UART baud rate
46 * Allows to configure transmit power
47 * Allows to activate eHCILL deep sleep mode
48 *
49 * Issues with mspgcc LTS:
50 * - 20 bit support is not there yet -> .text cannot get bigger than 48 kb
51 * - arrays cannot have more than 32k entries
52 *
53 * workarounds:
54 * - store init script in .fartext and use assembly code to read from there
55 * - split into two arrays
56 *
57 * Issues with AVR
58 * - Harvard architecture doesn't allow to store init script directly -> use avr-libc helpers
59 *
60 * Documentation for TI VS CC256x commands: http://processors.wiki.ti.com/index.php/CC256x_VS_HCI_Commands
61 *
62 */
63
64 #include "btstack_config.h"
65 #include "btstack_chipset_cc256x.h"
66 #include "btstack_debug.h"
67 #include "hci.h"
68
69 #include <stddef.h> /* NULL */
70 #include <stdio.h>
71 #include <string.h> /* memcpy */
72
73 // assert outgoing and incoming hci packet buffers can hold max hci command resp. event packet
74 #if HCI_OUTGOING_PACKET_BUFFER_SIZE < (HCI_CMD_HEADER_SIZE + 255)
75 #error "HCI_OUTGOING_PACKET_BUFFER_SIZE to small. Outgoing HCI packet buffer to small for largest HCI Command packet. Please set HCI_ACL_PAYLOAD_SIZE to 258 or higher."
76 #endif
77 #if HCI_INCOMING_PACKET_BUFFER_SIZE < (HCI_EVENT_HEADER_SIZE + 255)
78 #error "HCI_INCOMING_PACKET_BUFFER_SIZE to small. Incoming HCI packet buffer to small for largest HCI Event packet. Please set HCI_ACL_PAYLOAD_SIZE to 257 or higher."
79 #endif
80
81 #if defined(ENABLE_SCO_OVER_HCI) && defined(ENABLE_SCO_OVER_PCM)
82 #error "SCO can either be routed over HCI or PCM, please define only one of: ENABLE_SCO_OVER_HCI or ENABLE_SCO_OVER_PCM"
83 #endif
84
85 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0)
86 #include "hal_compat.h"
87 #endif
88
89 #ifdef __AVR__
90 #include <avr/pgmspace.h>
91 #endif
92
93 #include "btstack_control.h"
94
95
96 // default init script provided by separate .c file
97 extern const uint8_t cc256x_init_script[];
98 extern const uint32_t cc256x_init_script_size;
99
100 // custom init script set by btstack_chipset_cc256x_set_init_script
101 // used to select init scripts before each power up
102 static const uint8_t * custom_init_script;
103 static uint32_t custom_init_script_size;
104
105 // init script to use: either cc256x_init_script or custom_init_script
106 static const uint8_t * init_script;
107 static uint32_t init_script_size;
108
109 // power in db - set by btstack_chipset_cc256x_set_power
110 static int16_t init_power_in_dB = 13; // 13 dBm
111
112 // explicit power vectors of 16 uint8_t bytes
113 static const uint8_t * init_power_vectors[3];
114
115 // upload position
116 static uint32_t init_script_offset = 0;
117
118 // support for SCO over HCI
119 #ifdef ENABLE_SCO_OVER_HCI
120 static int init_send_route_sco_over_hci = 0;
121 static const uint8_t hci_route_sco_over_hci[] = {
122 // Follow recommendation from https://e2e.ti.com/support/wireless_connectivity/bluetooth_cc256x/f/660/t/397004
123 // route SCO over HCI (connection type=1, tx buffer size = 120, tx buffer max latency= 720, accept packets with CRC Error
124 0x10, 0xfe, 0x05, 0x01, 0x78, 0xd0, 0x02, 0x01,
125 };
126 #endif
127 #ifdef ENABLE_SCO_OVER_PCM
128 static int init_send_sco_i2s_config_cvsd = 0;
129 static const uint8_t hci_write_codec_config_cvsd[] = {
130 0x06, 0xFD, // HCI opcode = HCI_VS_Write_CODEC_Config
131 0x22, // HCI param length
132 0x00, 0x01, // PCM clock rate 256, - clock rate 256000 Hz
133 0x00, // PCM clock direction = master
134 0x40, 0x1F, 0x00, 0x00, // PCM frame sync = 8kHz
135 0x10, 0x00, // PCM frame sync duty cycle = 16 clk
136 0x01, // PCM frame edge = rising edge
137 0x00, // PCM frame polarity = active high
138 0x00, // Reserved
139 0x10, 0x00, // PCM channel 1 out size = 16
140 0x01, 0x00, // PCM channel 1 out offset = 1
141 0x01, // PCM channel 1 out edge = rising
142 0x10, 0x00, // PCM channel 1 in size = 16
143 0x01, 0x00, // PCM channel 1 in offset = 1
144 0x00, // PCM channel 1 in edge = falling
145 0x00, // Reserved
146 0x10, 0x00, // PCM channel 2 out size = 16
147 0x11, 0x00, // PCM channel 2 out offset = 17
148 0x01, // PCM channel 2 out edge = rising
149 0x10, 0x00, // PCM channel 2 in size = 16
150 0x11, 0x00, // PCM channel 2 in offset = 17
151 0x00, // PCM channel 2 in edge = falling
152 0x00, // Reserved
153 };
154 #endif
155
chipset_init(const void * config)156 static void chipset_init(const void * config){
157 UNUSED(config);
158 init_script_offset = 0;
159 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0)
160 // On MSP430, custom init script is not supported
161 init_script_size = cc256x_init_script_size;
162 #else
163 if (custom_init_script){
164 log_info("cc256x: using custom init script");
165 init_script = custom_init_script;
166 init_script_size = custom_init_script_size;
167 } else {
168 log_info("cc256x: using default init script");
169 init_script = cc256x_init_script;
170 init_script_size = cc256x_init_script_size;
171 }
172 #endif
173 #ifdef ENABLE_SCO_OVER_HCI
174 init_send_route_sco_over_hci = 1;
175 #endif
176 #ifdef ENABLE_SCO_OVER_PCM
177 init_send_sco_i2s_config_cvsd = 1;
178 #endif
179 }
180
chipset_set_baudrate_command(uint32_t baudrate,uint8_t * hci_cmd_buffer)181 static void chipset_set_baudrate_command(uint32_t baudrate, uint8_t *hci_cmd_buffer){
182 hci_cmd_buffer[0] = 0x36;
183 hci_cmd_buffer[1] = 0xFF;
184 hci_cmd_buffer[2] = 0x04;
185 hci_cmd_buffer[3] = baudrate & 0xff;
186 hci_cmd_buffer[4] = (baudrate >> 8) & 0xff;
187 hci_cmd_buffer[5] = (baudrate >> 16) & 0xff;
188 hci_cmd_buffer[6] = 0;
189 }
190
chipset_set_bd_addr_command(bd_addr_t addr,uint8_t * hci_cmd_buffer)191 static void chipset_set_bd_addr_command(bd_addr_t addr, uint8_t *hci_cmd_buffer){
192 hci_cmd_buffer[0] = 0x06;
193 hci_cmd_buffer[1] = 0xFC;
194 hci_cmd_buffer[2] = 0x06;
195 reverse_bd_addr(addr, &hci_cmd_buffer[3]);
196 }
197
198 // Output Power control from: http://e2e.ti.com/support/low_power_rf/f/660/p/134853/484767.aspx
199 #define NUM_POWER_LEVELS 16
200 #define DB_MIN_LEVEL -35
201 #define DB_PER_LEVEL 5
202 #define DB_DYNAMIC_RANGE 30
203
get_max_power_for_modulation_type(int type)204 static int get_max_power_for_modulation_type(int type){
205 // a) limit max output power
206 int power_db;
207 switch (type){
208 case 0: // GFSK
209 power_db = 12;
210 break;
211 default: // EDRx
212 power_db = 10;
213 break;
214 }
215 if (power_db > init_power_in_dB) {
216 power_db = init_power_in_dB;
217 }
218 return power_db;
219 }
220
get_highest_level_for_given_power(int power_db,int recommended_db)221 static int get_highest_level_for_given_power(int power_db, int recommended_db){
222 int i = NUM_POWER_LEVELS-1;
223 while (i) {
224 if (power_db <= recommended_db) {
225 return i;
226 }
227 power_db -= DB_PER_LEVEL;
228 i--;
229 }
230 return 0;
231 }
232
update_set_power_vector(uint8_t * hci_cmd_buffer)233 static void update_set_power_vector(uint8_t *hci_cmd_buffer){
234 uint8_t modulation_type = hci_cmd_buffer[3];
235 btstack_assert(modulation_type <= 2);
236
237 // explicit power vector provided by user
238 if (init_power_vectors[modulation_type] != NULL){
239 (void)memcpy(&hci_cmd_buffer[4], init_power_vectors[modulation_type], 16);
240 return;
241 }
242
243 unsigned int i;
244 int power_db = get_max_power_for_modulation_type(modulation_type);
245 int dynamic_range = 0;
246
247 // f) don't touch level 0
248 for ( i = (NUM_POWER_LEVELS-1) ; i >= 1 ; i--){
249
250 #ifdef ENABLE_BLE
251 // level 1 is BLE transmit power for GFSK
252 if (i == 1 && modulation_type == 0) {
253 hci_cmd_buffer[4+1] = 2 * get_max_power_for_modulation_type(modulation_type);
254 // as level 0 isn't set, we're done
255 continue;
256 }
257 #endif
258 hci_cmd_buffer[4+i] = 2 * power_db;
259
260 if (dynamic_range + DB_PER_LEVEL > DB_DYNAMIC_RANGE) continue; // e)
261
262 power_db -= DB_PER_LEVEL; // d)
263 dynamic_range += DB_PER_LEVEL;
264
265 if (power_db > DB_MIN_LEVEL) continue;
266
267 power_db = DB_MIN_LEVEL; // b)
268 }
269 }
270
271 // max permitted power for class 2 devices: 4 dBm
update_set_class2_single_power(uint8_t * hci_cmd_buffer)272 static void update_set_class2_single_power(uint8_t * hci_cmd_buffer){
273 const int max_power_class_2 = 4;
274 int i = 0;
275 for (i=0;i<3;i++){
276 hci_cmd_buffer[3+i] = get_highest_level_for_given_power(get_max_power_for_modulation_type(i), max_power_class_2);
277 }
278 }
279
280 // eHCILL activate from http://e2e.ti.com/support/low_power_rf/f/660/p/134855/484776.aspx
update_sleep_mode_configurations(uint8_t * hci_cmd_buffer)281 static void update_sleep_mode_configurations(uint8_t * hci_cmd_buffer){
282 #ifdef ENABLE_EHCILL
283 hci_cmd_buffer[4] = 1;
284 #else
285 hci_cmd_buffer[4] = 0;
286 #endif
287 }
288
update_init_script_command(uint8_t * hci_cmd_buffer)289 static void update_init_script_command(uint8_t *hci_cmd_buffer){
290
291 uint16_t opcode = hci_cmd_buffer[0] | (hci_cmd_buffer[1] << 8);
292
293 switch (opcode){
294 case 0xFD87:
295 update_set_class2_single_power(hci_cmd_buffer);
296 break;
297 case 0xFD82:
298 update_set_power_vector(hci_cmd_buffer);
299 break;
300 case 0xFD0C:
301 update_sleep_mode_configurations(hci_cmd_buffer);
302 break;
303 default:
304 break;
305 }
306 }
307
chipset_next_command(uint8_t * hci_cmd_buffer)308 static btstack_chipset_result_t chipset_next_command(uint8_t * hci_cmd_buffer){
309 if (init_script_offset >= init_script_size) {
310
311 #ifdef ENABLE_SCO_OVER_HCI
312 // append send route SCO over HCI if requested
313 if (init_send_route_sco_over_hci){
314 init_send_route_sco_over_hci = 0;
315 memcpy(hci_cmd_buffer, hci_route_sco_over_hci, sizeof(hci_route_sco_over_hci));
316 return BTSTACK_CHIPSET_VALID_COMMAND;
317 }
318 #endif
319 #ifdef ENABLE_SCO_OVER_PCM
320 // append sco i2s cvsd config
321 if (init_send_sco_i2s_config_cvsd){
322 init_send_sco_i2s_config_cvsd = 0;
323 memcpy(hci_cmd_buffer, hci_write_codec_config_cvsd, sizeof(hci_write_codec_config_cvsd));
324 return BTSTACK_CHIPSET_VALID_COMMAND;
325 }
326 #endif
327 return BTSTACK_CHIPSET_DONE;
328 }
329
330 // extracted init script has 0x01 cmd packet type, but BTstack expects them without
331 init_script_offset++;
332
333 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0)
334
335 // workaround: use FlashReadBlock with 32-bit integer and assume init script starts at 0x10000
336 uint32_t init_script_addr = 0x10000;
337 FlashReadBlock(&hci_cmd_buffer[0], init_script_addr + init_script_offset, 3); // cmd header
338 init_script_offset += 3;
339 int payload_len = hci_cmd_buffer[2];
340 FlashReadBlock(&hci_cmd_buffer[3], init_script_addr + init_script_offset, payload_len); // cmd payload
341
342 #elif defined (__AVR__)
343
344 // workaround: use memcpy_P to access init script in lower 64 kB of flash
345 memcpy_P(&hci_cmd_buffer[0], &init_script[init_script_offset], 3);
346 init_script_offset += 3;
347 int payload_len = hci_cmd_buffer[2];
348 memcpy_P(&hci_cmd_buffer[3], &init_script[init_script_offset], payload_len);
349
350 #else
351
352 // use memcpy with pointer
353 uint8_t * init_script_ptr = (uint8_t*) &init_script[0];
354 memcpy(&hci_cmd_buffer[0], init_script_ptr + init_script_offset, 3); // cmd header
355 init_script_offset += 3;
356 int payload_len = hci_cmd_buffer[2];
357 memcpy(&hci_cmd_buffer[3], init_script_ptr + init_script_offset, payload_len); // cmd payload
358
359 #endif
360
361 init_script_offset += payload_len;
362
363 // control power commands and ehcill
364 update_init_script_command(hci_cmd_buffer);
365
366 return BTSTACK_CHIPSET_VALID_COMMAND;
367 }
368
369
370 // MARK: public API
btstack_chipset_cc256x_set_power(int16_t power_in_dB)371 void btstack_chipset_cc256x_set_power(int16_t power_in_dB){
372 init_power_in_dB = power_in_dB;
373 }
374
btstack_chipset_cc256x_set_power_vector(uint8_t modulation_type,const uint8_t * power_vector)375 void btstack_chipset_cc256x_set_power_vector(uint8_t modulation_type, const uint8_t * power_vector){
376 btstack_assert(modulation_type <= 2);
377 init_power_vectors[modulation_type] = power_vector;
378 }
379
btstack_chipset_cc256x_set_init_script(uint8_t * data,uint32_t size)380 void btstack_chipset_cc256x_set_init_script(uint8_t * data, uint32_t size){
381 custom_init_script = data;
382 custom_init_script_size = size;
383 }
384
385 static const btstack_chipset_t btstack_chipset_cc256x = {
386 "CC256x",
387 chipset_init,
388 chipset_next_command,
389 chipset_set_baudrate_command,
390 chipset_set_bd_addr_command,
391 };
392
btstack_chipset_cc256x_instance(void)393 const btstack_chipset_t * btstack_chipset_cc256x_instance(void){
394 return &btstack_chipset_cc256x;
395 }
396
397