1 /* 2 * Copyright (C) 2009-2012 by Matthias Ringwald 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY MATTHIAS RINGWALD AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS 24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at [email protected] 34 * 35 */ 36 37 #define BTSTACK_FILE__ "btstack_chipset_cc256x.c" 38 39 /* 40 * btstack_chipset_cc256x.c 41 * 42 * Adapter to use cc256x-based chipsets with BTstack 43 * 44 * Handles init script (a.k.a. Service Patch) 45 * Allows for non-standard UART baud rate 46 * Allows to configure transmit power 47 * Allows to activate eHCILL deep sleep mode 48 * 49 * Issues with mspgcc LTS: 50 * - 20 bit support is not there yet -> .text cannot get bigger than 48 kb 51 * - arrays cannot have more than 32k entries 52 * 53 * workarounds: 54 * - store init script in .fartext and use assembly code to read from there 55 * - split into two arrays 56 * 57 * Issues with AVR 58 * - Harvard architecture doesn't allow to store init script directly -> use avr-libc helpers 59 * 60 * Documentation for TI VS CC256x commands: http://processors.wiki.ti.com/index.php/CC256x_VS_HCI_Commands 61 * 62 */ 63 64 #include "btstack_config.h" 65 #include "btstack_chipset_cc256x.h" 66 #include "btstack_debug.h" 67 #include "hci.h" 68 69 #include <stddef.h> /* NULL */ 70 #include <stdio.h> 71 #include <string.h> /* memcpy */ 72 73 // assert outgoing and incoming hci packet buffers can hold max hci command resp. event packet 74 #if HCI_OUTGOING_PACKET_BUFFER_SIZE < (HCI_CMD_HEADER_SIZE + 255) 75 #error "HCI_OUTGOING_PACKET_BUFFER_SIZE to small. Outgoing HCI packet buffer to small for largest HCI Command packet. Please set HCI_ACL_PAYLOAD_SIZE to 258 or higher." 76 #endif 77 #if HCI_INCOMING_PACKET_BUFFER_SIZE < (HCI_EVENT_HEADER_SIZE + 255) 78 #error "HCI_INCOMING_PACKET_BUFFER_SIZE to small. Incoming HCI packet buffer to small for largest HCI Event packet. Please set HCI_ACL_PAYLOAD_SIZE to 257 or higher." 79 #endif 80 81 #if defined(ENABLE_SCO_OVER_HCI) && defined(ENABLE_SCO_OVER_PCM) 82 #error "SCO can either be routed over HCI or PCM, please define only one of: ENABLE_SCO_OVER_HCI or ENABLE_SCO_OVER_PCM" 83 #endif 84 85 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 86 #include "hal_compat.h" 87 #endif 88 89 #ifdef __AVR__ 90 #include <avr/pgmspace.h> 91 #endif 92 93 #include "btstack_control.h" 94 95 96 // default init script provided by separate .c file 97 extern const uint8_t cc256x_init_script[]; 98 extern const uint32_t cc256x_init_script_size; 99 100 // custom init script set by btstack_chipset_cc256x_set_init_script 101 // used to select init scripts before each power up 102 static const uint8_t * custom_init_script; 103 static uint32_t custom_init_script_size; 104 105 // init script to use: either cc256x_init_script or custom_init_script 106 static const uint8_t * init_script; 107 static uint32_t init_script_size; 108 109 // power in db - set by btstack_chipset_cc256x_set_power 110 static int16_t init_power_in_dB = 13; // 13 dBm 111 112 // explicit power vectors of 16 uint8_t bytes 113 static const uint8_t * init_power_vectors[3]; 114 115 // upload position 116 static uint32_t init_script_offset = 0; 117 118 // support for SCO over HCI 119 #ifdef ENABLE_SCO_OVER_HCI 120 static int init_send_route_sco_over_hci = 0; 121 static const uint8_t hci_route_sco_over_hci[] = { 122 // Follow recommendation from https://e2e.ti.com/support/wireless_connectivity/bluetooth_cc256x/f/660/t/397004 123 // route SCO over HCI (connection type=1, tx buffer size = 120, tx buffer max latency= 720, accept packets with CRC Error 124 0x10, 0xfe, 0x05, 0x01, 0x78, 0xd0, 0x02, 0x01, 125 }; 126 #endif 127 #ifdef ENABLE_SCO_OVER_PCM 128 static int init_send_sco_i2s_config_cvsd = 0; 129 static const uint8_t hci_write_codec_config_cvsd[] = { 130 0x06, 0xFD, // HCI opcode = HCI_VS_Write_CODEC_Config 131 0x22, // HCI param length 132 0x00, 0x01, // PCM clock rate 256, - clock rate 256000 Hz 133 0x00, // PCM clock direction = master 134 0x40, 0x1F, 0x00, 0x00, // PCM frame sync = 8kHz 135 0x10, 0x00, // PCM frame sync duty cycle = 16 clk 136 0x01, // PCM frame edge = rising edge 137 0x00, // PCM frame polarity = active high 138 0x00, // Reserved 139 0x10, 0x00, // PCM channel 1 out size = 16 140 0x01, 0x00, // PCM channel 1 out offset = 1 141 0x01, // PCM channel 1 out edge = rising 142 0x10, 0x00, // PCM channel 1 in size = 16 143 0x01, 0x00, // PCM channel 1 in offset = 1 144 0x00, // PCM channel 1 in edge = falling 145 0x00, // Reserved 146 0x10, 0x00, // PCM channel 2 out size = 16 147 0x11, 0x00, // PCM channel 2 out offset = 17 148 0x01, // PCM channel 2 out edge = rising 149 0x10, 0x00, // PCM channel 2 in size = 16 150 0x11, 0x00, // PCM channel 2 in offset = 17 151 0x00, // PCM channel 2 in edge = falling 152 0x00, // Reserved 153 }; 154 #endif 155 156 static void chipset_init(const void * config){ 157 init_script_offset = 0; 158 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 159 // On MSP430, custom init script is not supported 160 init_script_size = cc256x_init_script_size; 161 #else 162 if (custom_init_script){ 163 log_info("cc256x: using custom init script"); 164 init_script = custom_init_script; 165 init_script_size = custom_init_script_size; 166 } else { 167 log_info("cc256x: using default init script"); 168 init_script = cc256x_init_script; 169 init_script_size = cc256x_init_script_size; 170 } 171 #endif 172 #ifdef ENABLE_SCO_OVER_HCI 173 init_send_route_sco_over_hci = 1; 174 #endif 175 #ifdef ENABLE_SCO_OVER_PCM 176 init_send_sco_i2s_config_cvsd = 1; 177 #endif 178 } 179 180 static void chipset_set_baudrate_command(uint32_t baudrate, uint8_t *hci_cmd_buffer){ 181 hci_cmd_buffer[0] = 0x36; 182 hci_cmd_buffer[1] = 0xFF; 183 hci_cmd_buffer[2] = 0x04; 184 hci_cmd_buffer[3] = baudrate & 0xff; 185 hci_cmd_buffer[4] = (baudrate >> 8) & 0xff; 186 hci_cmd_buffer[5] = (baudrate >> 16) & 0xff; 187 hci_cmd_buffer[6] = 0; 188 } 189 190 static void chipset_set_bd_addr_command(bd_addr_t addr, uint8_t *hci_cmd_buffer){ 191 hci_cmd_buffer[0] = 0x06; 192 hci_cmd_buffer[1] = 0xFC; 193 hci_cmd_buffer[2] = 0x06; 194 reverse_bd_addr(addr, &hci_cmd_buffer[3]); 195 } 196 197 // Output Power control from: http://e2e.ti.com/support/low_power_rf/f/660/p/134853/484767.aspx 198 #define NUM_POWER_LEVELS 16 199 #define DB_MIN_LEVEL -35 200 #define DB_PER_LEVEL 5 201 #define DB_DYNAMIC_RANGE 30 202 203 static int get_max_power_for_modulation_type(int type){ 204 // a) limit max output power 205 int power_db; 206 switch (type){ 207 case 0: // GFSK 208 power_db = 12; 209 break; 210 default: // EDRx 211 power_db = 10; 212 break; 213 } 214 if (power_db > init_power_in_dB) { 215 power_db = init_power_in_dB; 216 } 217 return power_db; 218 } 219 220 static int get_highest_level_for_given_power(int power_db, int recommended_db){ 221 int i = NUM_POWER_LEVELS-1; 222 while (i) { 223 if (power_db <= recommended_db) { 224 return i; 225 } 226 power_db -= DB_PER_LEVEL; 227 i--; 228 } 229 return 0; 230 } 231 232 static void update_set_power_vector(uint8_t *hci_cmd_buffer){ 233 uint8_t modulation_type = hci_cmd_buffer[3]; 234 btstack_assert(modulation_type <= 2); 235 236 // explicit power vector provided by user 237 if (init_power_vectors[modulation_type] != NULL){ 238 (void)memcpy(&hci_cmd_buffer[4], init_power_vectors[modulation_type], 16); 239 return; 240 } 241 242 unsigned int i; 243 int power_db = get_max_power_for_modulation_type(modulation_type); 244 int dynamic_range = 0; 245 246 // f) don't touch level 0 247 for ( i = (NUM_POWER_LEVELS-1) ; i >= 1 ; i--){ 248 249 #ifdef ENABLE_BLE 250 // level 1 is BLE transmit power for GFSK 251 if (i == 1 && modulation_type == 0) { 252 hci_cmd_buffer[4+1] = 2 * get_max_power_for_modulation_type(modulation_type); 253 // as level 0 isn't set, we're done 254 continue; 255 } 256 #endif 257 hci_cmd_buffer[4+i] = 2 * power_db; 258 259 if (dynamic_range + DB_PER_LEVEL > DB_DYNAMIC_RANGE) continue; // e) 260 261 power_db -= DB_PER_LEVEL; // d) 262 dynamic_range += DB_PER_LEVEL; 263 264 if (power_db > DB_MIN_LEVEL) continue; 265 266 power_db = DB_MIN_LEVEL; // b) 267 } 268 } 269 270 // max permitted power for class 2 devices: 4 dBm 271 static void update_set_class2_single_power(uint8_t * hci_cmd_buffer){ 272 const int max_power_class_2 = 4; 273 int i = 0; 274 for (i=0;i<3;i++){ 275 hci_cmd_buffer[3+i] = get_highest_level_for_given_power(get_max_power_for_modulation_type(i), max_power_class_2); 276 } 277 } 278 279 // eHCILL activate from http://e2e.ti.com/support/low_power_rf/f/660/p/134855/484776.aspx 280 static void update_sleep_mode_configurations(uint8_t * hci_cmd_buffer){ 281 #ifdef ENABLE_EHCILL 282 hci_cmd_buffer[4] = 1; 283 #else 284 hci_cmd_buffer[4] = 0; 285 #endif 286 } 287 288 static void update_init_script_command(uint8_t *hci_cmd_buffer){ 289 290 uint16_t opcode = hci_cmd_buffer[0] | (hci_cmd_buffer[1] << 8); 291 292 switch (opcode){ 293 case 0xFD87: 294 update_set_class2_single_power(hci_cmd_buffer); 295 break; 296 case 0xFD82: 297 update_set_power_vector(hci_cmd_buffer); 298 break; 299 case 0xFD0C: 300 update_sleep_mode_configurations(hci_cmd_buffer); 301 break; 302 default: 303 break; 304 } 305 } 306 307 static btstack_chipset_result_t chipset_next_command(uint8_t * hci_cmd_buffer){ 308 if (init_script_offset >= init_script_size) { 309 310 #ifdef ENABLE_SCO_OVER_HCI 311 // append send route SCO over HCI if requested 312 if (init_send_route_sco_over_hci){ 313 init_send_route_sco_over_hci = 0; 314 memcpy(hci_cmd_buffer, hci_route_sco_over_hci, sizeof(hci_route_sco_over_hci)); 315 return BTSTACK_CHIPSET_VALID_COMMAND; 316 } 317 #endif 318 #ifdef ENABLE_SCO_OVER_PCM 319 // append sco i2s cvsd config 320 if (init_send_sco_i2s_config_cvsd){ 321 init_send_sco_i2s_config_cvsd = 0; 322 memcpy(hci_cmd_buffer, hci_write_codec_config_cvsd, sizeof(hci_write_codec_config_cvsd)); 323 return BTSTACK_CHIPSET_VALID_COMMAND; 324 } 325 #endif 326 return BTSTACK_CHIPSET_DONE; 327 } 328 329 // extracted init script has 0x01 cmd packet type, but BTstack expects them without 330 init_script_offset++; 331 332 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 333 334 // workaround: use FlashReadBlock with 32-bit integer and assume init script starts at 0x10000 335 uint32_t init_script_addr = 0x10000; 336 FlashReadBlock(&hci_cmd_buffer[0], init_script_addr + init_script_offset, 3); // cmd header 337 init_script_offset += 3; 338 int payload_len = hci_cmd_buffer[2]; 339 FlashReadBlock(&hci_cmd_buffer[3], init_script_addr + init_script_offset, payload_len); // cmd payload 340 341 #elif defined (__AVR__) 342 343 // workaround: use memcpy_P to access init script in lower 64 kB of flash 344 memcpy_P(&hci_cmd_buffer[0], &init_script[init_script_offset], 3); 345 init_script_offset += 3; 346 int payload_len = hci_cmd_buffer[2]; 347 memcpy_P(&hci_cmd_buffer[3], &init_script[init_script_offset], payload_len); 348 349 #else 350 351 // use memcpy with pointer 352 uint8_t * init_script_ptr = (uint8_t*) &init_script[0]; 353 memcpy(&hci_cmd_buffer[0], init_script_ptr + init_script_offset, 3); // cmd header 354 init_script_offset += 3; 355 int payload_len = hci_cmd_buffer[2]; 356 memcpy(&hci_cmd_buffer[3], init_script_ptr + init_script_offset, payload_len); // cmd payload 357 358 #endif 359 360 init_script_offset += payload_len; 361 362 // control power commands and ehcill 363 update_init_script_command(hci_cmd_buffer); 364 365 return BTSTACK_CHIPSET_VALID_COMMAND; 366 } 367 368 369 // MARK: public API 370 void btstack_chipset_cc256x_set_power(int16_t power_in_dB){ 371 init_power_in_dB = power_in_dB; 372 } 373 374 void btstack_chipset_cc256x_set_power_vector(uint8_t modulation_type, const uint8_t * power_vector){ 375 btstack_assert(modulation_type <= 2); 376 init_power_vectors[modulation_type] = power_vector; 377 } 378 379 void btstack_chipset_cc256x_set_init_script(uint8_t * data, uint32_t size){ 380 custom_init_script = data; 381 custom_init_script_size = size; 382 } 383 384 static const btstack_chipset_t btstack_chipset_cc256x = { 385 "CC256x", 386 chipset_init, 387 chipset_next_command, 388 chipset_set_baudrate_command, 389 chipset_set_bd_addr_command, 390 }; 391 392 const btstack_chipset_t * btstack_chipset_cc256x_instance(void){ 393 return &btstack_chipset_cc256x; 394 } 395 396