1 /* 2 * Copyright (C) 2009-2012 by Matthias Ringwald 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY MATTHIAS RINGWALD AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS 24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at [email protected] 34 * 35 */ 36 37 #define __BTSTACK_FILE__ "btstack_chipset_cc256x.c" 38 39 /* 40 * btstack_chipset_cc256x.c 41 * 42 * Adapter to use cc256x-based chipsets with BTstack 43 * 44 * Handles init script (a.k.a. Service Patch) 45 * Allows for non-standard UART baud rate 46 * Allows to configure transmit power 47 * Allows to activate eHCILL deep sleep mode 48 * 49 * Issues with mspgcc LTS: 50 * - 20 bit support is not there yet -> .text cannot get bigger than 48 kb 51 * - arrays cannot have more than 32k entries 52 * 53 * workarounds: 54 * - store init script in .fartext and use assembly code to read from there 55 * - split into two arrays 56 * 57 * Issues with AVR 58 * - Harvard architecture doesn't allow to store init script directly -> use avr-libc helpers 59 * 60 * Documentation for TI VS CC256x commands: http://processors.wiki.ti.com/index.php/CC256x_VS_HCI_Commands 61 * 62 */ 63 64 #include "btstack_config.h" 65 #include "btstack_chipset_cc256x.h" 66 67 #include <stddef.h> /* NULL */ 68 #include <stdio.h> 69 #include <string.h> /* memcpy */ 70 71 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 72 #include "hal_compat.h" 73 #endif 74 75 #ifdef __AVR__ 76 #include <avr/pgmspace.h> 77 #endif 78 79 #include "btstack_control.h" 80 81 82 // actual init script provided by seperate .c file 83 extern const uint8_t cc256x_init_script[]; 84 extern const uint32_t cc256x_init_script_size; 85 86 // init script 87 static uint32_t init_script_offset = 0; 88 static int16_t init_power_in_dB = 13; // 13 dBm 89 90 // support for SCO over HCI 91 #ifdef ENABLE_SCO_OVER_HCI 92 static int init_send_route_sco_over_hci = 0; 93 static const uint8_t hci_route_sco_over_hci[] = { 94 #if 1 95 // Follow recommendation from https://e2e.ti.com/support/wireless_connectivity/bluetooth_cc256x/f/660/t/397004 96 // route SCO over HCI (connection type=1, tx buffer size = 120, tx buffer max latency= 720, accept packets with CRC Error 97 0x10, 0xfe, 0x05, 0x01, 0x78, 0xd0, 0x02, 0x01, 98 #else 99 // Configure SCO via I2S interface - 256 kbps 100 // Send_HCI_VS_Write_CODEC_Config 0xFD06, 101 0x06, 0xfd, 102 // len 103 34, 104 //3072, - clock rate 3072000 hz 105 0x00, 0x01, 106 // 0x00 - clock direction: output = master 107 0x00, 108 // 8000, framesync frequency in hz 109 0x40, 0x1f, 0x00, 0x00, 110 // 0x0001, framesync duty cycle 111 0x01, 0x00, 112 // 1, framesync edge 113 1, 114 // 0x00, framesync polarity 115 0x00, 116 // 0x00, RESERVED 117 0x00, 118 // 16, channel 1 out size 119 8, 0, 120 // 0x0001, channel 1 out offset 121 0x01, 0x00, 122 // 1, channel 1 out edge 123 1, 124 // 16, channel 1 in size 125 8, 0, 126 // 0x0001, channel 1 in offset 127 0x01, 0x00, 128 // 0, channel 1 in edge 129 0, 130 // 0x00, RESERVED 131 0x00, 132 // 16, channel 2 out size 133 8, 0, 134 // 17, channel 2 out offset 135 9, 0, 136 // 0x01, channel 2 out edge 137 0x01, 138 // 16, channel 2 in size 139 8, 0, 140 // 17, channel 2 in offset 141 9, 0, 142 // 0x00, channel 2 in edge 143 0x00, 144 // 0x0001, RESERVED 145 0x00 146 #endif 147 }; 148 #endif 149 150 static void chipset_init(const void * config){ 151 init_script_offset = 0; 152 #ifdef ENABLE_SCO_OVER_HCI 153 init_send_route_sco_over_hci = 1; 154 #endif 155 } 156 157 static void chipset_set_baudrate_command(uint32_t baudrate, uint8_t *hci_cmd_buffer){ 158 hci_cmd_buffer[0] = 0x36; 159 hci_cmd_buffer[1] = 0xFF; 160 hci_cmd_buffer[2] = 0x04; 161 hci_cmd_buffer[3] = baudrate & 0xff; 162 hci_cmd_buffer[4] = (baudrate >> 8) & 0xff; 163 hci_cmd_buffer[5] = (baudrate >> 16) & 0xff; 164 hci_cmd_buffer[6] = 0; 165 } 166 167 static void chipset_set_bd_addr_command(bd_addr_t addr, uint8_t *hci_cmd_buffer){ 168 hci_cmd_buffer[0] = 0x06; 169 hci_cmd_buffer[1] = 0xFC; 170 hci_cmd_buffer[2] = 0x06; 171 reverse_bd_addr(addr, &hci_cmd_buffer[3]); 172 } 173 174 // Output Power control from: http://e2e.ti.com/support/low_power_rf/f/660/p/134853/484767.aspx 175 #define NUM_POWER_LEVELS 16 176 #define DB_MIN_LEVEL -35 177 #define DB_PER_LEVEL 5 178 #define DB_DYNAMIC_RANGE 30 179 180 static int get_max_power_for_modulation_type(int type){ 181 // a) limit max output power 182 int power_db; 183 switch (type){ 184 case 0: // GFSK 185 power_db = 12; 186 break; 187 default: // EDRx 188 power_db = 10; 189 break; 190 } 191 if (power_db > init_power_in_dB) { 192 power_db = init_power_in_dB; 193 } 194 return power_db; 195 } 196 197 static int get_highest_level_for_given_power(int power_db, int recommended_db){ 198 int i = NUM_POWER_LEVELS-1; 199 while (i) { 200 if (power_db <= recommended_db) { 201 return i; 202 } 203 power_db -= DB_PER_LEVEL; 204 i--; 205 } 206 return 0; 207 } 208 209 static void update_set_power_vector(uint8_t *hci_cmd_buffer){ 210 int i; 211 int modulation_type = hci_cmd_buffer[3]; 212 int power_db = get_max_power_for_modulation_type(modulation_type); 213 int dynamic_range = 0; 214 215 // f) don't touch level 0 216 for ( i = (NUM_POWER_LEVELS-1) ; i >= 1 ; i--){ 217 218 #ifdef ENABLE_BLE 219 // level 1 is BLE transmit power for GFSK 220 if (i == 1 && modulation_type == 0) { 221 hci_cmd_buffer[4+1] = 2 * get_max_power_for_modulation_type(modulation_type); 222 // as level 0 isn't set, we're done 223 continue; 224 } 225 #endif 226 hci_cmd_buffer[4+i] = 2 * power_db; 227 228 if (dynamic_range + DB_PER_LEVEL > DB_DYNAMIC_RANGE) continue; // e) 229 230 power_db -= DB_PER_LEVEL; // d) 231 dynamic_range += DB_PER_LEVEL; 232 233 if (power_db > DB_MIN_LEVEL) continue; 234 235 power_db = DB_MIN_LEVEL; // b) 236 } 237 } 238 239 // max permitted power for class 2 devices: 4 dBm 240 static void update_set_class2_single_power(uint8_t * hci_cmd_buffer){ 241 const int max_power_class_2 = 4; 242 int i = 0; 243 for (i=0;i<3;i++){ 244 hci_cmd_buffer[3+i] = get_highest_level_for_given_power(get_max_power_for_modulation_type(i), max_power_class_2); 245 } 246 } 247 248 // eHCILL activate from http://e2e.ti.com/support/low_power_rf/f/660/p/134855/484776.aspx 249 static void update_sleep_mode_configurations(uint8_t * hci_cmd_buffer){ 250 #ifdef ENABLE_EHCILL 251 hci_cmd_buffer[4] = 1; 252 #else 253 hci_cmd_buffer[4] = 0; 254 #endif 255 } 256 257 static void update_init_script_command(uint8_t *hci_cmd_buffer){ 258 259 uint16_t opcode = hci_cmd_buffer[0] | (hci_cmd_buffer[1] << 8); 260 261 switch (opcode){ 262 case 0xFD87: 263 update_set_class2_single_power(hci_cmd_buffer); 264 break; 265 case 0xFD82: 266 update_set_power_vector(hci_cmd_buffer); 267 break; 268 case 0xFD0C: 269 update_sleep_mode_configurations(hci_cmd_buffer); 270 break; 271 default: 272 break; 273 } 274 } 275 276 static btstack_chipset_result_t chipset_next_command(uint8_t * hci_cmd_buffer){ 277 if (init_script_offset >= cc256x_init_script_size) { 278 279 #ifdef ENABLE_SCO_OVER_HCI 280 // append send route SCO over HCI if requested 281 if (init_send_route_sco_over_hci){ 282 init_send_route_sco_over_hci = 0; 283 memcpy(hci_cmd_buffer, hci_route_sco_over_hci, sizeof(hci_route_sco_over_hci)); 284 return BTSTACK_CHIPSET_VALID_COMMAND; 285 } 286 #endif 287 288 return BTSTACK_CHIPSET_DONE; 289 } 290 291 // extracted init script has 0x01 cmd packet type, but BTstack expects them without 292 init_script_offset++; 293 294 #if defined(__GNUC__) && defined(__MSP430X__) && (__MSP430X__ > 0) 295 296 // workaround: use FlashReadBlock with 32-bit integer and assume init script starts at 0x10000 297 uint32_t init_script_addr = 0x10000; 298 FlashReadBlock(&hci_cmd_buffer[0], init_script_addr + init_script_offset, 3); // cmd header 299 init_script_offset += 3; 300 int payload_len = hci_cmd_buffer[2]; 301 FlashReadBlock(&hci_cmd_buffer[3], init_script_addr + init_script_offset, payload_len); // cmd payload 302 303 #elif defined (__AVR__) 304 305 // workaround: use memcpy_P to access init script in lower 64 kB of flash 306 memcpy_P(&hci_cmd_buffer[0], &cc256x_init_script[init_script_offset], 3); 307 init_script_offset += 3; 308 int payload_len = hci_cmd_buffer[2]; 309 memcpy_P(&hci_cmd_buffer[3], &cc256x_init_script[init_script_offset], payload_len); 310 311 #else 312 313 // use memcpy with pointer 314 uint8_t * init_script_ptr = (uint8_t*) &cc256x_init_script[0]; 315 memcpy(&hci_cmd_buffer[0], init_script_ptr + init_script_offset, 3); // cmd header 316 init_script_offset += 3; 317 int payload_len = hci_cmd_buffer[2]; 318 memcpy(&hci_cmd_buffer[3], init_script_ptr + init_script_offset, payload_len); // cmd payload 319 320 #endif 321 322 init_script_offset += payload_len; 323 324 // control power commands and ehcill 325 update_init_script_command(hci_cmd_buffer); 326 327 return BTSTACK_CHIPSET_VALID_COMMAND; 328 } 329 330 331 // MARK: public API 332 void btstack_chipset_cc256x_set_power(int16_t power_in_dB){ 333 init_power_in_dB = power_in_dB; 334 } 335 336 static const btstack_chipset_t btstack_chipset_cc256x = { 337 "CC256x", 338 chipset_init, 339 chipset_next_command, 340 chipset_set_baudrate_command, 341 chipset_set_bd_addr_command, 342 }; 343 344 const btstack_chipset_t * btstack_chipset_cc256x_instance(void){ 345 return &btstack_chipset_cc256x; 346 } 347 348