1// Copyright 2022 The Go Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style 3// license that can be found in the LICENSE file. 4 5package loong64 6 7import ( 8 "cmd/internal/obj" 9) 10 11//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64 12 13const ( 14 NSNAME = 8 15 NSYM = 50 16 NREG = 32 // number of general registers 17 NFREG = 32 // number of floating point registers 18) 19 20const ( 21 REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32 22 REG_R1 23 REG_R2 24 REG_R3 25 REG_R4 26 REG_R5 27 REG_R6 28 REG_R7 29 REG_R8 30 REG_R9 31 REG_R10 32 REG_R11 33 REG_R12 34 REG_R13 35 REG_R14 36 REG_R15 37 REG_R16 38 REG_R17 39 REG_R18 40 REG_R19 41 REG_R20 42 REG_R21 43 REG_R22 44 REG_R23 45 REG_R24 46 REG_R25 47 REG_R26 48 REG_R27 49 REG_R28 50 REG_R29 51 REG_R30 52 REG_R31 53 54 REG_F0 // must be a multiple of 32 55 REG_F1 56 REG_F2 57 REG_F3 58 REG_F4 59 REG_F5 60 REG_F6 61 REG_F7 62 REG_F8 63 REG_F9 64 REG_F10 65 REG_F11 66 REG_F12 67 REG_F13 68 REG_F14 69 REG_F15 70 REG_F16 71 REG_F17 72 REG_F18 73 REG_F19 74 REG_F20 75 REG_F21 76 REG_F22 77 REG_F23 78 REG_F24 79 REG_F25 80 REG_F26 81 REG_F27 82 REG_F28 83 REG_F29 84 REG_F30 85 REG_F31 86 87 REG_FCSR0 // must be a multiple of 32 88 REG_FCSR1 89 REG_FCSR2 90 REG_FCSR3 // only four registers are needed 91 REG_FCSR4 92 REG_FCSR5 93 REG_FCSR6 94 REG_FCSR7 95 REG_FCSR8 96 REG_FCSR9 97 REG_FCSR10 98 REG_FCSR11 99 REG_FCSR12 100 REG_FCSR13 101 REG_FCSR14 102 REG_FCSR15 103 REG_FCSR16 104 REG_FCSR17 105 REG_FCSR18 106 REG_FCSR19 107 REG_FCSR20 108 REG_FCSR21 109 REG_FCSR22 110 REG_FCSR23 111 REG_FCSR24 112 REG_FCSR25 113 REG_FCSR26 114 REG_FCSR27 115 REG_FCSR28 116 REG_FCSR29 117 REG_FCSR30 118 REG_FCSR31 119 120 REG_FCC0 // must be a multiple of 32 121 REG_FCC1 122 REG_FCC2 123 REG_FCC3 124 REG_FCC4 125 REG_FCC5 126 REG_FCC6 127 REG_FCC7 // only eight registers are needed 128 REG_FCC8 129 REG_FCC9 130 REG_FCC10 131 REG_FCC11 132 REG_FCC12 133 REG_FCC13 134 REG_FCC14 135 REG_FCC15 136 REG_FCC16 137 REG_FCC17 138 REG_FCC18 139 REG_FCC19 140 REG_FCC20 141 REG_FCC21 142 REG_FCC22 143 REG_FCC23 144 REG_FCC24 145 REG_FCC25 146 REG_FCC26 147 REG_FCC27 148 REG_FCC28 149 REG_FCC29 150 REG_FCC30 151 REG_FCC31 152 153 REG_LAST = REG_FCC31 // the last defined register 154 155 REG_SPECIAL = REG_FCSR0 156 157 REGZERO = REG_R0 // set to zero 158 REGLINK = REG_R1 159 REGSP = REG_R3 160 REGRET = REG_R20 // not use 161 REGARG = -1 // -1 disables passing the first argument in register 162 REGRT1 = REG_R20 // reserved for runtime, duffzero and duffcopy 163 REGRT2 = REG_R21 // reserved for runtime, duffcopy 164 REGCTXT = REG_R29 // context for closures 165 REGG = REG_R22 // G in loong64 166 REGTMP = REG_R30 // used by the assembler 167 FREGRET = REG_F0 // not use 168) 169 170var LOONG64DWARFRegisters = map[int16]int16{} 171 172func init() { 173 // f assigns dwarfregisters[from:to] = (base):(to-from+base) 174 f := func(from, to, base int16) { 175 for r := int16(from); r <= to; r++ { 176 LOONG64DWARFRegisters[r] = (r - from) + base 177 } 178 } 179 f(REG_R0, REG_R31, 0) 180 f(REG_F0, REG_F31, 32) 181 182} 183 184const ( 185 BIG = 2046 186) 187 188const ( 189 // mark flags 190 LABEL = 1 << 0 191 LEAF = 1 << 1 192 SYNC = 1 << 2 193 BRANCH = 1 << 3 194) 195 196const ( 197 C_NONE = iota 198 C_REG 199 C_FREG 200 C_FCSRREG 201 C_FCCREG 202 C_ZCON 203 C_SCON // 12 bit signed 204 C_UCON // 32 bit signed, low 12 bits 0 205 C_ADD0CON 206 C_AND0CON 207 C_ADDCON // -0x800 <= v < 0 208 C_ANDCON // 0 < v <= 0xFFF 209 C_LCON // other 32 210 C_DCON // other 64 (could subdivide further) 211 C_SACON // $n(REG) where n <= int12 212 C_SECON 213 C_LACON // $n(REG) where int12 < n <= int32 214 C_LECON 215 C_DACON // $n(REG) where int32 < n 216 C_STCON // $tlsvar 217 C_SBRA 218 C_LBRA 219 C_SAUTO 220 C_LAUTO 221 C_SEXT 222 C_LEXT 223 C_ZOREG 224 C_SOREG 225 C_LOREG 226 C_GOK 227 C_ADDR 228 C_TLS_LE 229 C_TLS_IE 230 C_GOTADDR 231 C_TEXTSIZE 232 233 C_NCLASS // must be the last 234) 235 236const ( 237 AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota 238 AABSF 239 AADD 240 AADDD 241 AADDF 242 AADDU 243 244 AADDW 245 AAND 246 ABEQ 247 ABGEZ 248 ABLEZ 249 ABGTZ 250 ABLTZ 251 ABFPF 252 ABFPT 253 254 ABNE 255 ABREAK 256 ACLO 257 ACLZ 258 259 ACMPEQD 260 ACMPEQF 261 262 ACMPGED // ACMPGED -> fcmp.sle.d 263 ACMPGEF // ACMPGEF -> fcmp.sle.s 264 ACMPGTD // ACMPGTD -> fcmp.slt.d 265 ACMPGTF // ACMPGTF -> fcmp.slt.s 266 267 ALU12IW 268 ALU32ID 269 ALU52ID 270 APCALAU12I 271 APCADDU12I 272 AJIRL 273 ABGE 274 ABLT 275 ABLTU 276 ABGEU 277 278 ADIV 279 ADIVD 280 ADIVF 281 ADIVU 282 ADIVW 283 284 ALL 285 ALLV 286 287 ALUI 288 289 AMOVB 290 AMOVBU 291 292 AMOVD 293 AMOVDF 294 AMOVDW 295 AMOVF 296 AMOVFD 297 AMOVFW 298 299 AMOVH 300 AMOVHU 301 AMOVW 302 303 AMOVWD 304 AMOVWF 305 306 AMOVWL 307 AMOVWR 308 309 AMUL 310 AMULD 311 AMULF 312 AMULU 313 AMULH 314 AMULHU 315 AMULW 316 ANEGD 317 ANEGF 318 319 ANEGW 320 ANEGV 321 322 ANOOP // hardware nop 323 ANOR 324 AOR 325 AREM 326 AREMU 327 328 ARFE 329 330 ASC 331 ASCV 332 333 ASGT 334 ASGTU 335 336 ASLL 337 ASQRTD 338 ASQRTF 339 ASRA 340 ASRL 341 AROTR 342 ASUB 343 ASUBD 344 ASUBF 345 346 ASUBU 347 ASUBW 348 ADBAR 349 ASYSCALL 350 351 ATEQ 352 ATNE 353 354 AWORD 355 356 AXOR 357 358 AMASKEQZ 359 AMASKNEZ 360 361 // 64-bit 362 AMOVV 363 AMOVVL 364 AMOVVR 365 366 ASLLV 367 ASRAV 368 ASRLV 369 AROTRV 370 ADIVV 371 ADIVVU 372 373 AREMV 374 AREMVU 375 376 AMULV 377 AMULVU 378 AMULHV 379 AMULHVU 380 AADDV 381 AADDVU 382 ASUBV 383 ASUBVU 384 385 // 64-bit FP 386 ATRUNCFV 387 ATRUNCDV 388 ATRUNCFW 389 ATRUNCDW 390 391 AMOVWU 392 AMOVFV 393 AMOVDV 394 AMOVVF 395 AMOVVD 396 397 // 2.2.7. Atomic Memory Access Instructions 398 AAMSWAPB 399 AAMSWAPH 400 AAMSWAPW 401 AAMSWAPV 402 AAMCASB 403 AAMCASH 404 AAMCASW 405 AAMCASV 406 AAMADDW 407 AAMADDV 408 AAMANDW 409 AAMANDV 410 AAMORW 411 AAMORV 412 AAMXORW 413 AAMXORV 414 AAMMAXW 415 AAMMAXV 416 AAMMINW 417 AAMMINV 418 AAMMAXWU 419 AAMMAXVU 420 AAMMINWU 421 AAMMINVU 422 AAMSWAPDBB 423 AAMSWAPDBH 424 AAMSWAPDBW 425 AAMSWAPDBV 426 AAMCASDBB 427 AAMCASDBH 428 AAMCASDBW 429 AAMCASDBV 430 AAMADDDBW 431 AAMADDDBV 432 AAMANDDBW 433 AAMANDDBV 434 AAMORDBW 435 AAMORDBV 436 AAMXORDBW 437 AAMXORDBV 438 AAMMAXDBW 439 AAMMAXDBV 440 AAMMINDBW 441 AAMMINDBV 442 AAMMAXDBWU 443 AAMMAXDBVU 444 AAMMINDBWU 445 AAMMINDBVU 446 447 // 2.2.10. Other Miscellaneous Instructions 448 ARDTIMELW 449 ARDTIMEHW 450 ARDTIMED 451 452 ALAST 453 454 // aliases 455 AJMP = obj.AJMP 456 AJAL = obj.ACALL 457 ARET = obj.ARET 458) 459 460func init() { 461 // The asm encoder generally assumes that the lowest 5 bits of the 462 // REG_XX constants match the machine instruction encoding, i.e. 463 // the lowest 5 bits is the register number. 464 // Check this here. 465 if REG_R0%32 != 0 { 466 panic("REG_R0 is not a multiple of 32") 467 } 468 if REG_F0%32 != 0 { 469 panic("REG_F0 is not a multiple of 32") 470 } 471 if REG_FCSR0%32 != 0 { 472 panic("REG_FCSR0 is not a multiple of 32") 473 } 474 if REG_FCC0%32 != 0 { 475 panic("REG_FCC0 is not a multiple of 32") 476 } 477} 478