1// Copyright 2015 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// This file encapsulates some of the odd characteristics of the
6// 64-bit PowerPC (PPC64) instruction set, to minimize its interaction
7// with the core of the assembler.
8
9package arch
10
11import (
12	"cmd/internal/obj"
13	"cmd/internal/obj/ppc64"
14)
15
16func jumpPPC64(word string) bool {
17	switch word {
18	case "BC", "BCL", "BEQ", "BGE", "BGT", "BL", "BLE", "BLT", "BNE", "BR", "BVC", "BVS", "BDNZ", "BDZ", "CALL", "JMP":
19		return true
20	}
21	return false
22}
23
24// IsPPC64CMP reports whether the op (as defined by an ppc64.A* constant) is
25// one of the CMP instructions that require special handling.
26func IsPPC64CMP(op obj.As) bool {
27	switch op {
28	case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPO, ppc64.AFCMPU:
29		return true
30	}
31	return false
32}
33
34// IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is
35// one of the NEG-like instructions that require special handling.
36func IsPPC64NEG(op obj.As) bool {
37	switch op {
38	case ppc64.AADDMECC, ppc64.AADDMEVCC, ppc64.AADDMEV, ppc64.AADDME,
39		ppc64.AADDZECC, ppc64.AADDZEVCC, ppc64.AADDZEV, ppc64.AADDZE,
40		ppc64.ACNTLZDCC, ppc64.ACNTLZD, ppc64.ACNTLZWCC, ppc64.ACNTLZW,
41		ppc64.AEXTSBCC, ppc64.AEXTSB, ppc64.AEXTSHCC, ppc64.AEXTSH,
42		ppc64.AEXTSWCC, ppc64.AEXTSW, ppc64.ANEGCC, ppc64.ANEGVCC,
43		ppc64.ANEGV, ppc64.ANEG, ppc64.ASLBMFEE, ppc64.ASLBMFEV,
44		ppc64.ASLBMTE, ppc64.ASUBMECC, ppc64.ASUBMEVCC, ppc64.ASUBMEV,
45		ppc64.ASUBME, ppc64.ASUBZECC, ppc64.ASUBZEVCC, ppc64.ASUBZEV,
46		ppc64.ASUBZE:
47		return true
48	}
49	return false
50}
51
52func ppc64RegisterNumber(name string, n int16) (int16, bool) {
53	switch name {
54	case "CR":
55		if 0 <= n && n <= 7 {
56			return ppc64.REG_CR0 + n, true
57		}
58	case "A":
59		if 0 <= n && n <= 8 {
60			return ppc64.REG_A0 + n, true
61		}
62	case "VS":
63		if 0 <= n && n <= 63 {
64			return ppc64.REG_VS0 + n, true
65		}
66	case "V":
67		if 0 <= n && n <= 31 {
68			return ppc64.REG_V0 + n, true
69		}
70	case "F":
71		if 0 <= n && n <= 31 {
72			return ppc64.REG_F0 + n, true
73		}
74	case "R":
75		if 0 <= n && n <= 31 {
76			return ppc64.REG_R0 + n, true
77		}
78	case "SPR":
79		if 0 <= n && n <= 1024 {
80			return ppc64.REG_SPR0 + n, true
81		}
82	}
83	return 0, false
84}
85