1//===- IntrinsicsLoongArch.td - Defines LoongArch intrinsics *- tablegen -*===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the LoongArch-specific intrinsics. 10// 11//===----------------------------------------------------------------------===// 12 13let TargetPrefix = "loongarch" in { 14 15//===----------------------------------------------------------------------===// 16// Atomics 17 18// T @llvm.<name>.T.<p>(any*, T, T, T imm); 19class MaskedAtomicRMW<LLVMType itype> 20 : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype], 21 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>; 22 23// We define 32-bit and 64-bit variants of the above, where T stands for i32 24// or i64 respectively: 25multiclass MaskedAtomicRMWIntrinsics { 26 // i32 @llvm.<name>.i32.<p>(any*, i32, i32, i32 imm); 27 def _i32 : MaskedAtomicRMW<llvm_i32_ty>; 28 // i64 @llvm.<name>.i32.<p>(any*, i64, i64, i64 imm); 29 def _i64 : MaskedAtomicRMW<llvm_i64_ty>; 30} 31 32multiclass MaskedAtomicRMWFiveOpIntrinsics { 33 // TODO: Support cmpxchg on LA32. 34 // i64 @llvm.<name>.i64.<p>(any*, i64, i64, i64, i64 imm); 35 def _i64 : MaskedAtomicRMWFiveArg<llvm_i64_ty>; 36} 37 38defm int_loongarch_masked_atomicrmw_xchg : MaskedAtomicRMWIntrinsics; 39defm int_loongarch_masked_atomicrmw_add : MaskedAtomicRMWIntrinsics; 40defm int_loongarch_masked_atomicrmw_sub : MaskedAtomicRMWIntrinsics; 41defm int_loongarch_masked_atomicrmw_nand : MaskedAtomicRMWIntrinsics; 42defm int_loongarch_masked_atomicrmw_umax : MaskedAtomicRMWIntrinsics; 43defm int_loongarch_masked_atomicrmw_umin : MaskedAtomicRMWIntrinsics; 44defm int_loongarch_masked_atomicrmw_max : MaskedAtomicRMWFiveOpIntrinsics; 45defm int_loongarch_masked_atomicrmw_min : MaskedAtomicRMWFiveOpIntrinsics; 46 47// @llvm.loongarch.masked.cmpxchg.i64.<p>( 48// ptr addr, grlen cmpval, grlen newval, grlen mask, grlenimm ordering) 49defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics; 50 51//===----------------------------------------------------------------------===// 52// LoongArch BASE 53 54class BaseInt<list<LLVMType> ret_types, list<LLVMType> param_types, 55 list<IntrinsicProperty> intr_properties = []> 56 : Intrinsic<ret_types, param_types, intr_properties>, 57 ClangBuiltin<!subst("int_loongarch", "__builtin_loongarch", NAME)>; 58 59def int_loongarch_break : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 60def int_loongarch_cacop_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], 61 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 62def int_loongarch_cacop_w : BaseInt<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 63 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 64def int_loongarch_dbar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 65 66def int_loongarch_ibar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 67def int_loongarch_movfcsr2gr : BaseInt<[llvm_i32_ty], [llvm_i32_ty], 68 [ImmArg<ArgIndex<0>>]>; 69def int_loongarch_movgr2fcsr : BaseInt<[], [llvm_i32_ty, llvm_i32_ty], 70 [ImmArg<ArgIndex<0>>]>; 71def int_loongarch_syscall : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; 72 73def int_loongarch_crc_w_b_w : BaseInt<[llvm_i32_ty], 74 [llvm_i32_ty, llvm_i32_ty]>; 75def int_loongarch_crc_w_h_w : BaseInt<[llvm_i32_ty], 76 [llvm_i32_ty, llvm_i32_ty]>; 77def int_loongarch_crc_w_w_w : BaseInt<[llvm_i32_ty], 78 [llvm_i32_ty, llvm_i32_ty]>; 79def int_loongarch_crc_w_d_w : BaseInt<[llvm_i32_ty], 80 [llvm_i64_ty, llvm_i32_ty]>; 81 82def int_loongarch_crcc_w_b_w : BaseInt<[llvm_i32_ty], 83 [llvm_i32_ty, llvm_i32_ty]>; 84def int_loongarch_crcc_w_h_w : BaseInt<[llvm_i32_ty], 85 [llvm_i32_ty, llvm_i32_ty]>; 86def int_loongarch_crcc_w_w_w : BaseInt<[llvm_i32_ty], 87 [llvm_i32_ty, llvm_i32_ty]>; 88def int_loongarch_crcc_w_d_w : BaseInt<[llvm_i32_ty], 89 [llvm_i64_ty, llvm_i32_ty]>; 90 91def int_loongarch_csrrd_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty], 92 [ImmArg<ArgIndex<0>>]>; 93def int_loongarch_csrrd_d : BaseInt<[llvm_i64_ty], [llvm_i32_ty], 94 [ImmArg<ArgIndex<0>>]>; 95def int_loongarch_csrwr_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 96 [ImmArg<ArgIndex<1>>]>; 97def int_loongarch_csrwr_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty], 98 [ImmArg<ArgIndex<1>>]>; 99def int_loongarch_csrxchg_w : BaseInt<[llvm_i32_ty], 100 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 101 [ImmArg<ArgIndex<2>>]>; 102def int_loongarch_csrxchg_d : BaseInt<[llvm_i64_ty], 103 [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], 104 [ImmArg<ArgIndex<2>>]>; 105 106def int_loongarch_iocsrrd_b : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 107def int_loongarch_iocsrrd_h : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 108def int_loongarch_iocsrrd_w : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 109def int_loongarch_iocsrrd_d : BaseInt<[llvm_i64_ty], [llvm_i32_ty]>; 110 111def int_loongarch_iocsrwr_b : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>; 112def int_loongarch_iocsrwr_h : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>; 113def int_loongarch_iocsrwr_w : BaseInt<[], [llvm_i32_ty, llvm_i32_ty]>; 114def int_loongarch_iocsrwr_d : BaseInt<[], [llvm_i64_ty, llvm_i32_ty]>; 115 116def int_loongarch_cpucfg : BaseInt<[llvm_i32_ty], [llvm_i32_ty]>; 117 118def int_loongarch_asrtle_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty]>; 119def int_loongarch_asrtgt_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty]>; 120 121def int_loongarch_lddir_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], 122 [ImmArg<ArgIndex<1>>]>; 123def int_loongarch_ldpte_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty], 124 [ImmArg<ArgIndex<1>>]>; 125} // TargetPrefix = "loongarch" 126 127/// Vector intrinsic 128 129class VecInt<list<LLVMType> ret_types, list<LLVMType> param_types, 130 list<IntrinsicProperty> intr_properties = []> 131 : Intrinsic<ret_types, param_types, intr_properties>, 132 ClangBuiltin<!subst("int_loongarch", "__builtin", NAME)>; 133 134//===----------------------------------------------------------------------===// 135// LSX 136 137let TargetPrefix = "loongarch" in { 138 139foreach inst = ["vadd_b", "vsub_b", 140 "vsadd_b", "vsadd_bu", "vssub_b", "vssub_bu", 141 "vavg_b", "vavg_bu", "vavgr_b", "vavgr_bu", 142 "vabsd_b", "vabsd_bu", "vadda_b", 143 "vmax_b", "vmax_bu", "vmin_b", "vmin_bu", 144 "vmul_b", "vmuh_b", "vmuh_bu", 145 "vdiv_b", "vdiv_bu", "vmod_b", "vmod_bu", "vsigncov_b", 146 "vand_v", "vor_v", "vxor_v", "vnor_v", "vandn_v", "vorn_v", 147 "vsll_b", "vsrl_b", "vsra_b", "vrotr_b", "vsrlr_b", "vsrar_b", 148 "vbitclr_b", "vbitset_b", "vbitrev_b", 149 "vseq_b", "vsle_b", "vsle_bu", "vslt_b", "vslt_bu", 150 "vpackev_b", "vpackod_b", "vpickev_b", "vpickod_b", 151 "vilvl_b", "vilvh_b"] in 152 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], 153 [llvm_v16i8_ty, llvm_v16i8_ty], 154 [IntrNoMem]>; 155 156foreach inst = ["vadd_h", "vsub_h", 157 "vsadd_h", "vsadd_hu", "vssub_h", "vssub_hu", 158 "vavg_h", "vavg_hu", "vavgr_h", "vavgr_hu", 159 "vabsd_h", "vabsd_hu", "vadda_h", 160 "vmax_h", "vmax_hu", "vmin_h", "vmin_hu", 161 "vmul_h", "vmuh_h", "vmuh_hu", 162 "vdiv_h", "vdiv_hu", "vmod_h", "vmod_hu", "vsigncov_h", 163 "vsll_h", "vsrl_h", "vsra_h", "vrotr_h", "vsrlr_h", "vsrar_h", 164 "vbitclr_h", "vbitset_h", "vbitrev_h", 165 "vseq_h", "vsle_h", "vsle_hu", "vslt_h", "vslt_hu", 166 "vpackev_h", "vpackod_h", "vpickev_h", "vpickod_h", 167 "vilvl_h", "vilvh_h"] in 168 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 169 [llvm_v8i16_ty, llvm_v8i16_ty], 170 [IntrNoMem]>; 171 172foreach inst = ["vadd_w", "vsub_w", 173 "vsadd_w", "vsadd_wu", "vssub_w", "vssub_wu", 174 "vavg_w", "vavg_wu", "vavgr_w", "vavgr_wu", 175 "vabsd_w", "vabsd_wu", "vadda_w", 176 "vmax_w", "vmax_wu", "vmin_w", "vmin_wu", 177 "vmul_w", "vmuh_w", "vmuh_wu", 178 "vdiv_w", "vdiv_wu", "vmod_w", "vmod_wu", "vsigncov_w", 179 "vsll_w", "vsrl_w", "vsra_w", "vrotr_w", "vsrlr_w", "vsrar_w", 180 "vbitclr_w", "vbitset_w", "vbitrev_w", 181 "vseq_w", "vsle_w", "vsle_wu", "vslt_w", "vslt_wu", 182 "vpackev_w", "vpackod_w", "vpickev_w", "vpickod_w", 183 "vilvl_w", "vilvh_w"] in 184 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 185 [llvm_v4i32_ty, llvm_v4i32_ty], 186 [IntrNoMem]>; 187 188foreach inst = ["vadd_d", "vadd_q", "vsub_d", "vsub_q", 189 "vsadd_d", "vsadd_du", "vssub_d", "vssub_du", 190 "vhaddw_q_d", "vhaddw_qu_du", "vhsubw_q_d", "vhsubw_qu_du", 191 "vaddwev_q_d", "vaddwod_q_d", "vsubwev_q_d", "vsubwod_q_d", 192 "vaddwev_q_du", "vaddwod_q_du", "vsubwev_q_du", "vsubwod_q_du", 193 "vaddwev_q_du_d", "vaddwod_q_du_d", 194 "vavg_d", "vavg_du", "vavgr_d", "vavgr_du", 195 "vabsd_d", "vabsd_du", "vadda_d", 196 "vmax_d", "vmax_du", "vmin_d", "vmin_du", 197 "vmul_d", "vmuh_d", "vmuh_du", 198 "vmulwev_q_d", "vmulwod_q_d", "vmulwev_q_du", "vmulwod_q_du", 199 "vmulwev_q_du_d", "vmulwod_q_du_d", 200 "vdiv_d", "vdiv_du", "vmod_d", "vmod_du", "vsigncov_d", 201 "vsll_d", "vsrl_d", "vsra_d", "vrotr_d", "vsrlr_d", "vsrar_d", 202 "vbitclr_d", "vbitset_d", "vbitrev_d", 203 "vseq_d", "vsle_d", "vsle_du", "vslt_d", "vslt_du", 204 "vpackev_d", "vpackod_d", "vpickev_d", "vpickod_d", 205 "vilvl_d", "vilvh_d"] in 206 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 207 [llvm_v2i64_ty, llvm_v2i64_ty], 208 [IntrNoMem]>; 209 210foreach inst = ["vaddi_bu", "vsubi_bu", 211 "vmaxi_b", "vmaxi_bu", "vmini_b", "vmini_bu", 212 "vsat_b", "vsat_bu", 213 "vandi_b", "vori_b", "vxori_b", "vnori_b", 214 "vslli_b", "vsrli_b", "vsrai_b", "vrotri_b", 215 "vsrlri_b", "vsrari_b", 216 "vbitclri_b", "vbitseti_b", "vbitrevi_b", 217 "vseqi_b", "vslei_b", "vslei_bu", "vslti_b", "vslti_bu", 218 "vreplvei_b", "vbsll_v", "vbsrl_v", "vshuf4i_b"] in 219 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], 220 [llvm_v16i8_ty, llvm_i32_ty], 221 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 222foreach inst = ["vaddi_hu", "vsubi_hu", 223 "vmaxi_h", "vmaxi_hu", "vmini_h", "vmini_hu", 224 "vsat_h", "vsat_hu", 225 "vslli_h", "vsrli_h", "vsrai_h", "vrotri_h", 226 "vsrlri_h", "vsrari_h", 227 "vbitclri_h", "vbitseti_h", "vbitrevi_h", 228 "vseqi_h", "vslei_h", "vslei_hu", "vslti_h", "vslti_hu", 229 "vreplvei_h", "vshuf4i_h"] in 230 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 231 [llvm_v8i16_ty, llvm_i32_ty], 232 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 233foreach inst = ["vaddi_wu", "vsubi_wu", 234 "vmaxi_w", "vmaxi_wu", "vmini_w", "vmini_wu", 235 "vsat_w", "vsat_wu", 236 "vslli_w", "vsrli_w", "vsrai_w", "vrotri_w", 237 "vsrlri_w", "vsrari_w", 238 "vbitclri_w", "vbitseti_w", "vbitrevi_w", 239 "vseqi_w", "vslei_w", "vslei_wu", "vslti_w", "vslti_wu", 240 "vreplvei_w", "vshuf4i_w"] in 241 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 242 [llvm_v4i32_ty, llvm_i32_ty], 243 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 244foreach inst = ["vaddi_du", "vsubi_du", 245 "vmaxi_d", "vmaxi_du", "vmini_d", "vmini_du", 246 "vsat_d", "vsat_du", 247 "vslli_d", "vsrli_d", "vsrai_d", "vrotri_d", 248 "vsrlri_d", "vsrari_d", 249 "vbitclri_d", "vbitseti_d", "vbitrevi_d", 250 "vseqi_d", "vslei_d", "vslei_du", "vslti_d", "vslti_du", 251 "vreplvei_d"] in 252 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 253 [llvm_v2i64_ty, llvm_i32_ty], 254 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 255 256foreach inst = ["vhaddw_h_b", "vhaddw_hu_bu", "vhsubw_h_b", "vhsubw_hu_bu", 257 "vaddwev_h_b", "vaddwod_h_b", "vsubwev_h_b", "vsubwod_h_b", 258 "vaddwev_h_bu", "vaddwod_h_bu", "vsubwev_h_bu", "vsubwod_h_bu", 259 "vaddwev_h_bu_b", "vaddwod_h_bu_b", 260 "vmulwev_h_b", "vmulwod_h_b", "vmulwev_h_bu", "vmulwod_h_bu", 261 "vmulwev_h_bu_b", "vmulwod_h_bu_b"] in 262 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 263 [llvm_v16i8_ty, llvm_v16i8_ty], 264 [IntrNoMem]>; 265 266foreach inst = ["vhaddw_w_h", "vhaddw_wu_hu", "vhsubw_w_h", "vhsubw_wu_hu", 267 "vaddwev_w_h", "vaddwod_w_h", "vsubwev_w_h", "vsubwod_w_h", 268 "vaddwev_w_hu", "vaddwod_w_hu", "vsubwev_w_hu", "vsubwod_w_hu", 269 "vaddwev_w_hu_h", "vaddwod_w_hu_h", 270 "vmulwev_w_h", "vmulwod_w_h", "vmulwev_w_hu", "vmulwod_w_hu", 271 "vmulwev_w_hu_h", "vmulwod_w_hu_h"] in 272 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 273 [llvm_v8i16_ty, llvm_v8i16_ty], 274 [IntrNoMem]>; 275 276foreach inst = ["vhaddw_d_w", "vhaddw_du_wu", "vhsubw_d_w", "vhsubw_du_wu", 277 "vaddwev_d_w", "vaddwod_d_w", "vsubwev_d_w", "vsubwod_d_w", 278 "vaddwev_d_wu", "vaddwod_d_wu", "vsubwev_d_wu", "vsubwod_d_wu", 279 "vaddwev_d_wu_w", "vaddwod_d_wu_w", 280 "vmulwev_d_w", "vmulwod_d_w", "vmulwev_d_wu", "vmulwod_d_wu", 281 "vmulwev_d_wu_w", "vmulwod_d_wu_w"] in 282 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 283 [llvm_v4i32_ty, llvm_v4i32_ty], 284 [IntrNoMem]>; 285 286foreach inst = ["vsrln_b_h", "vsran_b_h", "vsrlrn_b_h", "vsrarn_b_h", 287 "vssrln_b_h", "vssran_b_h", "vssrln_bu_h", "vssran_bu_h", 288 "vssrlrn_b_h", "vssrarn_b_h", "vssrlrn_bu_h", "vssrarn_bu_h"] in 289 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], 290 [llvm_v8i16_ty, llvm_v8i16_ty], 291 [IntrNoMem]>; 292 293foreach inst = ["vsrln_h_w", "vsran_h_w", "vsrlrn_h_w", "vsrarn_h_w", 294 "vssrln_h_w", "vssran_h_w", "vssrln_hu_w", "vssran_hu_w", 295 "vssrlrn_h_w", "vssrarn_h_w", "vssrlrn_hu_w", "vssrarn_hu_w"] in 296 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 297 [llvm_v4i32_ty, llvm_v4i32_ty], 298 [IntrNoMem]>; 299 300foreach inst = ["vsrln_w_d", "vsran_w_d", "vsrlrn_w_d", "vsrarn_w_d", 301 "vssrln_w_d", "vssran_w_d", "vssrln_wu_d", "vssran_wu_d", 302 "vssrlrn_w_d", "vssrarn_w_d", "vssrlrn_wu_d", "vssrarn_wu_d"] in 303 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 304 [llvm_v2i64_ty, llvm_v2i64_ty], 305 [IntrNoMem]>; 306 307foreach inst = ["vmadd_b", "vmsub_b", "vfrstp_b", "vbitsel_v", "vshuf_b"] in 308 def int_loongarch_lsx_#inst 309 : VecInt<[llvm_v16i8_ty], 310 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], 311 [IntrNoMem]>; 312foreach inst = ["vmadd_h", "vmsub_h", "vfrstp_h", "vshuf_h"] in 313 def int_loongarch_lsx_#inst 314 : VecInt<[llvm_v8i16_ty], 315 [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], 316 [IntrNoMem]>; 317foreach inst = ["vmadd_w", "vmsub_w", "vshuf_w"] in 318 def int_loongarch_lsx_#inst 319 : VecInt<[llvm_v4i32_ty], 320 [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 321 [IntrNoMem]>; 322foreach inst = ["vmadd_d", "vmsub_d", "vshuf_d"] in 323 def int_loongarch_lsx_#inst 324 : VecInt<[llvm_v2i64_ty], 325 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], 326 [IntrNoMem]>; 327 328foreach inst = ["vsrlni_b_h", "vsrani_b_h", "vsrlrni_b_h", "vsrarni_b_h", 329 "vssrlni_b_h", "vssrani_b_h", "vssrlni_bu_h", "vssrani_bu_h", 330 "vssrlrni_b_h", "vssrarni_b_h", "vssrlrni_bu_h", "vssrarni_bu_h", 331 "vfrstpi_b", "vbitseli_b", "vextrins_b"] in 332 def int_loongarch_lsx_#inst 333 : VecInt<[llvm_v16i8_ty], 334 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty], 335 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 336foreach inst = ["vsrlni_h_w", "vsrani_h_w", "vsrlrni_h_w", "vsrarni_h_w", 337 "vssrlni_h_w", "vssrani_h_w", "vssrlni_hu_w", "vssrani_hu_w", 338 "vssrlrni_h_w", "vssrarni_h_w", "vssrlrni_hu_w", "vssrarni_hu_w", 339 "vfrstpi_h", "vextrins_h"] in 340 def int_loongarch_lsx_#inst 341 : VecInt<[llvm_v8i16_ty], 342 [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty], 343 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 344foreach inst = ["vsrlni_w_d", "vsrani_w_d", "vsrlrni_w_d", "vsrarni_w_d", 345 "vssrlni_w_d", "vssrani_w_d", "vssrlni_wu_d", "vssrani_wu_d", 346 "vssrlrni_w_d", "vssrarni_w_d", "vssrlrni_wu_d", "vssrarni_wu_d", 347 "vpermi_w", "vextrins_w"] in 348 def int_loongarch_lsx_#inst 349 : VecInt<[llvm_v4i32_ty], 350 [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], 351 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 352foreach inst = ["vsrlni_d_q", "vsrani_d_q", "vsrlrni_d_q", "vsrarni_d_q", 353 "vssrlni_d_q", "vssrani_d_q", "vssrlni_du_q", "vssrani_du_q", 354 "vssrlrni_d_q", "vssrarni_d_q", "vssrlrni_du_q", "vssrarni_du_q", 355 "vshuf4i_d", "vextrins_d"] in 356 def int_loongarch_lsx_#inst 357 : VecInt<[llvm_v2i64_ty], 358 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty], 359 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 360 361foreach inst = ["vmaddwev_h_b", "vmaddwod_h_b", "vmaddwev_h_bu", 362 "vmaddwod_h_bu", "vmaddwev_h_bu_b", "vmaddwod_h_bu_b"] in 363 def int_loongarch_lsx_#inst 364 : VecInt<[llvm_v8i16_ty], 365 [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], 366 [IntrNoMem]>; 367foreach inst = ["vmaddwev_w_h", "vmaddwod_w_h", "vmaddwev_w_hu", 368 "vmaddwod_w_hu", "vmaddwev_w_hu_h", "vmaddwod_w_hu_h"] in 369 def int_loongarch_lsx_#inst 370 : VecInt<[llvm_v4i32_ty], 371 [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], 372 [IntrNoMem]>; 373foreach inst = ["vmaddwev_d_w", "vmaddwod_d_w", "vmaddwev_d_wu", 374 "vmaddwod_d_wu", "vmaddwev_d_wu_w", "vmaddwod_d_wu_w"] in 375 def int_loongarch_lsx_#inst 376 : VecInt<[llvm_v2i64_ty], 377 [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty], 378 [IntrNoMem]>; 379foreach inst = ["vmaddwev_q_d", "vmaddwod_q_d", "vmaddwev_q_du", 380 "vmaddwod_q_du", "vmaddwev_q_du_d", "vmaddwod_q_du_d"] in 381 def int_loongarch_lsx_#inst 382 : VecInt<[llvm_v2i64_ty], 383 [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty], 384 [IntrNoMem]>; 385 386foreach inst = ["vsllwil_h_b", "vsllwil_hu_bu"] in 387 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 388 [llvm_v16i8_ty, llvm_i32_ty], 389 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 390foreach inst = ["vsllwil_w_h", "vsllwil_wu_hu"] in 391 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 392 [llvm_v8i16_ty, llvm_i32_ty], 393 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 394foreach inst = ["vsllwil_d_w", "vsllwil_du_wu"] in 395 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 396 [llvm_v4i32_ty, llvm_i32_ty], 397 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 398 399foreach inst = ["vneg_b", "vmskltz_b", "vmskgez_b", "vmsknz_b", 400 "vclo_b", "vclz_b", "vpcnt_b"] in 401 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty], 402 [IntrNoMem]>; 403foreach inst = ["vneg_h", "vmskltz_h", "vclo_h", "vclz_h", "vpcnt_h"] in 404 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty], 405 [IntrNoMem]>; 406foreach inst = ["vneg_w", "vmskltz_w", "vclo_w", "vclz_w", "vpcnt_w"] in 407 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty], 408 [IntrNoMem]>; 409foreach inst = ["vneg_d", "vexth_q_d", "vexth_qu_du", "vmskltz_d", 410 "vextl_q_d", "vextl_qu_du", "vclo_d", "vclz_d", "vpcnt_d"] in 411 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty], 412 [IntrNoMem]>; 413 414foreach inst = ["vexth_h_b", "vexth_hu_bu"] in 415 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], [llvm_v16i8_ty], 416 [IntrNoMem]>; 417foreach inst = ["vexth_w_h", "vexth_wu_hu"] in 418 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v8i16_ty], 419 [IntrNoMem]>; 420foreach inst = ["vexth_d_w", "vexth_du_wu"] in 421 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v4i32_ty], 422 [IntrNoMem]>; 423 424def int_loongarch_lsx_vldi : VecInt<[llvm_v2i64_ty], [llvm_i32_ty], 425 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 426def int_loongarch_lsx_vrepli_b : VecInt<[llvm_v16i8_ty], [llvm_i32_ty], 427 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 428def int_loongarch_lsx_vrepli_h : VecInt<[llvm_v8i16_ty], [llvm_i32_ty], 429 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 430def int_loongarch_lsx_vrepli_w : VecInt<[llvm_v4i32_ty], [llvm_i32_ty], 431 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 432def int_loongarch_lsx_vrepli_d : VecInt<[llvm_v2i64_ty], [llvm_i32_ty], 433 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 434 435def int_loongarch_lsx_vreplgr2vr_b : VecInt<[llvm_v16i8_ty], [llvm_i32_ty], 436 [IntrNoMem]>; 437def int_loongarch_lsx_vreplgr2vr_h : VecInt<[llvm_v8i16_ty], [llvm_i32_ty], 438 [IntrNoMem]>; 439def int_loongarch_lsx_vreplgr2vr_w : VecInt<[llvm_v4i32_ty], [llvm_i32_ty], 440 [IntrNoMem]>; 441def int_loongarch_lsx_vreplgr2vr_d : VecInt<[llvm_v2i64_ty], [llvm_i64_ty], 442 [IntrNoMem]>; 443 444def int_loongarch_lsx_vinsgr2vr_b 445 : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], 446 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 447def int_loongarch_lsx_vinsgr2vr_h 448 : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty], 449 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 450def int_loongarch_lsx_vinsgr2vr_w 451 : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty], 452 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 453def int_loongarch_lsx_vinsgr2vr_d 454 : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty], 455 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 456 457def int_loongarch_lsx_vreplve_b 458 : VecInt<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; 459def int_loongarch_lsx_vreplve_h 460 : VecInt<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>; 461def int_loongarch_lsx_vreplve_w 462 : VecInt<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>; 463def int_loongarch_lsx_vreplve_d 464 : VecInt<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; 465 466foreach inst = ["vpickve2gr_b", "vpickve2gr_bu" ] in 467 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty], 468 [llvm_v16i8_ty, llvm_i32_ty], 469 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 470foreach inst = ["vpickve2gr_h", "vpickve2gr_hu" ] in 471 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty], 472 [llvm_v8i16_ty, llvm_i32_ty], 473 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 474foreach inst = ["vpickve2gr_w", "vpickve2gr_wu" ] in 475 def int_loongarch_lsx_#inst : VecInt<[llvm_i32_ty], 476 [llvm_v4i32_ty, llvm_i32_ty], 477 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 478foreach inst = ["vpickve2gr_d", "vpickve2gr_du" ] in 479 def int_loongarch_lsx_#inst : VecInt<[llvm_i64_ty], 480 [llvm_v2i64_ty, llvm_i32_ty], 481 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 482 483def int_loongarch_lsx_bz_b : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 484 [IntrNoMem]>; 485def int_loongarch_lsx_bz_h : VecInt<[llvm_i32_ty], [llvm_v8i16_ty], 486 [IntrNoMem]>; 487def int_loongarch_lsx_bz_w : VecInt<[llvm_i32_ty], [llvm_v4i32_ty], 488 [IntrNoMem]>; 489def int_loongarch_lsx_bz_d : VecInt<[llvm_i32_ty], [llvm_v2i64_ty], 490 [IntrNoMem]>; 491def int_loongarch_lsx_bz_v : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 492 [IntrNoMem]>; 493 494def int_loongarch_lsx_bnz_v : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 495 [IntrNoMem]>; 496def int_loongarch_lsx_bnz_b : VecInt<[llvm_i32_ty], [llvm_v16i8_ty], 497 [IntrNoMem]>; 498def int_loongarch_lsx_bnz_h : VecInt<[llvm_i32_ty], [llvm_v8i16_ty], 499 [IntrNoMem]>; 500def int_loongarch_lsx_bnz_w : VecInt<[llvm_i32_ty], [llvm_v4i32_ty], 501 [IntrNoMem]>; 502def int_loongarch_lsx_bnz_d : VecInt<[llvm_i32_ty], [llvm_v2i64_ty], 503 [IntrNoMem]>; 504 505// LSX Float 506 507foreach inst = ["vfadd_s", "vfsub_s", "vfmul_s", "vfdiv_s", 508 "vfmax_s", "vfmin_s", "vfmaxa_s", "vfmina_s"] in 509 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], 510 [llvm_v4f32_ty, llvm_v4f32_ty], 511 [IntrNoMem]>; 512foreach inst = ["vfadd_d", "vfsub_d", "vfmul_d", "vfdiv_d", 513 "vfmax_d", "vfmin_d", "vfmaxa_d", "vfmina_d"] in 514 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], 515 [llvm_v2f64_ty, llvm_v2f64_ty], 516 [IntrNoMem]>; 517 518foreach inst = ["vfmadd_s", "vfmsub_s", "vfnmadd_s", "vfnmsub_s"] in 519 def int_loongarch_lsx_#inst 520 : VecInt<[llvm_v4f32_ty], 521 [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty], 522 [IntrNoMem]>; 523foreach inst = ["vfmadd_d", "vfmsub_d", "vfnmadd_d", "vfnmsub_d"] in 524 def int_loongarch_lsx_#inst 525 : VecInt<[llvm_v2f64_ty], 526 [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], 527 [IntrNoMem]>; 528 529foreach inst = ["vflogb_s", "vfsqrt_s", "vfrecip_s", "vfrsqrt_s", "vfrint_s", 530 "vfrintrne_s", "vfrintrz_s", "vfrintrp_s", "vfrintrm_s"] in 531 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4f32_ty], 532 [IntrNoMem]>; 533foreach inst = ["vflogb_d", "vfsqrt_d", "vfrecip_d", "vfrsqrt_d", "vfrint_d", 534 "vfrintrne_d", "vfrintrz_d", "vfrintrp_d", "vfrintrm_d"] in 535 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2f64_ty], 536 [IntrNoMem]>; 537 538foreach inst = ["vfcvtl_s_h", "vfcvth_s_h"] in 539 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v8i16_ty], 540 [IntrNoMem]>; 541foreach inst = ["vfcvtl_d_s", "vfcvth_d_s"] in 542 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v4f32_ty], 543 [IntrNoMem]>; 544 545foreach inst = ["vftintrne_w_s", "vftintrz_w_s", "vftintrp_w_s", "vftintrm_w_s", 546 "vftint_w_s", "vftintrz_wu_s", "vftint_wu_s", "vfclass_s"] in 547 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], [llvm_v4f32_ty], 548 [IntrNoMem]>; 549foreach inst = ["vftintrne_l_d", "vftintrz_l_d", "vftintrp_l_d", "vftintrm_l_d", 550 "vftint_l_d", "vftintrz_lu_d", "vftint_lu_d", "vfclass_d"] in 551 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v2f64_ty], 552 [IntrNoMem]>; 553 554foreach inst = ["vftintrnel_l_s", "vftintrneh_l_s", "vftintrzl_l_s", 555 "vftintrzh_l_s", "vftintrpl_l_s", "vftintrph_l_s", 556 "vftintrml_l_s", "vftintrmh_l_s", "vftintl_l_s", 557 "vftinth_l_s"] in 558 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], [llvm_v4f32_ty], 559 [IntrNoMem]>; 560 561foreach inst = ["vffint_s_w", "vffint_s_wu"] in 562 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4i32_ty], 563 [IntrNoMem]>; 564foreach inst = ["vffint_d_l", "vffint_d_lu"] in 565 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2i64_ty], 566 [IntrNoMem]>; 567 568foreach inst = ["vffintl_d_w", "vffinth_d_w"] in 569 def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v4i32_ty], 570 [IntrNoMem]>; 571 572foreach inst = ["vffint_s_l"] in 573 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], 574 [llvm_v2i64_ty, llvm_v2i64_ty], 575 [IntrNoMem]>; 576foreach inst = ["vftintrne_w_d", "vftintrz_w_d", "vftintrp_w_d", "vftintrm_w_d", 577 "vftint_w_d"] in 578 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 579 [llvm_v2f64_ty, llvm_v2f64_ty], 580 [IntrNoMem]>; 581 582foreach inst = ["vfcvt_h_s"] in 583 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty], 584 [llvm_v4f32_ty, llvm_v4f32_ty], 585 [IntrNoMem]>; 586foreach inst = ["vfcvt_s_d"] in 587 def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], 588 [llvm_v2f64_ty, llvm_v2f64_ty], 589 [IntrNoMem]>; 590 591foreach inst = ["vfcmp_caf_s", "vfcmp_cun_s", "vfcmp_ceq_s", "vfcmp_cueq_s", 592 "vfcmp_clt_s", "vfcmp_cult_s", "vfcmp_cle_s", "vfcmp_cule_s", 593 "vfcmp_cne_s", "vfcmp_cor_s", "vfcmp_cune_s", 594 "vfcmp_saf_s", "vfcmp_sun_s", "vfcmp_seq_s", "vfcmp_sueq_s", 595 "vfcmp_slt_s", "vfcmp_sult_s", "vfcmp_sle_s", "vfcmp_sule_s", 596 "vfcmp_sne_s", "vfcmp_sor_s", "vfcmp_sune_s"] in 597 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty], 598 [llvm_v4f32_ty, llvm_v4f32_ty], 599 [IntrNoMem]>; 600foreach inst = ["vfcmp_caf_d", "vfcmp_cun_d", "vfcmp_ceq_d", "vfcmp_cueq_d", 601 "vfcmp_clt_d", "vfcmp_cult_d", "vfcmp_cle_d", "vfcmp_cule_d", 602 "vfcmp_cne_d", "vfcmp_cor_d", "vfcmp_cune_d", 603 "vfcmp_saf_d", "vfcmp_sun_d", "vfcmp_seq_d", "vfcmp_sueq_d", 604 "vfcmp_slt_d", "vfcmp_sult_d", "vfcmp_sle_d", "vfcmp_sule_d", 605 "vfcmp_sne_d", "vfcmp_sor_d", "vfcmp_sune_d"] in 606 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty], 607 [llvm_v2f64_ty, llvm_v2f64_ty], 608 [IntrNoMem]>; 609 610// LSX load/store 611def int_loongarch_lsx_vld 612 : VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty], 613 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 614def int_loongarch_lsx_vldx 615 : VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i64_ty], 616 [IntrReadMem, IntrArgMemOnly]>; 617def int_loongarch_lsx_vldrepl_b 618 : VecInt<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty], 619 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 620def int_loongarch_lsx_vldrepl_h 621 : VecInt<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty], 622 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 623def int_loongarch_lsx_vldrepl_w 624 : VecInt<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty], 625 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 626def int_loongarch_lsx_vldrepl_d 627 : VecInt<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty], 628 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 629 630def int_loongarch_lsx_vst 631 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty], 632 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>]>; 633def int_loongarch_lsx_vstx 634 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i64_ty], 635 [IntrWriteMem, IntrArgMemOnly]>; 636def int_loongarch_lsx_vstelm_b 637 : VecInt<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 638 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 639def int_loongarch_lsx_vstelm_h 640 : VecInt<[], [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 641 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 642def int_loongarch_lsx_vstelm_w 643 : VecInt<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 644 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 645def int_loongarch_lsx_vstelm_d 646 : VecInt<[], [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 647 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 648 649} // TargetPrefix = "loongarch" 650 651//===----------------------------------------------------------------------===// 652// LASX 653 654let TargetPrefix = "loongarch" in { 655foreach inst = ["xvadd_b", "xvsub_b", 656 "xvsadd_b", "xvsadd_bu", "xvssub_b", "xvssub_bu", 657 "xvavg_b", "xvavg_bu", "xvavgr_b", "xvavgr_bu", 658 "xvabsd_b", "xvabsd_bu", "xvadda_b", 659 "xvmax_b", "xvmax_bu", "xvmin_b", "xvmin_bu", 660 "xvmul_b", "xvmuh_b", "xvmuh_bu", 661 "xvdiv_b", "xvdiv_bu", "xvmod_b", "xvmod_bu", "xvsigncov_b", 662 "xvand_v", "xvor_v", "xvxor_v", "xvnor_v", "xvandn_v", "xvorn_v", 663 "xvsll_b", "xvsrl_b", "xvsra_b", "xvrotr_b", "xvsrlr_b", "xvsrar_b", 664 "xvbitclr_b", "xvbitset_b", "xvbitrev_b", 665 "xvseq_b", "xvsle_b", "xvsle_bu", "xvslt_b", "xvslt_bu", 666 "xvpackev_b", "xvpackod_b", "xvpickev_b", "xvpickod_b", 667 "xvilvl_b", "xvilvh_b"] in 668 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], 669 [llvm_v32i8_ty, llvm_v32i8_ty], 670 [IntrNoMem]>; 671 672foreach inst = ["xvadd_h", "xvsub_h", 673 "xvsadd_h", "xvsadd_hu", "xvssub_h", "xvssub_hu", 674 "xvavg_h", "xvavg_hu", "xvavgr_h", "xvavgr_hu", 675 "xvabsd_h", "xvabsd_hu", "xvadda_h", 676 "xvmax_h", "xvmax_hu", "xvmin_h", "xvmin_hu", 677 "xvmul_h", "xvmuh_h", "xvmuh_hu", 678 "xvdiv_h", "xvdiv_hu", "xvmod_h", "xvmod_hu", "xvsigncov_h", 679 "xvsll_h", "xvsrl_h", "xvsra_h", "xvrotr_h", "xvsrlr_h", "xvsrar_h", 680 "xvbitclr_h", "xvbitset_h", "xvbitrev_h", 681 "xvseq_h", "xvsle_h", "xvsle_hu", "xvslt_h", "xvslt_hu", 682 "xvpackev_h", "xvpackod_h", "xvpickev_h", "xvpickod_h", 683 "xvilvl_h", "xvilvh_h"] in 684 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 685 [llvm_v16i16_ty, llvm_v16i16_ty], 686 [IntrNoMem]>; 687 688foreach inst = ["xvadd_w", "xvsub_w", 689 "xvsadd_w", "xvsadd_wu", "xvssub_w", "xvssub_wu", 690 "xvavg_w", "xvavg_wu", "xvavgr_w", "xvavgr_wu", 691 "xvabsd_w", "xvabsd_wu", "xvadda_w", 692 "xvmax_w", "xvmax_wu", "xvmin_w", "xvmin_wu", 693 "xvmul_w", "xvmuh_w", "xvmuh_wu", 694 "xvdiv_w", "xvdiv_wu", "xvmod_w", "xvmod_wu", "xvsigncov_w", 695 "xvsll_w", "xvsrl_w", "xvsra_w", "xvrotr_w", "xvsrlr_w", "xvsrar_w", 696 "xvbitclr_w", "xvbitset_w", "xvbitrev_w", 697 "xvseq_w", "xvsle_w", "xvsle_wu", "xvslt_w", "xvslt_wu", 698 "xvpackev_w", "xvpackod_w", "xvpickev_w", "xvpickod_w", 699 "xvilvl_w", "xvilvh_w", "xvperm_w"] in 700 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 701 [llvm_v8i32_ty, llvm_v8i32_ty], 702 [IntrNoMem]>; 703 704foreach inst = ["xvadd_d", "xvadd_q", "xvsub_d", "xvsub_q", 705 "xvsadd_d", "xvsadd_du", "xvssub_d", "xvssub_du", 706 "xvhaddw_q_d", "xvhaddw_qu_du", "xvhsubw_q_d", "xvhsubw_qu_du", 707 "xvaddwev_q_d", "xvaddwod_q_d", "xvsubwev_q_d", "xvsubwod_q_d", 708 "xvaddwev_q_du", "xvaddwod_q_du", "xvsubwev_q_du", "xvsubwod_q_du", 709 "xvaddwev_q_du_d", "xvaddwod_q_du_d", 710 "xvavg_d", "xvavg_du", "xvavgr_d", "xvavgr_du", 711 "xvabsd_d", "xvabsd_du", "xvadda_d", 712 "xvmax_d", "xvmax_du", "xvmin_d", "xvmin_du", 713 "xvmul_d", "xvmuh_d", "xvmuh_du", 714 "xvmulwev_q_d", "xvmulwod_q_d", "xvmulwev_q_du", "xvmulwod_q_du", 715 "xvmulwev_q_du_d", "xvmulwod_q_du_d", 716 "xvdiv_d", "xvdiv_du", "xvmod_d", "xvmod_du", "xvsigncov_d", 717 "xvsll_d", "xvsrl_d", "xvsra_d", "xvrotr_d", "xvsrlr_d", "xvsrar_d", 718 "xvbitclr_d", "xvbitset_d", "xvbitrev_d", 719 "xvseq_d", "xvsle_d", "xvsle_du", "xvslt_d", "xvslt_du", 720 "xvpackev_d", "xvpackod_d", "xvpickev_d", "xvpickod_d", 721 "xvilvl_d", "xvilvh_d"] in 722 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 723 [llvm_v4i64_ty, llvm_v4i64_ty], 724 [IntrNoMem]>; 725 726foreach inst = ["xvaddi_bu", "xvsubi_bu", 727 "xvmaxi_b", "xvmaxi_bu", "xvmini_b", "xvmini_bu", 728 "xvsat_b", "xvsat_bu", 729 "xvandi_b", "xvori_b", "xvxori_b", "xvnori_b", 730 "xvslli_b", "xvsrli_b", "xvsrai_b", "xvrotri_b", 731 "xvsrlri_b", "xvsrari_b", 732 "xvbitclri_b", "xvbitseti_b", "xvbitrevi_b", 733 "xvseqi_b", "xvslei_b", "xvslei_bu", "xvslti_b", "xvslti_bu", 734 "xvrepl128vei_b", "xvbsll_v", "xvbsrl_v", "xvshuf4i_b"] in 735 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], 736 [llvm_v32i8_ty, llvm_i32_ty], 737 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 738foreach inst = ["xvaddi_hu", "xvsubi_hu", 739 "xvmaxi_h", "xvmaxi_hu", "xvmini_h", "xvmini_hu", 740 "xvsat_h", "xvsat_hu", 741 "xvslli_h", "xvsrli_h", "xvsrai_h", "xvrotri_h", 742 "xvsrlri_h", "xvsrari_h", 743 "xvbitclri_h", "xvbitseti_h", "xvbitrevi_h", 744 "xvseqi_h", "xvslei_h", "xvslei_hu", "xvslti_h", "xvslti_hu", 745 "xvrepl128vei_h", "xvshuf4i_h"] in 746 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 747 [llvm_v16i16_ty, llvm_i32_ty], 748 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 749foreach inst = ["xvaddi_wu", "xvsubi_wu", 750 "xvmaxi_w", "xvmaxi_wu", "xvmini_w", "xvmini_wu", 751 "xvsat_w", "xvsat_wu", 752 "xvslli_w", "xvsrli_w", "xvsrai_w", "xvrotri_w", 753 "xvsrlri_w", "xvsrari_w", 754 "xvbitclri_w", "xvbitseti_w", "xvbitrevi_w", 755 "xvseqi_w", "xvslei_w", "xvslei_wu", "xvslti_w", "xvslti_wu", 756 "xvrepl128vei_w", "xvshuf4i_w", "xvpickve_w"] in 757 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 758 [llvm_v8i32_ty, llvm_i32_ty], 759 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 760foreach inst = ["xvaddi_du", "xvsubi_du", 761 "xvmaxi_d", "xvmaxi_du", "xvmini_d", "xvmini_du", 762 "xvsat_d", "xvsat_du", 763 "xvslli_d", "xvsrli_d", "xvsrai_d", "xvrotri_d", 764 "xvsrlri_d", "xvsrari_d", 765 "xvbitclri_d", "xvbitseti_d", "xvbitrevi_d", 766 "xvseqi_d", "xvslei_d", "xvslei_du", "xvslti_d", "xvslti_du", 767 "xvrepl128vei_d", "xvpermi_d", "xvpickve_d"] in 768 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 769 [llvm_v4i64_ty, llvm_i32_ty], 770 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 771 772foreach inst = ["xvhaddw_h_b", "xvhaddw_hu_bu", "xvhsubw_h_b", "xvhsubw_hu_bu", 773 "xvaddwev_h_b", "xvaddwod_h_b", "xvsubwev_h_b", "xvsubwod_h_b", 774 "xvaddwev_h_bu", "xvaddwod_h_bu", "xvsubwev_h_bu", "xvsubwod_h_bu", 775 "xvaddwev_h_bu_b", "xvaddwod_h_bu_b", 776 "xvmulwev_h_b", "xvmulwod_h_b", "xvmulwev_h_bu", "xvmulwod_h_bu", 777 "xvmulwev_h_bu_b", "xvmulwod_h_bu_b"] in 778 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 779 [llvm_v32i8_ty, llvm_v32i8_ty], 780 [IntrNoMem]>; 781 782foreach inst = ["xvhaddw_w_h", "xvhaddw_wu_hu", "xvhsubw_w_h", "xvhsubw_wu_hu", 783 "xvaddwev_w_h", "xvaddwod_w_h", "xvsubwev_w_h", "xvsubwod_w_h", 784 "xvaddwev_w_hu", "xvaddwod_w_hu", "xvsubwev_w_hu", "xvsubwod_w_hu", 785 "xvaddwev_w_hu_h", "xvaddwod_w_hu_h", 786 "xvmulwev_w_h", "xvmulwod_w_h", "xvmulwev_w_hu", "xvmulwod_w_hu", 787 "xvmulwev_w_hu_h", "xvmulwod_w_hu_h"] in 788 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 789 [llvm_v16i16_ty, llvm_v16i16_ty], 790 [IntrNoMem]>; 791 792foreach inst = ["xvhaddw_d_w", "xvhaddw_du_wu", "xvhsubw_d_w", "xvhsubw_du_wu", 793 "xvaddwev_d_w", "xvaddwod_d_w", "xvsubwev_d_w", "xvsubwod_d_w", 794 "xvaddwev_d_wu", "xvaddwod_d_wu", "xvsubwev_d_wu", "xvsubwod_d_wu", 795 "xvaddwev_d_wu_w", "xvaddwod_d_wu_w", 796 "xvmulwev_d_w", "xvmulwod_d_w", "xvmulwev_d_wu", "xvmulwod_d_wu", 797 "xvmulwev_d_wu_w", "xvmulwod_d_wu_w"] in 798 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 799 [llvm_v8i32_ty, llvm_v8i32_ty], 800 [IntrNoMem]>; 801 802foreach inst = ["xvsrln_b_h", "xvsran_b_h", "xvsrlrn_b_h", "xvsrarn_b_h", 803 "xvssrln_b_h", "xvssran_b_h", "xvssrln_bu_h", "xvssran_bu_h", 804 "xvssrlrn_b_h", "xvssrarn_b_h", "xvssrlrn_bu_h", "xvssrarn_bu_h"] in 805 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], 806 [llvm_v16i16_ty, llvm_v16i16_ty], 807 [IntrNoMem]>; 808 809foreach inst = ["xvsrln_h_w", "xvsran_h_w", "xvsrlrn_h_w", "xvsrarn_h_w", 810 "xvssrln_h_w", "xvssran_h_w", "xvssrln_hu_w", "xvssran_hu_w", 811 "xvssrlrn_h_w", "xvssrarn_h_w", "xvssrlrn_hu_w", "xvssrarn_hu_w"] in 812 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 813 [llvm_v8i32_ty, llvm_v8i32_ty], 814 [IntrNoMem]>; 815 816foreach inst = ["xvsrln_w_d", "xvsran_w_d", "xvsrlrn_w_d", "xvsrarn_w_d", 817 "xvssrln_w_d", "xvssran_w_d", "xvssrln_wu_d", "xvssran_wu_d", 818 "xvssrlrn_w_d", "xvssrarn_w_d", "xvssrlrn_wu_d", "xvssrarn_wu_d"] in 819 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 820 [llvm_v4i64_ty, llvm_v4i64_ty], 821 [IntrNoMem]>; 822 823foreach inst = ["xvmadd_b", "xvmsub_b", "xvfrstp_b", "xvbitsel_v", "xvshuf_b"] in 824 def int_loongarch_lasx_#inst 825 : VecInt<[llvm_v32i8_ty], 826 [llvm_v32i8_ty, llvm_v32i8_ty, llvm_v32i8_ty], 827 [IntrNoMem]>; 828foreach inst = ["xvmadd_h", "xvmsub_h", "xvfrstp_h", "xvshuf_h"] in 829 def int_loongarch_lasx_#inst 830 : VecInt<[llvm_v16i16_ty], 831 [llvm_v16i16_ty, llvm_v16i16_ty, llvm_v16i16_ty], 832 [IntrNoMem]>; 833foreach inst = ["xvmadd_w", "xvmsub_w", "xvshuf_w"] in 834 def int_loongarch_lasx_#inst 835 : VecInt<[llvm_v8i32_ty], 836 [llvm_v8i32_ty, llvm_v8i32_ty, llvm_v8i32_ty], 837 [IntrNoMem]>; 838foreach inst = ["xvmadd_d", "xvmsub_d", "xvshuf_d"] in 839 def int_loongarch_lasx_#inst 840 : VecInt<[llvm_v4i64_ty], 841 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty], 842 [IntrNoMem]>; 843 844foreach inst = ["xvsrlni_b_h", "xvsrani_b_h", "xvsrlrni_b_h", "xvsrarni_b_h", 845 "xvssrlni_b_h", "xvssrani_b_h", "xvssrlni_bu_h", "xvssrani_bu_h", 846 "xvssrlrni_b_h", "xvssrarni_b_h", "xvssrlrni_bu_h", "xvssrarni_bu_h", 847 "xvfrstpi_b", "xvbitseli_b", "xvextrins_b", "xvpermi_q"] in 848 def int_loongarch_lasx_#inst 849 : VecInt<[llvm_v32i8_ty], 850 [llvm_v32i8_ty, llvm_v32i8_ty, llvm_i32_ty], 851 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 852foreach inst = ["xvsrlni_h_w", "xvsrani_h_w", "xvsrlrni_h_w", "xvsrarni_h_w", 853 "xvssrlni_h_w", "xvssrani_h_w", "xvssrlni_hu_w", "xvssrani_hu_w", 854 "xvssrlrni_h_w", "xvssrarni_h_w", "xvssrlrni_hu_w", "xvssrarni_hu_w", 855 "xvfrstpi_h", "xvextrins_h"] in 856 def int_loongarch_lasx_#inst 857 : VecInt<[llvm_v16i16_ty], 858 [llvm_v16i16_ty, llvm_v16i16_ty, llvm_i32_ty], 859 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 860foreach inst = ["xvsrlni_w_d", "xvsrani_w_d", "xvsrlrni_w_d", "xvsrarni_w_d", 861 "xvssrlni_w_d", "xvssrani_w_d", "xvssrlni_wu_d", "xvssrani_wu_d", 862 "xvssrlrni_w_d", "xvssrarni_w_d", "xvssrlrni_wu_d", "xvssrarni_wu_d", 863 "xvpermi_w", "xvextrins_w", "xvinsve0_w"] in 864 def int_loongarch_lasx_#inst 865 : VecInt<[llvm_v8i32_ty], 866 [llvm_v8i32_ty, llvm_v8i32_ty, llvm_i32_ty], 867 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 868foreach inst = ["xvsrlni_d_q", "xvsrani_d_q", "xvsrlrni_d_q", "xvsrarni_d_q", 869 "xvssrlni_d_q", "xvssrani_d_q", "xvssrlni_du_q", "xvssrani_du_q", 870 "xvssrlrni_d_q", "xvssrarni_d_q", "xvssrlrni_du_q", "xvssrarni_du_q", 871 "xvshuf4i_d", "xvextrins_d", "xvinsve0_d"] in 872 def int_loongarch_lasx_#inst 873 : VecInt<[llvm_v4i64_ty], 874 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_i32_ty], 875 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 876 877foreach inst = ["xvmaddwev_h_b", "xvmaddwod_h_b", "xvmaddwev_h_bu", 878 "xvmaddwod_h_bu", "xvmaddwev_h_bu_b", "xvmaddwod_h_bu_b"] in 879 def int_loongarch_lasx_#inst 880 : VecInt<[llvm_v16i16_ty], 881 [llvm_v16i16_ty, llvm_v32i8_ty, llvm_v32i8_ty], 882 [IntrNoMem]>; 883foreach inst = ["xvmaddwev_w_h", "xvmaddwod_w_h", "xvmaddwev_w_hu", 884 "xvmaddwod_w_hu", "xvmaddwev_w_hu_h", "xvmaddwod_w_hu_h"] in 885 def int_loongarch_lasx_#inst 886 : VecInt<[llvm_v8i32_ty], 887 [llvm_v8i32_ty, llvm_v16i16_ty, llvm_v16i16_ty], 888 [IntrNoMem]>; 889foreach inst = ["xvmaddwev_d_w", "xvmaddwod_d_w", "xvmaddwev_d_wu", 890 "xvmaddwod_d_wu", "xvmaddwev_d_wu_w", "xvmaddwod_d_wu_w"] in 891 def int_loongarch_lasx_#inst 892 : VecInt<[llvm_v4i64_ty], 893 [llvm_v4i64_ty, llvm_v8i32_ty, llvm_v8i32_ty], 894 [IntrNoMem]>; 895foreach inst = ["xvmaddwev_q_d", "xvmaddwod_q_d", "xvmaddwev_q_du", 896 "xvmaddwod_q_du", "xvmaddwev_q_du_d", "xvmaddwod_q_du_d"] in 897 def int_loongarch_lasx_#inst 898 : VecInt<[llvm_v4i64_ty], 899 [llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty], 900 [IntrNoMem]>; 901 902foreach inst = ["xvsllwil_h_b", "xvsllwil_hu_bu"] in 903 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 904 [llvm_v32i8_ty, llvm_i32_ty], 905 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 906foreach inst = ["xvsllwil_w_h", "xvsllwil_wu_hu"] in 907 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 908 [llvm_v16i16_ty, llvm_i32_ty], 909 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 910foreach inst = ["xvsllwil_d_w", "xvsllwil_du_wu"] in 911 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 912 [llvm_v8i32_ty, llvm_i32_ty], 913 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 914 915foreach inst = ["xvneg_b", "xvmskltz_b", "xvmskgez_b", "xvmsknz_b", 916 "xvclo_b", "xvclz_b", "xvpcnt_b", 917 "xvreplve0_b", "xvreplve0_q"] in 918 def int_loongarch_lasx_#inst : VecInt<[llvm_v32i8_ty], [llvm_v32i8_ty], 919 [IntrNoMem]>; 920foreach inst = ["xvneg_h", "xvmskltz_h", "xvclo_h", "xvclz_h", "xvpcnt_h", 921 "xvreplve0_h"] in 922 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], [llvm_v16i16_ty], 923 [IntrNoMem]>; 924foreach inst = ["xvneg_w", "xvmskltz_w", "xvclo_w", "xvclz_w", "xvpcnt_w", 925 "xvreplve0_w"] in 926 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty], 927 [IntrNoMem]>; 928foreach inst = ["xvneg_d", "xvexth_q_d", "xvexth_qu_du", "xvmskltz_d", 929 "xvextl_q_d", "xvextl_qu_du", "xvclo_d", "xvclz_d", "xvpcnt_d", 930 "xvreplve0_d"] in 931 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty], 932 [IntrNoMem]>; 933 934foreach inst = ["xvexth_h_b", "xvexth_hu_bu", "vext2xv_h_b", "vext2xv_hu_bu"] in 935 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], [llvm_v32i8_ty], 936 [IntrNoMem]>; 937foreach inst = ["xvexth_w_h", "xvexth_wu_hu", "vext2xv_w_h", "vext2xv_wu_hu"] in 938 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v16i16_ty], 939 [IntrNoMem]>; 940foreach inst = ["xvexth_d_w", "xvexth_du_wu", "vext2xv_d_w", "vext2xv_du_wu"] in 941 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v8i32_ty], 942 [IntrNoMem]>; 943 944foreach inst = ["vext2xv_w_b", "vext2xv_wu_bu"] in 945 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v32i8_ty], 946 [IntrNoMem]>; 947foreach inst = ["vext2xv_d_h", "vext2xv_du_hu"] in 948 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v16i16_ty], 949 [IntrNoMem]>; 950 951foreach inst = ["vext2xv_d_b", "vext2xv_du_bu"] in 952 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v32i8_ty], 953 [IntrNoMem]>; 954 955def int_loongarch_lasx_xvldi : VecInt<[llvm_v4i64_ty], [llvm_i32_ty], 956 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 957def int_loongarch_lasx_xvrepli_b : VecInt<[llvm_v32i8_ty], [llvm_i32_ty], 958 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 959def int_loongarch_lasx_xvrepli_h : VecInt<[llvm_v16i16_ty], [llvm_i32_ty], 960 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 961def int_loongarch_lasx_xvrepli_w : VecInt<[llvm_v8i32_ty], [llvm_i32_ty], 962 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 963def int_loongarch_lasx_xvrepli_d : VecInt<[llvm_v4i64_ty], [llvm_i32_ty], 964 [IntrNoMem, ImmArg<ArgIndex<0>>]>; 965 966def int_loongarch_lasx_xvreplgr2vr_b : VecInt<[llvm_v32i8_ty], [llvm_i32_ty], 967 [IntrNoMem]>; 968def int_loongarch_lasx_xvreplgr2vr_h : VecInt<[llvm_v16i16_ty], [llvm_i32_ty], 969 [IntrNoMem]>; 970def int_loongarch_lasx_xvreplgr2vr_w : VecInt<[llvm_v8i32_ty], [llvm_i32_ty], 971 [IntrNoMem]>; 972def int_loongarch_lasx_xvreplgr2vr_d : VecInt<[llvm_v4i64_ty], [llvm_i64_ty], 973 [IntrNoMem]>; 974 975def int_loongarch_lasx_xvinsgr2vr_w 976 : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i32_ty, llvm_i32_ty], 977 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 978def int_loongarch_lasx_xvinsgr2vr_d 979 : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i64_ty, llvm_i32_ty], 980 [IntrNoMem, ImmArg<ArgIndex<2>>]>; 981 982def int_loongarch_lasx_xvreplve_b 983 : VecInt<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>; 984def int_loongarch_lasx_xvreplve_h 985 : VecInt<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_i32_ty], [IntrNoMem]>; 986def int_loongarch_lasx_xvreplve_w 987 : VecInt<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i32_ty], [IntrNoMem]>; 988def int_loongarch_lasx_xvreplve_d 989 : VecInt<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_i32_ty], [IntrNoMem]>; 990 991foreach inst = ["xvpickve2gr_w", "xvpickve2gr_wu" ] in 992 def int_loongarch_lasx_#inst : VecInt<[llvm_i32_ty], 993 [llvm_v8i32_ty, llvm_i32_ty], 994 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 995foreach inst = ["xvpickve2gr_d", "xvpickve2gr_du" ] in 996 def int_loongarch_lasx_#inst : VecInt<[llvm_i64_ty], 997 [llvm_v4i64_ty, llvm_i32_ty], 998 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 999 1000def int_loongarch_lasx_xbz_b : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1001 [IntrNoMem]>; 1002def int_loongarch_lasx_xbz_h : VecInt<[llvm_i32_ty], [llvm_v16i16_ty], 1003 [IntrNoMem]>; 1004def int_loongarch_lasx_xbz_w : VecInt<[llvm_i32_ty], [llvm_v8i32_ty], 1005 [IntrNoMem]>; 1006def int_loongarch_lasx_xbz_d : VecInt<[llvm_i32_ty], [llvm_v4i64_ty], 1007 [IntrNoMem]>; 1008def int_loongarch_lasx_xbz_v : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1009 [IntrNoMem]>; 1010 1011def int_loongarch_lasx_xbnz_v : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1012 [IntrNoMem]>; 1013def int_loongarch_lasx_xbnz_b : VecInt<[llvm_i32_ty], [llvm_v32i8_ty], 1014 [IntrNoMem]>; 1015def int_loongarch_lasx_xbnz_h : VecInt<[llvm_i32_ty], [llvm_v16i16_ty], 1016 [IntrNoMem]>; 1017def int_loongarch_lasx_xbnz_w : VecInt<[llvm_i32_ty], [llvm_v8i32_ty], 1018 [IntrNoMem]>; 1019def int_loongarch_lasx_xbnz_d : VecInt<[llvm_i32_ty], [llvm_v4i64_ty], 1020 [IntrNoMem]>; 1021 1022// LASX Float 1023 1024foreach inst = ["xvfadd_s", "xvfsub_s", "xvfmul_s", "xvfdiv_s", 1025 "xvfmax_s", "xvfmin_s", "xvfmaxa_s", "xvfmina_s"] in 1026 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], 1027 [llvm_v8f32_ty, llvm_v8f32_ty], 1028 [IntrNoMem]>; 1029foreach inst = ["xvfadd_d", "xvfsub_d", "xvfmul_d", "xvfdiv_d", 1030 "xvfmax_d", "xvfmin_d", "xvfmaxa_d", "xvfmina_d"] in 1031 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], 1032 [llvm_v4f64_ty, llvm_v4f64_ty], 1033 [IntrNoMem]>; 1034 1035foreach inst = ["xvfmadd_s", "xvfmsub_s", "xvfnmadd_s", "xvfnmsub_s"] in 1036 def int_loongarch_lasx_#inst 1037 : VecInt<[llvm_v8f32_ty], 1038 [llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty], 1039 [IntrNoMem]>; 1040foreach inst = ["xvfmadd_d", "xvfmsub_d", "xvfnmadd_d", "xvfnmsub_d"] in 1041 def int_loongarch_lasx_#inst 1042 : VecInt<[llvm_v4f64_ty], 1043 [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], 1044 [IntrNoMem]>; 1045 1046foreach inst = ["xvflogb_s", "xvfsqrt_s", "xvfrecip_s", "xvfrsqrt_s", "xvfrint_s", 1047 "xvfrintrne_s", "xvfrintrz_s", "xvfrintrp_s", "xvfrintrm_s"] in 1048 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty], 1049 [IntrNoMem]>; 1050foreach inst = ["xvflogb_d", "xvfsqrt_d", "xvfrecip_d", "xvfrsqrt_d", "xvfrint_d", 1051 "xvfrintrne_d", "xvfrintrz_d", "xvfrintrp_d", "xvfrintrm_d"] in 1052 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty], 1053 [IntrNoMem]>; 1054 1055foreach inst = ["xvfcvtl_s_h", "xvfcvth_s_h"] in 1056 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v16i16_ty], 1057 [IntrNoMem]>; 1058foreach inst = ["xvfcvtl_d_s", "xvfcvth_d_s"] in 1059 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v8f32_ty], 1060 [IntrNoMem]>; 1061 1062foreach inst = ["xvftintrne_w_s", "xvftintrz_w_s", "xvftintrp_w_s", "xvftintrm_w_s", 1063 "xvftint_w_s", "xvftintrz_wu_s", "xvftint_wu_s", "xvfclass_s"] in 1064 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], [llvm_v8f32_ty], 1065 [IntrNoMem]>; 1066foreach inst = ["xvftintrne_l_d", "xvftintrz_l_d", "xvftintrp_l_d", "xvftintrm_l_d", 1067 "xvftint_l_d", "xvftintrz_lu_d", "xvftint_lu_d", "xvfclass_d"] in 1068 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v4f64_ty], 1069 [IntrNoMem]>; 1070 1071foreach inst = ["xvftintrnel_l_s", "xvftintrneh_l_s", "xvftintrzl_l_s", 1072 "xvftintrzh_l_s", "xvftintrpl_l_s", "xvftintrph_l_s", 1073 "xvftintrml_l_s", "xvftintrmh_l_s", "xvftintl_l_s", 1074 "xvftinth_l_s"] in 1075 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], [llvm_v8f32_ty], 1076 [IntrNoMem]>; 1077 1078foreach inst = ["xvffint_s_w", "xvffint_s_wu"] in 1079 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8i32_ty], 1080 [IntrNoMem]>; 1081foreach inst = ["xvffint_d_l", "xvffint_d_lu"] in 1082 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4i64_ty], 1083 [IntrNoMem]>; 1084 1085foreach inst = ["xvffintl_d_w", "xvffinth_d_w"] in 1086 def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v8i32_ty], 1087 [IntrNoMem]>; 1088 1089foreach inst = ["xvffint_s_l"] in 1090 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], 1091 [llvm_v4i64_ty, llvm_v4i64_ty], 1092 [IntrNoMem]>; 1093foreach inst = ["xvftintrne_w_d", "xvftintrz_w_d", "xvftintrp_w_d", "xvftintrm_w_d", 1094 "xvftint_w_d"] in 1095 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 1096 [llvm_v4f64_ty, llvm_v4f64_ty], 1097 [IntrNoMem]>; 1098 1099foreach inst = ["xvfcvt_h_s"] in 1100 def int_loongarch_lasx_#inst : VecInt<[llvm_v16i16_ty], 1101 [llvm_v8f32_ty, llvm_v8f32_ty], 1102 [IntrNoMem]>; 1103foreach inst = ["xvfcvt_s_d"] in 1104 def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], 1105 [llvm_v4f64_ty, llvm_v4f64_ty], 1106 [IntrNoMem]>; 1107 1108foreach inst = ["xvfcmp_caf_s", "xvfcmp_cun_s", "xvfcmp_ceq_s", "xvfcmp_cueq_s", 1109 "xvfcmp_clt_s", "xvfcmp_cult_s", "xvfcmp_cle_s", "xvfcmp_cule_s", 1110 "xvfcmp_cne_s", "xvfcmp_cor_s", "xvfcmp_cune_s", 1111 "xvfcmp_saf_s", "xvfcmp_sun_s", "xvfcmp_seq_s", "xvfcmp_sueq_s", 1112 "xvfcmp_slt_s", "xvfcmp_sult_s", "xvfcmp_sle_s", "xvfcmp_sule_s", 1113 "xvfcmp_sne_s", "xvfcmp_sor_s", "xvfcmp_sune_s"] in 1114 def int_loongarch_lasx_#inst : VecInt<[llvm_v8i32_ty], 1115 [llvm_v8f32_ty, llvm_v8f32_ty], 1116 [IntrNoMem]>; 1117foreach inst = ["xvfcmp_caf_d", "xvfcmp_cun_d", "xvfcmp_ceq_d", "xvfcmp_cueq_d", 1118 "xvfcmp_clt_d", "xvfcmp_cult_d", "xvfcmp_cle_d", "xvfcmp_cule_d", 1119 "xvfcmp_cne_d", "xvfcmp_cor_d", "xvfcmp_cune_d", 1120 "xvfcmp_saf_d", "xvfcmp_sun_d", "xvfcmp_seq_d", "xvfcmp_sueq_d", 1121 "xvfcmp_slt_d", "xvfcmp_sult_d", "xvfcmp_sle_d", "xvfcmp_sule_d", 1122 "xvfcmp_sne_d", "xvfcmp_sor_d", "xvfcmp_sune_d"] in 1123 def int_loongarch_lasx_#inst : VecInt<[llvm_v4i64_ty], 1124 [llvm_v4f64_ty, llvm_v4f64_ty], 1125 [IntrNoMem]>; 1126 1127def int_loongarch_lasx_xvpickve_w_f 1128 : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_i32_ty], 1129 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1130def int_loongarch_lasx_xvpickve_d_f 1131 : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_i32_ty], 1132 [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1133 1134// LASX load/store 1135def int_loongarch_lasx_xvld 1136 : VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty], 1137 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1138def int_loongarch_lasx_xvldx 1139 : VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i64_ty], 1140 [IntrReadMem, IntrArgMemOnly]>; 1141def int_loongarch_lasx_xvldrepl_b 1142 : VecInt<[llvm_v32i8_ty], [llvm_ptr_ty, llvm_i32_ty], 1143 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1144def int_loongarch_lasx_xvldrepl_h 1145 : VecInt<[llvm_v16i16_ty], [llvm_ptr_ty, llvm_i32_ty], 1146 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1147def int_loongarch_lasx_xvldrepl_w 1148 : VecInt<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_i32_ty], 1149 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1150def int_loongarch_lasx_xvldrepl_d 1151 : VecInt<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_i32_ty], 1152 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; 1153 1154def int_loongarch_lasx_xvst 1155 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty], 1156 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>]>; 1157def int_loongarch_lasx_xvstx 1158 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i64_ty], 1159 [IntrWriteMem, IntrArgMemOnly]>; 1160def int_loongarch_lasx_xvstelm_b 1161 : VecInt<[], [llvm_v32i8_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1162 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1163def int_loongarch_lasx_xvstelm_h 1164 : VecInt<[], [llvm_v16i16_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1165 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1166def int_loongarch_lasx_xvstelm_w 1167 : VecInt<[], [llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1168 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1169def int_loongarch_lasx_xvstelm_d 1170 : VecInt<[], [llvm_v4i64_ty, llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 1171 [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1172} // TargetPrefix = "loongarch" 1173