1 /******************************************************************************
2 *
3 * Copyright 1999-2012 Broadcom Corporation
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18
19 /******************************************************************************
20 *
21 * This file contains function of the HCIC unit to format and send HCI
22 * commands.
23 *
24 ******************************************************************************/
25
26 #include <base/functional/bind.h>
27 #include <base/functional/callback_forward.h>
28 #include <string.h>
29
30 #include "device/include/esco_parameters.h"
31 #include "hcidefs.h"
32 #include "hcimsgs.h"
33 #include "internal_include/bt_target.h"
34 #include "main/shim/acl_api.h"
35 #include "osi/include/allocator.h"
36 #include "stack/include/bt_dev_class.h"
37 #include "stack/include/bt_hdr.h"
38 #include "stack/include/bt_lap.h"
39 #include "stack/include/bt_octets.h"
40 #include "stack/include/bt_types.h"
41 #include "stack/include/btu_hcif.h"
42 #include "types/raw_address.h"
43
44 /* Message by message.... */
45
46 #define HCIC_PARAM_SIZE_INQUIRY 5
47
48 #define HCIC_INQ_INQ_LAP_OFF 0
49 #define HCIC_INQ_DUR_OFF 3
50 #define HCIC_INQ_RSP_CNT_OFF 4
51
52 /* Periodic Inquiry Mode */
53 #define HCIC_PARAM_SIZE_PER_INQ_MODE 9
54
55 #define HCI_PER_INQ_MAX_INTRVL_OFF 0
56 #define HCI_PER_INQ_MIN_INTRVL_OFF 2
57 #define HCI_PER_INQ_INQ_LAP_OFF 4
58 #define HCI_PER_INQ_DURATION_OFF 7
59 #define HCI_PER_INQ_RSP_CNT_OFF 8
60 /* Periodic Inquiry Mode */
61
62 /* Exit Periodic Inquiry Mode */
63 #define HCIC_PARAM_SIZE_EXIT_PER_INQ 0
64
65 /* Create Connection */
66 #define HCIC_PARAM_SIZE_CREATE_CONN 13
67
68 #define HCIC_CR_CONN_BD_ADDR_OFF 0
69 #define HCIC_CR_CONN_PKT_TYPES_OFF 6
70 #define HCIC_CR_CONN_REP_MODE_OFF 8
71 #define HCIC_CR_CONN_PAGE_SCAN_MODE_OFF 9
72 #define HCIC_CR_CONN_CLK_OFF_OFF 10
73 #define HCIC_CR_CONN_ALLOW_SWITCH_OFF 12
74 /* Create Connection */
75
76 /* Disconnect */
77 #define HCIC_PARAM_SIZE_DISCONNECT 3
78
79 #define HCI_DISC_HANDLE_OFF 0
80 #define HCI_DISC_REASON_OFF 2
81 /* Disconnect */
82
83 /* Add SCO Connection */
84 #define HCIC_PARAM_SIZE_ADD_SCO_CONN 4
85
86 #define HCI_ADD_SCO_HANDLE_OFF 0
87 #define HCI_ADD_SCO_PACKET_TYPES_OFF 2
88 /* Add SCO Connection */
89
90 /* Create Connection Cancel */
91 #define HCIC_PARAM_SIZE_CREATE_CONN_CANCEL 6
92
93 #define HCIC_CR_CONN_CANCEL_BD_ADDR_OFF 0
94 /* Create Connection Cancel */
95
96 /* Accept Connection Request */
97 #define HCIC_PARAM_SIZE_ACCEPT_CONN 7
98
99 #define HCI_ACC_CONN_BD_ADDR_OFF 0
100 #define HCI_ACC_CONN_ROLE_OFF 6
101 /* Accept Connection Request */
102
103 /* Reject Connection Request */
104 #define HCIC_PARAM_SIZE_REJECT_CONN 7
105
106 #define HCI_REJ_CONN_BD_ADDR_OFF 0
107 #define HCI_REJ_CONN_REASON_OFF 6
108 /* Reject Connection Request */
109
110 /* Link Key Request Reply */
111 #define HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY 22
112
113 #define HCI_LINK_KEY_REPLY_BD_ADDR_OFF 0
114 #define HCI_LINK_KEY_REPLY_LINK_KEY_OFF 6
115 /* Link Key Request Reply */
116
117 /* Link Key Request Neg Reply */
118 #define HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY 6
119
120 #define HCI_LINK_KEY_NEG_REP_BD_ADR_OFF 0
121 /* Link Key Request Neg Reply */
122
123 /* PIN Code Request Reply */
124 #define HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY 23
125
126 #define HCI_PIN_CODE_REPLY_BD_ADDR_OFF 0
127 #define HCI_PIN_CODE_REPLY_PIN_LEN_OFF 6
128 #define HCI_PIN_CODE_REPLY_PIN_CODE_OFF 7
129 /* PIN Code Request Reply */
130
131 /* Link Key Request Neg Reply */
132 #define HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY 6
133
134 #define HCI_PIN_CODE_NEG_REP_BD_ADR_OFF 0
135 /* Link Key Request Neg Reply */
136
137 /* Change Connection Type */
138 #define HCIC_PARAM_SIZE_CHANGE_CONN_TYPE 4
139
140 #define HCI_CHNG_PKT_TYPE_HANDLE_OFF 0
141 #define HCI_CHNG_PKT_TYPE_PKT_TYPE_OFF 2
142 /* Change Connection Type */
143
144 #define HCIC_PARAM_SIZE_CMD_HANDLE 2
145
146 #define HCI_CMD_HANDLE_HANDLE_OFF 0
147
148 /* Set Connection Encryption */
149 #define HCIC_PARAM_SIZE_SET_CONN_ENCRYPT 3
150
151 #define HCI_SET_ENCRYPT_HANDLE_OFF 0
152 #define HCI_SET_ENCRYPT_ENABLE_OFF 2
153 /* Set Connection Encryption */
154
155 /* Remote Name Request */
156 #define HCIC_PARAM_SIZE_RMT_NAME_REQ 10
157
158 #define HCI_RMT_NAME_BD_ADDR_OFF 0
159 #define HCI_RMT_NAME_REP_MODE_OFF 6
160 #define HCI_RMT_NAME_PAGE_SCAN_MODE_OFF 7
161 #define HCI_RMT_NAME_CLK_OFF_OFF 8
162 /* Remote Name Request */
163
164 /* Remote Name Request Cancel */
165 #define HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL 6
166
167 #define HCI_RMT_NAME_CANCEL_BD_ADDR_OFF 0
168 /* Remote Name Request Cancel */
169
170 /* Remote Extended Features */
171 #define HCIC_PARAM_SIZE_RMT_EXT_FEATURES 3
172
173 #define HCI_RMT_EXT_FEATURES_HANDLE_OFF 0
174 #define HCI_RMT_EXT_FEATURES_PAGE_NUM_OFF 2
175 /* Remote Extended Features */
176
177 #define HCIC_PARAM_SIZE_SETUP_ESCO 17
178
179 #define HCI_SETUP_ESCO_HANDLE_OFF 0
180 #define HCI_SETUP_ESCO_TX_BW_OFF 2
181 #define HCI_SETUP_ESCO_RX_BW_OFF 6
182 #define HCI_SETUP_ESCO_MAX_LAT_OFF 10
183 #define HCI_SETUP_ESCO_VOICE_OFF 12
184 #define HCI_SETUP_ESCO_RETRAN_EFF_OFF 14
185 #define HCI_SETUP_ESCO_PKT_TYPES_OFF 15
186
187 #define HCIC_PARAM_SIZE_ACCEPT_ESCO 21
188
189 #define HCI_ACCEPT_ESCO_BDADDR_OFF 0
190 #define HCI_ACCEPT_ESCO_TX_BW_OFF 6
191 #define HCI_ACCEPT_ESCO_RX_BW_OFF 10
192 #define HCI_ACCEPT_ESCO_MAX_LAT_OFF 14
193 #define HCI_ACCEPT_ESCO_VOICE_OFF 16
194 #define HCI_ACCEPT_ESCO_RETRAN_EFF_OFF 18
195 #define HCI_ACCEPT_ESCO_PKT_TYPES_OFF 19
196
197 #define HCIC_PARAM_SIZE_REJECT_ESCO 7
198
199 #define HCI_REJECT_ESCO_BDADDR_OFF 0
200 #define HCI_REJECT_ESCO_REASON_OFF 6
201
202 /* Hold Mode */
203 #define HCIC_PARAM_SIZE_HOLD_MODE 6
204
205 #define HCI_HOLD_MODE_HANDLE_OFF 0
206 #define HCI_HOLD_MODE_MAX_PER_OFF 2
207 #define HCI_HOLD_MODE_MIN_PER_OFF 4
208 /* Hold Mode */
209
210 /* Sniff Mode */
211 #define HCIC_PARAM_SIZE_SNIFF_MODE 10
212
213 #define HCI_SNIFF_MODE_HANDLE_OFF 0
214 #define HCI_SNIFF_MODE_MAX_PER_OFF 2
215 #define HCI_SNIFF_MODE_MIN_PER_OFF 4
216 #define HCI_SNIFF_MODE_ATTEMPT_OFF 6
217 #define HCI_SNIFF_MODE_TIMEOUT_OFF 8
218 /* Sniff Mode */
219
220 /* Park Mode */
221 #define HCIC_PARAM_SIZE_PARK_MODE 6
222
223 #define HCI_PARK_MODE_HANDLE_OFF 0
224 #define HCI_PARK_MODE_MAX_PER_OFF 2
225 #define HCI_PARK_MODE_MIN_PER_OFF 4
226 /* Park Mode */
227
228 /* QoS Setup */
229 #define HCIC_PARAM_SIZE_QOS_SETUP 20
230
231 #define HCI_QOS_HANDLE_OFF 0
232 #define HCI_QOS_FLAGS_OFF 2
233 #define HCI_QOS_SERVICE_TYPE_OFF 3
234 #define HCI_QOS_TOKEN_RATE_OFF 4
235 #define HCI_QOS_PEAK_BANDWIDTH_OFF 8
236 #define HCI_QOS_LATENCY_OFF 12
237 #define HCI_QOS_DELAY_VAR_OFF 16
238 /* QoS Setup */
239
240 #define HCIC_PARAM_SIZE_SWITCH_ROLE 7
241
242 #define HCI_SWITCH_BD_ADDR_OFF 0
243 #define HCI_SWITCH_ROLE_OFF 6
244 /* Switch Role Request */
245
246 /* Write Policy Settings */
247 #define HCIC_PARAM_SIZE_WRITE_POLICY_SET 4
248
249 #define HCI_WRITE_POLICY_HANDLE_OFF 0
250 #define HCI_WRITE_POLICY_SETTINGS_OFF 2
251 /* Write Policy Settings */
252
253 /* Write Default Policy Settings */
254 #define HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET 2
255
256 #define HCI_WRITE_DEF_POLICY_SETTINGS_OFF 0
257 /* Write Default Policy Settings */
258
259 #define HCIC_PARAM_SIZE_SNIFF_SUB_RATE 8
260
261 #define HCI_SNIFF_SUB_RATE_HANDLE_OFF 0
262 #define HCI_SNIFF_SUB_RATE_MAX_LAT_OFF 2
263 #define HCI_SNIFF_SUB_RATE_MIN_REM_LAT_OFF 4
264 #define HCI_SNIFF_SUB_RATE_MIN_LOC_LAT_OFF 6
265 /* Sniff Subrating */
266
267 /* Extended Inquiry Response */
268 #define HCIC_PARAM_SIZE_EXT_INQ_RESP 241
269
270 #define HCIC_EXT_INQ_RESP_FEC_OFF 0
271 #define HCIC_EXT_INQ_RESP_RESPONSE 1
272 /* IO Capabilities Response */
273 #define HCIC_PARAM_SIZE_IO_CAP_RESP 9
274
275 #define HCI_IO_CAP_BD_ADDR_OFF 0
276 #define HCI_IO_CAPABILITY_OFF 6
277 #define HCI_IO_CAP_OOB_DATA_OFF 7
278 #define HCI_IO_CAP_AUTH_REQ_OFF 8
279
280 /* IO Capabilities Req Neg Reply */
281 #define HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY 7
282
283 #define HCI_IO_CAP_NR_BD_ADDR_OFF 0
284 #define HCI_IO_CAP_NR_ERR_CODE 6
285
286 /* Read Local OOB Data */
287 #define HCIC_PARAM_SIZE_R_LOCAL_OOB 0
288
289 /* Read Local OOB Extended Data */
290 #define HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED 0
291
292 #define HCIC_PARAM_SIZE_UCONF_REPLY 6
293
294 #define HCI_USER_CONF_BD_ADDR_OFF 0
295
296 #define HCIC_PARAM_SIZE_U_PKEY_REPLY 10
297
298 #define HCI_USER_PASSKEY_BD_ADDR_OFF 0
299 #define HCI_USER_PASSKEY_VALUE_OFF 6
300
301 #define HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY 6
302
303 #define HCI_USER_PASSKEY_NEG_BD_ADDR_OFF 0
304
305 /* Remote OOB Data Request Reply */
306 #define HCIC_PARAM_SIZE_REM_OOB_REPLY 38
307
308 #define HCI_REM_OOB_DATA_BD_ADDR_OFF 0
309 #define HCI_REM_OOB_DATA_C_OFF 6
310 #define HCI_REM_OOB_DATA_R_OFF 22
311
312 /* Remote OOB Data Request Negative Reply */
313 #define HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY 6
314
315 #define HCI_REM_OOB_DATA_NEG_BD_ADDR_OFF 0
316
317 /* Read Tx Power Level */
318 #define HCIC_PARAM_SIZE_R_TX_POWER 0
319
320 /* Read Default Erroneous Data Reporting */
321 #define HCIC_PARAM_SIZE_R_ERR_DATA_RPT 0
322
323 #define HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF 7
324
325 #define HCI_SEND_KEYPRESS_NOTIF_BD_ADDR_OFF 0
326 #define HCI_SEND_KEYPRESS_NOTIF_NOTIF_OFF 6
327
328 /**** end of Simple Pairing Commands ****/
329
330 #define HCIC_PARAM_SIZE_SET_EVT_FILTER 9
331
332 #define HCI_FILT_COND_FILT_TYPE_OFF 0
333 #define HCI_FILT_COND_COND_TYPE_OFF 1
334 #define HCI_FILT_COND_FILT_OFF 2
335 /* Set Event Filter */
336
337 /* Delete Stored Key */
338 #define HCIC_PARAM_SIZE_DELETE_STORED_KEY 7
339
340 #define HCI_DELETE_KEY_BD_ADDR_OFF 0
341 #define HCI_DELETE_KEY_ALL_FLAG_OFF 6
342 /* Delete Stored Key */
343
344 #define HCIC_PARAM_SIZE_READ_CMD 0
345
346 #define HCIC_PARAM_SIZE_WRITE_PARAM1 1
347
348 #define HCIC_WRITE_PARAM1_PARAM_OFF 0
349
350 #define HCIC_PARAM_SIZE_WRITE_PARAM2 2
351
352 #define HCIC_WRITE_PARAM2_PARAM_OFF 0
353
354 #define HCIC_PARAM_SIZE_WRITE_PARAM3 3
355
356 #define HCIC_WRITE_PARAM3_PARAM_OFF 0
357
358 #define HCIC_PARAM_SIZE_SET_AFH_CHANNELS 10
359
360 #define HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN 59
361 #define HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN 63
362
363 #define HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG 4
364
365 #define HCI_SCAN_CFG_INTERVAL_OFF 0
366 #define HCI_SCAN_CFG_WINDOW_OFF 2
367 /* Write Page Scan Activity */
368
369 /* Write Inquiry Scan Activity */
370 #define HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG 4
371
372 #define HCI_SCAN_CFG_INTERVAL_OFF 0
373 #define HCI_SCAN_CFG_WINDOW_OFF 2
374 /* Write Inquiry Scan Activity */
375
376 /* Host Controller to Host flow control */
377 #define HCI_HOST_FLOW_CTRL_OFF 0
378 #define HCI_HOST_FLOW_CTRL_ACL_ON 1
379 #define HCI_HOST_FLOW_CTRL_SCO_ON 2
380 #define HCI_HOST_FLOW_CTRL_BOTH_ON 3
381
382 #define HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT 4
383
384 #define HCI_FLUSH_TOUT_HANDLE_OFF 0
385 #define HCI_FLUSH_TOUT_TOUT_OFF 2
386
387 #define HCIC_PARAM_SIZE_READ_TX_POWER 3
388
389 #define HCI_READ_TX_POWER_HANDLE_OFF 0
390 #define HCI_READ_TX_POWER_TYPE_OFF 2
391
392 /* Read transmit power level parameter */
393 #define HCI_READ_CURRENT 0x00
394 #define HCI_READ_MAXIMUM 0x01
395
396 #define HCIC_PARAM_SIZE_NUM_PKTS_DONE_SIZE sizeof(btmsg_hcic_num_pkts_done_t)
397
398 #define MAX_DATA_HANDLES 10
399
400 #define HCI_PKTS_DONE_NUM_HANDLES_OFF 0
401 #define HCI_PKTS_DONE_HANDLE_OFF 1
402 #define HCI_PKTS_DONE_NUM_PKTS_OFF 3
403
404 #define HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT 4
405
406 #define HCI_LINK_SUPER_TOUT_HANDLE_OFF 0
407 #define HCI_LINK_SUPER_TOUT_TOUT_OFF 2
408 /* Write Link Supervision Timeout */
409
410 #define MAX_IAC_LAPS 0x40
411
412 #define HCI_WRITE_IAC_LAP_NUM_OFF 0
413 #define HCI_WRITE_IAC_LAP_LAP_OFF 1
414 /* Write Current IAC LAP */
415
416 #define HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH 3
417
418 /*******************************************************************************
419 * BLE Commands
420 * Note: "local_controller_id" is for transport, not counted in HCI
421 * message size
422 ******************************************************************************/
423 #define HCIC_BLE_RAND_DI_SIZE 8
424 #define HCIC_BLE_IRK_SIZE 16
425
426 #define HCIC_PARAM_SIZE_SET_USED_FEAT_CMD 8
427 #define HCIC_PARAM_SIZE_WRITE_RANDOM_ADDR_CMD 6
428 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_PARAMS 15
429 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_RSP 31
430 #define HCIC_PARAM_SIZE_WRITE_ADV_ENABLE 1
431 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_PARAM 7
432 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_ENABLE 2
433 #define HCIC_PARAM_SIZE_BLE_CREATE_LL_CONN 25
434 #define HCIC_PARAM_SIZE_BLE_CREATE_CONN_CANCEL 0
435 #define HCIC_PARAM_SIZE_CLEAR_ACCEPTLIST 0
436 #define HCIC_PARAM_SIZE_ADD_ACCEPTLIST 7
437 #define HCIC_PARAM_SIZE_REMOVE_ACCEPTLIST 7
438 #define HCIC_PARAM_SIZE_BLE_UPD_LL_CONN_PARAMS 14
439 #define HCIC_PARAM_SIZE_SET_HOST_CHNL_CLASS 5
440 #define HCIC_PARAM_SIZE_READ_CHNL_MAP 2
441 #define HCIC_PARAM_SIZE_BLE_READ_REMOTE_FEAT 2
442 #define HCIC_PARAM_SIZE_BLE_ENCRYPT 32
443 #define HCIC_PARAM_SIZE_WRITE_LE_HOST_SUPPORTED 2
444
445 #define HCIC_BLE_RAND_DI_SIZE 8
446 #define HCIC_BLE_ENCRYPT_KEY_SIZE 16
447 #define HCIC_PARAM_SIZE_BLE_START_ENC (4 + HCIC_BLE_RAND_DI_SIZE + HCIC_BLE_ENCRYPT_KEY_SIZE)
448 #define HCIC_PARAM_SIZE_LTK_REQ_REPLY (2 + HCIC_BLE_ENCRYPT_KEY_SIZE)
449 #define HCIC_PARAM_SIZE_LTK_REQ_NEG_REPLY 2
450 #define HCIC_BLE_CHNL_MAP_SIZE 5
451 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_DATA 31
452
453 #define HCIC_PARAM_SIZE_BLE_ADD_DEV_RESOLVING_LIST (7 + HCIC_BLE_IRK_SIZE * 2)
454 #define HCIC_PARAM_SIZE_BLE_RM_DEV_RESOLVING_LIST 7
455 #define HCIC_PARAM_SIZE_BLE_SET_PRIVACY_MODE 8
456 #define HCIC_PARAM_SIZE_BLE_CLEAR_RESOLVING_LIST 0
457 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVING_LIST_SIZE 0
458 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_PEER 7
459 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_LOCAL 7
460 #define HCIC_PARAM_SIZE_BLE_SET_ADDR_RESOLUTION_ENABLE 1
461 #define HCIC_PARAM_SIZE_BLE_SET_RAND_PRIV_ADDR_TIMEOUT 2
462
463 #define HCIC_PARAM_SIZE_BLE_READ_PHY 2
464 #define HCIC_PARAM_SIZE_BLE_SET_DEFAULT_PHY 3
465 #define HCIC_PARAM_SIZE_BLE_SET_PHY 7
466 #define HCIC_PARAM_SIZE_BLE_ENH_RX_TEST 3
467 #define HCIC_PARAM_SIZE_BLE_ENH_TX_TEST 4
468
469 #define HCIC_PARAM_SIZE_BLE_SET_DATA_LENGTH 6
470 #define HCIC_PARAM_SIZE_BLE_WRITE_EXTENDED_SCAN_PARAM 11
471
472 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_REPLY 14
473 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_NEG_REPLY 3
474
btsnd_hcic_disconnect(uint16_t handle,uint8_t reason)475 static void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) {
476 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
477 uint8_t* pp = (uint8_t*)(p + 1);
478
479 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT;
480 p->offset = 0;
481
482 UINT16_TO_STREAM(pp, HCI_DISCONNECT);
483 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT);
484 UINT16_TO_STREAM(pp, handle);
485 UINT8_TO_STREAM(pp, reason);
486
487 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
488 }
489
btsnd_hcic_add_SCO_conn(uint16_t handle,uint16_t packet_types)490 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) {
491 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
492 uint8_t* pp = (uint8_t*)(p + 1);
493
494 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN;
495 p->offset = 0;
496
497 UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION);
498 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN);
499
500 UINT16_TO_STREAM(pp, handle);
501 UINT16_TO_STREAM(pp, packet_types);
502
503 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
504 }
505
btsnd_hcic_create_conn_cancel(const RawAddress & dest)506 void btsnd_hcic_create_conn_cancel(const RawAddress& dest) {
507 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
508 uint8_t* pp = (uint8_t*)(p + 1);
509
510 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL;
511 p->offset = 0;
512
513 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL);
514 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL);
515
516 BDADDR_TO_STREAM(pp, dest);
517
518 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
519 }
520
btsnd_hcic_reject_conn(const RawAddress & dest,uint8_t reason)521 void btsnd_hcic_reject_conn(const RawAddress& dest, uint8_t reason) {
522 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
523 uint8_t* pp = (uint8_t*)(p + 1);
524
525 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN;
526 p->offset = 0;
527
528 UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST);
529 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN);
530
531 BDADDR_TO_STREAM(pp, dest);
532 UINT8_TO_STREAM(pp, reason);
533
534 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
535 }
536
btsnd_hcic_link_key_req_reply(const RawAddress & bd_addr,const LinkKey & link_key)537 void btsnd_hcic_link_key_req_reply(const RawAddress& bd_addr, const LinkKey& link_key) {
538 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
539 uint8_t* pp = (uint8_t*)(p + 1);
540
541 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY;
542 p->offset = 0;
543
544 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY);
545 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY);
546
547 BDADDR_TO_STREAM(pp, bd_addr);
548 ARRAY16_TO_STREAM(pp, link_key.data());
549
550 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
551 }
552
btsnd_hcic_link_key_neg_reply(const RawAddress & bd_addr)553 void btsnd_hcic_link_key_neg_reply(const RawAddress& bd_addr) {
554 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
555 uint8_t* pp = (uint8_t*)(p + 1);
556
557 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY;
558 p->offset = 0;
559
560 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY);
561 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY);
562
563 BDADDR_TO_STREAM(pp, bd_addr);
564
565 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
566 }
567
btsnd_hcic_pin_code_req_reply(const RawAddress & bd_addr,uint8_t pin_code_len,PIN_CODE pin_code)568 void btsnd_hcic_pin_code_req_reply(const RawAddress& bd_addr, uint8_t pin_code_len,
569 PIN_CODE pin_code) {
570 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
571 uint8_t* pp = (uint8_t*)(p + 1);
572 int i;
573
574 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY;
575 p->offset = 0;
576
577 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY);
578 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY);
579
580 BDADDR_TO_STREAM(pp, bd_addr);
581 UINT8_TO_STREAM(pp, pin_code_len);
582
583 for (i = 0; i < pin_code_len; i++) {
584 *pp++ = *pin_code++;
585 }
586
587 for (; i < PIN_CODE_LEN; i++) {
588 *pp++ = 0;
589 }
590
591 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
592 }
593
btsnd_hcic_pin_code_neg_reply(const RawAddress & bd_addr)594 void btsnd_hcic_pin_code_neg_reply(const RawAddress& bd_addr) {
595 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
596 uint8_t* pp = (uint8_t*)(p + 1);
597
598 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY;
599 p->offset = 0;
600
601 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY);
602 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY);
603
604 BDADDR_TO_STREAM(pp, bd_addr);
605
606 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
607 }
608
btsnd_hcic_change_conn_type(uint16_t handle,uint16_t packet_types)609 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) {
610 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
611 uint8_t* pp = (uint8_t*)(p + 1);
612
613 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE;
614 p->offset = 0;
615
616 UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE);
617 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE);
618
619 UINT16_TO_STREAM(pp, handle);
620 UINT16_TO_STREAM(pp, packet_types);
621
622 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
623 }
624
btsnd_hcic_auth_request(uint16_t handle)625 void btsnd_hcic_auth_request(uint16_t handle) {
626 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
627 uint8_t* pp = (uint8_t*)(p + 1);
628
629 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
630 p->offset = 0;
631
632 UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED);
633 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
634
635 UINT16_TO_STREAM(pp, handle);
636
637 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
638 }
639
btsnd_hcic_set_conn_encrypt(uint16_t handle,bool enable)640 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) {
641 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
642 uint8_t* pp = (uint8_t*)(p + 1);
643
644 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT;
645 p->offset = 0;
646
647 UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION);
648 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT);
649
650 UINT16_TO_STREAM(pp, handle);
651 UINT8_TO_STREAM(pp, enable);
652
653 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
654 }
655
btsnd_hcic_rmt_ext_features(uint16_t handle,uint8_t page_num)656 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) {
657 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
658 uint8_t* pp = (uint8_t*)(p + 1);
659
660 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES;
661 p->offset = 0;
662
663 UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES);
664 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES);
665
666 UINT16_TO_STREAM(pp, handle);
667 UINT8_TO_STREAM(pp, page_num);
668
669 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
670 }
671
btsnd_hcic_rmt_ver_req(uint16_t handle)672 void btsnd_hcic_rmt_ver_req(uint16_t handle) {
673 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
674 uint8_t* pp = (uint8_t*)(p + 1);
675
676 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
677 p->offset = 0;
678
679 UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO);
680 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
681
682 UINT16_TO_STREAM(pp, handle);
683
684 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
685 }
686
btsnd_hcic_read_rmt_clk_offset(uint16_t handle)687 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) {
688 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
689 uint8_t* pp = (uint8_t*)(p + 1);
690
691 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
692 p->offset = 0;
693
694 UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET);
695 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
696
697 UINT16_TO_STREAM(pp, handle);
698
699 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
700 }
701
btsnd_hcic_setup_esco_conn(uint16_t handle,uint32_t transmit_bandwidth,uint32_t receive_bandwidth,uint16_t max_latency,uint16_t voice,uint8_t retrans_effort,uint16_t packet_types)702 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth,
703 uint32_t receive_bandwidth, uint16_t max_latency, uint16_t voice,
704 uint8_t retrans_effort, uint16_t packet_types) {
705 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
706 uint8_t* pp = (uint8_t*)(p + 1);
707
708 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO;
709 p->offset = 0;
710
711 UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION);
712 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO);
713
714 UINT16_TO_STREAM(pp, handle);
715 UINT32_TO_STREAM(pp, transmit_bandwidth);
716 UINT32_TO_STREAM(pp, receive_bandwidth);
717 UINT16_TO_STREAM(pp, max_latency);
718 UINT16_TO_STREAM(pp, voice);
719 UINT8_TO_STREAM(pp, retrans_effort);
720 UINT16_TO_STREAM(pp, packet_types);
721
722 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
723 }
724
btsnd_hcic_accept_esco_conn(const RawAddress & bd_addr,uint32_t transmit_bandwidth,uint32_t receive_bandwidth,uint16_t max_latency,uint16_t content_fmt,uint8_t retrans_effort,uint16_t packet_types)725 void btsnd_hcic_accept_esco_conn(const RawAddress& bd_addr, uint32_t transmit_bandwidth,
726 uint32_t receive_bandwidth, uint16_t max_latency,
727 uint16_t content_fmt, uint8_t retrans_effort,
728 uint16_t packet_types) {
729 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
730 uint8_t* pp = (uint8_t*)(p + 1);
731
732 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO;
733 p->offset = 0;
734
735 UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION);
736 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO);
737
738 BDADDR_TO_STREAM(pp, bd_addr);
739 UINT32_TO_STREAM(pp, transmit_bandwidth);
740 UINT32_TO_STREAM(pp, receive_bandwidth);
741 UINT16_TO_STREAM(pp, max_latency);
742 UINT16_TO_STREAM(pp, content_fmt);
743 UINT8_TO_STREAM(pp, retrans_effort);
744 UINT16_TO_STREAM(pp, packet_types);
745
746 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
747 }
748
btsnd_hcic_reject_esco_conn(const RawAddress & bd_addr,uint8_t reason)749 void btsnd_hcic_reject_esco_conn(const RawAddress& bd_addr, uint8_t reason) {
750 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
751 uint8_t* pp = (uint8_t*)(p + 1);
752
753 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO;
754 p->offset = 0;
755
756 UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION);
757 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO);
758
759 BDADDR_TO_STREAM(pp, bd_addr);
760 UINT8_TO_STREAM(pp, reason);
761
762 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
763 }
764
btsnd_hcic_hold_mode(uint16_t handle,uint16_t max_hold_period,uint16_t min_hold_period)765 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period, uint16_t min_hold_period) {
766 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
767 uint8_t* pp = (uint8_t*)(p + 1);
768
769 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE;
770 p->offset = 0;
771
772 UINT16_TO_STREAM(pp, HCI_HOLD_MODE);
773 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE);
774
775 UINT16_TO_STREAM(pp, handle);
776 UINT16_TO_STREAM(pp, max_hold_period);
777 UINT16_TO_STREAM(pp, min_hold_period);
778
779 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
780 }
781
btsnd_hcic_sniff_mode(uint16_t handle,uint16_t max_sniff_period,uint16_t min_sniff_period,uint16_t sniff_attempt,uint16_t sniff_timeout)782 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period, uint16_t min_sniff_period,
783 uint16_t sniff_attempt, uint16_t sniff_timeout) {
784 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
785 uint8_t* pp = (uint8_t*)(p + 1);
786
787 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE;
788 p->offset = 0;
789
790 UINT16_TO_STREAM(pp, HCI_SNIFF_MODE);
791 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE);
792
793 UINT16_TO_STREAM(pp, handle);
794 UINT16_TO_STREAM(pp, max_sniff_period);
795 UINT16_TO_STREAM(pp, min_sniff_period);
796 UINT16_TO_STREAM(pp, sniff_attempt);
797 UINT16_TO_STREAM(pp, sniff_timeout);
798
799 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
800 }
801
btsnd_hcic_exit_sniff_mode(uint16_t handle)802 void btsnd_hcic_exit_sniff_mode(uint16_t handle) {
803 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
804 uint8_t* pp = (uint8_t*)(p + 1);
805
806 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
807 p->offset = 0;
808
809 UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE);
810 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
811
812 UINT16_TO_STREAM(pp, handle);
813
814 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
815 }
816
btsnd_hcic_park_mode(uint16_t handle,uint16_t beacon_max_interval,uint16_t beacon_min_interval)817 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval,
818 uint16_t beacon_min_interval) {
819 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
820 uint8_t* pp = (uint8_t*)(p + 1);
821
822 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE;
823 p->offset = 0;
824
825 UINT16_TO_STREAM(pp, HCI_PARK_MODE);
826 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE);
827
828 UINT16_TO_STREAM(pp, handle);
829 UINT16_TO_STREAM(pp, beacon_max_interval);
830 UINT16_TO_STREAM(pp, beacon_min_interval);
831
832 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
833 }
834
btsnd_hcic_exit_park_mode(uint16_t handle)835 void btsnd_hcic_exit_park_mode(uint16_t handle) {
836 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
837 uint8_t* pp = (uint8_t*)(p + 1);
838
839 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
840 p->offset = 0;
841
842 UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE);
843 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
844
845 UINT16_TO_STREAM(pp, handle);
846
847 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
848 }
849
btsnd_hcic_switch_role(const RawAddress & bd_addr,uint8_t role)850 static void btsnd_hcic_switch_role(const RawAddress& bd_addr, uint8_t role) {
851 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
852 uint8_t* pp = (uint8_t*)(p + 1);
853
854 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE;
855 p->offset = 0;
856
857 UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE);
858 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE);
859
860 BDADDR_TO_STREAM(pp, bd_addr);
861 UINT8_TO_STREAM(pp, role);
862
863 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
864 }
865
btsnd_hcic_write_policy_set(uint16_t handle,uint16_t settings)866 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) {
867 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
868 uint8_t* pp = (uint8_t*)(p + 1);
869
870 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET;
871 p->offset = 0;
872 UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS);
873 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET);
874
875 UINT16_TO_STREAM(pp, handle);
876 UINT16_TO_STREAM(pp, settings);
877
878 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
879 }
880
btsnd_hcic_write_def_policy_set(uint16_t settings)881 void btsnd_hcic_write_def_policy_set(uint16_t settings) {
882 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
883 uint8_t* pp = (uint8_t*)(p + 1);
884
885 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET;
886 p->offset = 0;
887 UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS);
888 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET);
889
890 UINT16_TO_STREAM(pp, settings);
891
892 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
893 }
894
btsnd_hcic_set_event_filter(uint8_t filt_type,uint8_t filt_cond_type,uint8_t * filt_cond,uint8_t filt_cond_len)895 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type, uint8_t* filt_cond,
896 uint8_t filt_cond_len) {
897 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
898 uint8_t* pp = (uint8_t*)(p + 1);
899
900 p->offset = 0;
901
902 UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER);
903
904 if (filt_type) {
905 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len);
906 UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len));
907
908 UINT8_TO_STREAM(pp, filt_type);
909 UINT8_TO_STREAM(pp, filt_cond_type);
910
911 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) {
912 DEVCLASS_TO_STREAM(pp, filt_cond);
913 filt_cond += kDevClassLength;
914 DEVCLASS_TO_STREAM(pp, filt_cond);
915 filt_cond += kDevClassLength;
916
917 filt_cond_len -= (2 * kDevClassLength);
918 } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) {
919 BDADDR_TO_STREAM(pp, *((RawAddress*)filt_cond));
920 filt_cond += BD_ADDR_LEN;
921
922 filt_cond_len -= BD_ADDR_LEN;
923 }
924
925 if (filt_cond_len) {
926 ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len);
927 }
928 } else {
929 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1);
930 UINT8_TO_STREAM(pp, 1);
931
932 UINT8_TO_STREAM(pp, filt_type);
933 }
934
935 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
936 }
937
btsnd_hcic_write_pin_type(uint8_t type)938 void btsnd_hcic_write_pin_type(uint8_t type) {
939 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
940 uint8_t* pp = (uint8_t*)(p + 1);
941
942 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
943 p->offset = 0;
944
945 UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE);
946 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
947
948 UINT8_TO_STREAM(pp, type);
949
950 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
951 }
952
btsnd_hcic_delete_stored_key(const RawAddress & bd_addr,bool delete_all_flag)953 void btsnd_hcic_delete_stored_key(const RawAddress& bd_addr, bool delete_all_flag) {
954 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
955 uint8_t* pp = (uint8_t*)(p + 1);
956
957 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY;
958 p->offset = 0;
959
960 UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY);
961 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY);
962
963 BDADDR_TO_STREAM(pp, bd_addr);
964 UINT8_TO_STREAM(pp, delete_all_flag);
965
966 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
967 }
968
btsnd_hcic_read_name(void)969 void btsnd_hcic_read_name(void) {
970 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
971 uint8_t* pp = (uint8_t*)(p + 1);
972
973 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
974 p->offset = 0;
975
976 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME);
977 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
978
979 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
980 }
981
btsnd_hcic_write_page_tout(uint16_t timeout)982 void btsnd_hcic_write_page_tout(uint16_t timeout) {
983 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
984 uint8_t* pp = (uint8_t*)(p + 1);
985
986 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
987 p->offset = 0;
988
989 UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT);
990 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
991
992 UINT16_TO_STREAM(pp, timeout);
993
994 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
995 }
996
btsnd_hcic_write_scan_enable(uint8_t flag)997 void btsnd_hcic_write_scan_enable(uint8_t flag) {
998 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
999 uint8_t* pp = (uint8_t*)(p + 1);
1000
1001 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1002 p->offset = 0;
1003
1004 UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE);
1005 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1006
1007 UINT8_TO_STREAM(pp, flag);
1008
1009 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1010 }
1011
btsnd_hcic_write_pagescan_cfg(uint16_t interval,uint16_t window)1012 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) {
1013 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1014 uint8_t* pp = (uint8_t*)(p + 1);
1015
1016 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG;
1017 p->offset = 0;
1018
1019 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG);
1020 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG);
1021
1022 UINT16_TO_STREAM(pp, interval);
1023 UINT16_TO_STREAM(pp, window);
1024
1025 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1026 }
1027
btsnd_hcic_write_inqscan_cfg(uint16_t interval,uint16_t window)1028 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) {
1029 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1030 uint8_t* pp = (uint8_t*)(p + 1);
1031
1032 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG;
1033 p->offset = 0;
1034
1035 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG);
1036 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG);
1037
1038 UINT16_TO_STREAM(pp, interval);
1039 UINT16_TO_STREAM(pp, window);
1040
1041 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1042 }
1043
btsnd_hcic_write_auth_enable(uint8_t flag)1044 void btsnd_hcic_write_auth_enable(uint8_t flag) {
1045 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1046 uint8_t* pp = (uint8_t*)(p + 1);
1047
1048 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1049 p->offset = 0;
1050
1051 UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE);
1052 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1053
1054 UINT8_TO_STREAM(pp, flag);
1055
1056 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1057 }
1058
btsnd_hcic_write_dev_class(DEV_CLASS dev_class)1059 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) {
1060 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1061 uint8_t* pp = (uint8_t*)(p + 1);
1062
1063 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3;
1064 p->offset = 0;
1065
1066 UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE);
1067 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3);
1068
1069 DEVCLASS_TO_STREAM(pp, dev_class);
1070
1071 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1072 }
1073
btsnd_hcic_write_voice_settings(uint16_t flags)1074 void btsnd_hcic_write_voice_settings(uint16_t flags) {
1075 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1076 uint8_t* pp = (uint8_t*)(p + 1);
1077
1078 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
1079 p->offset = 0;
1080
1081 UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS);
1082 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
1083
1084 UINT16_TO_STREAM(pp, flags);
1085
1086 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1087 }
1088
btsnd_hcic_write_auto_flush_tout(uint16_t handle,uint16_t tout)1089 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) {
1090 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1091 uint8_t* pp = (uint8_t*)(p + 1);
1092
1093 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT;
1094 p->offset = 0;
1095
1096 UINT16_TO_STREAM(pp, HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
1097 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
1098
1099 UINT16_TO_STREAM(pp, handle);
1100 UINT16_TO_STREAM(pp, tout);
1101
1102 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1103 }
1104
btsnd_hcic_read_tx_power(uint16_t handle,uint8_t type)1105 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) {
1106 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1107 uint8_t* pp = (uint8_t*)(p + 1);
1108
1109 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER;
1110 p->offset = 0;
1111
1112 UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL);
1113 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER);
1114
1115 UINT16_TO_STREAM(pp, handle);
1116 UINT8_TO_STREAM(pp, type);
1117
1118 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1119 }
1120
btsnd_hcic_write_link_super_tout(uint16_t handle,uint16_t timeout)1121 void btsnd_hcic_write_link_super_tout(uint16_t handle, uint16_t timeout) {
1122 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1123 uint8_t* pp = (uint8_t*)(p + 1);
1124
1125 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT;
1126 p->offset = 0;
1127
1128 UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT);
1129 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT);
1130
1131 UINT16_TO_STREAM(pp, handle);
1132 UINT16_TO_STREAM(pp, timeout);
1133
1134 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1135 }
1136
btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac,LAP * const iac_lap)1137 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) {
1138 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1139 uint8_t* pp = (uint8_t*)(p + 1);
1140
1141 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac);
1142 p->offset = 0;
1143
1144 UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP);
1145 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE);
1146
1147 UINT8_TO_STREAM(pp, num_cur_iac);
1148
1149 for (int i = 0; i < num_cur_iac; i++) {
1150 LAP_TO_STREAM(pp, iac_lap[i]);
1151 }
1152
1153 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1154 }
1155
1156 /******************************************
1157 * Lisbon Features
1158 ******************************************/
btsnd_hcic_sniff_sub_rate(uint16_t handle,uint16_t max_lat,uint16_t min_remote_lat,uint16_t min_local_lat)1159 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat, uint16_t min_remote_lat,
1160 uint16_t min_local_lat) {
1161 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1162 uint8_t* pp = (uint8_t*)(p + 1);
1163
1164 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE;
1165 p->offset = 0;
1166
1167 UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE);
1168 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE);
1169
1170 UINT16_TO_STREAM(pp, handle);
1171 UINT16_TO_STREAM(pp, max_lat);
1172 UINT16_TO_STREAM(pp, min_remote_lat);
1173 UINT16_TO_STREAM(pp, min_local_lat);
1174
1175 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1176 }
1177
1178 /**** Extended Inquiry Response Commands ****/
btsnd_hcic_write_ext_inquiry_response(void * buffer,uint8_t fec_req)1179 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) {
1180 BT_HDR* p = (BT_HDR*)buffer;
1181 uint8_t* pp = (uint8_t*)(p + 1);
1182
1183 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP;
1184 p->offset = 0;
1185
1186 UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE);
1187 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP);
1188
1189 UINT8_TO_STREAM(pp, fec_req);
1190
1191 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1192 }
1193
btsnd_hcic_io_cap_req_reply(const RawAddress & bd_addr,uint8_t capability,uint8_t oob_present,uint8_t auth_req)1194 void btsnd_hcic_io_cap_req_reply(const RawAddress& bd_addr, uint8_t capability, uint8_t oob_present,
1195 uint8_t auth_req) {
1196 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1197 uint8_t* pp = (uint8_t*)(p + 1);
1198
1199 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP;
1200 p->offset = 0;
1201
1202 UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY);
1203 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP);
1204
1205 BDADDR_TO_STREAM(pp, bd_addr);
1206 UINT8_TO_STREAM(pp, capability);
1207 UINT8_TO_STREAM(pp, oob_present);
1208 UINT8_TO_STREAM(pp, auth_req);
1209
1210 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1211 }
1212
btsnd_hcic_enhanced_set_up_synchronous_connection(uint16_t conn_handle,enh_esco_params_t * p_params)1213 void btsnd_hcic_enhanced_set_up_synchronous_connection(uint16_t conn_handle,
1214 enh_esco_params_t* p_params) {
1215 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1216 uint8_t* pp = (uint8_t*)(p + 1);
1217
1218 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN;
1219 p->offset = 0;
1220
1221 UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION);
1222 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN);
1223
1224 UINT16_TO_STREAM(pp, conn_handle);
1225 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1226 UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1227 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1228 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1229 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.vendor_specific_codec_id);
1230 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1231 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1232 UINT16_TO_STREAM(pp, p_params->receive_coding_format.vendor_specific_codec_id);
1233 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1234 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1235 UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1236 UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1237 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1238 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1239 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1240 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1241 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1242 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1243 UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1244 UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1245 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1246 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1247 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1248 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1249 UINT8_TO_STREAM(pp, p_params->input_data_path);
1250 UINT8_TO_STREAM(pp, p_params->output_data_path);
1251 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1252 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1253 UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1254 UINT16_TO_STREAM(pp, p_params->packet_types);
1255 UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1256
1257 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1258 }
1259
btsnd_hcic_enhanced_accept_synchronous_connection(const RawAddress & bd_addr,enh_esco_params_t * p_params)1260 void btsnd_hcic_enhanced_accept_synchronous_connection(const RawAddress& bd_addr,
1261 enh_esco_params_t* p_params) {
1262 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1263 uint8_t* pp = (uint8_t*)(p + 1);
1264
1265 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN;
1266 p->offset = 0;
1267
1268 UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION);
1269 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN);
1270
1271 BDADDR_TO_STREAM(pp, bd_addr);
1272 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1273 UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1274 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1275 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1276 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.vendor_specific_codec_id);
1277 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1278 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1279 UINT16_TO_STREAM(pp, p_params->receive_coding_format.vendor_specific_codec_id);
1280 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1281 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1282 UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1283 UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1284 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1285 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1286 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1287 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1288 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1289 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1290 UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1291 UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1292 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1293 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1294 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1295 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1296 UINT8_TO_STREAM(pp, p_params->input_data_path);
1297 UINT8_TO_STREAM(pp, p_params->output_data_path);
1298 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1299 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1300 UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1301 UINT16_TO_STREAM(pp, p_params->packet_types);
1302 UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1303
1304 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1305 }
1306
btsnd_hcic_io_cap_req_neg_reply(const RawAddress & bd_addr,uint8_t err_code)1307 void btsnd_hcic_io_cap_req_neg_reply(const RawAddress& bd_addr, uint8_t err_code) {
1308 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1309 uint8_t* pp = (uint8_t*)(p + 1);
1310
1311 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY;
1312 p->offset = 0;
1313
1314 UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY);
1315 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY);
1316
1317 BDADDR_TO_STREAM(pp, bd_addr);
1318 UINT8_TO_STREAM(pp, err_code);
1319
1320 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1321 }
1322
btsnd_hcic_read_local_oob_data(void)1323 void btsnd_hcic_read_local_oob_data(void) {
1324 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1325 uint8_t* pp = (uint8_t*)(p + 1);
1326
1327 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB;
1328 p->offset = 0;
1329
1330 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA);
1331 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB);
1332
1333 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1334 }
1335
btsnd_hcic_read_local_oob_extended_data(void)1336 void btsnd_hcic_read_local_oob_extended_data(void) {
1337 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1338 uint8_t* pp = (uint8_t*)(p + 1);
1339
1340 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED;
1341 p->offset = 0;
1342
1343 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_EXTENDED_DATA);
1344 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED);
1345
1346 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1347 }
1348
btsnd_hcic_user_conf_reply(const RawAddress & bd_addr,bool is_yes)1349 void btsnd_hcic_user_conf_reply(const RawAddress& bd_addr, bool is_yes) {
1350 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1351 uint8_t* pp = (uint8_t*)(p + 1);
1352
1353 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY;
1354 p->offset = 0;
1355
1356 if (!is_yes) {
1357 /* Negative reply */
1358 UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY);
1359 } else {
1360 /* Confirmation */
1361 UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY);
1362 }
1363
1364 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY);
1365
1366 BDADDR_TO_STREAM(pp, bd_addr);
1367
1368 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1369 }
1370
btsnd_hcic_user_passkey_reply(const RawAddress & bd_addr,uint32_t value)1371 void btsnd_hcic_user_passkey_reply(const RawAddress& bd_addr, uint32_t value) {
1372 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1373 uint8_t* pp = (uint8_t*)(p + 1);
1374
1375 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY;
1376 p->offset = 0;
1377
1378 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY);
1379 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY);
1380
1381 BDADDR_TO_STREAM(pp, bd_addr);
1382 UINT32_TO_STREAM(pp, value);
1383
1384 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1385 }
1386
btsnd_hcic_user_passkey_neg_reply(const RawAddress & bd_addr)1387 void btsnd_hcic_user_passkey_neg_reply(const RawAddress& bd_addr) {
1388 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1389 uint8_t* pp = (uint8_t*)(p + 1);
1390
1391 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY;
1392 p->offset = 0;
1393
1394 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY);
1395 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY);
1396
1397 BDADDR_TO_STREAM(pp, bd_addr);
1398
1399 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1400 }
1401
btsnd_hcic_rem_oob_reply(const RawAddress & bd_addr,const Octet16 & c,const Octet16 & r)1402 void btsnd_hcic_rem_oob_reply(const RawAddress& bd_addr, const Octet16& c, const Octet16& r) {
1403 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1404 uint8_t* pp = (uint8_t*)(p + 1);
1405
1406 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY;
1407 p->offset = 0;
1408
1409 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY);
1410 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY);
1411
1412 BDADDR_TO_STREAM(pp, bd_addr);
1413 ARRAY16_TO_STREAM(pp, c.data());
1414 ARRAY16_TO_STREAM(pp, r.data());
1415
1416 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1417 }
1418
btsnd_hcic_rem_oob_neg_reply(const RawAddress & bd_addr)1419 void btsnd_hcic_rem_oob_neg_reply(const RawAddress& bd_addr) {
1420 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1421 uint8_t* pp = (uint8_t*)(p + 1);
1422
1423 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY;
1424 p->offset = 0;
1425
1426 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY);
1427 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY);
1428
1429 BDADDR_TO_STREAM(pp, bd_addr);
1430
1431 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1432 }
1433
1434 /**** end of Simple Pairing Commands ****/
1435
1436 /*************************
1437 * End of Lisbon Commands
1438 *************************/
1439
btsnd_hcic_read_rssi(uint16_t handle)1440 void btsnd_hcic_read_rssi(uint16_t handle) {
1441 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1442 uint8_t* pp = (uint8_t*)(p + 1);
1443
1444 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1445 p->offset = 0;
1446
1447 UINT16_TO_STREAM(pp, HCI_READ_RSSI);
1448 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1449
1450 UINT16_TO_STREAM(pp, handle);
1451
1452 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1453 }
1454
read_encryption_key_size_complete(ReadEncKeySizeCb cb,uint8_t * return_parameters,uint16_t)1455 static void read_encryption_key_size_complete(ReadEncKeySizeCb cb, uint8_t* return_parameters,
1456 uint16_t /* return_parameters_length */) {
1457 uint8_t status;
1458 uint16_t handle;
1459 uint8_t key_size;
1460 STREAM_TO_UINT8(status, return_parameters);
1461 STREAM_TO_UINT16(handle, return_parameters);
1462 STREAM_TO_UINT8(key_size, return_parameters);
1463
1464 std::move(cb).Run(status, handle, key_size);
1465 }
1466
btsnd_hcic_read_encryption_key_size(uint16_t handle,ReadEncKeySizeCb cb)1467 void btsnd_hcic_read_encryption_key_size(uint16_t handle, ReadEncKeySizeCb cb) {
1468 constexpr uint8_t len = 2;
1469 uint8_t param[len];
1470 memset(param, 0, len);
1471
1472 uint8_t* p = param;
1473 UINT16_TO_STREAM(p, handle);
1474
1475 btu_hcif_send_cmd_with_cb(FROM_HERE, HCI_READ_ENCR_KEY_SIZE, param, len,
1476 base::Bind(&read_encryption_key_size_complete, base::Passed(&cb)));
1477 }
1478
btsnd_hcic_read_failed_contact_counter(uint16_t handle)1479 void btsnd_hcic_read_failed_contact_counter(uint16_t handle) {
1480 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1481 uint8_t* pp = (uint8_t*)(p + 1);
1482
1483 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1484 p->offset = 0;
1485
1486 UINT16_TO_STREAM(pp, HCI_READ_FAILED_CONTACT_COUNTER);
1487 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1488
1489 UINT16_TO_STREAM(pp, handle);
1490
1491 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1492 }
1493
btsnd_hcic_enable_test_mode(void)1494 void btsnd_hcic_enable_test_mode(void) {
1495 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1496 uint8_t* pp = (uint8_t*)(p + 1);
1497
1498 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
1499 p->offset = 0;
1500
1501 UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE);
1502 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
1503
1504 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1505 }
1506
btsnd_hcic_write_inqscan_type(uint8_t type)1507 void btsnd_hcic_write_inqscan_type(uint8_t type) {
1508 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1509 uint8_t* pp = (uint8_t*)(p + 1);
1510
1511 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1512 p->offset = 0;
1513
1514 UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE);
1515 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1516
1517 UINT8_TO_STREAM(pp, type);
1518
1519 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1520 }
1521
btsnd_hcic_write_inquiry_mode(uint8_t mode)1522 void btsnd_hcic_write_inquiry_mode(uint8_t mode) {
1523 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1524 uint8_t* pp = (uint8_t*)(p + 1);
1525
1526 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1527 p->offset = 0;
1528
1529 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE);
1530 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1531
1532 UINT8_TO_STREAM(pp, mode);
1533
1534 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1535 }
1536
btsnd_hcic_write_pagescan_type(uint8_t type)1537 void btsnd_hcic_write_pagescan_type(uint8_t type) {
1538 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1539 uint8_t* pp = (uint8_t*)(p + 1);
1540
1541 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1542 p->offset = 0;
1543
1544 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE);
1545 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1546
1547 UINT8_TO_STREAM(pp, type);
1548
1549 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1550 }
1551
btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB * p_vsc_cplt_cback,uint16_t opcode,uint8_t * data,uint16_t len)1552 static void btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB* p_vsc_cplt_cback, uint16_t opcode,
1553 uint8_t* data, uint16_t len) {
1554 /* If there was a callback address for vcs complete, call it */
1555 if (p_vsc_cplt_cback) {
1556 tBTM_VSC_CMPL vcs_cplt_params;
1557 vcs_cplt_params.opcode = opcode;
1558 vcs_cplt_params.param_len = len;
1559 vcs_cplt_params.p_param_buf = data;
1560 /* Call the VSC complete callback function */
1561 (*p_vsc_cplt_cback)(&vcs_cplt_params);
1562 }
1563 }
1564
btsnd_hcic_vendor_spec_cmd(uint16_t opcode,uint8_t len,uint8_t * p_data,tBTM_VSC_CMPL_CB * p_cmd_cplt_cback)1565 void btsnd_hcic_vendor_spec_cmd(uint16_t opcode, uint8_t len, uint8_t* p_data,
1566 tBTM_VSC_CMPL_CB* p_cmd_cplt_cback) {
1567 uint16_t v_opcode = HCI_GRP_VENDOR_SPECIFIC | opcode;
1568
1569 btu_hcif_send_cmd_with_cb(FROM_HERE, v_opcode, p_data, len,
1570 base::BindOnce(&btsnd_hcic_vendor_spec_complete,
1571 base::Unretained(p_cmd_cplt_cback), v_opcode));
1572 }
1573
btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction,uint8_t data_path_id,std::vector<uint8_t> vendor_config)1574 void btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction, uint8_t data_path_id,
1575 std::vector<uint8_t> vendor_config) {
1576 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1577 uint8_t* pp = (uint8_t*)(p + 1);
1578 uint8_t size = static_cast<uint8_t>(vendor_config.size());
1579 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size;
1580 p->offset = 0;
1581
1582 UINT16_TO_STREAM(pp, HCI_CONFIGURE_DATA_PATH);
1583 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size);
1584 UINT8_TO_STREAM(pp, data_path_direction);
1585 UINT8_TO_STREAM(pp, data_path_id);
1586 UINT8_TO_STREAM(pp, vendor_config.size());
1587 if (size != 0) {
1588 ARRAY_TO_STREAM(pp, vendor_config.data(), size);
1589 }
1590
1591 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1592 }
1593
1594 namespace bluetooth::legacy::hci {
1595 class InterfaceImpl : public Interface {
Disconnect(uint16_t handle,uint8_t reason) const1596 void Disconnect(uint16_t handle, uint8_t reason) const override {
1597 btsnd_hcic_disconnect(handle, reason);
1598 }
ChangeConnectionPacketType(uint16_t handle,uint16_t packet_types) const1599 void ChangeConnectionPacketType(uint16_t handle, uint16_t packet_types) const override {
1600 btsnd_hcic_change_conn_type(handle, packet_types);
1601 }
StartRoleSwitch(const RawAddress & bd_addr,uint8_t role) const1602 void StartRoleSwitch(const RawAddress& bd_addr, uint8_t role) const override {
1603 btsnd_hcic_switch_role(bd_addr, role);
1604 }
ConfigureDataPath(hci_data_direction_t data_path_direction,uint8_t data_path_id,std::vector<uint8_t> vendor_config) const1605 void ConfigureDataPath(hci_data_direction_t data_path_direction, uint8_t data_path_id,
1606 std::vector<uint8_t> vendor_config) const override {
1607 btsnd_hcic_configure_data_path(data_path_direction, data_path_id, vendor_config);
1608 }
1609 };
1610
1611 namespace {
1612 const InterfaceImpl interface_;
1613 }
1614
GetInterface()1615 const Interface& GetInterface() { return interface_; }
1616 } // namespace bluetooth::legacy::hci
1617