1 /*
2 * Copyright (C) 2023 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "gtest/gtest.h"
18
19 #include <malloc.h> // memalign
20 #include <sys/mman.h>
21 #include <unistd.h>
22
23 #include <algorithm> // copy_n, fill_n
24 #include <cfenv>
25 #include <csignal>
26 #include <cstdint>
27 #include <cstring>
28 #include <memory>
29
30 #include "berberis/base/bit_util.h"
31 #include "berberis/base/checks.h"
32 #include "berberis/guest_os_primitives/guest_thread.h"
33 #include "berberis/guest_state/guest_addr.h"
34 #include "berberis/guest_state/guest_state.h"
35 #include "berberis/interpreter/riscv64/interpreter.h"
36 #include "berberis/intrinsics/guest_cpu_flags.h" // GuestModeFromHostRounding
37 #include "berberis/intrinsics/guest_rounding_modes.h" // ScopedRoundingMode
38 #include "berberis/intrinsics/simd_register.h"
39 #include "berberis/intrinsics/vector_intrinsics.h"
40 #include "berberis/runtime_primitives/memory_region_reservation.h"
41
42 #include "../faulty_memory_accesses.h"
43
44 namespace berberis {
45
46 namespace {
47
48 #if defined(__i386__)
49 constexpr size_t kRegIP = REG_EIP;
50 #elif defined(__x86_64__)
51 constexpr size_t kRegIP = REG_RIP;
52 #else
53 #error "Unsupported arch"
54 #endif
55
56 bool sighandler_called = false;
57
FaultHandler(int,siginfo_t *,void * ctx)58 void FaultHandler(int /* sig */, siginfo_t* /* info */, void* ctx) {
59 ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(ctx);
60 static_assert(sizeof(void*) == sizeof(greg_t), "Unsupported type sizes");
61 void* fault_addr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[kRegIP]);
62 void* recovery_addr = FindFaultyMemoryAccessRecoveryAddrForTesting(fault_addr);
63 sighandler_called = true;
64 CHECK(recovery_addr);
65 ucontext->uc_mcontext.gregs[kRegIP] = reinterpret_cast<greg_t>(recovery_addr);
66 }
67
68 class ScopedFaultySigaction {
69 public:
ScopedFaultySigaction()70 ScopedFaultySigaction() {
71 struct sigaction sa;
72 sa.sa_flags = SA_SIGINFO;
73 sigemptyset(&sa.sa_mask);
74 sa.sa_sigaction = FaultHandler;
75 CHECK_EQ(sigaction(SIGSEGV, &sa, &old_sa_), 0);
76 }
77
~ScopedFaultySigaction()78 ~ScopedFaultySigaction() { CHECK_EQ(sigaction(SIGSEGV, &old_sa_, nullptr), 0); }
79
80 private:
81 struct sigaction old_sa_;
82 };
83
84 // Interpreter decodes the size itself, but we need to accept this template parameter to share
85 // tests with translators.
86 template <uint8_t kInsnSize = 4>
RunOneInstruction(ThreadState * state,GuestAddr stop_pc)87 bool RunOneInstruction(ThreadState* state, GuestAddr stop_pc) {
88 InterpretInsn(state);
89 return state->cpu.insn_addr == stop_pc;
90 }
91
92 class Riscv64InterpreterTest : public ::testing::Test {
93 public:
94 // Non-Compressed Instructions.
Riscv64InterpreterTest()95 Riscv64InterpreterTest()
96 : state_{
97 .cpu = {.vtype = uint64_t{1} << 63, .frm = intrinsics::GuestModeFromHostRounding()}} {}
98
InterpretFence(uint32_t insn_bytes)99 void InterpretFence(uint32_t insn_bytes) {
100 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
101 InterpretInsn(&state_);
102 }
103
104 // Vector instructions.
105 template <typename ElementType>
TestFPExceptions(uint32_t insn_bytes)106 void TestFPExceptions(uint32_t insn_bytes) {
107 // Install the following arguments: NaN, 1.0, 1.0, NaN.
108 // Then try to mask out NaNs with vstart, vl, and mask.
109 state_.cpu.v[24] = state_.cpu.v[16] = state_.cpu.v[8] =
110 SIMD128Register{__v2du{0x7ff4'0000'0000'0000, 0x3ff0'0000'0000'0000}}.Get<__uint128_t>();
111 state_.cpu.v[25] = state_.cpu.v[17] = state_.cpu.v[9] =
112 SIMD128Register{__v2du{0x3ff0'0000'0000'0000, 0x7ff4'0000'0000'0000}}.Get<__uint128_t>();
113 state_.cpu.v[26] = state_.cpu.v[18] = state_.cpu.v[10] = SIMD128Register{
114 __v4su{
115 0x7fa0'0000, 0x3f80'0000, 0x3f80'0000, 0x7fa0'0000}}.Get<__uint128_t>();
116 state_.cpu.f[1] = 0xffff'ffff'3f80'0000;
117 state_.cpu.f[2] = 0x3ff0'0000'0000'0000;
118 ;
119 state_.cpu.vtype = (BitUtilLog2(sizeof(ElementType)) << 3) | /*vlmul=*/1;
120 // First clear exceptions and execute the instruction with vstart = 0, vl = 4.
121 // This should produce FE_INVALID with most floating point instructions.
122 EXPECT_EQ(feclearexcept(FE_ALL_EXCEPT), 0);
123 state_.cpu.vstart = 0;
124 state_.cpu.vl = 4;
125 state_.cpu.v[0] = 0b1111;
126 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
127 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
128 EXPECT_TRUE(bool(fetestexcept(FE_ALL_EXCEPT)));
129 // Mask NaNs using vstart and vl.
130 EXPECT_EQ(feclearexcept(FE_ALL_EXCEPT), 0);
131 state_.cpu.vstart = 1;
132 state_.cpu.vl = 3;
133 state_.cpu.v[0] = 0b1111;
134 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
135 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
136 EXPECT_FALSE(bool(fetestexcept(FE_ALL_EXCEPT)));
137 // Mask NaNs using mask.
138 EXPECT_EQ(feclearexcept(FE_ALL_EXCEPT), 0);
139 state_.cpu.vstart = 0;
140 state_.cpu.vl = 4;
141 state_.cpu.v[0] = 0b0110;
142 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
143 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
144 EXPECT_FALSE(bool(fetestexcept(FE_ALL_EXCEPT)));
145 }
146
147 template <size_t kNFfields>
TestVlXreXX(uint32_t insn_bytes)148 void TestVlXreXX(uint32_t insn_bytes) {
149 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
150 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
151 SetXReg<1>(state_.cpu, ToGuestAddr(&kVectorComparisonSource));
152 for (size_t index = 0; index < 8; index++) {
153 state_.cpu.v[8 + index] = kUndisturbedValue;
154 }
155 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
156 for (size_t index = 0; index < 8; index++) {
157 EXPECT_EQ(state_.cpu.v[8 + index],
158 (index >= kNFfields
159 ? kUndisturbedValue
160 : SIMD128Register{kVectorComparisonSource[index]}.Get<__uint128_t>()));
161 }
162 }
163
164 template <typename ElementType, size_t kNFfields, size_t kLmul>
VlxsegXeiXX(uint32_t insn_bytes,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (sizeof (SIMD128Register)/sizeof (ElementType))])165 void VlxsegXeiXX(
166 uint32_t insn_bytes,
167 const ElementType::BaseType (&expected_results)[kNFfields * kLmul][static_cast<int>(
168 sizeof(SIMD128Register) / sizeof(ElementType))]) {
169 VlxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes, expected_results);
170 VlxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes | 0x8000000, expected_results);
171 VlxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x5000, expected_results);
172 VlxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x8005000, expected_results);
173 VlxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x6000, expected_results);
174 VlxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x8006000, expected_results);
175 VlxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x7000, expected_results);
176 VlxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x8007000, expected_results);
177 }
178
179 template <typename DataElementType, typename IndexElementType, size_t kNFfields, size_t kLmul>
VlxsegXeiXX(uint32_t insn_bytes,const DataElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (sizeof (SIMD128Register)/sizeof (DataElementType))])180 void VlxsegXeiXX(
181 uint32_t insn_bytes,
182 const DataElementType::BaseType (&expected_results)[kNFfields * kLmul][static_cast<int>(
183 sizeof(SIMD128Register) / sizeof(DataElementType))]) {
184 constexpr size_t kElementsCount = sizeof(SIMD128Register) / sizeof(IndexElementType);
185 constexpr size_t kTotalElements =
186 sizeof(SIMD128Register) / sizeof(DataElementType) * kLmul * kNFfields;
187 // If we need more indexes than may fit into 8 vector registers then such operation is
188 // impossible on RISC-V and we should skip that combination.
189 if constexpr (sizeof(IndexElementType) * kTotalElements <= sizeof(SIMD128Register) * 8) {
190 TestVectorLoad<DataElementType, kNFfields, kLmul>(insn_bytes, expected_results, [this] {
191 for (size_t reg_no = 0; reg_no < AlignUp<kElementsCount>(kTotalElements) / kElementsCount;
192 ++reg_no) {
193 SIMD128Register index_register;
194 for (size_t index = 0; index < kElementsCount; ++index) {
195 index_register.Set(IndexElementType{static_cast<typename IndexElementType::BaseType>(
196 kPermutedIndexes[index + reg_no * kElementsCount] *
197 sizeof(DataElementType) * kNFfields)},
198 index);
199 }
200 state_.cpu.v[16 + reg_no] = index_register.Get<__uint128_t>();
201 }
202 });
203 }
204 }
205
206 template <typename ElementType, size_t kNFfields, size_t kLmul>
TestVlsegXeXX(uint32_t insn_bytes,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (16/sizeof (ElementType))])207 void TestVlsegXeXX(
208 uint32_t insn_bytes,
209 const ElementType::BaseType (
210 &expected_results)[kNFfields * kLmul][static_cast<int>(16 / sizeof(ElementType))]) {
211 TestVectorLoad<ElementType, kNFfields, kLmul>(insn_bytes, expected_results, [] {});
212 // Turn Vector Unit-Stride Segment Loads and Stores into Fault-Only-First Load.
213 TestVectorLoad<ElementType, kNFfields, kLmul>(insn_bytes | 0x1000000, expected_results, [] {});
214 }
215
216 template <typename ElementType, size_t kNFfields, size_t kLmul>
TestVlssegXeXX(uint32_t insn_bytes,uint64_t stride,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (16/sizeof (ElementType))])217 void TestVlssegXeXX(
218 uint32_t insn_bytes,
219 uint64_t stride,
220 const ElementType::BaseType (
221 &expected_results)[kNFfields * kLmul][static_cast<int>(16 / sizeof(ElementType))]) {
222 TestVectorLoad<ElementType, kNFfields, kLmul>(
223 insn_bytes, expected_results, [stride, this] { SetXReg<2>(state_.cpu, stride); });
224 }
225
226 template <typename ElementType, size_t kNFfields, size_t kLmul, typename ExtraCPUInitType>
TestVectorLoad(uint32_t insn_bytes,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (16/sizeof (ElementType))],ExtraCPUInitType ExtraCPUInit)227 void TestVectorLoad(
228 uint32_t insn_bytes,
229 const ElementType::BaseType (
230 &expected_results)[kNFfields * kLmul][static_cast<int>(16 / sizeof(ElementType))],
231 ExtraCPUInitType ExtraCPUInit) {
232 constexpr int kElementsCount = static_cast<int>(16 / sizeof(ElementType));
233 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
234 for (uint8_t vstart = 0; vstart <= kElementsCount * kLmul; ++vstart) {
235 for (uint8_t vl = 0; vl <= kElementsCount * kLmul; ++vl) {
236 for (uint8_t vta = 0; vta < 2; ++vta) {
237 // Handle three masking cases:
238 // no masking (vma == 0), agnostic (vma == 1), undisturbed (vma == 2)
239 for (uint8_t vma = 0; vma < 3; ++vma) {
240 state_.cpu.vtype = (vma & 1) << 7 | (vta << 6) |
241 (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
242 state_.cpu.vstart = vstart;
243 state_.cpu.vl = vl;
244 uint32_t insn_bytes_with_vm = insn_bytes;
245 // If masking is supposed to be disabled then we need to set vm bit (#25).
246 if (!vma) {
247 insn_bytes_with_vm |= (1 << 25);
248 }
249 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
250 SetXReg<1>(state_.cpu, ToGuestAddr(&kVectorCalculationsSource));
251 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
252 for (size_t index = 0; index < 8; index++) {
253 state_.cpu.v[8 + index] = kUndisturbedValue;
254 }
255 ExtraCPUInit();
256 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
257 EXPECT_EQ(state_.cpu.vstart, 0);
258 EXPECT_EQ(state_.cpu.vl, vl);
259 for (size_t field = 0; field < kNFfields; field++) {
260 for (size_t index = 0; index < kLmul; index++) {
261 for (size_t element = 0; element < kElementsCount; ++element) {
262 ElementType expected_element;
263 if (vstart >= vl) {
264 // When vstart ⩾ vl, there are no body elements, and no elements are updated in
265 // any destinationvector register group, including that no tail elements are
266 // updated with agnostic values.
267 expected_element =
268 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
269 } else if (element + index * kElementsCount < std::min(vstart, vl)) {
270 // Elements before vstart are undisturbed if vstart is less than vl.
271 expected_element =
272 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
273 } else if (element + index * kElementsCount >= vl) {
274 // Element after vl have to be processed with vta policy.
275 if (vta == 1) {
276 expected_element = ~ElementType{0};
277 } else {
278 expected_element =
279 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
280 }
281 } else if (vma &&
282 (~(state_.cpu.v[0]) >> (element + index * kElementsCount)) & 1) {
283 // If element is inactive it's processed with vma policy.
284 if (vma == 1) {
285 expected_element = ~ElementType{0};
286 } else {
287 expected_element =
288 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
289 }
290 } else {
291 expected_element =
292 ElementType{expected_results[index + field * kLmul][element]};
293 }
294 EXPECT_EQ(
295 SIMD128Register{state_.cpu.v[8 + index + field * kLmul]}.Get<ElementType>(
296 element),
297 expected_element);
298 }
299 }
300 }
301 for (size_t index = kNFfields * kLmul; index < 8; index++) {
302 EXPECT_EQ(state_.cpu.v[8 + index], kUndisturbedValue);
303 }
304 }
305 }
306 }
307 }
308 }
309
TestVlm(uint32_t insn_bytes,__v16qu expected_results)310 void TestVlm(uint32_t insn_bytes, __v16qu expected_results) {
311 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
312 // Vlm.v is special form of normal vector load which mostly ignores vtype.
313 // The only bit that it honors is vill: https://github.com/riscv/riscv-v-spec/pull/877
314 // Verify that changes to vtype don't affect the execution (but vstart and vl do).
315 for (uint8_t sew = 0; sew < 4; ++sew) {
316 for (uint8_t vlmul = 0; vlmul < 4; ++vlmul) {
317 const uint8_t kElementsCount = (16 >> sew) << vlmul;
318 for (uint8_t vstart = 0; vstart <= kElementsCount; ++vstart) {
319 for (uint8_t vl = 0; vl <= kElementsCount; ++vl) {
320 const uint8_t kVlmVl = AlignUp<CHAR_BIT>(vl) / CHAR_BIT;
321 for (uint8_t vta = 0; vta < 2; ++vta) {
322 for (uint8_t vma = 0; vma < 2; ++vma) {
323 state_.cpu.vtype = (vma << 7) | (vta << 6) | (sew << 3) | vlmul;
324 state_.cpu.vstart = vstart;
325 state_.cpu.vl = vl;
326 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
327 SetXReg<1>(state_.cpu, ToGuestAddr(&kVectorCalculationsSource));
328 state_.cpu.v[8] = kUndisturbedValue;
329 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
330 EXPECT_EQ(state_.cpu.vstart, 0);
331 EXPECT_EQ(state_.cpu.vl, vl);
332 for (size_t element = 0; element < 16; ++element) {
333 UInt8 expected_element;
334 if (element < vstart || vstart >= kVlmVl) {
335 expected_element = SIMD128Register{kUndisturbedResult}.Get<UInt8>(element);
336 } else if (element >= kVlmVl) {
337 expected_element = ~UInt8{0};
338 } else {
339 expected_element = UInt8{expected_results[element]};
340 }
341 EXPECT_EQ(SIMD128Register{state_.cpu.v[8]}.Get<UInt8>(element), expected_element);
342 }
343 }
344 }
345 }
346 }
347 }
348 }
349 }
350
351 template <typename ElementType, size_t kNFfields, size_t kLmul, size_t kResultSize>
VsxsegXeiXX(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize])352 void VsxsegXeiXX(uint32_t insn_bytes, const uint64_t (&expected_results)[kResultSize]) {
353 VsxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes, expected_results);
354 VsxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes | 0x8000000, expected_results);
355 VsxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x5000, expected_results);
356 VsxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x8005000, expected_results);
357 VsxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x6000, expected_results);
358 VsxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x8006000, expected_results);
359 VsxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x7000, expected_results);
360 VsxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x8007000, expected_results);
361 }
362
363 template <typename DataElementType,
364 typename IndexElementType,
365 size_t kNFfields,
366 size_t kLmul,
367 size_t kResultSize>
VsxsegXeiXX(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize])368 void VsxsegXeiXX(uint32_t insn_bytes, const uint64_t (&expected_results)[kResultSize]) {
369 constexpr size_t kElementsCount = sizeof(SIMD128Register) / sizeof(IndexElementType);
370 constexpr size_t kTotalElements =
371 sizeof(SIMD128Register) / sizeof(DataElementType) * kLmul * kNFfields;
372 // If we need more indexes than may fit into 8 vector registers then such operation is
373 // impossible on RISC-V and we should skip that combination.
374 if constexpr (sizeof(IndexElementType) * kTotalElements <= sizeof(SIMD128Register) * 8) {
375 TestVectorStore<DataElementType, kNFfields, kLmul>(insn_bytes, expected_results, [this] {
376 for (size_t reg_no = 0; reg_no < AlignUp<kElementsCount>(kTotalElements) / kElementsCount;
377 ++reg_no) {
378 SIMD128Register index_register;
379 for (size_t index = 0; index < kElementsCount; ++index) {
380 index_register.Set(IndexElementType{static_cast<typename IndexElementType::BaseType>(
381 kPermutedIndexes[index + reg_no * kElementsCount] *
382 sizeof(DataElementType) * kNFfields)},
383 index);
384 }
385 state_.cpu.v[16 + reg_no] = index_register.Get<__uint128_t>();
386 }
387 });
388 }
389 }
390
391 template <typename ElementType, size_t kNFfields, size_t kLmul, size_t kResultSize>
TestVssegXeXX(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize])392 void TestVssegXeXX(uint32_t insn_bytes, const uint64_t (&expected_results)[kResultSize]) {
393 TestVectorStore<ElementType, kNFfields, kLmul>(insn_bytes, expected_results, [] {});
394 }
395
396 template <typename ElementType, size_t kNFfields, size_t kLmul, size_t kResultSize>
TestVsssegXeXX(uint32_t insn_bytes,uint64_t stride,const uint64_t (& expected_results)[kResultSize])397 void TestVsssegXeXX(uint32_t insn_bytes,
398 uint64_t stride,
399 const uint64_t (&expected_results)[kResultSize]) {
400 TestVectorStore<ElementType, kNFfields, kLmul>(
401 insn_bytes, expected_results, [stride, this] { SetXReg<2>(state_.cpu, stride); });
402 }
403
404 template <typename ElementType,
405 size_t kNFfields,
406 size_t kLmul,
407 size_t kResultSize,
408 typename ExtraCPUInitType>
TestVectorStore(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize],ExtraCPUInitType ExtraCPUInit)409 void TestVectorStore(uint32_t insn_bytes,
410 const uint64_t (&expected_results)[kResultSize],
411 ExtraCPUInitType ExtraCPUInit) {
412 constexpr size_t kElementsCount = 16 / sizeof(ElementType);
413 const SIMD128Register kUndisturbedValue = SIMD128Register{kUndisturbedResult};
414 state_.cpu.vtype = (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
415 state_.cpu.vstart = 0;
416 state_.cpu.vl = kElementsCount * kLmul;
417 // First verify that store works with no inactive elements and no masking.
418 uint32_t insn_bytes_with_vm = insn_bytes | (1 << 25);
419 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
420 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
421 for (size_t index = 0; index < 8; ++index) {
422 state_.cpu.v[8 + index] =
423 SIMD128Register{kVectorCalculationsSource[index]}.Get<__uint128_t>();
424 }
425 for (uint64_t& element : store_area_) {
426 element = kUndisturbedResult[0];
427 }
428 ExtraCPUInit();
429 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
430 for (size_t index = 0; index < std::size(store_area_); ++index) {
431 if (index >= std::size(expected_results)) {
432 EXPECT_EQ(store_area_[index], static_cast<uint64_t>(kUndisturbedResult[0]));
433 } else {
434 EXPECT_EQ(store_area_[index], expected_results[index]);
435 }
436 }
437 // Most vector instruction apply masks to *target* operands which means we may apply the exact
438 // same, well-tested logic to verify how they work. But store instructions apply masks to *data
439 // source* operand which makes generation of expected target problematic (especially for
440 // complicated store with segments and strides and/or indexes). To sidestep the issue we are
441 // first testing that full version with all elements active works (above) and then reuse it to
442 // verify that `vstart`, `vl` ������ `mask` operands work as expected. This wouldn't work if some
443 // elements are overlapping, but these instructions, while technically permitted, already are
444 // allowed to produce many possible different results, thus we are not testing them.
445 for (uint8_t vstart = 0; vstart <= kElementsCount * kLmul; ++vstart) {
446 for (uint8_t vl = 0; vl <= kElementsCount * kLmul; ++vl) {
447 for (uint8_t vta = 0; vta < 2; ++vta) {
448 // Handle three masking cases:
449 // no masking (vma == 0), agnostic (vma == 1), undisturbed (vma == 2)
450 // Note: vta and vma settings are ignored by store instructions, we are just verifying
451 // this is what actually happens.
452 for (uint8_t vma = 0; vma < 3; ++vma) {
453 // Use instruction in the mode tested above to generate expected results.
454 state_.cpu.vtype = (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
455 state_.cpu.vstart = 0;
456 state_.cpu.vl = kElementsCount * kLmul;
457 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
458 decltype(store_area_) expected_store_area;
459 SetXReg<1>(state_.cpu, ToGuestAddr(&expected_store_area));
460 for (size_t index = 0; index < kLmul; ++index) {
461 for (size_t field = 0; field < kNFfields; ++field) {
462 SIMD128Register register_value =
463 SIMD128Register{kVectorCalculationsSource[index + field * kLmul]};
464 if (vma) {
465 auto ApplyMask = [®ister_value, &kUndisturbedValue, index](auto mask) {
466 register_value =
467 (register_value & mask[index]) | (kUndisturbedValue & ~mask[index]);
468 };
469 if constexpr (sizeof(ElementType) == sizeof(Int8)) {
470 ApplyMask(kMaskInt8);
471 } else if constexpr (sizeof(ElementType) == sizeof(Int16)) {
472 ApplyMask(kMaskInt16);
473 } else if constexpr (sizeof(ElementType) == sizeof(Int32)) {
474 ApplyMask(kMaskInt32);
475 } else if constexpr (sizeof(ElementType) == sizeof(Int64)) {
476 ApplyMask(kMaskInt64);
477 } else {
478 static_assert(kDependentTypeFalse<ElementType>);
479 }
480 }
481 if (vstart > kElementsCount * index) {
482 for (size_t prefix_id = 0;
483 prefix_id < std::min(kElementsCount, vstart - kElementsCount * index);
484 ++prefix_id) {
485 register_value.Set(kUndisturbedValue.Get<ElementType>(0), prefix_id);
486 }
487 }
488 if (vl <= kElementsCount * index) {
489 register_value = kUndisturbedValue.Get<__uint128_t>();
490 } else if (vl < kElementsCount * (index + 1)) {
491 for (size_t suffix_id = vl - kElementsCount * index; suffix_id < kElementsCount;
492 ++suffix_id) {
493 register_value.Set(kUndisturbedValue.Get<ElementType>(0), suffix_id);
494 }
495 }
496 state_.cpu.v[8 + index + field * kLmul] = register_value.Get<__uint128_t>();
497 }
498 }
499 for (uint64_t& element : expected_store_area) {
500 element = kUndisturbedResult[0];
501 }
502 ExtraCPUInit();
503 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
504 // Now execute instruction with mode that we want to actually test.
505 state_.cpu.vtype = (vma & 1) << 7 | (vta << 6) |
506 (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
507 state_.cpu.vstart = vstart;
508 state_.cpu.vl = vl;
509 uint32_t insn_bytes_with_vm = insn_bytes;
510 // If masking is supposed to be disabled then we need to set vm bit (#25).
511 if (!vma) {
512 insn_bytes_with_vm |= (1 << 25);
513 }
514 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
515 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
516 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
517 for (size_t index = 0; index < 8; ++index) {
518 state_.cpu.v[8 + index] =
519 SIMD128Register{kVectorCalculationsSource[index]}.Get<__uint128_t>();
520 }
521 for (uint64_t& element : store_area_) {
522 element = kUndisturbedResult[0];
523 }
524 ExtraCPUInit();
525 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
526 for (size_t index = 0; index < std::size(store_area_); ++index) {
527 EXPECT_EQ(store_area_[index], expected_store_area[index]);
528 }
529 }
530 }
531 }
532 }
533 }
534
TestVsm(uint32_t insn_bytes,__v16qu expected_results)535 void TestVsm(uint32_t insn_bytes, __v16qu expected_results) {
536 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
537 // Vlm.v is special form of normal vector load which mostly ignores vtype.
538 // The only bit that it honors is vill: https://github.com/riscv/riscv-v-spec/pull/877
539 // Verify that changes to vtype don't affect the execution (but vstart and vl do).
540 for (uint8_t sew = 0; sew < 4; ++sew) {
541 for (uint8_t vlmul = 0; vlmul < 4; ++vlmul) {
542 const uint8_t kElementsCount = (16 >> sew) << vlmul;
543 for (uint8_t vstart = 0; vstart <= kElementsCount; ++vstart) {
544 for (uint8_t vl = 0; vl <= kElementsCount; ++vl) {
545 const uint8_t kVlmVl = AlignUp<CHAR_BIT>(vl) / CHAR_BIT;
546 for (uint8_t vta = 0; vta < 2; ++vta) {
547 for (uint8_t vma = 0; vma < 2; ++vma) {
548 state_.cpu.vtype = (vma << 7) | (vta << 6) | (sew << 3) | vlmul;
549 state_.cpu.vstart = vstart;
550 state_.cpu.vl = vl;
551 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
552 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
553 store_area_[0] = kUndisturbedResult[0];
554 store_area_[1] = kUndisturbedResult[1];
555 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
556 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
557 EXPECT_EQ(state_.cpu.vstart, 0);
558 EXPECT_EQ(state_.cpu.vl, vl);
559 SIMD128Register memory_result =
560 SIMD128Register{__v2du{store_area_[0], store_area_[1]}};
561 for (size_t element = 0; element < 16; ++element) {
562 UInt8 expected_element;
563 if (element < vstart || element >= kVlmVl) {
564 expected_element = SIMD128Register{kUndisturbedResult}.Get<UInt8>(element);
565 } else {
566 expected_element = UInt8{expected_results[element]};
567 }
568 EXPECT_EQ(memory_result.Get<UInt8>(element), expected_element);
569 }
570 }
571 }
572 }
573 }
574 }
575 }
576 }
577
578 // Vector instructions.
TestVleXXff(uint32_t insn_bytes,uint8_t loadable_bytes,uint8_t vsew,uint8_t expected_vl,bool fail_on_first=false)579 void TestVleXXff(uint32_t insn_bytes,
580 uint8_t loadable_bytes,
581 uint8_t vsew,
582 uint8_t expected_vl,
583 bool fail_on_first = false) {
584 ScopedFaultySigaction scoped_sa;
585 sighandler_called = false;
586 char* buffer;
587 const size_t kPageSize = sysconf(_SC_PAGE_SIZE);
588 buffer = (char*)memalign(kPageSize, 2 * kPageSize);
589 mprotect(buffer, kPageSize * 2, PROT_WRITE);
590 char* p = buffer + kPageSize - loadable_bytes;
591 std::memcpy(p, &kVectorCalculationsSource[0], 128);
592 mprotect(buffer + kPageSize, kPageSize, PROT_NONE);
593
594 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, (vsew << 3) | 3);
595 state_.cpu.vstart = 0;
596 state_.cpu.vl = vlmax;
597 state_.cpu.vtype = vtype;
598 insn_bytes = insn_bytes | (1 << 25);
599 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
600 SetXReg<1>(state_.cpu, ToGuestAddr(p));
601
602 if (fail_on_first) {
603 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr));
604 } else {
605 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
606 }
607 if (loadable_bytes < 128) {
608 EXPECT_TRUE(sighandler_called);
609 } else {
610 EXPECT_FALSE(sighandler_called);
611 }
612 EXPECT_EQ(state_.cpu.vl, expected_vl);
613 }
614
615 // Vector instructions.
TestVleXX(uint32_t insn_bytes,const __v16qu (& expected_result_int8)[8],const __v8hu (& expected_result_int16)[8],const __v4su (& expected_result_int32)[8],const __v2du (& expected_result_int64)[8],uint8_t veew,const __v2du (& source)[16])616 void TestVleXX(uint32_t insn_bytes,
617 const __v16qu (&expected_result_int8)[8],
618 const __v8hu (&expected_result_int16)[8],
619 const __v4su (&expected_result_int32)[8],
620 const __v2du (&expected_result_int64)[8],
621 uint8_t veew,
622 const __v2du (&source)[16]) {
623 auto Verify = [this, &source](uint32_t insn_bytes,
624 uint8_t vsew,
625 uint8_t veew,
626 uint8_t vlmul_max,
627 const auto& expected_result,
628 auto mask) {
629 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
630 for (uint8_t vlmul = 0; vlmul < vlmul_max; ++vlmul) {
631 int vemul = SignExtend<3>(vlmul);
632 vemul += vsew; // Multiply by SEW.
633 vemul -= veew; // Divide by EEW.
634 if (vemul < -3 || vemul > 3) {
635 // Incompatible vlmul
636 continue;
637 }
638
639 for (uint8_t vta = 0; vta < 2; ++vta) {
640 for (uint8_t vma = 0; vma < 2; ++vma) {
641 auto [vlmax, vtype] =
642 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
643 if (vlmax == 0) {
644 continue;
645 }
646 // Test vstart/vl changes with only with vemul == 2 (4 registers)
647 if (vemul == 2) {
648 state_.cpu.vstart = vlmax / 8;
649 state_.cpu.vl = (vlmax * 5) / 8;
650 } else {
651 state_.cpu.vstart = 0;
652 state_.cpu.vl = vlmax;
653 }
654 state_.cpu.vtype = vtype;
655
656 // Set expected_result vector registers into 0b01010101… pattern.
657 for (size_t index = 0; index < 8; ++index) {
658 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
659 }
660 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
661 SetXReg<1>(state_.cpu, ToGuestAddr(&source));
662 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
663 // Values for inactive elements (i.e. corresponding mask bit is 0).
664 const size_t n = std::size(source);
665 __m128i expected_inactive[n];
666 std::fill_n(expected_inactive, n, (vma ? kAgnosticResult : kUndisturbedResult));
667 if (vemul >= 0) {
668 for (size_t index = 0; index < 1 << vemul; ++index) {
669 if (index == 0 && vemul == 2) {
670 EXPECT_EQ(state_.cpu.v[8 + index],
671 SIMD128Register{
672 (kUndisturbedResult & kFractionMaskInt8[3]) |
673 (expected_result[index] & mask[index] & ~kFractionMaskInt8[3]) |
674 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3])}
675 .Get<__uint128_t>());
676 } else if (index == 2 && vemul == 2) {
677 EXPECT_EQ(
678 state_.cpu.v[8 + index],
679 SIMD128Register{
680 (expected_result[index] & mask[index] & kFractionMaskInt8[3]) |
681 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
682 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[3])}
683 .Get<__uint128_t>());
684 } else if (index == 3 && vemul == 2 && vta) {
685 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
686 } else if (index == 3 && vemul == 2) {
687 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult});
688 } else {
689 EXPECT_EQ(state_.cpu.v[8 + index],
690 SIMD128Register{(expected_result[index] & mask[index]) |
691 (expected_inactive[index] & ~mask[index])}
692 .Get<__uint128_t>());
693 }
694 }
695
696 } else {
697 EXPECT_EQ(state_.cpu.v[8],
698 SIMD128Register{
699 (expected_result[0] & mask[0] & kFractionMaskInt8[(vemul + 4)]) |
700 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[(vemul + 4)]) |
701 ((vta ? kAgnosticResult : kUndisturbedResult) &
702 ~kFractionMaskInt8[(vemul + 4)])}
703 .Get<__uint128_t>());
704 }
705 }
706 }
707 }
708 };
709 switch (veew) {
710 case 0:
711 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int8, kNoMask);
712 Verify(insn_bytes, veew, veew, 8, expected_result_int8, kMaskInt8);
713 break;
714 case 1:
715 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int16, kNoMask);
716 Verify(insn_bytes, veew, veew, 8, expected_result_int16, kMaskInt16);
717 break;
718 case 2:
719 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int32, kNoMask);
720 Verify(insn_bytes, veew, veew, 8, expected_result_int32, kMaskInt32);
721 break;
722 case 3:
723 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int64, kNoMask);
724 Verify(insn_bytes, veew, veew, 8, expected_result_int64, kMaskInt64);
725 break;
726 default:
727 break;
728 }
729 }
730
731 // Vector instructions.
TestVseXX(uint32_t insn_bytes,const __v16qu (& expected_result_int8)[8],const __v8hu (& expected_result_int16)[8],const __v4su (& expected_result_int32)[8],const __v2du (& expected_result_int64)[8],uint8_t veew,const __v2du (& source)[16])732 void TestVseXX(uint32_t insn_bytes,
733 const __v16qu (&expected_result_int8)[8],
734 const __v8hu (&expected_result_int16)[8],
735 const __v4su (&expected_result_int32)[8],
736 const __v2du (&expected_result_int64)[8],
737 uint8_t veew,
738 const __v2du (&source)[16]) {
739 auto Verify = [this, &source](uint32_t insn_bytes,
740 uint8_t vsew,
741 uint8_t veew,
742 uint8_t vlmul_max,
743 const auto& expected_result,
744 auto mask) {
745 SIMD128Register expected_result_in_register;
746 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
747 for (uint8_t vlmul = 0; vlmul < vlmul_max; ++vlmul) {
748 int vemul = SignExtend<3>(vlmul);
749 vemul += vsew; // Multiply by SEW.
750 vemul -= veew; // Divide by EEW.
751 if (vemul < -3 || vemul > 3) {
752 // Incompatible vlmul
753 continue;
754 }
755
756 for (uint8_t vma = 0; vma < 2; ++vma) {
757 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, (vma << 7) | (vsew << 3) | vlmul);
758 if (vlmax == 0) {
759 continue;
760 }
761 // Test vstart/vl changes with only with vemul == 2 (4 registers)
762 if (vemul == 2) {
763 state_.cpu.vstart = vlmax / 8;
764 state_.cpu.vl = (vlmax * 5) / 8;
765 } else {
766 state_.cpu.vstart = 0;
767 state_.cpu.vl = vlmax;
768 }
769 state_.cpu.vtype = vtype;
770
771 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
772 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
773 for (size_t index = 0; index < 8; index++) {
774 state_.cpu.v[8 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
775 store_area_[index * 2] = kUndisturbedResult[0];
776 store_area_[index * 2 + 1] = kUndisturbedResult[1];
777 }
778 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
779 // Values for inactive elements (i.e. corresponding mask bit is 0).
780 const size_t n = std::size(source);
781 __m128i expected_inactive[n];
782 std::fill_n(expected_inactive, n, kUndisturbedResult);
783 if (vemul >= 0) {
784 for (size_t index = 0; index < 1 << vemul; ++index) {
785 if (index == 0 && vemul == 2) {
786 expected_result_in_register = SIMD128Register{
787 (kUndisturbedResult & kFractionMaskInt8[3]) |
788 (expected_result[index] & mask[index] & ~kFractionMaskInt8[3]) |
789 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3])};
790 } else if (index == 2 && vemul == 2) {
791 expected_result_in_register = SIMD128Register{
792 (expected_result[index] & mask[index] & kFractionMaskInt8[3]) |
793 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
794 ((kUndisturbedResult) & ~kFractionMaskInt8[3])};
795 } else if (index == 3 && vemul == 2) {
796 expected_result_in_register = SIMD128Register{kUndisturbedResult};
797 } else {
798 expected_result_in_register =
799 SIMD128Register{(expected_result[index] & mask[index]) |
800 (expected_inactive[index] & ~mask[index])};
801 }
802
803 EXPECT_EQ(store_area_[index * 2], expected_result_in_register.Get<uint64_t>(0));
804 EXPECT_EQ(store_area_[index * 2 + 1], expected_result_in_register.Get<uint64_t>(1));
805 }
806
807 } else {
808 expected_result_in_register =
809 SIMD128Register{(expected_result[0] & mask[0] & kFractionMaskInt8[(vemul + 4)]) |
810 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[(vemul + 4)]) |
811 ((kUndisturbedResult) & ~kFractionMaskInt8[(vemul + 4)])};
812 EXPECT_EQ(store_area_[0], expected_result_in_register.Get<uint64_t>(0));
813 EXPECT_EQ(store_area_[1], expected_result_in_register.Get<uint64_t>(1));
814 }
815 }
816 }
817 };
818 switch (veew) {
819 case 0:
820 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int8, kNoMask);
821 Verify(insn_bytes, veew, veew, 8, expected_result_int8, kMaskInt8);
822 break;
823 case 1:
824 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int16, kNoMask);
825 Verify(insn_bytes, veew, veew, 8, expected_result_int16, kMaskInt16);
826 break;
827 case 2:
828 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int32, kNoMask);
829 Verify(insn_bytes, veew, veew, 8, expected_result_int32, kMaskInt32);
830 break;
831 case 3:
832 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int64, kNoMask);
833 Verify(insn_bytes, veew, veew, 8, expected_result_int64, kMaskInt64);
834 break;
835 default:
836 break;
837 }
838 }
839
840 template <int kNFfields>
TestVmvXr(uint32_t insn_bytes)841 void TestVmvXr(uint32_t insn_bytes) {
842 TestVmvXr<Int8, kNFfields>(insn_bytes);
843 TestVmvXr<Int16, kNFfields>(insn_bytes);
844 TestVmvXr<Int32, kNFfields>(insn_bytes);
845 TestVmvXr<Int64, kNFfields>(insn_bytes);
846 }
847
848 template <typename ElementType, int kNFfields>
TestVmvXr(uint32_t insn_bytes)849 void TestVmvXr(uint32_t insn_bytes) {
850 // Note that VmvXr actually DOES depend on vtype, contrary to what RISC-V V 1.0 manual says:
851 // https://github.com/riscv/riscv-v-spec/pull/872
852 state_.cpu.vtype = BitUtilLog2(sizeof(ElementType)) << 3;
853 state_.cpu.vl = 0;
854 constexpr int kElementsCount = static_cast<int>(sizeof(SIMD128Register) / sizeof(ElementType));
855 for (int vstart = 0; vstart <= kElementsCount * kNFfields; ++vstart) {
856 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
857 state_.cpu.vstart = vstart;
858 for (size_t index = 0; index < 16; ++index) {
859 state_.cpu.v[8 + index] =
860 SIMD128Register{kVectorComparisonSource[index]}.Get<__uint128_t>();
861 }
862 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
863 for (int index = 0; index < 8; ++index) {
864 SIMD128Register expected_state{kVectorComparisonSource[index]};
865 SIMD128Register source_value{kVectorComparisonSource[index + 8]};
866 if ((vstart < kElementsCount * kNFfields) && index < kNFfields) {
867 // The usual property that no elements are written if vstart >= vl does not apply to these
868 // instructions. Instead, no elements are written if vstart >= evl.
869 for (int element_index = 0; element_index < kElementsCount; ++element_index) {
870 if (element_index + index * kElementsCount >= vstart) {
871 expected_state.Set(source_value.Get<ElementType>(element_index), element_index);
872 }
873 }
874 }
875 EXPECT_EQ(state_.cpu.v[8 + index], expected_state.Get<__uint128_t>());
876 }
877 EXPECT_EQ(state_.cpu.vstart, 0);
878 }
879 }
880
881 template <typename ElementType>
TestVfmvfs(uint32_t insn_bytes,uint64_t expected_result)882 void TestVfmvfs(uint32_t insn_bytes, uint64_t expected_result) {
883 state_.cpu.vtype = BitUtilLog2(sizeof(ElementType)) << 3;
884 state_.cpu.vstart = 0;
885 state_.cpu.vl = 0;
886 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
887 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
888 SetFReg<1>(state_.cpu, 0x5555'5555'5555'5555);
889 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
890 EXPECT_EQ(GetFReg<1>(state_.cpu), expected_result);
891 }
892
893 template <typename ElementType>
TestVfmvsf(uint32_t insn_bytes,uint64_t boxed_value,ElementType unboxed_value)894 void TestVfmvsf(uint32_t insn_bytes, uint64_t boxed_value, ElementType unboxed_value) {
895 for (uint8_t vstart = 0; vstart < 2; ++vstart) {
896 for (uint8_t vl = 0; vl < 2; ++vl) {
897 for (uint8_t vta = 0; vta < 2; ++vta) {
898 state_.cpu.vtype = (vta << 6) | (BitUtilLog2(sizeof(ElementType)) << 3);
899 state_.cpu.vstart = vstart;
900 state_.cpu.vl = vl;
901 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
902 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
903 SetFReg<1>(state_.cpu, boxed_value);
904 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
905 if (vstart == 0 && vl != 0) {
906 SIMD128Register expected_result =
907 vta ? ~SIMD128Register{} : SIMD128Register{kVectorCalculationsSource[0]};
908 expected_result.Set<ElementType>(unboxed_value, 0);
909 EXPECT_EQ(state_.cpu.v[8], expected_result);
910 } else {
911 EXPECT_EQ(state_.cpu.v[8],
912 SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>());
913 }
914 }
915 }
916 }
917 }
918
919 template <typename ElementType>
TestVmvsx(uint32_t insn_bytes)920 void TestVmvsx(uint32_t insn_bytes) {
921 for (uint8_t vstart = 0; vstart < 2; ++vstart) {
922 for (uint8_t vl = 0; vl < 2; ++vl) {
923 for (uint8_t vta = 0; vta < 2; ++vta) {
924 state_.cpu.vtype = (vta << 6) | (BitUtilLog2(sizeof(ElementType)) << 3);
925 state_.cpu.vstart = vstart;
926 state_.cpu.vl = vl;
927 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
928 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
929 SetXReg<1>(state_.cpu, 0x5555'5555'5555'5555);
930 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
931 if (vstart == 0 && vl != 0) {
932 SIMD128Register expected_result =
933 vta ? ~SIMD128Register{} : SIMD128Register{kVectorCalculationsSource[0]};
934 expected_result.Set<ElementType>(MaybeTruncateTo<ElementType>(0x5555'5555'5555'5555),
935 0);
936 EXPECT_EQ(state_.cpu.v[8], expected_result);
937 } else {
938 EXPECT_EQ(state_.cpu.v[8],
939 SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>());
940 }
941 }
942 }
943 }
944 }
945
946 template <typename ElementType>
TestVmvxs(uint32_t insn_bytes,uint64_t expected_result)947 void TestVmvxs(uint32_t insn_bytes, uint64_t expected_result) {
948 state_.cpu.vtype = BitUtilLog2(sizeof(ElementType)) << 3;
949 state_.cpu.vstart = 0;
950 state_.cpu.vl = 0;
951 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
952 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
953 SetXReg<1>(state_.cpu, 0x5555'5555'5555'5555);
954 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
955 EXPECT_EQ(GetXReg<1>(state_.cpu), expected_result);
956 }
957
958 template <size_t kNFfields>
TestVsX(uint32_t insn_bytes)959 void TestVsX(uint32_t insn_bytes) {
960 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
961 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
962 for (size_t index = 0; index < 8; index++) {
963 state_.cpu.v[8 + index] = SIMD128Register{kVectorComparisonSource[index]}.Get<__uint128_t>();
964 store_area_[index * 2] = kUndisturbedResult[0];
965 store_area_[index * 2 + 1] = kUndisturbedResult[1];
966 }
967 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
968 for (size_t index = 0; index < 8; index++) {
969 EXPECT_EQ(
970 store_area_[index * 2],
971 (index >= kNFfields ? kUndisturbedResult[0]
972 : SIMD128Register{kVectorComparisonSource[index]}.Get<uint64_t>(0)));
973 EXPECT_EQ(
974 store_area_[index * 2 + 1],
975 (index >= kNFfields ? kUndisturbedResult[1]
976 : SIMD128Register{kVectorComparisonSource[index]}.Get<uint64_t>(1)));
977 }
978 }
979
TestVectorRegisterGather(uint32_t insn_bytes,const __v16qu (& expected_result_int8)[8],const __v8hu (& expected_result_int16)[8],const __v4su (& expected_result_int32)[8],const __v2du (& expected_result_int64)[8],const uint8_t vlmul,const __v2du (& source)[16])980 void TestVectorRegisterGather(uint32_t insn_bytes,
981 const __v16qu (&expected_result_int8)[8],
982 const __v8hu (&expected_result_int16)[8],
983 const __v4su (&expected_result_int32)[8],
984 const __v2du (&expected_result_int64)[8],
985 const uint8_t vlmul,
986 const __v2du (&source)[16]) {
987 auto Verify = [this, &source, &vlmul](
988 uint32_t insn_bytes, uint8_t vsew, const auto& expected_result, auto mask) {
989 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
990 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
991 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
992 for (size_t index = 0; index < 8; ++index) {
993 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
994 }
995
996 for (uint8_t vta = 0; vta < 2; ++vta) {
997 for (uint8_t vma = 0; vma < 2; ++vma) {
998 auto [vlmax, vtype] =
999 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1000 // Incompatible vsew and vlmax. Skip it.
1001 if (vlmax == 0) {
1002 continue;
1003 }
1004
1005 // Make sure indexes in src2 fall within vlmax.
1006 uint64_t src2_mask{0};
1007 const size_t kElementSize = 8 << vsew;
1008 const uint64_t kIndexMask = (1 << BitUtilLog2(vlmax)) - 1;
1009 for (uint8_t index = 0; index < 64 / kElementSize; index++) {
1010 src2_mask |= kIndexMask << (kElementSize * index);
1011 }
1012 for (size_t index = 0; index < 8; ++index) {
1013 __v2du masked_register = {source[8 + index][0] & src2_mask, source[8 + index][1]};
1014 state_.cpu.v[24 + index] = SIMD128Register{masked_register}.Get<__uint128_t>();
1015 }
1016 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaaULL & kIndexMask);
1017
1018 // To make tests quick enough we don't test vstart and vl change with small register
1019 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of
1020 // first
1021 // register and half of last register.
1022 if (vlmul == 2) {
1023 state_.cpu.vstart = vlmax / 8;
1024 state_.cpu.vl = (vlmax * 5) / 8;
1025 } else {
1026 state_.cpu.vstart = 0;
1027 state_.cpu.vl = vlmax;
1028 }
1029 state_.cpu.vtype = vtype;
1030
1031 // Set expected_result vector registers into 0b01010101… pattern.
1032 for (size_t index = 0; index < 8; ++index) {
1033 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1034 }
1035
1036 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1037 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1038
1039 // Values for inactive elements (i.e. corresponding mask bit is 0).
1040 const size_t n = std::size(source) * 2;
1041 __m128i expected_inactive[n];
1042 // For most instructions, follow basic inactive processing rules based on vma flag.
1043 std::fill_n(expected_inactive, n, (vma ? kAgnosticResult : kUndisturbedResult));
1044
1045 if (vlmul < 4) {
1046 for (size_t index = 0; index < 1 << vlmul; ++index) {
1047 if (index == 0 && vlmul == 2) {
1048 EXPECT_EQ(state_.cpu.v[8 + index],
1049 SIMD128Register{
1050 (kUndisturbedResult & kFractionMaskInt8[3]) |
1051 (expected_result[index] & mask[index] & ~kFractionMaskInt8[3]) |
1052 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3])}
1053 .Get<__uint128_t>());
1054 } else if (index == 2 && vlmul == 2) {
1055 EXPECT_EQ(
1056 state_.cpu.v[8 + index],
1057 SIMD128Register{
1058 (expected_result[index] & mask[index] & kFractionMaskInt8[3]) |
1059 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
1060 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[3])}
1061 .Get<__uint128_t>());
1062 } else if (index == 3 && vlmul == 2 && vta) {
1063 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1064 } else if (index == 3 && vlmul == 2) {
1065 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult});
1066 } else {
1067 EXPECT_EQ(state_.cpu.v[8 + index],
1068 SIMD128Register{(expected_result[index] & mask[index]) |
1069 (expected_inactive[index] & ~mask[index])}
1070 .Get<__uint128_t>());
1071 }
1072 }
1073 } else {
1074 EXPECT_EQ(
1075 state_.cpu.v[8],
1076 SIMD128Register{
1077 (expected_result[0] & mask[0] & kFractionMaskInt8[vlmul - 4]) |
1078 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[vlmul - 4]) |
1079 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[vlmul - 4])}
1080 .Get<__uint128_t>());
1081 }
1082
1083 if (vlmul == 2) {
1084 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1085 EXPECT_EQ(state_.cpu.vstart, 0);
1086 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1087 }
1088 }
1089 }
1090 };
1091 Verify(insn_bytes, 0, expected_result_int8, kMaskInt8);
1092 Verify(insn_bytes | (1 << 25), 0, expected_result_int8, kNoMask);
1093 Verify(insn_bytes, 1, expected_result_int16, kMaskInt16);
1094 Verify(insn_bytes | (1 << 25), 1, expected_result_int16, kNoMask);
1095 Verify(insn_bytes, 2, expected_result_int32, kMaskInt32);
1096 Verify(insn_bytes | (1 << 25), 2, expected_result_int32, kNoMask);
1097 Verify(insn_bytes, 3, expected_result_int64, kMaskInt64);
1098 Verify(insn_bytes | (1 << 25), 3, expected_result_int64, kNoMask);
1099 }
1100
TestVectorFloatInstruction(uint32_t insn_bytes,const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16])1101 void TestVectorFloatInstruction(uint32_t insn_bytes,
1102 const UInt32x4Tuple (&expected_result_int32)[8],
1103 const UInt64x2Tuple (&expected_result_int64)[8],
1104 const __v2du (&source)[16]) {
1105 TestVectorInstruction<TestVectorInstructionKind::kFloat, TestVectorInstructionMode::kDefault>(
1106 insn_bytes, source, expected_result_int32, expected_result_int64);
1107 }
1108
TestVectorInstruction(uint32_t insn_bytes,const UInt8x16Tuple (& expected_result_int8)[8],const UInt16x8Tuple (& expected_result_int16)[8],const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16])1109 void TestVectorInstruction(uint32_t insn_bytes,
1110 const UInt8x16Tuple (&expected_result_int8)[8],
1111 const UInt16x8Tuple (&expected_result_int16)[8],
1112 const UInt32x4Tuple (&expected_result_int32)[8],
1113 const UInt64x2Tuple (&expected_result_int64)[8],
1114 const __v2du (&source)[16]) {
1115 TestVectorInstruction<TestVectorInstructionKind::kInteger, TestVectorInstructionMode::kDefault>(
1116 insn_bytes,
1117 source,
1118 expected_result_int8,
1119 expected_result_int16,
1120 expected_result_int32,
1121 expected_result_int64);
1122 }
1123
TestVectorMergeFloatInstruction(uint32_t insn_bytes,const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16])1124 void TestVectorMergeFloatInstruction(uint32_t insn_bytes,
1125 const UInt32x4Tuple (&expected_result_int32)[8],
1126 const UInt64x2Tuple (&expected_result_int64)[8],
1127 const __v2du (&source)[16]) {
1128 TestVectorInstruction<TestVectorInstructionKind::kFloat, TestVectorInstructionMode::kVMerge>(
1129 insn_bytes, source, expected_result_int32, expected_result_int64);
1130 }
1131
TestVectorMergeInstruction(uint32_t insn_bytes,const UInt8x16Tuple (& expected_result_int8)[8],const UInt16x8Tuple (& expected_result_int16)[8],const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16])1132 void TestVectorMergeInstruction(uint32_t insn_bytes,
1133 const UInt8x16Tuple (&expected_result_int8)[8],
1134 const UInt16x8Tuple (&expected_result_int16)[8],
1135 const UInt32x4Tuple (&expected_result_int32)[8],
1136 const UInt64x2Tuple (&expected_result_int64)[8],
1137 const __v2du (&source)[16]) {
1138 TestVectorInstruction<TestVectorInstructionKind::kInteger, TestVectorInstructionMode::kVMerge>(
1139 insn_bytes,
1140 source,
1141 expected_result_int8,
1142 expected_result_int16,
1143 expected_result_int32,
1144 expected_result_int64);
1145 }
1146
TestWideningVectorFloatInstruction(uint32_t insn_bytes,const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16],__m128i dst_result=kUndisturbedResult)1147 void TestWideningVectorFloatInstruction(uint32_t insn_bytes,
1148 const UInt64x2Tuple (&expected_result_int64)[8],
1149 const __v2du (&source)[16],
1150 __m128i dst_result = kUndisturbedResult) {
1151 TestVectorInstructionInternal<TestVectorInstructionKind::kFloat,
1152 TestVectorInstructionMode::kWidening>(
1153 insn_bytes, dst_result, source, expected_result_int64);
1154 }
1155
TestWideningVectorFloatInstruction(uint32_t insn_bytes,const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16])1156 void TestWideningVectorFloatInstruction(uint32_t insn_bytes,
1157 const UInt32x4Tuple (&expected_result_int32)[8],
1158 const UInt64x2Tuple (&expected_result_int64)[8],
1159 const __v2du (&source)[16]) {
1160 TestVectorInstruction<TestVectorInstructionKind::kFloat, TestVectorInstructionMode::kWidening>(
1161 insn_bytes, source, expected_result_int32, expected_result_int64);
1162 }
1163
1164 enum class TestVectorInstructionKind { kInteger, kFloat };
1165 enum class TestVectorInstructionMode { kDefault, kWidening, kNarrowing, kVMerge };
1166
1167 template <TestVectorInstructionKind kTestVectorInstructionKind,
1168 TestVectorInstructionMode kTestVectorInstructionMode,
1169 typename... ExpectedResultType>
TestVectorInstruction(uint32_t insn_bytes,const __v2du (& source)[16],const ExpectedResultType &...expected_result)1170 void TestVectorInstruction(uint32_t insn_bytes,
1171 const __v2du (&source)[16],
1172 const ExpectedResultType&... expected_result) {
1173 TestVectorInstructionInternal<kTestVectorInstructionKind, kTestVectorInstructionMode>(
1174 insn_bytes, kUndisturbedResult, source, expected_result...);
1175 }
1176
1177 template <TestVectorInstructionKind kTestVectorInstructionKind,
1178 TestVectorInstructionMode kTestVectorInstructionMode,
1179 typename... ExpectedResultType>
TestVectorInstructionInternal(uint32_t insn_bytes,__m128i dst_result,const __v2du (& source)[16],const ExpectedResultType &...expected_result)1180 void TestVectorInstructionInternal(uint32_t insn_bytes,
1181 __m128i dst_result,
1182 const __v2du (&source)[16],
1183 const ExpectedResultType&... expected_result) {
1184 auto Verify = [this, &source, dst_result](uint32_t insn_bytes,
1185 uint8_t vsew,
1186 uint8_t vlmul_max,
1187 const auto& expected_result,
1188 auto mask) {
1189 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1190 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1191 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1192 for (size_t index = 0; index < std::size(source); ++index) {
1193 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1194 }
1195 if (kTestVectorInstructionKind == TestVectorInstructionKind::kInteger) {
1196 // Set x1 for vx instructions.
1197 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1198 } else {
1199 // We only support Float32/Float64 for float instructions, but there are conversion
1200 // instructions that work with double width floats.
1201 // These instructions never use float registers though and thus we don't need to store
1202 // anything into f1 register, if they are used.
1203 // For Float32/Float64 case we load 5.625 of the appropriate type into f1.
1204 ASSERT_LE(vsew, 3);
1205 if (vsew == 2) {
1206 SetFReg<1>(state_.cpu, 0xffff'ffff'40b4'0000); // float 5.625
1207 } else if (vsew == 3) {
1208 SetFReg<1>(state_.cpu, 0x4016'8000'0000'0000); // double 5.625
1209 }
1210 }
1211 for (uint8_t vlmul = 0; vlmul < vlmul_max; ++vlmul) {
1212 if constexpr (kTestVectorInstructionMode == TestVectorInstructionMode::kNarrowing ||
1213 kTestVectorInstructionMode == TestVectorInstructionMode::kWidening) {
1214 // Incompatible vlmul for narrowing.
1215 if (vlmul == 3) {
1216 continue;
1217 }
1218 }
1219 for (uint8_t vta = 0; vta < 2; ++vta) {
1220 for (uint8_t vma = 0; vma < 2; ++vma) {
1221 auto [vlmax, vtype] =
1222 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1223 // Incompatible vsew and vlmax. Skip it.
1224 if (vlmax == 0) {
1225 continue;
1226 }
1227 uint8_t emul =
1228 (vlmul + (kTestVectorInstructionMode == TestVectorInstructionMode::kWidening)) &
1229 0b111;
1230
1231 // To make tests quick enough we don't test vstart and vl change with small register
1232 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1233 // register, last register and half of next-to last register.
1234 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1235 // result.
1236 if (emul == 2) {
1237 state_.cpu.vstart = vlmax / 8;
1238 state_.cpu.vl = (vlmax * 5) / 8;
1239 } else {
1240 state_.cpu.vstart = 0;
1241 state_.cpu.vl = vlmax;
1242 }
1243 state_.cpu.vtype = vtype;
1244
1245 // Set expected_result vector registers into 0b01010101… pattern.
1246 for (size_t index = 0; index < 8; ++index) {
1247 state_.cpu.v[8 + index] = SIMD128Register{dst_result}.Get<__uint128_t>();
1248 }
1249
1250 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1251 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1252
1253 // Values for inactive elements (i.e. corresponding mask bit is 0).
1254 __m128i expected_inactive[8];
1255 if constexpr (kTestVectorInstructionMode == TestVectorInstructionMode::kVMerge) {
1256 // vs2 is the start of the source vector register group.
1257 // Note: copy_n input/output args are backwards compared to fill_n below.
1258 std::copy_n(source, 8, expected_inactive);
1259 } else {
1260 // For most instructions, follow basic inactive processing rules based on vma flag.
1261 std::fill_n(expected_inactive, 8, (vma ? kAgnosticResult : dst_result));
1262 }
1263
1264 if (emul < 4) {
1265 for (size_t index = 0; index < 1 << emul; ++index) {
1266 if (index == 0 && emul == 2) {
1267 EXPECT_EQ(state_.cpu.v[8 + index],
1268 ((dst_result & kFractionMaskInt8[3]) |
1269 (SIMD128Register{expected_result[index]} & mask[index] &
1270 ~kFractionMaskInt8[3]) |
1271 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3]))
1272 .template Get<__uint128_t>());
1273 } else if (index == 2 && emul == 2) {
1274 EXPECT_EQ(state_.cpu.v[8 + index],
1275 ((SIMD128Register{expected_result[index]} & mask[index] &
1276 kFractionMaskInt8[3]) |
1277 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
1278 ((vta ? kAgnosticResult : dst_result) & ~kFractionMaskInt8[3]))
1279 .template Get<__uint128_t>());
1280 } else if (index == 3 && emul == 2 && vta) {
1281 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1282 } else if (index == 3 && emul == 2) {
1283 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{dst_result});
1284 } else {
1285 EXPECT_EQ(state_.cpu.v[8 + index],
1286 ((SIMD128Register{expected_result[index]} & mask[index]) |
1287 ((expected_inactive[index] & ~mask[index])))
1288 .template Get<__uint128_t>());
1289 }
1290 }
1291 } else {
1292 EXPECT_EQ(
1293 state_.cpu.v[8],
1294 ((SIMD128Register{expected_result[0]} & mask[0] & kFractionMaskInt8[emul - 4]) |
1295 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[emul - 4]) |
1296 ((vta ? kAgnosticResult : dst_result) & ~kFractionMaskInt8[emul - 4]))
1297 .template Get<__uint128_t>());
1298 }
1299
1300 if (emul == 2) {
1301 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1302 EXPECT_EQ(state_.cpu.vstart, 0);
1303 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1304 }
1305 }
1306 }
1307 }
1308 };
1309
1310 // Some instructions don't support use of mask register, but in these instructions bit
1311 // #25 is set. This function doesn't support these. Verify that vm bit is not set.
1312 EXPECT_EQ(insn_bytes & (1 << 25), 0U);
1313 // Every insruction is tested with vm bit not set (and mask register used) and with vm bit
1314 // set (and mask register is not used).
1315 ((Verify(insn_bytes,
1316 BitUtilLog2(sizeof(std::remove_cvref_t<decltype(std::get<0>(expected_result[0]))>)) -
1317 (kTestVectorInstructionMode == TestVectorInstructionMode::kWidening),
1318 8,
1319 expected_result,
1320 MaskForElem<std::remove_cvref_t<decltype(std::get<0>(expected_result[0]))>>()),
1321 Verify((insn_bytes &
1322 ~(0x01f00000 * (kTestVectorInstructionMode == TestVectorInstructionMode::kVMerge))) |
1323 (1 << 25),
1324 BitUtilLog2(sizeof(std::remove_cvref_t<decltype(std::get<0>(expected_result[0]))>)) -
1325 (kTestVectorInstructionMode == TestVectorInstructionMode::kWidening),
1326 8,
1327 expected_result,
1328 kNoMask)),
1329 ...);
1330 }
1331
TestVectorMaskInstruction(uint8_t max_vstart,intrinsics::InactiveProcessing vma,uint32_t insn_bytes,const __v2du expected_result)1332 void TestVectorMaskInstruction(uint8_t max_vstart,
1333 intrinsics::InactiveProcessing vma,
1334 uint32_t insn_bytes,
1335 const __v2du expected_result) {
1336 // Mask instructions don't look on vtype directly, but they still require valid one because it
1337 // affects vlmax;
1338 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, 3 | (static_cast<uint8_t>(vma) << 7));
1339 // We need mask with a few bits set for Vmsₓf instructions. Inverse of normal kMask works.
1340 const __uint128_t mask = SIMD128Register{~kMask}.Get<__uint128_t>();
1341 const __uint128_t undisturbed = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1342 const __uint128_t src1 = SIMD128Register{kVectorCalculationsSourceLegacy[0]}.Get<__uint128_t>();
1343 const __uint128_t src2 = SIMD128Register{kVectorCalculationsSourceLegacy[8]}.Get<__uint128_t>();
1344 const __uint128_t expected = SIMD128Register{expected_result}.Get<__uint128_t>();
1345 state_.cpu.vtype = vtype;
1346 for (uint8_t vl = 0; vl <= vlmax; ++vl) {
1347 state_.cpu.vl = vl;
1348 for (uint8_t vstart = 0; vstart <= max_vstart; ++vstart) {
1349 state_.cpu.vstart = vstart;
1350 // Set expected_result vector registers into 0b01010101… pattern.
1351 state_.cpu.v[0] = mask;
1352 state_.cpu.v[8] = undisturbed;
1353 state_.cpu.v[16] = src1;
1354 state_.cpu.v[24] = src2;
1355
1356 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1357 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1358
1359 for (uint8_t bit_pos = 0; bit_pos < 128; ++bit_pos) {
1360 __uint128_t bit = __uint128_t{1} << bit_pos;
1361 // When vstart ⩾ vl, there are no body elements, and no elements are updated in any
1362 // destinationvector register group, including that no tail elements are updated with
1363 // agnostic values.
1364 if (bit_pos < vstart || vstart >= vl) {
1365 EXPECT_EQ(state_.cpu.v[8] & bit, undisturbed & bit);
1366 } else if (bit_pos >= vl) {
1367 EXPECT_EQ(state_.cpu.v[8] & bit, bit);
1368 } else {
1369 EXPECT_EQ(state_.cpu.v[8] & bit, expected & bit);
1370 }
1371 }
1372 }
1373 }
1374 }
1375
1376 template <typename ElementType>
MaskForElem()1377 auto MaskForElem() {
1378 if constexpr (std::is_same_v<ElementType, uint8_t>) {
1379 return kMaskInt8;
1380 } else if constexpr (std::is_same_v<ElementType, uint16_t>) {
1381 return kMaskInt16;
1382 } else if constexpr (std::is_same_v<ElementType, uint32_t>) {
1383 return kMaskInt32;
1384 } else if constexpr (std::is_same_v<ElementType, uint64_t>) {
1385 return kMaskInt64;
1386 } else {
1387 static_assert(kDependentTypeFalse<ElementType>);
1388 }
1389 }
1390
TestVectorMaskTargetInstruction(uint32_t insn_bytes,const uint32_t expected_result_int32,const uint16_t expected_result_int64,const __v2du (& source)[16])1391 void TestVectorMaskTargetInstruction(uint32_t insn_bytes,
1392 const uint32_t expected_result_int32,
1393 const uint16_t expected_result_int64,
1394 const __v2du (&source)[16]) {
1395 TestVectorMaskTargetInstruction(
1396 insn_bytes, source, expected_result_int32, expected_result_int64);
1397 }
1398
TestVectorMaskTargetInstruction(uint32_t insn_bytes,const UInt8x16Tuple (& expected_result_int8),const uint64_t expected_result_int16,const uint32_t expected_result_int32,const uint16_t expected_result_int64,const __v2du (& source)[16])1399 void TestVectorMaskTargetInstruction(uint32_t insn_bytes,
1400 const UInt8x16Tuple(&expected_result_int8),
1401 const uint64_t expected_result_int16,
1402 const uint32_t expected_result_int32,
1403 const uint16_t expected_result_int64,
1404 const __v2du (&source)[16]) {
1405 TestVectorMaskTargetInstruction(insn_bytes,
1406 source,
1407 expected_result_int8,
1408 expected_result_int16,
1409 expected_result_int32,
1410 expected_result_int64);
1411 }
1412
1413 template <typename... ExpectedResultType>
TestVectorMaskTargetInstruction(uint32_t insn_bytes,const __v2du (& source)[16],const ExpectedResultType (&...expected_result))1414 void TestVectorMaskTargetInstruction(uint32_t insn_bytes,
1415 const __v2du (&source)[16],
1416 const ExpectedResultType(&... expected_result)) {
1417 auto Verify = [this, &source](
1418 uint32_t insn_bytes, uint8_t vsew, const auto& expected_result, auto mask) {
1419 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1420 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1421 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1422 for (size_t index = 0; index < std::size(source); ++index) {
1423 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1424 }
1425 // Set x1 for vx instructions.
1426 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1427 // Set f1 for vf instructions.
1428 if (vsew == 2) {
1429 SetFReg<1>(state_.cpu, 0xffff'ffff'40b4'0000); // float 5.625
1430 } else if (vsew == 3) {
1431 SetFReg<1>(state_.cpu, 0x4016'8000'0000'0000); // double 5.625
1432 }
1433 for (uint8_t vlmul = 0; vlmul < 8; ++vlmul) {
1434 for (uint8_t vta = 0; vta < 2; ++vta) { // vta should be ignored but we test both values!
1435 for (uint8_t vma = 0; vma < 2; ++vma) {
1436 auto [vlmax, vtype] =
1437 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1438 // Incompatible vsew and vlmax. Skip it.
1439 if (vlmax == 0) {
1440 continue;
1441 }
1442
1443 // To make tests quick enough we don't test vstart and vl change with small register
1444 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1445 // register, last register and half of next-to last register.
1446 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1447 // result.
1448 if (vlmul == 2) {
1449 state_.cpu.vstart = vlmax / 8;
1450 state_.cpu.vl = (vlmax * 5) / 8;
1451 } else {
1452 state_.cpu.vstart = 0;
1453 state_.cpu.vl = vlmax;
1454 }
1455 state_.cpu.vtype = vtype;
1456
1457 // Set expected_result vector registers into 0b01010101… pattern.
1458 for (size_t index = 0; index < 8; ++index) {
1459 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1460 }
1461
1462 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1463 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1464
1465 SIMD128Register expected_result_in_register(expected_result);
1466 if (vma == 0) {
1467 expected_result_in_register = (expected_result_in_register & SIMD128Register{mask}) |
1468 (kUndisturbedResult & ~SIMD128Register{mask});
1469 } else {
1470 expected_result_in_register = expected_result_in_register | ~SIMD128Register{mask};
1471 }
1472 // Mask registers are always processing tail like vta is set.
1473 if (vlmax != 128)
1474 expected_result_in_register |= std::get<0>(
1475 intrinsics::MakeBitmaskFromVl((vlmul == 2) ? (vlmax * 5) / 8 : vlmax));
1476 if (vlmul == 2) {
1477 const auto [start_mask] = intrinsics::MakeBitmaskFromVl(vlmax / 8);
1478 expected_result_in_register = (SIMD128Register{kUndisturbedResult} & ~start_mask) |
1479 (expected_result_in_register & start_mask);
1480 }
1481 EXPECT_EQ(state_.cpu.v[8], expected_result_in_register);
1482
1483 if (vlmul == 2) {
1484 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1485 EXPECT_EQ(state_.cpu.vstart, 0);
1486 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1487 }
1488 }
1489 }
1490 }
1491 };
1492
1493 ((Verify(insn_bytes,
1494 BitUtilLog2(sizeof(SIMD128Register) / sizeof(ExpectedResultType)),
1495 expected_result,
1496 kMask),
1497 Verify(insn_bytes | (1 << 25),
1498 BitUtilLog2(sizeof(SIMD128Register) / sizeof(ExpectedResultType)),
1499 expected_result,
1500 kNoMask[0])),
1501 ...);
1502 }
1503
TestVectorCarryInstruction(uint32_t insn_bytes,const UInt8x16Tuple (& expected_result_int8)[8],const UInt16x8Tuple (& expected_result_int16)[8],const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16])1504 void TestVectorCarryInstruction(uint32_t insn_bytes,
1505 const UInt8x16Tuple (&expected_result_int8)[8],
1506 const UInt16x8Tuple (&expected_result_int16)[8],
1507 const UInt32x4Tuple (&expected_result_int32)[8],
1508 const UInt64x2Tuple (&expected_result_int64)[8],
1509 const __v2du (&source)[16]) {
1510 auto Verify = [this, &source](uint32_t insn_bytes, uint8_t vsew, const auto& expected_result) {
1511 __m128i dst_result = kUndisturbedResult;
1512
1513 // Set mask register
1514 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1515
1516 // Set source registers
1517 for (size_t index = 0; index < std::size(source); ++index) {
1518 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1519 }
1520
1521 // Set x1 for vx instructions.
1522 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1523
1524 for (uint8_t vlmul = 0; vlmul < 8; ++vlmul) {
1525 for (uint8_t vta = 0; vta < 2; ++vta) {
1526 uint8_t vma = 0;
1527 auto [vlmax, vtype] =
1528 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1529 // Incompatible vsew and vlmax. Skip it.
1530 if (vlmax == 0) {
1531 continue;
1532 }
1533 uint8_t emul = vlmul & 0b111;
1534
1535 // To make tests quick enough we don't test vstart and vl change with small register
1536 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1537 // register, last register and half of next-to last register.
1538 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1539 // result.
1540 if (vlmul == 2) {
1541 state_.cpu.vstart = vlmax / 8;
1542 state_.cpu.vl = (vlmax * 5) / 8;
1543 } else {
1544 state_.cpu.vstart = 0;
1545 state_.cpu.vl = vlmax;
1546 }
1547 state_.cpu.vtype = vtype;
1548
1549 // Set expected_result vector registers into 0b01010101… pattern.
1550 for (size_t index = 0; index < 8; ++index) {
1551 state_.cpu.v[8 + index] = SIMD128Register{dst_result}.Get<__uint128_t>();
1552 }
1553
1554 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1555 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1556
1557 if (emul < 4) {
1558 for (size_t index = 0; index < 1 << emul; ++index) {
1559 if (index == 0 && emul == 2) {
1560 EXPECT_EQ(state_.cpu.v[8 + index],
1561 ((dst_result & kFractionMaskInt8[3]) |
1562 (SIMD128Register{expected_result[index]} & ~kFractionMaskInt8[3]))
1563 .template Get<__uint128_t>());
1564 } else if (index == 2 && emul == 2) {
1565 EXPECT_EQ(state_.cpu.v[8 + index],
1566 ((SIMD128Register{expected_result[index]} & kFractionMaskInt8[3]) |
1567 ((vta ? kAgnosticResult : dst_result) & ~kFractionMaskInt8[3]))
1568 .template Get<__uint128_t>());
1569 } else if (index == 3 && emul == 2 && vta) {
1570 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1571 } else if (index == 3 && emul == 2) {
1572 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{dst_result});
1573 } else {
1574 EXPECT_EQ(state_.cpu.v[8 + index],
1575 (SIMD128Register{expected_result[index]}).template Get<__uint128_t>());
1576 }
1577 }
1578 } else {
1579 EXPECT_EQ(state_.cpu.v[8],
1580 ((SIMD128Register{expected_result[0]} & kFractionMaskInt8[emul - 4]) |
1581 ((vta ? kAgnosticResult : dst_result) & ~kFractionMaskInt8[emul - 4]))
1582 .template Get<__uint128_t>());
1583 }
1584
1585 if (emul == 2) {
1586 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1587 EXPECT_EQ(state_.cpu.vstart, 0);
1588 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1589 }
1590 }
1591 }
1592 };
1593
1594 // Some instructions don't support use of mask register, but in these instructions bit
1595 // #25 is set. This function doesn't support these. Verify that vm bit is not set.
1596 EXPECT_EQ(insn_bytes & (1 << 25), 0U);
1597
1598 Verify(insn_bytes, 0, expected_result_int8);
1599 Verify(insn_bytes, 1, expected_result_int16);
1600 Verify(insn_bytes, 2, expected_result_int32);
1601 Verify(insn_bytes, 3, expected_result_int64);
1602 }
1603
TestVXmXXsInstruction(uint32_t insn_bytes,const uint64_t (& expected_result_no_mask)[129],const uint64_t (& expected_result_with_mask)[129],const __v2du source)1604 void TestVXmXXsInstruction(uint32_t insn_bytes,
1605 const uint64_t (&expected_result_no_mask)[129],
1606 const uint64_t (&expected_result_with_mask)[129],
1607 const __v2du source) {
1608 auto Verify = [this, &source](uint32_t insn_bytes,
1609 const uint64_t (&expected_result)[129]) {
1610 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1611
1612 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, 3);
1613 state_.cpu.vtype = vtype;
1614 state_.cpu.vstart = 0;
1615 state_.cpu.v[16] = SIMD128Register{source}.Get<__uint128_t>();
1616
1617 for (uint8_t vl = 0; vl <= vlmax; ++vl) {
1618 state_.cpu.vl = vl;
1619 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1620
1621 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1622 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1623 EXPECT_EQ(GetXReg<1>(state_.cpu), expected_result[vl]) << std::to_string(vl);
1624 }
1625 };
1626
1627 Verify(insn_bytes, expected_result_with_mask);
1628 Verify(insn_bytes | (1 << 25), expected_result_no_mask);
1629 }
1630
TestVectorFloatPermutationInstruction(uint32_t insn_bytes,const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16],uint8_t vlmul,uint64_t skip=0,bool ignore_vma_for_last=false,bool last_elem_is_f1=false)1631 void TestVectorFloatPermutationInstruction(uint32_t insn_bytes,
1632 const UInt32x4Tuple (&expected_result_int32)[8],
1633 const UInt64x2Tuple (&expected_result_int64)[8],
1634 const __v2du (&source)[16],
1635 uint8_t vlmul,
1636 uint64_t skip = 0,
1637 bool ignore_vma_for_last = false,
1638 bool last_elem_is_f1 = false) {
1639 TestVectorPermutationInstruction<TestVectorInstructionKind::kFloat>(insn_bytes,
1640 source,
1641 vlmul,
1642 skip,
1643 ignore_vma_for_last,
1644 last_elem_is_f1,
1645 /* regx1 */ 0x0,
1646 expected_result_int32,
1647 expected_result_int64);
1648 }
1649
TestVectorPermutationInstruction(uint32_t insn_bytes,const UInt8x16Tuple (& expected_result_int8)[8],const UInt16x8Tuple (& expected_result_int16)[8],const UInt32x4Tuple (& expected_result_int32)[8],const UInt64x2Tuple (& expected_result_int64)[8],const __v2du (& source)[16],uint8_t vlmul,uint64_t regx1=0x0,uint64_t skip=0,bool ignore_vma_for_last=false,bool last_elem_is_x1=false)1650 void TestVectorPermutationInstruction(uint32_t insn_bytes,
1651 const UInt8x16Tuple (&expected_result_int8)[8],
1652 const UInt16x8Tuple (&expected_result_int16)[8],
1653 const UInt32x4Tuple (&expected_result_int32)[8],
1654 const UInt64x2Tuple (&expected_result_int64)[8],
1655 const __v2du (&source)[16],
1656 uint8_t vlmul,
1657 uint64_t regx1 = 0x0,
1658 uint64_t skip = 0,
1659 bool ignore_vma_for_last = false,
1660 bool last_elem_is_x1 = false) {
1661 TestVectorPermutationInstruction<TestVectorInstructionKind::kInteger>(insn_bytes,
1662 source,
1663 vlmul,
1664 skip,
1665 ignore_vma_for_last,
1666 last_elem_is_x1,
1667 regx1,
1668 expected_result_int8,
1669 expected_result_int16,
1670 expected_result_int32,
1671 expected_result_int64);
1672 }
1673
1674 // Unlike regular arithmetic instructions, the result of a permutation
1675 // instruction depends also on vlmul. Also, the vslideup specs mention that
1676 // the destination vector remains unchanged the first |offset| elements (in
1677 // effect, the offset acts akin to vstart), in those cases skip can be used
1678 // to specify how many elements' mask will be skipped (counting from the
1679 // beginning, should be the same as the offset).
1680 //
1681 // If |ignore_vma_for_last| is true, an inactive element at vl-1 will be
1682 // treated as if vma=0 (Undisturbed).
1683 // If |last_elem_is_reg1| is true, the last element of the vector in
1684 // expected_result (that is, at vl-1) will be expected to be the same as
1685 // |regx1| when VL < VMAX and said element is active.
1686 template <TestVectorInstructionKind kTestVectorInstructionKind,
1687 typename... ExpectedResultType,
1688 size_t... kResultsCount>
TestVectorPermutationInstruction(uint32_t insn_bytes,const __v2du (& source)[16],uint8_t vlmul,uint64_t skip,bool ignore_vma_for_last,bool last_elem_is_reg1,uint64_t regx1,const ExpectedResultType &...expected_result)1689 void TestVectorPermutationInstruction(uint32_t insn_bytes,
1690 const __v2du (&source)[16],
1691 uint8_t vlmul,
1692 uint64_t skip,
1693 bool ignore_vma_for_last,
1694 bool last_elem_is_reg1,
1695 uint64_t regx1,
1696 const ExpectedResultType&... expected_result) {
1697 auto Verify = [this, &source, vlmul, regx1, skip, ignore_vma_for_last, last_elem_is_reg1](
1698 uint32_t insn_bytes,
1699 uint8_t vsew,
1700 const auto& expected_result_raw,
1701 auto mask) {
1702 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1703 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1704 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1705 for (size_t index = 0; index < std::size(source); ++index) {
1706 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1707 }
1708
1709 if constexpr (kTestVectorInstructionKind == TestVectorInstructionKind::kFloat) {
1710 UNUSED(regx1);
1711 // We only support Float32/Float64 for float instructions, but there are conversion
1712 // instructions that work with double width floats.
1713 // These instructions never use float registers though and thus we don't need to store
1714 // anything into f1 register, if they are used.
1715 // For Float32/Float64 case we load 5.625 of the appropriate type into f1.
1716 ASSERT_LE(vsew, 3);
1717 if (vsew == 2) {
1718 SetFReg<1>(state_.cpu, 0xffff'ffff'40b4'0000); // float 5.625
1719 } else if (vsew == 3) {
1720 SetFReg<1>(state_.cpu, 0x4016'8000'0000'0000); // double 5.625
1721 }
1722 } else {
1723 // Set x1 for vx instructions.
1724 SetXReg<1>(state_.cpu, regx1);
1725 }
1726
1727 const size_t kElementSize = 1 << vsew;
1728 size_t num_regs = 1 << vlmul;
1729 if (vlmul > 3) {
1730 num_regs = 1;
1731 }
1732 // Values for which the mask is not applied due to being before the offset when doing
1733 // vslideup.
1734 SIMD128Register skip_mask[num_regs];
1735 int64_t toskip = skip;
1736 for (size_t index = 0; index < num_regs && toskip > 0; ++index) {
1737 size_t skip_bits = toskip * kElementSize * 8;
1738 skip_mask[index] =
1739 ~std::get<0>(intrinsics::MakeBitmaskFromVl(skip_bits > 128 ? 128 : skip_bits));
1740 toskip -= 16 / kElementSize;
1741 }
1742
1743 for (uint8_t vta = 0; vta < 2; ++vta) {
1744 for (uint8_t vma = 0; vma < 2; ++vma) {
1745 auto [vlmax, vtype] =
1746 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1747 // Incompatible vsew and vlmax. Skip it.
1748 if (vlmax == 0) {
1749 continue;
1750 }
1751
1752 // To make tests quick enough we don't test vstart and vl change with small register
1753 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1754 // register, last register and half of next-to last register.
1755 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1756 // result.
1757 if (vlmul == 2) {
1758 state_.cpu.vstart = vlmax / 8;
1759 state_.cpu.vl = (vlmax * 5) / 8;
1760 } else {
1761 state_.cpu.vstart = 0;
1762 state_.cpu.vl = vlmax;
1763 }
1764 state_.cpu.vtype = vtype;
1765
1766 // Set dst vector registers into 0b01010101… pattern.
1767 for (size_t index = 0; index < 8; ++index) {
1768 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1769 }
1770
1771 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1772 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1773
1774 const size_t n = std::size(source);
1775 // Values for inactive elements (i.e. corresponding mask bit is 0).
1776 __m128i expected_inactive[n];
1777 // For most instructions, follow basic inactive processing rules based on vma flag.
1778 std::fill_n(expected_inactive, n, (vma ? kAgnosticResult : kUndisturbedResult));
1779
1780 const size_t kElementsPerRegister = 16 / kElementSize;
1781 const size_t last_reg = (state_.cpu.vl - 1) / kElementsPerRegister;
1782 const size_t last_elem = (state_.cpu.vl - 1) % kElementsPerRegister;
1783 const auto [mask_for_vl] = intrinsics::MakeBitmaskFromVl(last_elem * kElementSize * 8);
1784 if (vma && ignore_vma_for_last) {
1785 // Set expected value for inactive element at vl-1 to Undisturbed.
1786 expected_inactive[last_reg] =
1787 ((expected_inactive[last_reg] & ~mask_for_vl) | (kUndisturbedResult & mask_for_vl))
1788 .Get<__m128i>();
1789 }
1790
1791 SIMD128Register expected_result[std::size(expected_result_raw)];
1792 for (size_t index = 0; index < std::size(expected_result_raw); ++index) {
1793 expected_result[index] = SIMD128Register{expected_result_raw[index]};
1794 }
1795
1796 if (vlmul == 2 && last_elem_is_reg1) {
1797 switch (kElementSize) {
1798 case 1:
1799 expected_result[last_reg].template Set<uint8_t>(
1800 static_cast<uint8_t>(GetXReg<1>(state_.cpu)), last_elem);
1801 break;
1802 case 2:
1803 expected_result[last_reg].template Set<uint16_t>(
1804 static_cast<uint16_t>(GetXReg<1>(state_.cpu)), last_elem);
1805 break;
1806 case 4:
1807 if constexpr (kTestVectorInstructionKind == TestVectorInstructionKind::kFloat) {
1808 expected_result[last_reg].template Set<uint32_t>(
1809 static_cast<uint32_t>(GetFReg<1>(state_.cpu)), last_elem);
1810 } else {
1811 expected_result[last_reg].template Set<uint32_t>(
1812 static_cast<uint32_t>(GetXReg<1>(state_.cpu)), last_elem);
1813 }
1814 break;
1815 case 8:
1816 if constexpr (kTestVectorInstructionKind == TestVectorInstructionKind::kFloat) {
1817 expected_result[last_reg].template Set<uint64_t>(
1818 static_cast<uint64_t>(GetFReg<1>(state_.cpu)), last_elem);
1819 } else {
1820 expected_result[last_reg].template Set<uint64_t>(
1821 static_cast<uint64_t>(GetXReg<1>(state_.cpu)), last_elem);
1822 }
1823 break;
1824 default:
1825 FAIL() << "Element size is " << kElementSize;
1826 }
1827 }
1828
1829 if (vlmul < 4) {
1830 for (size_t index = 0; index < num_regs; ++index) {
1831 if (index == 0 && vlmul == 2) {
1832 EXPECT_EQ(
1833 state_.cpu.v[8 + index],
1834 SIMD128Register{(kUndisturbedResult & kFractionMaskInt8[3]) |
1835 (expected_result[index] & (mask[index] | skip_mask[index]) &
1836 ~kFractionMaskInt8[3]) |
1837 (expected_inactive[index] & ~mask[index] & ~skip_mask[index] &
1838 ~kFractionMaskInt8[3])}
1839 .Get<__uint128_t>());
1840 } else if (index == 2 && vlmul == 2) {
1841 EXPECT_EQ(
1842 state_.cpu.v[8 + index],
1843 SIMD128Register{
1844 (expected_result[index] & (mask[index] | skip_mask[index]) &
1845 kFractionMaskInt8[3]) |
1846 (expected_inactive[index] & ~mask[index] & ~skip_mask[index] &
1847 kFractionMaskInt8[3]) |
1848 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[3])}
1849 .Get<__uint128_t>());
1850 } else if (index == 3 && vlmul == 2 && vta) {
1851 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1852 } else if (index == 3 && vlmul == 2) {
1853 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult});
1854 } else {
1855 EXPECT_EQ(
1856 state_.cpu.v[8 + index],
1857 SIMD128Register{(expected_result[index] & (mask[index] | skip_mask[index])) |
1858 (expected_inactive[index] & ~(mask[index] | skip_mask[index]))}
1859 .Get<__uint128_t>());
1860 }
1861 }
1862 } else {
1863 __uint128_t v8 = state_.cpu.v[8];
1864 SIMD128Register affected_part{expected_result[0] &
1865 (mask[0] & kFractionMaskInt8[vlmul - 4] | skip_mask[0])};
1866 SIMD128Register masked_part{expected_inactive[0] & ~mask[0] & ~skip_mask[0] &
1867 kFractionMaskInt8[vlmul - 4]};
1868 SIMD128Register tail_part{(vta ? kAgnosticResult : kUndisturbedResult) &
1869 ~kFractionMaskInt8[vlmul - 4]};
1870
1871 EXPECT_EQ(v8, (affected_part | masked_part | tail_part).Get<__uint128_t>());
1872 }
1873
1874 if (vlmul == 2) {
1875 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1876 EXPECT_EQ(state_.cpu.vstart, 0);
1877 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1878 }
1879 }
1880 }
1881 };
1882
1883 // Test with and without masking enabled.
1884 (Verify(insn_bytes,
1885 BitUtilLog2(sizeof(std::remove_cvref_t<decltype(std::get<0>(expected_result[0]))>)),
1886 expected_result,
1887 MaskForElem<std::remove_cvref_t<decltype(std::get<0>(expected_result[0]))>>()),
1888 ...);
1889 (Verify(insn_bytes | (1 << 25),
1890 BitUtilLog2(sizeof(std::remove_cvref_t<decltype(std::get<0>(expected_result[0]))>)),
1891 expected_result,
1892 kNoMask),
1893 ...);
1894 }
1895
1896 protected:
1897 static constexpr __v2du kVectorCalculationsSource[16] = {
1898 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
1899 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
1900 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
1901 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
1902 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
1903 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
1904 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
1905 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978},
1906
1907 {0x9e0c'9a09'9604'9200, 0x8e1c'8a18'8614'8211},
1908 {0xbe2c'ba29'b624'b220, 0xae3c'aa38'a634'a231},
1909 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
1910 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
1911 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
1912 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
1913 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
1914 {0x7eec'7ae9'76e4'72e0, 0x6efc'6af8'66f4'62f1},
1915 };
1916
1917 static constexpr __v2du kVfClassSource[16] = {
1918 {0x8000'0000'0000'0000, 0x8e1c'8a18'8614'8211},
1919 {0x0000'0000'0000'0000, 0xae3c'aa38'a634'a231},
1920 {0x7ff0'0000'0000'0000, 0xff80'0000'7f80'0000},
1921 {0xfff0'0000'0000'0000, 0xee7c'ea78'e674'e271},
1922 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
1923 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
1924 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
1925 {0x7fb7'ffff'7fb7'ffff, 0x7ff7'ffff'ffff'ffff},
1926
1927 {0x8000'0000'0000'0000, 0x8e1c'8a18'8614'8211},
1928 {0x0000'0000'0000'0000, 0xae3c'aa38'a634'a231},
1929 {0x7ff0'0000'0000'0000, 0xff80'0000'7f80'0000},
1930 {0xfff0'0000'0000'0000, 0xee7c'ea78'e674'e271},
1931 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
1932 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
1933 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
1934 {0x7fb7'ffff'7fb7'ffff, 0x7ff7'ffff'ffff'ffff},
1935 };
1936
1937 static constexpr __v2du kVectorCalculationsSourceLegacy[16] = {
1938 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
1939 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
1940 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
1941 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
1942 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
1943 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
1944 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
1945 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978},
1946
1947 {0x0e0c'0a09'0604'0200, 0x1e1c'1a18'1614'1211},
1948 {0x2e2c'2a29'2624'2220, 0x3e3c'3a38'3634'3231},
1949 {0x4e4c'4a49'4644'4240, 0x5e5c'5a58'5654'5251},
1950 {0x6e6c'6a69'6664'6260, 0x7e7c'7a78'7674'7271},
1951 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
1952 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
1953 {0xcecc'cac9'c6c4'c2c0, 0xdedc'dad8'd6d4'd2d1},
1954 {0xeeec'eae9'e6e4'e2e0, 0xfefc'faf8'f6f4'f2f1},
1955 };
1956
1957 static constexpr __v2du kVectorComparisonSource[16] = {
1958 {0xf005'f005'f005'f005, 0xffff'ffff'4040'4040},
1959 {0xffff'ffff'40b4'40b4, 0xffff'ffff'40b4'0000},
1960 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
1961 {0xaaaa'aaaa'aaaa'aaaa, 0x1111'1111'1111'1111},
1962 {0xfff4'fff4'fff4'fff4, 0xfff6'fff6'fff6'fff6},
1963 {0xfff8'fff8'fff4'fff4, 0xfff5'fff5'fff5'fff5},
1964 {0xa9bb'bbbb'a9bb'bbbb, 0xa9bb'bbbb'a9bb'bbbb},
1965 {0xa9a9'a9a9'a9a9'a9a9, 0xa9a9'a9a9'a9a9'a9a9},
1966
1967 {0xf005'f005'f005'f005, 0xffff'ffff'4040'4040},
1968 {0x1111'1111'1111'1111, 0x1111'1111'1111'1111},
1969 {0xfff1'fff1'fff1'fff1, 0xfff1'fff1'fff1'fff1},
1970 {0x6e6c'6a69'6664'6260, 0x7e7c'7a78'7674'7271},
1971 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
1972 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
1973 {0xcecc'cac9'c6c4'c2c0, 0xdedc'dad8'd6d4'd2d1},
1974 {0xeeec'eae9'e6e4'e2e0, 0xfefc'faf8'f6f4'f2f1},
1975 };
1976
1977 // Mask in form suitable for storing in v0 and use in v0.t form.
1978 static constexpr __v2du kMask = {0xd5ad'd6b5'ad6b'b5ad, 0x6af7'57bb'deed'7bb5};
1979 // Mask used with vsew = 0 (8bit) elements.
1980 static constexpr __v16qu kMaskInt8[8] = {
1981 {255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255},
1982 {255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255},
1983 {255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255},
1984 {255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 0, 255, 255},
1985 {255, 0, 255, 0, 255, 255, 0, 255, 255, 255, 0, 255, 255, 255, 255, 0},
1986 {255, 0, 255, 255, 0, 255, 255, 255, 0, 255, 255, 255, 255, 0, 255, 255},
1987 {255, 255, 0, 255, 255, 255, 0, 255, 255, 255, 255, 0, 255, 0, 255, 0},
1988 {255, 255, 255, 0, 255, 255, 255, 255, 0, 255, 0, 255, 0, 255, 255, 0},
1989 };
1990 // Mask used with vsew = 1 (16bit) elements.
1991 static constexpr __v8hu kMaskInt16[8] = {
1992 {0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff},
1993 {0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff},
1994 {0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff, 0x0000},
1995 {0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff},
1996 {0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff},
1997 {0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff},
1998 {0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff},
1999 {0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff},
2000 };
2001 // Mask used with vsew = 2 (32bit) elements.
2002 static constexpr __v4su kMaskInt32[8] = {
2003 {0xffff'ffff, 0x0000'0000, 0xffff'ffff, 0xffff'ffff},
2004 {0x0000'0000, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2005 {0xffff'ffff, 0x0000'0000, 0xffff'ffff, 0x0000'0000},
2006 {0xffff'ffff, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2007 {0xffff'ffff, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2008 {0x0000'0000, 0xffff'ffff, 0xffff'ffff, 0x0000'0000},
2009 {0xffff'ffff, 0x0000'0000, 0xffff'ffff, 0xffff'ffff},
2010 {0x0000'0000, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2011 };
2012 // Mask used with vsew = 3 (64bit) elements.
2013 static constexpr __v2du kMaskInt64[8] = {
2014 {0xffff'ffff'ffff'ffff, 0x0000'0000'0000'0000},
2015 {0xffff'ffff'ffff'ffff, 0xffff'ffff'ffff'ffff},
2016 {0x0000'0000'0000'0000, 0xffff'ffff'ffff'ffff},
2017 {0x0000'0000'0000'0000, 0xffff'ffff'ffff'ffff},
2018 {0xffff'ffff'ffff'ffff, 0x0000'0000'0000'0000},
2019 {0xffff'ffff'ffff'ffff, 0x0000'0000'0000'0000},
2020 {0xffff'ffff'ffff'ffff, 0xffff'ffff'ffff'ffff},
2021 {0x0000'0000'0000'0000, 0xffff'ffff'ffff'ffff},
2022 };
2023 // To verify operations without masking.
2024 static constexpr __v16qu kNoMask[8] = {
2025 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2026 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2027 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2028 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2029 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2030 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2031 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2032 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2033 };
2034 // Half of sub-register lmul.
2035 static constexpr __v16qu kFractionMaskInt8[5] = {
2036 {255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of ⅛ reg = ¹⁄₁₆
2037 {255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of ¼ reg = ⅛
2038 {255, 255, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of ½ reg = ¼
2039 {255, 255, 255, 255, 255, 255, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of full reg = ½
2040 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255}, // Full reg
2041 };
2042 // Agnostic result is -1 on RISC-V, not 0.
2043 static constexpr __m128i kAgnosticResult = {-1, -1};
2044 // Undisturbed result is put in registers v8, v9, …, v15 and is expected to get read back.
2045 static constexpr __m128i kUndisturbedResult = {0x5555'5555'5555'5555, 0x5555'5555'5555'5555};
2046 // Note: permutation of indexes here is not entirely random. First 32 indexes are limited to 31
2047 // maximum and first 64 indexes are limited to 63. That way we can guarantee that 8byte elements
2048 // and 4byte elements wouldn't need to access area outside of our 256-byte buffer.
2049 static constexpr uint8_t kPermutedIndexes[128] = {
2050 1, 0, 3, 2, 7, 5, 4, 6, 9, 14, 15, 11, 13, 12, 8, 10, 30, 31, 17,
2051 22, 18, 26, 25, 19, 29, 28, 16, 21, 27, 24, 20, 23, 44, 50, 52, 34, 61, 38,
2052 54, 43, 42, 63, 57, 40, 36, 46, 39, 47, 35, 41, 62, 59, 60, 51, 55, 53, 33,
2053 32, 58, 49, 56, 37, 45, 48, 124, 92, 78, 101, 114, 89, 75, 64, 98, 112, 111, 118,
2054 121, 102, 73, 105, 109, 68, 103, 72, 110, 79, 119, 96, 123, 85, 90, 126, 66, 69, 120,
2055 97, 113, 76, 100, 67, 125, 117, 65, 84, 104, 122, 71, 81, 99, 70, 91, 86, 115, 127,
2056 77, 107, 74, 93, 80, 106, 87, 94, 83, 95, 116, 108, 82, 88};
2057
2058 // Store area for store instructions. We need at least 16 uint64_t to handle 8×128bit registers,
2059 // plus 2× of that to test strided instructions.
2060 alignas(16) uint64_t store_area_[32];
2061
2062 ThreadState state_;
2063 };
2064
2065 #define TESTSUITE Riscv64InterpretInsnTest
2066 #define TESTING_INTERPRETER
2067
2068 #include "berberis/test_utils/insn_tests_riscv64-inl.h"
2069
2070 #undef TESTING_INTERPRETER
2071 #undef TESTSUITE
2072
2073 // Tests for Non-Compressed Instructions.
2074
TEST_F(Riscv64InterpreterTest,FenceInstructions)2075 TEST_F(Riscv64InterpreterTest, FenceInstructions) {
2076 // Fence
2077 InterpretFence(0x0ff0000f);
2078 // FenceTso
2079 InterpretFence(0x8330000f);
2080
2081 // FenceI explicitly not supported.
2082 }
2083
TEST_F(Riscv64InterpreterTest,SyscallWrite)2084 TEST_F(Riscv64InterpreterTest, SyscallWrite) {
2085 const char message[] = "Hello";
2086 // Prepare a pipe to write to.
2087 int pipefd[2];
2088 ASSERT_EQ(0, pipe(pipefd));
2089
2090 // Only ecall instruction needs guest thread, since it involves pending signals manipulations.
2091 std::unique_ptr<GuestThread, decltype(&GuestThread::Destroy)> guest_thread(
2092 GuestThread::CreateForTest(&state_), GuestThread::Destroy);
2093 state_.thread = guest_thread.get();
2094
2095 // SYS_write
2096 SetXReg<17>(state_.cpu, 0x40);
2097 // File descriptor
2098 SetXReg<10>(state_.cpu, pipefd[1]);
2099 // String
2100 SetXReg<11>(state_.cpu, bit_cast<uint64_t>(&message[0]));
2101 // Size
2102 SetXReg<12>(state_.cpu, sizeof(message));
2103
2104 uint32_t insn_bytes = 0x00000073;
2105 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
2106 InterpretInsn(&state_);
2107
2108 // Check number of bytes written.
2109 EXPECT_EQ(GetXReg<10>(state_.cpu), sizeof(message));
2110
2111 // Check the message was written to the pipe.
2112 char buf[sizeof(message)] = {};
2113 ssize_t read_size = read(pipefd[0], &buf, sizeof(buf));
2114 EXPECT_NE(read_size, -1);
2115 EXPECT_EQ(0, strcmp(message, buf));
2116 close(pipefd[0]);
2117 close(pipefd[1]);
2118 }
2119
TEST_F(Riscv64InterpreterTest,TestFPExceptions)2120 TEST_F(Riscv64InterpreterTest, TestFPExceptions) {
2121 // Keep the same sort as Section 19 "Vector Instruction Listing".
2122 TestFPExceptions<intrinsics::Float32>(0x012d1557); // Vfadd.vv v10, v18, v26, v0.t
2123 TestFPExceptions<intrinsics::Float64>(0x010c1457); // Vfadd.vv v8, v16, v24, v0.t
2124 TestFPExceptions<intrinsics::Float32>(0x0120d557); // Vfadd.vf v10, v18, f1, v0.t
2125 TestFPExceptions<intrinsics::Float64>(0x01015457); // Vfadd.vf v8, v16, f2, v0.t
2126 TestFPExceptions<intrinsics::Float32>(0x092d1557); // Vfsub.vv v10, v18, v26, v0.t
2127 TestFPExceptions<intrinsics::Float64>(0x090c1457); // Vfsub.vv v8, v16, v24, v0.t
2128 TestFPExceptions<intrinsics::Float32>(0x0920d557); // Vfsub.vf v10, v18, f1, v0.t
2129 TestFPExceptions<intrinsics::Float64>(0x09015457); // Vfsub.vf v8, v16, f2, v0.t
2130 TestFPExceptions<intrinsics::Float32>(0x812d1557); // Vfdiv.vv v10, v18, v26, v0.t
2131 TestFPExceptions<intrinsics::Float64>(0x810c1457); // Vfdiv.vv v8, v16, v24, v0.t
2132 TestFPExceptions<intrinsics::Float32>(0x8120d557); // Vfdiv.vf v10, v18, f1, v0.t
2133 TestFPExceptions<intrinsics::Float64>(0x81015457); // Vfdiv.vf v8, v16, f2, v0.t
2134 TestFPExceptions<intrinsics::Float32>(0x912d1557); // Vfmul.vv v10, v18, v26, v0.t
2135 TestFPExceptions<intrinsics::Float64>(0x910c1457); // Vfmul.vv v8, v16, v24, v0.t
2136 TestFPExceptions<intrinsics::Float32>(0x9120d557); // Vfmul.vf v10, v18, f1, v0.t
2137 TestFPExceptions<intrinsics::Float64>(0x91015457); // Vfmul.vf v8, v16, f2, v0.t
2138 TestFPExceptions<intrinsics::Float32>(0x9d20d557); // Vfrsub.vf v10, v18, f1, v0.t
2139 TestFPExceptions<intrinsics::Float64>(0x9d015457); // Vfrsub.vf v8, v16, f2, v0.t
2140 }
2141
TEST_F(Riscv64InterpreterTest,TestVlXreXX)2142 TEST_F(Riscv64InterpreterTest, TestVlXreXX) {
2143 TestVlXreXX<1>(0x2808407); // vl1re8.v v8, (x1)
2144 TestVlXreXX<2>(0x22808407); // vl2re8.v v8, (x1)
2145 TestVlXreXX<4>(0x62808407); // vl4re8.v v8, (x1)
2146 TestVlXreXX<8>(0xe2808407); // vl8re8.v v8, (x1)
2147
2148 TestVlXreXX<1>(0x280d407); // vl1re16.v v8, (x1)
2149 TestVlXreXX<2>(0x2280d407); // vl2re16.v v8, (x1)
2150 TestVlXreXX<4>(0x6280d407); // vl4re16.v v8, (x1)
2151 TestVlXreXX<8>(0xe280d407); // vl8re16.v v8, (x1)
2152
2153 TestVlXreXX<1>(0x280e407); // vl1re32.v v8, (x1)
2154 TestVlXreXX<2>(0x2280e407); // vl2re32.v v8, (x1)
2155 TestVlXreXX<4>(0x6280e407); // vl4re32.v v8, (x1)
2156 TestVlXreXX<8>(0xe280e407); // vl8re32.v v8, (x1)
2157
2158 TestVlXreXX<1>(0x280f407); // vl1re64.v v8, (x1)
2159 TestVlXreXX<2>(0x2280f407); // vl2re64.v v8, (x1)
2160 TestVlXreXX<4>(0x6280f407); // vl4re64.v v8, (x1)
2161 TestVlXreXX<8>(0xe280f407); // vl8re64.v v8, (x1)
2162 }
2163
TEST_F(Riscv64InterpreterTest,TestVmXr)2164 TEST_F(Riscv64InterpreterTest, TestVmXr) {
2165 TestVmvXr<1>(0x9f003457); // Vmv1r.v v8, v16
2166 TestVmvXr<2>(0x9f00b457); // Vmv2r.v v8, v16
2167 TestVmvXr<4>(0x9f01b457); // Vmv4r.v v8, v16
2168 TestVmvXr<8>(0x9f03b457); // Vmv8r.v v8, v16
2169 }
2170
TEST_F(Riscv64InterpreterTest,TestVfrsqrt7)2171 TEST_F(Riscv64InterpreterTest, TestVfrsqrt7) {
2172 TestVectorFloatInstruction(0x4d821457, // Vfrsqrt7.v v8, v24, v0.t
2173 {{0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2174 {0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2175 {0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2176 {0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2177 {0x53fb'8000, 0x4ff4'8000, 0x5bed'8000, 0x57e7'8000},
2178 {0x43e2'0000, 0x3fdc'8000, 0x4bd7'8000, 0x47d3'0000},
2179 {0x33ce'8000, 0x2fca'8000, 0x3bc6'8000, 0x37c3'0000},
2180 {0x23bf'8000, 0x1fbc'8000, 0x2bb9'0000, 0x27b6'8000}},
2181 {{0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2182 {0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2183 {0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2184 {0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2185 {0x50a1'1000'0000'0000, 0x5898'3000'0000'0000},
2186 {0x4091'1000'0000'0000, 0x4888'2000'0000'0000},
2187 {0x3081'0000'0000'0000, 0x3878'1000'0000'0000},
2188 {0x2071'0000'0000'0000, 0x2868'0000'0000'0000}},
2189 kVectorCalculationsSource);
2190 }
2191
TEST_F(Riscv64InterpreterTest,TestVfclass)2192 TEST_F(Riscv64InterpreterTest, TestVfclass) {
2193 TestVectorFloatInstruction(0x4d881457, // Vfclass.v v8, v24, v0.t
2194 {{0x0000'0010, 0x0000'0008, 0x0000'0002, 0x0000'0002},
2195 {0x0000'0010, 0x0000'0010, 0x0000'0002, 0x0000'0002},
2196 {0x0000'0010, 0x0000'0200, 0x0000'0080, 0x0000'0001},
2197 {0x0000'0010, 0x0000'0200, 0x0000'0002, 0x0000'0002},
2198 {0x0000'0040, 0x0000'0040, 0x0000'0040, 0x0000'0040},
2199 {0x0000'0040, 0x0000'0040, 0x0000'0040, 0x0000'0040},
2200 {0x0000'0040, 0x0000'0040, 0x0000'0040, 0x0000'0040},
2201 {0x0000'0100, 0x0000'0100, 0x0000'0200, 0x0000'0200}},
2202 {{0x0000'0000'0000'0008, 0x0000'0000'0000'0002},
2203 {0x0000'0000'0000'0010, 0x0000'0000'0000'0002},
2204 {0x0000'0000'0000'0080, 0x0000'0000'0000'0002},
2205 {0x0000'0000'0000'0001, 0x0000'0000'0000'0002},
2206 {0x0000'0000'0000'0040, 0x0000'0000'0000'0040},
2207 {0x0000'0000'0000'0040, 0x0000'0000'0000'0040},
2208 {0x0000'0000'0000'0040, 0x0000'0000'0000'0040},
2209 {0x0000'0000'0000'0040, 0x0000'0000'0000'0100}},
2210 kVfClassSource);
2211 }
2212
TEST_F(Riscv64InterpreterTest,TestVfmvfs)2213 TEST_F(Riscv64InterpreterTest, TestVfmvfs) {
2214 TestVfmvfs<intrinsics::Float32>(0x428010d7, 0xffff'ffff'8302'8100); // Vfmv.f.s f1, v8
2215 TestVfmvfs<intrinsics::Float64>(0x428010d7, 0x8706'8504'8302'8100); // Vfmv.f.s f1, v8
2216 }
2217
TEST_F(Riscv64InterpreterTest,TestVfmvsf)2218 TEST_F(Riscv64InterpreterTest, TestVfmvsf) {
2219 TestVfmvsf<intrinsics::Float32>(0x4200d457, // Vfmv.s.f v8, f1
2220 0xffff'ffff'40b4'0000,
2221 intrinsics::Float32{5.625f});
2222 TestVfmvsf<intrinsics::Float64>(0x4200d457, // Vfmv.s.f v8, f1
2223 0x4016'8000'0000'0000,
2224 intrinsics::Float64{5.625});
2225 }
2226
TEST_F(Riscv64InterpreterTest,TestVmvsx)2227 TEST_F(Riscv64InterpreterTest, TestVmvsx) {
2228 TestVmvsx<Int8>(0x4200e457); // Vmv.s.x v8, x1
2229 TestVmvsx<Int16>(0x4200e457); // Vmv.s.x v8, x1
2230 TestVmvsx<Int32>(0x4200e457); // Vmv.s.x v8, x1
2231 TestVmvsx<Int64>(0x4200e457); // Vmv.s.x v8, x1
2232 }
2233
TEST_F(Riscv64InterpreterTest,TestVmvxs)2234 TEST_F(Riscv64InterpreterTest, TestVmvxs) {
2235 TestVmvxs<Int8>(0x428020d7, 0); // Vmv.x.s x1, v8
2236 TestVmvxs<Int16>(0x428020d7, 0xffff'ffff'ffff'8100); // Vmv.x.s x1, v8
2237 TestVmvxs<Int32>(0x428020d7, 0xffff'ffff'8302'8100); // Vmv.x.s x1, v8
2238 TestVmvxs<Int64>(0x428020d7, 0x8706'8504'8302'8100); // Vmv.x.s x1, v8
2239 }
2240
TEST_F(Riscv64InterpreterTest,TestVsX)2241 TEST_F(Riscv64InterpreterTest, TestVsX) {
2242 TestVsX<1>(0x2808427); // vs1r.v v8, (x1)
2243 TestVsX<2>(0x22808427); // vs2r.v v8, (x1)
2244 TestVsX<4>(0x62808427); // vs4r.v v8, (x1)
2245 TestVsX<8>(0xe2808427); // vs8r.v v8, (x1)
2246 }
2247
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul1)2248 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul1) {
2249 VlxsegXeiXX<UInt8, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2250 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10}});
2251 }
2252
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul2)2253 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul2) {
2254 VlxsegXeiXX<UInt8, 1, 2>(
2255 0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2256 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10},
2257 {30, 159, 145, 22, 18, 26, 153, 147, 157, 28, 16, 149, 155, 24, 20, 151}});
2258 }
2259
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul4)2260 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul4) {
2261 VlxsegXeiXX<UInt8, 1, 4>(
2262 0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2263 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10},
2264 {30, 159, 145, 22, 18, 26, 153, 147, 157, 28, 16, 149, 155, 24, 20, 151},
2265 {44, 50, 52, 34, 189, 38, 54, 171, 42, 191, 185, 40, 36, 46, 167, 175},
2266 {163, 169, 62, 187, 60, 179, 183, 181, 161, 32, 58, 177, 56, 165, 173, 48}});
2267 }
2268
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul8)2269 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul8) {
2270 VlxsegXeiXX<UInt8, 1, 8>(
2271 0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2272 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10},
2273 {30, 159, 145, 22, 18, 26, 153, 147, 157, 28, 16, 149, 155, 24, 20, 151},
2274 {44, 50, 52, 34, 189, 38, 54, 171, 42, 191, 185, 40, 36, 46, 167, 175},
2275 {163, 169, 62, 187, 60, 179, 183, 181, 161, 32, 58, 177, 56, 165, 173, 48},
2276 {124, 92, 78, 229, 114, 217, 203, 64, 98, 112, 239, 118, 249, 102, 201, 233},
2277 {237, 68, 231, 72, 110, 207, 247, 96, 251, 213, 90, 126, 66, 197, 120, 225},
2278 {241, 76, 100, 195, 253, 245, 193, 84, 104, 122, 199, 209, 227, 70, 219, 86},
2279 {243, 255, 205, 235, 74, 221, 80, 106, 215, 94, 211, 223, 116, 108, 82, 88}});
2280 }
2281
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew8_vlmul1)2282 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew8_vlmul1) {
2283 VlxsegXeiXX<UInt8, 2, 1>(
2284 0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2285 {{2, 0, 6, 4, 14, 10, 8, 12, 18, 28, 30, 22, 26, 24, 16, 20},
2286 {131, 129, 135, 133, 143, 139, 137, 141, 147, 157, 159, 151, 155, 153, 145, 149}});
2287 }
2288
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew8_vlmul2)2289 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew8_vlmul2) {
2290 VlxsegXeiXX<UInt8, 2, 2>(
2291 0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2292 {{2, 0, 6, 4, 14, 10, 8, 12, 18, 28, 30, 22, 26, 24, 16, 20},
2293 {60, 62, 34, 44, 36, 52, 50, 38, 58, 56, 32, 42, 54, 48, 40, 46},
2294 {131, 129, 135, 133, 143, 139, 137, 141, 147, 157, 159, 151, 155, 153, 145, 149},
2295 {189, 191, 163, 173, 165, 181, 179, 167, 187, 185, 161, 171, 183, 177, 169, 175}});
2296 }
2297
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew8_vlmul4)2298 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew8_vlmul4) {
2299 VlxsegXeiXX<UInt8, 2, 4>(
2300 0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2301 {{2, 0, 6, 4, 14, 10, 8, 12, 18, 28, 30, 22, 26, 24, 16, 20},
2302 {60, 62, 34, 44, 36, 52, 50, 38, 58, 56, 32, 42, 54, 48, 40, 46},
2303 {88, 100, 104, 68, 122, 76, 108, 86, 84, 126, 114, 80, 72, 92, 78, 94},
2304 {70, 82, 124, 118, 120, 102, 110, 106, 66, 64, 116, 98, 112, 74, 90, 96},
2305 {131, 129, 135, 133, 143, 139, 137, 141, 147, 157, 159, 151, 155, 153, 145, 149},
2306 {189, 191, 163, 173, 165, 181, 179, 167, 187, 185, 161, 171, 183, 177, 169, 175},
2307 {217, 229, 233, 197, 251, 205, 237, 215, 213, 255, 243, 209, 201, 221, 207, 223},
2308 {199, 211, 253, 247, 249, 231, 239, 235, 195, 193, 245, 227, 241, 203, 219, 225}});
2309 }
2310
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew8_vlmul1)2311 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew8_vlmul1) {
2312 VlxsegXeiXX<UInt8, 3, 1>(
2313 0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2314 {{131, 0, 137, 6, 149, 143, 12, 18, 155, 42, 173, 161, 167, 36, 24, 30},
2315 {4, 129, 10, 135, 22, 16, 141, 147, 28, 171, 46, 34, 40, 165, 153, 159},
2316 {133, 2, 139, 8, 151, 145, 14, 20, 157, 44, 175, 163, 169, 38, 26, 32}});
2317 }
2318
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew8_vlmul2)2319 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew8_vlmul2) {
2320 VlxsegXeiXX<UInt8, 3, 2>(
2321 0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2322 {{131, 0, 137, 6, 149, 143, 12, 18, 155, 42, 173, 161, 167, 36, 24, 30},
2323 {90, 221, 179, 66, 54, 78, 203, 185, 215, 84, 48, 191, 209, 72, 60, 197},
2324 {4, 129, 10, 135, 22, 16, 141, 147, 28, 171, 46, 34, 40, 165, 153, 159},
2325 {219, 94, 52, 195, 183, 207, 76, 58, 88, 213, 177, 64, 82, 201, 189, 70},
2326 {133, 2, 139, 8, 151, 145, 14, 20, 157, 44, 175, 163, 169, 38, 26, 32},
2327 {92, 223, 181, 68, 56, 80, 205, 187, 217, 86, 50, 193, 211, 74, 62, 199}});
2328 }
2329
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew8_vlmul1)2330 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew8_vlmul1) {
2331 VlxsegXeiXX<UInt8, 4, 1>(
2332 0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2333 {{4, 0, 12, 8, 28, 20, 16, 24, 36, 56, 60, 44, 52, 48, 32, 40},
2334 {133, 129, 141, 137, 157, 149, 145, 153, 165, 185, 189, 173, 181, 177, 161, 169},
2335 {6, 2, 14, 10, 30, 22, 18, 26, 38, 58, 62, 46, 54, 50, 34, 42},
2336 {135, 131, 143, 139, 159, 151, 147, 155, 167, 187, 191, 175, 183, 179, 163, 171}});
2337 }
2338
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew4_vlmul2)2339 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew4_vlmul2) {
2340 VlxsegXeiXX<UInt8, 4, 2>(
2341 0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2342 {{4, 0, 12, 8, 28, 20, 16, 24, 36, 56, 60, 44, 52, 48, 32, 40},
2343 {120, 124, 68, 88, 72, 104, 100, 76, 116, 112, 64, 84, 108, 96, 80, 92},
2344 {133, 129, 141, 137, 157, 149, 145, 153, 165, 185, 189, 173, 181, 177, 161, 169},
2345 {249, 253, 197, 217, 201, 233, 229, 205, 245, 241, 193, 213, 237, 225, 209, 221},
2346 {6, 2, 14, 10, 30, 22, 18, 26, 38, 58, 62, 46, 54, 50, 34, 42},
2347 {122, 126, 70, 90, 74, 106, 102, 78, 118, 114, 66, 86, 110, 98, 82, 94},
2348 {135, 131, 143, 139, 159, 151, 147, 155, 167, 187, 191, 175, 183, 179, 163, 171},
2349 {251, 255, 199, 219, 203, 235, 231, 207, 247, 243, 195, 215, 239, 227, 211, 223}});
2350 }
2351
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew8)2352 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew8) {
2353 VlxsegXeiXX<UInt8, 5, 1>(
2354 0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2355 {{133, 0, 143, 10, 163, 153, 20, 30, 173, 70, 203, 183, 193, 60, 40, 50},
2356 {6, 129, 16, 139, 36, 26, 149, 159, 46, 199, 76, 56, 66, 189, 169, 179},
2357 {135, 2, 145, 12, 165, 155, 22, 32, 175, 72, 205, 185, 195, 62, 42, 52},
2358 {8, 131, 18, 141, 38, 28, 151, 161, 48, 201, 78, 58, 68, 191, 171, 181},
2359 {137, 4, 147, 14, 167, 157, 24, 34, 177, 74, 207, 187, 197, 64, 44, 54}});
2360 }
2361
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew8)2362 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew8) {
2363 VlxsegXeiXX<UInt8, 6, 1>(
2364 0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2365 {{6, 0, 18, 12, 42, 30, 24, 36, 54, 84, 90, 66, 78, 72, 48, 60},
2366 {135, 129, 147, 141, 171, 159, 153, 165, 183, 213, 219, 195, 207, 201, 177, 189},
2367 {8, 2, 20, 14, 44, 32, 26, 38, 56, 86, 92, 68, 80, 74, 50, 62},
2368 {137, 131, 149, 143, 173, 161, 155, 167, 185, 215, 221, 197, 209, 203, 179, 191},
2369 {10, 4, 22, 16, 46, 34, 28, 40, 58, 88, 94, 70, 82, 76, 52, 64},
2370 {139, 133, 151, 145, 175, 163, 157, 169, 187, 217, 223, 199, 211, 205, 181, 193}});
2371 }
2372
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew8)2373 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew8) {
2374 VlxsegXeiXX<UInt8, 7, 1>(
2375 0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2376 {{135, 0, 149, 14, 177, 163, 28, 42, 191, 98, 233, 205, 219, 84, 56, 70},
2377 {8, 129, 22, 143, 50, 36, 157, 171, 64, 227, 106, 78, 92, 213, 185, 199},
2378 {137, 2, 151, 16, 179, 165, 30, 44, 193, 100, 235, 207, 221, 86, 58, 72},
2379 {10, 131, 24, 145, 52, 38, 159, 173, 66, 229, 108, 80, 94, 215, 187, 201},
2380 {139, 4, 153, 18, 181, 167, 32, 46, 195, 102, 237, 209, 223, 88, 60, 74},
2381 {12, 133, 26, 147, 54, 40, 161, 175, 68, 231, 110, 82, 96, 217, 189, 203},
2382 {141, 6, 155, 20, 183, 169, 34, 48, 197, 104, 239, 211, 225, 90, 62, 76}});
2383 }
2384
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew8)2385 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew8) {
2386 VlxsegXeiXX<UInt8, 8, 1>(
2387 0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2388 {{8, 0, 24, 16, 56, 40, 32, 48, 72, 112, 120, 88, 104, 96, 64, 80},
2389 {137, 129, 153, 145, 185, 169, 161, 177, 201, 241, 249, 217, 233, 225, 193, 209},
2390 {10, 2, 26, 18, 58, 42, 34, 50, 74, 114, 122, 90, 106, 98, 66, 82},
2391 {139, 131, 155, 147, 187, 171, 163, 179, 203, 243, 251, 219, 235, 227, 195, 211},
2392 {12, 4, 28, 20, 60, 44, 36, 52, 76, 116, 124, 92, 108, 100, 68, 84},
2393 {141, 133, 157, 149, 189, 173, 165, 181, 205, 245, 253, 221, 237, 229, 197, 213},
2394 {14, 6, 30, 22, 62, 46, 38, 54, 78, 118, 126, 94, 110, 102, 70, 86},
2395 {143, 135, 159, 151, 191, 175, 167, 183, 207, 247, 255, 223, 239, 231, 199, 215}});
2396 }
2397
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul1)2398 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul1) {
2399 VlxsegXeiXX<UInt16, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2400 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c}});
2401 }
2402
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul2)2403 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul2) {
2404 VlxsegXeiXX<UInt16, 1, 2>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2405 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c},
2406 {0x9312, 0x9d1c, 0x9f1e, 0x9716, 0x9b1a, 0x9918, 0x9110, 0x9514}});
2407 }
2408
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul4)2409 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul4) {
2410 VlxsegXeiXX<UInt16, 1, 4>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2411 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c},
2412 {0x9312, 0x9d1c, 0x9f1e, 0x9716, 0x9b1a, 0x9918, 0x9110, 0x9514},
2413 {0xbd3c, 0xbf3e, 0xa322, 0xad2c, 0xa524, 0xb534, 0xb332, 0xa726},
2414 {0xbb3a, 0xb938, 0xa120, 0xab2a, 0xb736, 0xb130, 0xa928, 0xaf2e}});
2415 }
2416
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul8)2417 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul8) {
2418 VlxsegXeiXX<UInt16, 1, 8>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2419 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c},
2420 {0x9312, 0x9d1c, 0x9f1e, 0x9716, 0x9b1a, 0x9918, 0x9110, 0x9514},
2421 {0xbd3c, 0xbf3e, 0xa322, 0xad2c, 0xa524, 0xb534, 0xb332, 0xa726},
2422 {0xbb3a, 0xb938, 0xa120, 0xab2a, 0xb736, 0xb130, 0xa928, 0xaf2e},
2423 {0xd958, 0xe564, 0xe968, 0xc544, 0xfb7a, 0xcd4c, 0xed6c, 0xd756},
2424 {0xd554, 0xff7e, 0xf372, 0xd150, 0xc948, 0xdd5c, 0xcf4e, 0xdf5e},
2425 {0xc746, 0xd352, 0xfd7c, 0xf776, 0xf978, 0xe766, 0xef6e, 0xeb6a},
2426 {0xc342, 0xc140, 0xf574, 0xe362, 0xf170, 0xcb4a, 0xdb5a, 0xe160}});
2427 }
2428
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew16_vlmul1)2429 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew16_vlmul1) {
2430 VlxsegXeiXX<UInt16, 2, 1>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2431 {{0x8504, 0x8100, 0x8d0c, 0x8908, 0x9d1c, 0x9514, 0x9110, 0x9918},
2432 {0x8706, 0x8302, 0x8f0e, 0x8b0a, 0x9f1e, 0x9716, 0x9312, 0x9b1a}});
2433 }
2434
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew16_vlmul2)2435 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew16_vlmul2) {
2436 VlxsegXeiXX<UInt16, 2, 2>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2437 {{0x8504, 0x8100, 0x8d0c, 0x8908, 0x9d1c, 0x9514, 0x9110, 0x9918},
2438 {0xa524, 0xb938, 0xbd3c, 0xad2c, 0xb534, 0xb130, 0xa120, 0xa928},
2439 {0x8706, 0x8302, 0x8f0e, 0x8b0a, 0x9f1e, 0x9716, 0x9312, 0x9b1a},
2440 {0xa726, 0xbb3a, 0xbf3e, 0xaf2e, 0xb736, 0xb332, 0xa322, 0xab2a}});
2441 }
2442
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew16_vlmul4)2443 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew16_vlmul4) {
2444 VlxsegXeiXX<UInt16, 2, 4>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2445 {{0x8504, 0x8100, 0x8d0c, 0x8908, 0x9d1c, 0x9514, 0x9110, 0x9918},
2446 {0xa524, 0xb938, 0xbd3c, 0xad2c, 0xb534, 0xb130, 0xa120, 0xa928},
2447 {0xf978, 0xfd7c, 0xc544, 0xd958, 0xc948, 0xe968, 0xe564, 0xcd4c},
2448 {0xf574, 0xf170, 0xc140, 0xd554, 0xed6c, 0xe160, 0xd150, 0xdd5c},
2449 {0x8706, 0x8302, 0x8f0e, 0x8b0a, 0x9f1e, 0x9716, 0x9312, 0x9b1a},
2450 {0xa726, 0xbb3a, 0xbf3e, 0xaf2e, 0xb736, 0xb332, 0xa322, 0xab2a},
2451 {0xfb7a, 0xff7e, 0xc746, 0xdb5a, 0xcb4a, 0xeb6a, 0xe766, 0xcf4e},
2452 {0xf776, 0xf372, 0xc342, 0xd756, 0xef6e, 0xe362, 0xd352, 0xdf5e}});
2453 }
2454
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew16_vlmul1)2455 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew16_vlmul1) {
2456 VlxsegXeiXX<UInt16, 3, 1>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2457 {{0x8706, 0x8100, 0x9312, 0x8d0c, 0xab2a, 0x9f1e, 0x9918, 0xa524},
2458 {0x8908, 0x8302, 0x9514, 0x8f0e, 0xad2c, 0xa120, 0x9b1a, 0xa726},
2459 {0x8b0a, 0x8504, 0x9716, 0x9110, 0xaf2e, 0xa322, 0x9d1c, 0xa928}});
2460 }
2461
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew16_vlmul2)2462 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew16_vlmul2) {
2463 VlxsegXeiXX<UInt16, 3, 2>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2464 {{0x8706, 0x8100, 0x9312, 0x8d0c, 0xab2a, 0x9f1e, 0x9918, 0xa524},
2465 {0xb736, 0xd554, 0xdb5a, 0xc342, 0xcf4e, 0xc948, 0xb130, 0xbd3c},
2466 {0x8908, 0x8302, 0x9514, 0x8f0e, 0xad2c, 0xa120, 0x9b1a, 0xa726},
2467 {0xb938, 0xd756, 0xdd5c, 0xc544, 0xd150, 0xcb4a, 0xb332, 0xbf3e},
2468 {0x8b0a, 0x8504, 0x9716, 0x9110, 0xaf2e, 0xa322, 0x9d1c, 0xa928},
2469 {0xbb3a, 0xd958, 0xdf5e, 0xc746, 0xd352, 0xcd4c, 0xb534, 0xc140}});
2470 }
2471
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew16_vlmul1)2472 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew16_vlmul1) {
2473 VlxsegXeiXX<UInt16, 4, 1>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2474 {{0x8908, 0x8100, 0x9918, 0x9110, 0xb938, 0xa928, 0xa120, 0xb130},
2475 {0x8b0a, 0x8302, 0x9b1a, 0x9312, 0xbb3a, 0xab2a, 0xa322, 0xb332},
2476 {0x8d0c, 0x8504, 0x9d1c, 0x9514, 0xbd3c, 0xad2c, 0xa524, 0xb534},
2477 {0x8f0e, 0x8706, 0x9f1e, 0x9716, 0xbf3e, 0xaf2e, 0xa726, 0xb736}});
2478 }
2479
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew16_vlmul2)2480 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew16_vlmul2) {
2481 VlxsegXeiXX<UInt16, 4, 2>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2482 {{0x8908, 0x8100, 0x9918, 0x9110, 0xb938, 0xa928, 0xa120, 0xb130},
2483 {0xc948, 0xf170, 0xf978, 0xd958, 0xe968, 0xe160, 0xc140, 0xd150},
2484 {0x8b0a, 0x8302, 0x9b1a, 0x9312, 0xbb3a, 0xab2a, 0xa322, 0xb332},
2485 {0xcb4a, 0xf372, 0xfb7a, 0xdb5a, 0xeb6a, 0xe362, 0xc342, 0xd352},
2486 {0x8d0c, 0x8504, 0x9d1c, 0x9514, 0xbd3c, 0xad2c, 0xa524, 0xb534},
2487 {0xcd4c, 0xf574, 0xfd7c, 0xdd5c, 0xed6c, 0xe564, 0xc544, 0xd554},
2488 {0x8f0e, 0x8706, 0x9f1e, 0x9716, 0xbf3e, 0xaf2e, 0xa726, 0xb736},
2489 {0xcf4e, 0xf776, 0xff7e, 0xdf5e, 0xef6e, 0xe766, 0xc746, 0xd756}});
2490 }
2491
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew16)2492 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew16) {
2493 VlxsegXeiXX<UInt16, 5, 1>(0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2494 {{0x8b0a, 0x8100, 0x9f1e, 0x9514, 0xc746, 0xb332, 0xa928, 0xbd3c},
2495 {0x8d0c, 0x8302, 0xa120, 0x9716, 0xc948, 0xb534, 0xab2a, 0xbf3e},
2496 {0x8f0e, 0x8504, 0xa322, 0x9918, 0xcb4a, 0xb736, 0xad2c, 0xc140},
2497 {0x9110, 0x8706, 0xa524, 0x9b1a, 0xcd4c, 0xb938, 0xaf2e, 0xc342},
2498 {0x9312, 0x8908, 0xa726, 0x9d1c, 0xcf4e, 0xbb3a, 0xb130, 0xc544}});
2499 }
2500
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew16)2501 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew16) {
2502 VlxsegXeiXX<UInt16, 6, 1>(0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2503 {{0x8d0c, 0x8100, 0xa524, 0x9918, 0xd554, 0xbd3c, 0xb130, 0xc948},
2504 {0x8f0e, 0x8302, 0xa726, 0x9b1a, 0xd756, 0xbf3e, 0xb332, 0xcb4a},
2505 {0x9110, 0x8504, 0xa928, 0x9d1c, 0xd958, 0xc140, 0xb534, 0xcd4c},
2506 {0x9312, 0x8706, 0xab2a, 0x9f1e, 0xdb5a, 0xc342, 0xb736, 0xcf4e},
2507 {0x9514, 0x8908, 0xad2c, 0xa120, 0xdd5c, 0xc544, 0xb938, 0xd150},
2508 {0x9716, 0x8b0a, 0xaf2e, 0xa322, 0xdf5e, 0xc746, 0xbb3a, 0xd352}});
2509 }
2510
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew16)2511 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew16) {
2512 VlxsegXeiXX<UInt16, 7, 1>(0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2513 {{0x8f0e, 0x8100, 0xab2a, 0x9d1c, 0xe362, 0xc746, 0xb938, 0xd554},
2514 {0x9110, 0x8302, 0xad2c, 0x9f1e, 0xe564, 0xc948, 0xbb3a, 0xd756},
2515 {0x9312, 0x8504, 0xaf2e, 0xa120, 0xe766, 0xcb4a, 0xbd3c, 0xd958},
2516 {0x9514, 0x8706, 0xb130, 0xa322, 0xe968, 0xcd4c, 0xbf3e, 0xdb5a},
2517 {0x9716, 0x8908, 0xb332, 0xa524, 0xeb6a, 0xcf4e, 0xc140, 0xdd5c},
2518 {0x9918, 0x8b0a, 0xb534, 0xa726, 0xed6c, 0xd150, 0xc342, 0xdf5e},
2519 {0x9b1a, 0x8d0c, 0xb736, 0xa928, 0xef6e, 0xd352, 0xc544, 0xe160}});
2520 }
2521
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew16)2522 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew16) {
2523 VlxsegXeiXX<UInt16, 8, 1>(0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2524 {{0x9110, 0x8100, 0xb130, 0xa120, 0xf170, 0xd150, 0xc140, 0xe160},
2525 {0x9312, 0x8302, 0xb332, 0xa322, 0xf372, 0xd352, 0xc342, 0xe362},
2526 {0x9514, 0x8504, 0xb534, 0xa524, 0xf574, 0xd554, 0xc544, 0xe564},
2527 {0x9716, 0x8706, 0xb736, 0xa726, 0xf776, 0xd756, 0xc746, 0xe766},
2528 {0x9918, 0x8908, 0xb938, 0xa928, 0xf978, 0xd958, 0xc948, 0xe968},
2529 {0x9b1a, 0x8b0a, 0xbb3a, 0xab2a, 0xfb7a, 0xdb5a, 0xcb4a, 0xeb6a},
2530 {0x9d1c, 0x8d0c, 0xbd3c, 0xad2c, 0xfd7c, 0xdd5c, 0xcd4c, 0xed6c},
2531 {0x9f1e, 0x8f0e, 0xbf3e, 0xaf2e, 0xff7e, 0xdf5e, 0xcf4e, 0xef6e}});
2532 }
2533
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul1)2534 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul1) {
2535 VlxsegXeiXX<UInt32, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2536 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908}});
2537 }
2538
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul2)2539 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul2) {
2540 VlxsegXeiXX<UInt32, 1, 2>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2541 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908},
2542 {0x9f1e'9d1c, 0x9716'9514, 0x9312'9110, 0x9b1a'9918}});
2543 }
2544
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul4)2545 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul4) {
2546 VlxsegXeiXX<UInt32, 1, 4>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2547 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908},
2548 {0x9f1e'9d1c, 0x9716'9514, 0x9312'9110, 0x9b1a'9918},
2549 {0xa726'a524, 0xbb3a'b938, 0xbf3e'bd3c, 0xaf2e'ad2c},
2550 {0xb736'b534, 0xb332'b130, 0xa322'a120, 0xab2a'a928}});
2551 }
2552
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul8)2553 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul8) {
2554 VlxsegXeiXX<UInt32, 1, 8>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2555 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908},
2556 {0x9f1e'9d1c, 0x9716'9514, 0x9312'9110, 0x9b1a'9918},
2557 {0xa726'a524, 0xbb3a'b938, 0xbf3e'bd3c, 0xaf2e'ad2c},
2558 {0xb736'b534, 0xb332'b130, 0xa322'a120, 0xab2a'a928},
2559 {0xfb7a'f978, 0xff7e'fd7c, 0xc746'c544, 0xdb5a'd958},
2560 {0xcb4a'c948, 0xeb6a'e968, 0xe766'e564, 0xcf4e'cd4c},
2561 {0xf776'f574, 0xf372'f170, 0xc342'c140, 0xd756'd554},
2562 {0xef6e'ed6c, 0xe362'e160, 0xd352'd150, 0xdf5e'dd5c}});
2563 }
2564
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew32_vlmul1)2565 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew32_vlmul1) {
2566 VlxsegXeiXX<UInt32, 2, 1>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2567 {{0x8b0a'8908, 0x8302'8100, 0x9b1a'9918, 0x9312'9110},
2568 {0x8f0e'8d0c, 0x8706'8504, 0x9f1e'9d1c, 0x9716'9514}});
2569 }
2570
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew32_vlmul2)2571 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew32_vlmul2) {
2572 VlxsegXeiXX<UInt32, 2, 2>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2573 {{0x8b0a'8908, 0x8302'8100, 0x9b1a'9918, 0x9312'9110},
2574 {0xbb3a'b938, 0xab2a'a928, 0xa322'a120, 0xb332'b130},
2575 {0x8f0e'8d0c, 0x8706'8504, 0x9f1e'9d1c, 0x9716'9514},
2576 {0xbf3e'bd3c, 0xaf2e'ad2c, 0xa726'a524, 0xb736'b534}});
2577 }
2578
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew32_vlmul4)2579 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew32_vlmul4) {
2580 VlxsegXeiXX<UInt32, 2, 4>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2581 {{0x8b0a'8908, 0x8302'8100, 0x9b1a'9918, 0x9312'9110},
2582 {0xbb3a'b938, 0xab2a'a928, 0xa322'a120, 0xb332'b130},
2583 {0xcb4a'c948, 0xf372'f170, 0xfb7a'f978, 0xdb5a'd958},
2584 {0xeb6a'e968, 0xe362'e160, 0xc342'c140, 0xd352'd150},
2585 {0x8f0e'8d0c, 0x8706'8504, 0x9f1e'9d1c, 0x9716'9514},
2586 {0xbf3e'bd3c, 0xaf2e'ad2c, 0xa726'a524, 0xb736'b534},
2587 {0xcf4e'cd4c, 0xf776'f574, 0xff7e'fd7c, 0xdf5e'dd5c},
2588 {0xef6e'ed6c, 0xe766'e564, 0xc746'c544, 0xd756'd554}});
2589 }
2590
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew32_vlmul1)2591 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew32_vlmul1) {
2592 VlxsegXeiXX<UInt32, 3, 1>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2593 {{0x8f0e'8d0c, 0x8302'8100, 0xa726'a524, 0x9b1a'9918},
2594 {0x9312'9110, 0x8706'8504, 0xab2a'a928, 0x9f1e'9d1c},
2595 {0x9716'9514, 0x8b0a'8908, 0xaf2e'ad2c, 0xa322'a120}});
2596 }
2597
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew32_vlmul2)2598 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew32_vlmul2) {
2599 VlxsegXeiXX<UInt32, 3, 2>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2600 {{0x8f0e'8d0c, 0x8302'8100, 0xa726'a524, 0x9b1a'9918},
2601 {0xd756'd554, 0xbf3e'bd3c, 0xb332'b130, 0xcb4a'c948},
2602 {0x9312'9110, 0x8706'8504, 0xab2a'a928, 0x9f1e'9d1c},
2603 {0xdb5a'd958, 0xc342'c140, 0xb736'b534, 0xcf4e'cd4c},
2604 {0x9716'9514, 0x8b0a'8908, 0xaf2e'ad2c, 0xa322'a120},
2605 {0xdf5e'dd5c, 0xc746'c544, 0xbb3a'b938, 0xd352'd150}});
2606 }
2607
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew32_vlmul1)2608 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew32_vlmul1) {
2609 VlxsegXeiXX<UInt32, 4, 1>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2610 {{0x9312'9110, 0x8302'8100, 0xb332'b130, 0xa322'a120},
2611 {0x9716'9514, 0x8706'8504, 0xb736'b534, 0xa726'a524},
2612 {0x9b1a'9918, 0x8b0a'8908, 0xbb3a'b938, 0xab2a'a928},
2613 {0x9f1e'9d1c, 0x8f0e'8d0c, 0xbf3e'bd3c, 0xaf2e'ad2c}});
2614 }
2615
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew32_vlmul2)2616 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew32_vlmul2) {
2617 VlxsegXeiXX<UInt32, 4, 2>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2618 {{0x9312'9110, 0x8302'8100, 0xb332'b130, 0xa322'a120},
2619 {0xf372'f170, 0xd352'd150, 0xc342'c140, 0xe362'e160},
2620 {0x9716'9514, 0x8706'8504, 0xb736'b534, 0xa726'a524},
2621 {0xf776'f574, 0xd756'd554, 0xc746'c544, 0xe766'e564},
2622 {0x9b1a'9918, 0x8b0a'8908, 0xbb3a'b938, 0xab2a'a928},
2623 {0xfb7a'f978, 0xdb5a'd958, 0xcb4a'c948, 0xeb6a'e968},
2624 {0x9f1e'9d1c, 0x8f0e'8d0c, 0xbf3e'bd3c, 0xaf2e'ad2c},
2625 {0xff7e'fd7c, 0xdf5e'dd5c, 0xcf4e'cd4c, 0xef6e'ed6c}});
2626 }
2627
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew32)2628 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew32) {
2629 VlxsegXeiXX<UInt32, 5, 1>(0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2630 {{0x9716'9514, 0x8302'8100, 0xbf3e'bd3c, 0xab2a'a928},
2631 {0x9b1a'9918, 0x8706'8504, 0xc342'c140, 0xaf2e'ad2c},
2632 {0x9f1e'9d1c, 0x8b0a'8908, 0xc746'c544, 0xb332'b130},
2633 {0xa322'a120, 0x8f0e'8d0c, 0xcb4a'c948, 0xb736'b534},
2634 {0xa726'a524, 0x9312'9110, 0xcf4e'cd4c, 0xbb3a'b938}});
2635 }
2636
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew32)2637 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew32) {
2638 VlxsegXeiXX<UInt32, 6, 1>(0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2639 {{0x9b1a'9918, 0x8302'8100, 0xcb4a'c948, 0xb332'b130},
2640 {0x9f1e'9d1c, 0x8706'8504, 0xcf4e'cd4c, 0xb736'b534},
2641 {0xa322'a120, 0x8b0a'8908, 0xd352'd150, 0xbb3a'b938},
2642 {0xa726'a524, 0x8f0e'8d0c, 0xd756'd554, 0xbf3e'bd3c},
2643 {0xab2a'a928, 0x9312'9110, 0xdb5a'd958, 0xc342'c140},
2644 {0xaf2e'ad2c, 0x9716'9514, 0xdf5e'dd5c, 0xc746'c544}});
2645 }
2646
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew32)2647 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew32) {
2648 VlxsegXeiXX<UInt32, 7, 1>(0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2649 {{0x9f1e'9d1c, 0x8302'8100, 0xd756'd554, 0xbb3a'b938},
2650 {0xa322'a120, 0x8706'8504, 0xdb5a'd958, 0xbf3e'bd3c},
2651 {0xa726'a524, 0x8b0a'8908, 0xdf5e'dd5c, 0xc342'c140},
2652 {0xab2a'a928, 0x8f0e'8d0c, 0xe362'e160, 0xc746'c544},
2653 {0xaf2e'ad2c, 0x9312'9110, 0xe766'e564, 0xcb4a'c948},
2654 {0xb332'b130, 0x9716'9514, 0xeb6a'e968, 0xcf4e'cd4c},
2655 {0xb736'b534, 0x9b1a'9918, 0xef6e'ed6c, 0xd352'd150}});
2656 }
2657
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew32)2658 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew32) {
2659 VlxsegXeiXX<UInt32, 8, 1>(0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2660 {{0xa322'a120, 0x8302'8100, 0xe362'e160, 0xc342'c140},
2661 {0xa726'a524, 0x8706'8504, 0xe766'e564, 0xc746'c544},
2662 {0xab2a'a928, 0x8b0a'8908, 0xeb6a'e968, 0xcb4a'c948},
2663 {0xaf2e'ad2c, 0x8f0e'8d0c, 0xef6e'ed6c, 0xcf4e'cd4c},
2664 {0xb332'b130, 0x9312'9110, 0xf372'f170, 0xd352'd150},
2665 {0xb736'b534, 0x9716'9514, 0xf776'f574, 0xd756'd554},
2666 {0xbb3a'b938, 0x9b1a'9918, 0xfb7a'f978, 0xdb5a'd958},
2667 {0xbf3e'bd3c, 0x9f1e'9d1c, 0xff7e'fd7c, 0xdf5e'dd5c}});
2668 }
2669
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul1)2670 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul1) {
2671 VlxsegXeiXX<UInt64, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2672 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100}});
2673 }
2674
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul2)2675 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul2) {
2676 VlxsegXeiXX<UInt64, 1, 2>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2677 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100},
2678 {0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110}});
2679 }
2680
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul4)2681 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul4) {
2682 VlxsegXeiXX<UInt64, 1, 4>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2683 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100},
2684 {0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110},
2685 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928},
2686 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130}});
2687 }
2688
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul8)2689 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul8) {
2690 VlxsegXeiXX<UInt64, 1, 8>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2691 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100},
2692 {0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110},
2693 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928},
2694 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
2695 {0xcf4e'cd4c'cb4a'c948, 0xf776'f574'f372'f170},
2696 {0xff7e'fd7c'fb7a'f978, 0xdf5e'dd5c'db5a'd958},
2697 {0xef6e'ed6c'eb6a'e968, 0xe766'e564'e362'e160},
2698 {0xc746'c544'c342'c140, 0xd756'd554'd352'd150}});
2699 }
2700
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew64_vlmul1)2701 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew64_vlmul1) {
2702 VlxsegXeiXX<UInt64, 2, 1>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2703 {{0x9716'9514'9312'9110, 0x8706'8504'8302'8100},
2704 {0x9f1e'9d1c'9b1a'9918, 0x8f0e'8d0c'8b0a'8908}});
2705 }
2706
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew64_vlmul2)2707 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew64_vlmul2) {
2708 VlxsegXeiXX<UInt64, 2, 2>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2709 {{0x9716'9514'9312'9110, 0x8706'8504'8302'8100},
2710 {0xb736'b534'b332'b130, 0xa726'a524'a322'a120},
2711 {0x9f1e'9d1c'9b1a'9918, 0x8f0e'8d0c'8b0a'8908},
2712 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928}});
2713 }
2714
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew64_vlmul4)2715 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew64_vlmul4) {
2716 VlxsegXeiXX<UInt64, 2, 4>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2717 {{0x9716'9514'9312'9110, 0x8706'8504'8302'8100},
2718 {0xb736'b534'b332'b130, 0xa726'a524'a322'a120},
2719 {0xf776'f574'f372'f170, 0xd756'd554'd352'd150},
2720 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
2721 {0x9f1e'9d1c'9b1a'9918, 0x8f0e'8d0c'8b0a'8908},
2722 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928},
2723 {0xff7e'fd7c'fb7a'f978, 0xdf5e'dd5c'db5a'd958},
2724 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968}});
2725 }
2726
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew64_vlmul1)2727 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew64_vlmul1) {
2728 VlxsegXeiXX<UInt64, 3, 1>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2729 {{0x9f1e'9d1c'9b1a'9918, 0x8706'8504'8302'8100},
2730 {0xa726'a524'a322'a120, 0x8f0e'8d0c'8b0a'8908},
2731 {0xaf2e'ad2c'ab2a'a928, 0x9716'9514'9312'9110}});
2732 }
2733
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew64_vlmul2)2734 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew64_vlmul2) {
2735 VlxsegXeiXX<UInt64, 3, 2>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2736 {{0x9f1e'9d1c'9b1a'9918, 0x8706'8504'8302'8100},
2737 {0xcf4e'cd4c'cb4a'c948, 0xb736'b534'b332'b130},
2738 {0xa726'a524'a322'a120, 0x8f0e'8d0c'8b0a'8908},
2739 {0xd756'd554'd352'd150, 0xbf3e'bd3c'bb3a'b938},
2740 {0xaf2e'ad2c'ab2a'a928, 0x9716'9514'9312'9110},
2741 {0xdf5e'dd5c'db5a'd958, 0xc746'c544'c342'c140}});
2742 }
2743
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew64_vlmul1)2744 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew64_vlmul1) {
2745 VlxsegXeiXX<UInt64, 4, 1>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2746 {{0xa726'a524'a322'a120, 0x8706'8504'8302'8100},
2747 {0xaf2e'ad2c'ab2a'a928, 0x8f0e'8d0c'8b0a'8908},
2748 {0xb736'b534'b332'b130, 0x9716'9514'9312'9110},
2749 {0xbf3e'bd3c'bb3a'b938, 0x9f1e'9d1c'9b1a'9918}});
2750 }
2751
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew64_vlmul2)2752 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew64_vlmul2) {
2753 VlxsegXeiXX<UInt64, 4, 2>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2754 {{0xa726'a524'a322'a120, 0x8706'8504'8302'8100},
2755 {0xe766'e564'e362'e160, 0xc746'c544'c342'c140},
2756 {0xaf2e'ad2c'ab2a'a928, 0x8f0e'8d0c'8b0a'8908},
2757 {0xef6e'ed6c'eb6a'e968, 0xcf4e'cd4c'cb4a'c948},
2758 {0xb736'b534'b332'b130, 0x9716'9514'9312'9110},
2759 {0xf776'f574'f372'f170, 0xd756'd554'd352'd150},
2760 {0xbf3e'bd3c'bb3a'b938, 0x9f1e'9d1c'9b1a'9918},
2761 {0xff7e'fd7c'fb7a'f978, 0xdf5e'dd5c'db5a'd958}});
2762 }
2763
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew64)2764 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew64) {
2765 VlxsegXeiXX<UInt64, 5, 1>(0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2766 {{0xaf2e'ad2c'ab2a'a928, 0x8706'8504'8302'8100},
2767 {0xb736'b534'b332'b130, 0x8f0e'8d0c'8b0a'8908},
2768 {0xbf3e'bd3c'bb3a'b938, 0x9716'9514'9312'9110},
2769 {0xc746'c544'c342'c140, 0x9f1e'9d1c'9b1a'9918},
2770 {0xcf4e'cd4c'cb4a'c948, 0xa726'a524'a322'a120}});
2771 }
2772
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew64)2773 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew64) {
2774 VlxsegXeiXX<UInt64, 6, 1>(0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2775 {{0xb736'b534'b332'b130, 0x8706'8504'8302'8100},
2776 {0xbf3e'bd3c'bb3a'b938, 0x8f0e'8d0c'8b0a'8908},
2777 {0xc746'c544'c342'c140, 0x9716'9514'9312'9110},
2778 {0xcf4e'cd4c'cb4a'c948, 0x9f1e'9d1c'9b1a'9918},
2779 {0xd756'd554'd352'd150, 0xa726'a524'a322'a120},
2780 {0xdf5e'dd5c'db5a'd958, 0xaf2e'ad2c'ab2a'a928}});
2781 }
2782
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew64)2783 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew64) {
2784 VlxsegXeiXX<UInt64, 7, 1>(0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2785 {{0xbf3e'bd3c'bb3a'b938, 0x8706'8504'8302'8100},
2786 {0xc746'c544'c342'c140, 0x8f0e'8d0c'8b0a'8908},
2787 {0xcf4e'cd4c'cb4a'c948, 0x9716'9514'9312'9110},
2788 {0xd756'd554'd352'd150, 0x9f1e'9d1c'9b1a'9918},
2789 {0xdf5e'dd5c'db5a'd958, 0xa726'a524'a322'a120},
2790 {0xe766'e564'e362'e160, 0xaf2e'ad2c'ab2a'a928},
2791 {0xef6e'ed6c'eb6a'e968, 0xb736'b534'b332'b130}});
2792 }
2793
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew64)2794 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew64) {
2795 VlxsegXeiXX<UInt64, 8, 1>(0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2796 {{0xc746'c544'c342'c140, 0x8706'8504'8302'8100},
2797 {0xcf4e'cd4c'cb4a'c948, 0x8f0e'8d0c'8b0a'8908},
2798 {0xd756'd554'd352'd150, 0x9716'9514'9312'9110},
2799 {0xdf5e'dd5c'db5a'd958, 0x9f1e'9d1c'9b1a'9918},
2800 {0xe766'e564'e362'e160, 0xa726'a524'a322'a120},
2801 {0xef6e'ed6c'eb6a'e968, 0xaf2e'ad2c'ab2a'a928},
2802 {0xf776'f574'f372'f170, 0xb736'b534'b332'b130},
2803 {0xff7e'fd7c'fb7a'f978, 0xbf3e'bd3c'bb3a'b938}});
2804 }
2805
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul1)2806 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul1) {
2807 TestVlsegXeXX<UInt8, 1, 1>(0x000008407, // vlse8.v v8, (x1), v0.t
2808 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143}});
2809 }
2810
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul2)2811 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul2) {
2812 TestVlsegXeXX<UInt8, 1, 2>(
2813 0x000008407, // vlse8.v v8, (x1), v0.t
2814 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
2815 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159}});
2816 }
2817
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul4)2818 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul4) {
2819 TestVlsegXeXX<UInt8, 1, 4>(
2820 0x000008407, // vlse8.v v8, (x1), v0.t
2821 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
2822 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
2823 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
2824 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191}});
2825 }
2826
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul8)2827 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul8) {
2828 TestVlsegXeXX<UInt8, 1, 8>(
2829 0x000008407, // vlse8.v v8, (x1), v0.t
2830 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
2831 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
2832 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
2833 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191},
2834 {64, 193, 66, 195, 68, 197, 70, 199, 72, 201, 74, 203, 76, 205, 78, 207},
2835 {80, 209, 82, 211, 84, 213, 86, 215, 88, 217, 90, 219, 92, 221, 94, 223},
2836 {96, 225, 98, 227, 100, 229, 102, 231, 104, 233, 106, 235, 108, 237, 110, 239},
2837 {112, 241, 114, 243, 116, 245, 118, 247, 120, 249, 122, 251, 124, 253, 126, 255}});
2838 }
2839
TEST_F(Riscv64InterpreterTest,TestVlseg2e8_vlmul1)2840 TEST_F(Riscv64InterpreterTest, TestVlseg2e8_vlmul1) {
2841 TestVlsegXeXX<UInt8, 2, 1>(
2842 0x20008407, // vlseg2e8.v v8, (x1), v0.t
2843 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
2844 {129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159}});
2845 }
2846
TEST_F(Riscv64InterpreterTest,TestVlseg2e8_vlmul2)2847 TEST_F(Riscv64InterpreterTest, TestVlseg2e8_vlmul2) {
2848 TestVlsegXeXX<UInt8, 2, 2>(
2849 0x20008407, // vlseg2e8.v v8, (x1), v0.t
2850 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
2851 {32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62},
2852 {129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159},
2853 {161, 163, 165, 167, 169, 171, 173, 175, 177, 179, 181, 183, 185, 187, 189, 191}});
2854 }
2855
TEST_F(Riscv64InterpreterTest,TestVlseg2e8_vlmul4)2856 TEST_F(Riscv64InterpreterTest, TestVlseg2e8_vlmul4) {
2857 TestVlsegXeXX<UInt8, 2, 4>(
2858 0x20008407, // vlseg2e8.v v8, (x1), v0.t
2859 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
2860 {32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62},
2861 {64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94},
2862 {96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126},
2863 {129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159},
2864 {161, 163, 165, 167, 169, 171, 173, 175, 177, 179, 181, 183, 185, 187, 189, 191},
2865 {193, 195, 197, 199, 201, 203, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223},
2866 {225, 227, 229, 231, 233, 235, 237, 239, 241, 243, 245, 247, 249, 251, 253, 255}});
2867 }
2868
TEST_F(Riscv64InterpreterTest,TestVlseg3e8_vlmul1)2869 TEST_F(Riscv64InterpreterTest, TestVlseg3e8_vlmul1) {
2870 TestVlsegXeXX<UInt8, 3, 1>(
2871 0x40008407, // vlseg3e8.v v8, (x1), v0.t
2872 {{0, 131, 6, 137, 12, 143, 18, 149, 24, 155, 30, 161, 36, 167, 42, 173},
2873 {129, 4, 135, 10, 141, 16, 147, 22, 153, 28, 159, 34, 165, 40, 171, 46},
2874 {2, 133, 8, 139, 14, 145, 20, 151, 26, 157, 32, 163, 38, 169, 44, 175}});
2875 }
2876
TEST_F(Riscv64InterpreterTest,TestVlseg3e8_vlmul2)2877 TEST_F(Riscv64InterpreterTest, TestVlseg3e8_vlmul2) {
2878 TestVlsegXeXX<UInt8, 3, 2>(
2879 0x40008407, // vlseg3e8.v v8, (x1), v0.t
2880 {{0, 131, 6, 137, 12, 143, 18, 149, 24, 155, 30, 161, 36, 167, 42, 173},
2881 {48, 179, 54, 185, 60, 191, 66, 197, 72, 203, 78, 209, 84, 215, 90, 221},
2882 {129, 4, 135, 10, 141, 16, 147, 22, 153, 28, 159, 34, 165, 40, 171, 46},
2883 {177, 52, 183, 58, 189, 64, 195, 70, 201, 76, 207, 82, 213, 88, 219, 94},
2884 {2, 133, 8, 139, 14, 145, 20, 151, 26, 157, 32, 163, 38, 169, 44, 175},
2885 {50, 181, 56, 187, 62, 193, 68, 199, 74, 205, 80, 211, 86, 217, 92, 223}});
2886 }
2887
TEST_F(Riscv64InterpreterTest,TestVlseg4e8_vlmul1)2888 TEST_F(Riscv64InterpreterTest, TestVlseg4e8_vlmul1) {
2889 TestVlsegXeXX<UInt8, 4, 1>(
2890 0x60008407, // vlseg4e8.v v8, (x1), v0.t
2891 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
2892 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
2893 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
2894 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191}});
2895 }
2896
TEST_F(Riscv64InterpreterTest,TestVlseg4e8_vlmul2)2897 TEST_F(Riscv64InterpreterTest, TestVlseg4e8_vlmul2) {
2898 TestVlsegXeXX<UInt8, 4, 2>(
2899 0x60008407, // vlseg4e8.v v8, (x1), v0.t
2900 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
2901 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
2902 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
2903 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
2904 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
2905 {66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126},
2906 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191},
2907 {195, 199, 203, 207, 211, 215, 219, 223, 227, 231, 235, 239, 243, 247, 251, 255}});
2908 }
2909
TEST_F(Riscv64InterpreterTest,TestVlseg5e8)2910 TEST_F(Riscv64InterpreterTest, TestVlseg5e8) {
2911 TestVlsegXeXX<UInt8, 5, 1>(
2912 0x80008407, // vlseg5e8.v v8, (x1), v0.t
2913 {{0, 133, 10, 143, 20, 153, 30, 163, 40, 173, 50, 183, 60, 193, 70, 203},
2914 {129, 6, 139, 16, 149, 26, 159, 36, 169, 46, 179, 56, 189, 66, 199, 76},
2915 {2, 135, 12, 145, 22, 155, 32, 165, 42, 175, 52, 185, 62, 195, 72, 205},
2916 {131, 8, 141, 18, 151, 28, 161, 38, 171, 48, 181, 58, 191, 68, 201, 78},
2917 {4, 137, 14, 147, 24, 157, 34, 167, 44, 177, 54, 187, 64, 197, 74, 207}});
2918 }
2919
TEST_F(Riscv64InterpreterTest,TestVlseg6e8)2920 TEST_F(Riscv64InterpreterTest, TestVlseg6e8) {
2921 TestVlsegXeXX<UInt8, 6, 1>(
2922 0xa0008407, // vlseg6e8.v v8, (x1), v0.t
2923 {{0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90},
2924 {129, 135, 141, 147, 153, 159, 165, 171, 177, 183, 189, 195, 201, 207, 213, 219},
2925 {2, 8, 14, 20, 26, 32, 38, 44, 50, 56, 62, 68, 74, 80, 86, 92},
2926 {131, 137, 143, 149, 155, 161, 167, 173, 179, 185, 191, 197, 203, 209, 215, 221},
2927 {4, 10, 16, 22, 28, 34, 40, 46, 52, 58, 64, 70, 76, 82, 88, 94},
2928 {133, 139, 145, 151, 157, 163, 169, 175, 181, 187, 193, 199, 205, 211, 217, 223}});
2929 }
2930
TEST_F(Riscv64InterpreterTest,TestVlseg7e8)2931 TEST_F(Riscv64InterpreterTest, TestVlseg7e8) {
2932 TestVlsegXeXX<UInt8, 7, 1>(
2933 0xc0008407, // vlseg7e8.v v8, (x1), v0.t
2934 {{0, 135, 14, 149, 28, 163, 42, 177, 56, 191, 70, 205, 84, 219, 98, 233},
2935 {129, 8, 143, 22, 157, 36, 171, 50, 185, 64, 199, 78, 213, 92, 227, 106},
2936 {2, 137, 16, 151, 30, 165, 44, 179, 58, 193, 72, 207, 86, 221, 100, 235},
2937 {131, 10, 145, 24, 159, 38, 173, 52, 187, 66, 201, 80, 215, 94, 229, 108},
2938 {4, 139, 18, 153, 32, 167, 46, 181, 60, 195, 74, 209, 88, 223, 102, 237},
2939 {133, 12, 147, 26, 161, 40, 175, 54, 189, 68, 203, 82, 217, 96, 231, 110},
2940 {6, 141, 20, 155, 34, 169, 48, 183, 62, 197, 76, 211, 90, 225, 104, 239}});
2941 }
2942
TEST_F(Riscv64InterpreterTest,TestVlseg8e8)2943 TEST_F(Riscv64InterpreterTest, TestVlseg8e8) {
2944 TestVlsegXeXX<UInt8, 8, 1>(
2945 0xe0008407, // vlseg8e8.v v8, (x1), v0.t
2946 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
2947 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
2948 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
2949 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
2950 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
2951 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253},
2952 {6, 14, 22, 30, 38, 46, 54, 62, 70, 78, 86, 94, 102, 110, 118, 126},
2953 {135, 143, 151, 159, 167, 175, 183, 191, 199, 207, 215, 223, 231, 239, 247, 255}});
2954 }
2955
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul1)2956 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul1) {
2957 TestVlsegXeXX<UInt16, 1, 1>(0x000d407, // vle16.v v8, (x1), v0.t
2958 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e}});
2959 }
2960
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul2)2961 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul2) {
2962 TestVlsegXeXX<UInt16, 1, 2>(0x000d407, // vle16.v v8, (x1), v0.t
2963 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
2964 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e}});
2965 }
2966
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul4)2967 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul4) {
2968 TestVlsegXeXX<UInt16, 1, 4>(0x000d407, // vle16.v v8, (x1), v0.t
2969 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
2970 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
2971 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
2972 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e}});
2973 }
2974
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul8)2975 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul8) {
2976 TestVlsegXeXX<UInt16, 1, 8>(0x000d407, // vle16.v v8, (x1), v0.t
2977 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
2978 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
2979 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
2980 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e},
2981 {0xc140, 0xc342, 0xc544, 0xc746, 0xc948, 0xcb4a, 0xcd4c, 0xcf4e},
2982 {0xd150, 0xd352, 0xd554, 0xd756, 0xd958, 0xdb5a, 0xdd5c, 0xdf5e},
2983 {0xe160, 0xe362, 0xe564, 0xe766, 0xe968, 0xeb6a, 0xed6c, 0xef6e},
2984 {0xf170, 0xf372, 0xf574, 0xf776, 0xf978, 0xfb7a, 0xfd7c, 0xff7e}});
2985 }
2986
TEST_F(Riscv64InterpreterTest,TestVlseg2e16_vlmul1)2987 TEST_F(Riscv64InterpreterTest, TestVlseg2e16_vlmul1) {
2988 TestVlsegXeXX<UInt16, 2, 1>(0x2000d407, // vlseg2e16.v v8, (x1), v0.t
2989 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
2990 {0x8302, 0x8706, 0x8b0a, 0x8f0e, 0x9312, 0x9716, 0x9b1a, 0x9f1e}});
2991 }
2992
TEST_F(Riscv64InterpreterTest,TestVlseg2e16_vlmul2)2993 TEST_F(Riscv64InterpreterTest, TestVlseg2e16_vlmul2) {
2994 TestVlsegXeXX<UInt16, 2, 2>(0x2000d407, // vlseg2e16.v v8, (x1), v0.t
2995 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
2996 {0xa120, 0xa524, 0xa928, 0xad2c, 0xb130, 0xb534, 0xb938, 0xbd3c},
2997 {0x8302, 0x8706, 0x8b0a, 0x8f0e, 0x9312, 0x9716, 0x9b1a, 0x9f1e},
2998 {0xa322, 0xa726, 0xab2a, 0xaf2e, 0xb332, 0xb736, 0xbb3a, 0xbf3e}});
2999 }
3000
TEST_F(Riscv64InterpreterTest,TestVlseg2e16_vlmul4)3001 TEST_F(Riscv64InterpreterTest, TestVlseg2e16_vlmul4) {
3002 TestVlsegXeXX<UInt16, 2, 4>(0x2000d407, // vlseg2e16.v v8, (x1), v0.t
3003 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
3004 {0xa120, 0xa524, 0xa928, 0xad2c, 0xb130, 0xb534, 0xb938, 0xbd3c},
3005 {0xc140, 0xc544, 0xc948, 0xcd4c, 0xd150, 0xd554, 0xd958, 0xdd5c},
3006 {0xe160, 0xe564, 0xe968, 0xed6c, 0xf170, 0xf574, 0xf978, 0xfd7c},
3007 {0x8302, 0x8706, 0x8b0a, 0x8f0e, 0x9312, 0x9716, 0x9b1a, 0x9f1e},
3008 {0xa322, 0xa726, 0xab2a, 0xaf2e, 0xb332, 0xb736, 0xbb3a, 0xbf3e},
3009 {0xc342, 0xc746, 0xcb4a, 0xcf4e, 0xd352, 0xd756, 0xdb5a, 0xdf5e},
3010 {0xe362, 0xe766, 0xeb6a, 0xef6e, 0xf372, 0xf776, 0xfb7a, 0xff7e}});
3011 }
3012
TEST_F(Riscv64InterpreterTest,TestVlseg3e16_vlmul1)3013 TEST_F(Riscv64InterpreterTest, TestVlseg3e16_vlmul1) {
3014 TestVlsegXeXX<UInt16, 3, 1>(0x4000d407, // vlseg3e16.v v8, (x1), v0.t
3015 {{0x8100, 0x8706, 0x8d0c, 0x9312, 0x9918, 0x9f1e, 0xa524, 0xab2a},
3016 {0x8302, 0x8908, 0x8f0e, 0x9514, 0x9b1a, 0xa120, 0xa726, 0xad2c},
3017 {0x8504, 0x8b0a, 0x9110, 0x9716, 0x9d1c, 0xa322, 0xa928, 0xaf2e}});
3018 }
3019
TEST_F(Riscv64InterpreterTest,TestVlseg3e16_vlmul2)3020 TEST_F(Riscv64InterpreterTest, TestVlseg3e16_vlmul2) {
3021 TestVlsegXeXX<UInt16, 3, 2>(0x4000d407, // vlseg3e16.v v8, (x1), v0.t
3022 {{0x8100, 0x8706, 0x8d0c, 0x9312, 0x9918, 0x9f1e, 0xa524, 0xab2a},
3023 {0xb130, 0xb736, 0xbd3c, 0xc342, 0xc948, 0xcf4e, 0xd554, 0xdb5a},
3024 {0x8302, 0x8908, 0x8f0e, 0x9514, 0x9b1a, 0xa120, 0xa726, 0xad2c},
3025 {0xb332, 0xb938, 0xbf3e, 0xc544, 0xcb4a, 0xd150, 0xd756, 0xdd5c},
3026 {0x8504, 0x8b0a, 0x9110, 0x9716, 0x9d1c, 0xa322, 0xa928, 0xaf2e},
3027 {0xb534, 0xbb3a, 0xc140, 0xc746, 0xcd4c, 0xd352, 0xd958, 0xdf5e}});
3028 }
3029
TEST_F(Riscv64InterpreterTest,TestVlseg4e16_vlmul1)3030 TEST_F(Riscv64InterpreterTest, TestVlseg4e16_vlmul1) {
3031 TestVlsegXeXX<UInt16, 4, 1>(0x6000d407, // vlseg4e16.v v8, (x1), v0.t
3032 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3033 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3034 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3035 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e}});
3036 }
3037
TEST_F(Riscv64InterpreterTest,TestVlseg4e16_vlmul2)3038 TEST_F(Riscv64InterpreterTest, TestVlseg4e16_vlmul2) {
3039 TestVlsegXeXX<UInt16, 4, 2>(0x6000d407, // vlseg4e16.v v8, (x1), v0.t
3040 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3041 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3042 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3043 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3044 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3045 {0xc544, 0xcd4c, 0xd554, 0xdd5c, 0xe564, 0xed6c, 0xf574, 0xfd7c},
3046 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e},
3047 {0xc746, 0xcf4e, 0xd756, 0xdf5e, 0xe766, 0xef6e, 0xf776, 0xff7e}});
3048 }
3049
TEST_F(Riscv64InterpreterTest,TestVlseg5e16)3050 TEST_F(Riscv64InterpreterTest, TestVlseg5e16) {
3051 TestVlsegXeXX<UInt16, 5, 1>(0x8000d407, // vlseg5e16.v v8, (x1), v0.t
3052 {{0x8100, 0x8b0a, 0x9514, 0x9f1e, 0xa928, 0xb332, 0xbd3c, 0xc746},
3053 {0x8302, 0x8d0c, 0x9716, 0xa120, 0xab2a, 0xb534, 0xbf3e, 0xc948},
3054 {0x8504, 0x8f0e, 0x9918, 0xa322, 0xad2c, 0xb736, 0xc140, 0xcb4a},
3055 {0x8706, 0x9110, 0x9b1a, 0xa524, 0xaf2e, 0xb938, 0xc342, 0xcd4c},
3056 {0x8908, 0x9312, 0x9d1c, 0xa726, 0xb130, 0xbb3a, 0xc544, 0xcf4e}});
3057 }
3058
TEST_F(Riscv64InterpreterTest,TestVlseg6e16)3059 TEST_F(Riscv64InterpreterTest, TestVlseg6e16) {
3060 TestVlsegXeXX<UInt16, 6, 1>(0xa000d407, // vlseg6e16.v v8, (x1), v0.t
3061 {{0x8100, 0x8d0c, 0x9918, 0xa524, 0xb130, 0xbd3c, 0xc948, 0xd554},
3062 {0x8302, 0x8f0e, 0x9b1a, 0xa726, 0xb332, 0xbf3e, 0xcb4a, 0xd756},
3063 {0x8504, 0x9110, 0x9d1c, 0xa928, 0xb534, 0xc140, 0xcd4c, 0xd958},
3064 {0x8706, 0x9312, 0x9f1e, 0xab2a, 0xb736, 0xc342, 0xcf4e, 0xdb5a},
3065 {0x8908, 0x9514, 0xa120, 0xad2c, 0xb938, 0xc544, 0xd150, 0xdd5c},
3066 {0x8b0a, 0x9716, 0xa322, 0xaf2e, 0xbb3a, 0xc746, 0xd352, 0xdf5e}});
3067 }
3068
TEST_F(Riscv64InterpreterTest,TestVlseg7e16)3069 TEST_F(Riscv64InterpreterTest, TestVlseg7e16) {
3070 TestVlsegXeXX<UInt16, 7, 1>(0xc000d407, // vlseg7e16.v v8, (x1), v0.t
3071 {{0x8100, 0x8f0e, 0x9d1c, 0xab2a, 0xb938, 0xc746, 0xd554, 0xe362},
3072 {0x8302, 0x9110, 0x9f1e, 0xad2c, 0xbb3a, 0xc948, 0xd756, 0xe564},
3073 {0x8504, 0x9312, 0xa120, 0xaf2e, 0xbd3c, 0xcb4a, 0xd958, 0xe766},
3074 {0x8706, 0x9514, 0xa322, 0xb130, 0xbf3e, 0xcd4c, 0xdb5a, 0xe968},
3075 {0x8908, 0x9716, 0xa524, 0xb332, 0xc140, 0xcf4e, 0xdd5c, 0xeb6a},
3076 {0x8b0a, 0x9918, 0xa726, 0xb534, 0xc342, 0xd150, 0xdf5e, 0xed6c},
3077 {0x8d0c, 0x9b1a, 0xa928, 0xb736, 0xc544, 0xd352, 0xe160, 0xef6e}});
3078 }
3079
TEST_F(Riscv64InterpreterTest,TestVlseg8e16)3080 TEST_F(Riscv64InterpreterTest, TestVlseg8e16) {
3081 TestVlsegXeXX<UInt16, 8, 1>(0xe000d407, // vlseg8e16.v v8, (x1), v0.t
3082 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3083 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3084 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3085 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3086 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3087 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a},
3088 {0x8d0c, 0x9d1c, 0xad2c, 0xbd3c, 0xcd4c, 0xdd5c, 0xed6c, 0xfd7c},
3089 {0x8f0e, 0x9f1e, 0xaf2e, 0xbf3e, 0xcf4e, 0xdf5e, 0xef6e, 0xff7e}});
3090 }
3091
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul1)3092 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul1) {
3093 TestVlsegXeXX<UInt32, 1, 1>(0x000e407, // vle32.v v8, (x1), v0.t
3094 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c}});
3095 }
3096
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul2)3097 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul2) {
3098 TestVlsegXeXX<UInt32, 1, 2>(0x000e407, // vle32.v v8, (x1), v0.t
3099 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
3100 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c}});
3101 }
3102
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul4)3103 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul4) {
3104 TestVlsegXeXX<UInt32, 1, 4>(0x000e407, // vle32.v v8, (x1), v0.t
3105 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
3106 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
3107 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
3108 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c}});
3109 }
3110
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul8)3111 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul8) {
3112 TestVlsegXeXX<UInt32, 1, 8>(0x000e407, // vle32.v v8, (x1), v0.t
3113 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
3114 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
3115 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
3116 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
3117 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
3118 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
3119 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
3120 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}});
3121 }
3122
TEST_F(Riscv64InterpreterTest,TestVlseg2e32_vlmul1)3123 TEST_F(Riscv64InterpreterTest, TestVlseg2e32_vlmul1) {
3124 TestVlsegXeXX<UInt32, 2, 1>(0x2000e407, // vlseg2e32.v v8, (x1), v0.t
3125 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3126 {0x8706'8504, 0x8f0e'8d0c, 0x9716'9514, 0x9f1e'9d1c}});
3127 }
3128
TEST_F(Riscv64InterpreterTest,TestVlseg2e32_vlmul2)3129 TEST_F(Riscv64InterpreterTest, TestVlseg2e32_vlmul2) {
3130 TestVlsegXeXX<UInt32, 2, 2>(0x2000e407, // vlseg2e32.v v8, (x1), v0.t
3131 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3132 {0xa322'a120, 0xab2a'a928, 0xb332'b130, 0xbb3a'b938},
3133 {0x8706'8504, 0x8f0e'8d0c, 0x9716'9514, 0x9f1e'9d1c},
3134 {0xa726'a524, 0xaf2e'ad2c, 0xb736'b534, 0xbf3e'bd3c}});
3135 }
3136
TEST_F(Riscv64InterpreterTest,TestVlseg2e32_vlmul4)3137 TEST_F(Riscv64InterpreterTest, TestVlseg2e32_vlmul4) {
3138 TestVlsegXeXX<UInt32, 2, 4>(0x2000e407, // vlseg2e32.v v8, (x1), v0.t
3139 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3140 {0xa322'a120, 0xab2a'a928, 0xb332'b130, 0xbb3a'b938},
3141 {0xc342'c140, 0xcb4a'c948, 0xd352'd150, 0xdb5a'd958},
3142 {0xe362'e160, 0xeb6a'e968, 0xf372'f170, 0xfb7a'f978},
3143 {0x8706'8504, 0x8f0e'8d0c, 0x9716'9514, 0x9f1e'9d1c},
3144 {0xa726'a524, 0xaf2e'ad2c, 0xb736'b534, 0xbf3e'bd3c},
3145 {0xc746'c544, 0xcf4e'cd4c, 0xd756'd554, 0xdf5e'dd5c},
3146 {0xe766'e564, 0xef6e'ed6c, 0xf776'f574, 0xff7e'fd7c}});
3147 }
3148
TEST_F(Riscv64InterpreterTest,TestVlseg3e32_vlmul1)3149 TEST_F(Riscv64InterpreterTest, TestVlseg3e32_vlmul1) {
3150 TestVlsegXeXX<UInt32, 3, 1>(0x4000e407, // vlseg3e32.v v8, (x1), v0.t
3151 {{0x8302'8100, 0x8f0e'8d0c, 0x9b1a'9918, 0xa726'a524},
3152 {0x8706'8504, 0x9312'9110, 0x9f1e'9d1c, 0xab2a'a928},
3153 {0x8b0a'8908, 0x9716'9514, 0xa322'a120, 0xaf2e'ad2c}});
3154 }
3155
TEST_F(Riscv64InterpreterTest,TestVlseg3e32_vlmul2)3156 TEST_F(Riscv64InterpreterTest, TestVlseg3e32_vlmul2) {
3157 TestVlsegXeXX<UInt32, 3, 2>(0x4000e407, // vlseg3e32.v v8, (x1), v0.t
3158 {{0x8302'8100, 0x8f0e'8d0c, 0x9b1a'9918, 0xa726'a524},
3159 {0xb332'b130, 0xbf3e'bd3c, 0xcb4a'c948, 0xd756'd554},
3160 {0x8706'8504, 0x9312'9110, 0x9f1e'9d1c, 0xab2a'a928},
3161 {0xb736'b534, 0xc342'c140, 0xcf4e'cd4c, 0xdb5a'd958},
3162 {0x8b0a'8908, 0x9716'9514, 0xa322'a120, 0xaf2e'ad2c},
3163 {0xbb3a'b938, 0xc746'c544, 0xd352'd150, 0xdf5e'dd5c}});
3164 }
3165
TEST_F(Riscv64InterpreterTest,TestVlseg4e32_vlmul1)3166 TEST_F(Riscv64InterpreterTest, TestVlseg4e32_vlmul1) {
3167 TestVlsegXeXX<UInt32, 4, 1>(0x6000e407, // vlseg4e32.v v8, (x1), v0.t
3168 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3169 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3170 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3171 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c}});
3172 }
3173
TEST_F(Riscv64InterpreterTest,TestVlseg4e32_vlmul2)3174 TEST_F(Riscv64InterpreterTest, TestVlseg4e32_vlmul2) {
3175 TestVlsegXeXX<UInt32, 4, 2>(0x6000e407, // vlseg4e32.v v8, (x1), v0.t
3176 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3177 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3178 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3179 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3180 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3181 {0xcb4a'c948, 0xdb5a'd958, 0xeb6a'e968, 0xfb7a'f978},
3182 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c},
3183 {0xcf4e'cd4c, 0xdf5e'dd5c, 0xef6e'ed6c, 0xff7e'fd7c}});
3184 }
3185
TEST_F(Riscv64InterpreterTest,TestVlseg5e32)3186 TEST_F(Riscv64InterpreterTest, TestVlseg5e32) {
3187 TestVlsegXeXX<UInt32, 5, 1>(0x8000e407, // vlseg5e32.v v8, (x1), v0.t
3188 {{0x8302'8100, 0x9716'9514, 0xab2a'a928, 0xbf3e'bd3c},
3189 {0x8706'8504, 0x9b1a'9918, 0xaf2e'ad2c, 0xc342'c140},
3190 {0x8b0a'8908, 0x9f1e'9d1c, 0xb332'b130, 0xc746'c544},
3191 {0x8f0e'8d0c, 0xa322'a120, 0xb736'b534, 0xcb4a'c948},
3192 {0x9312'9110, 0xa726'a524, 0xbb3a'b938, 0xcf4e'cd4c}});
3193 }
3194
TEST_F(Riscv64InterpreterTest,TestVlseg6e32)3195 TEST_F(Riscv64InterpreterTest, TestVlseg6e32) {
3196 TestVlsegXeXX<UInt32, 6, 1>(0xa000e407, // vlseg6e32.v v8, (x1), v0.t
3197 {{0x8302'8100, 0x9b1a'9918, 0xb332'b130, 0xcb4a'c948},
3198 {0x8706'8504, 0x9f1e'9d1c, 0xb736'b534, 0xcf4e'cd4c},
3199 {0x8b0a'8908, 0xa322'a120, 0xbb3a'b938, 0xd352'd150},
3200 {0x8f0e'8d0c, 0xa726'a524, 0xbf3e'bd3c, 0xd756'd554},
3201 {0x9312'9110, 0xab2a'a928, 0xc342'c140, 0xdb5a'd958},
3202 {0x9716'9514, 0xaf2e'ad2c, 0xc746'c544, 0xdf5e'dd5c}});
3203 }
3204
TEST_F(Riscv64InterpreterTest,TestVlseg7e32)3205 TEST_F(Riscv64InterpreterTest, TestVlseg7e32) {
3206 TestVlsegXeXX<UInt32, 7, 1>(0xc000e407, // vlseg7e32.v v8, (x1), v0.t
3207 {{0x8302'8100, 0x9f1e'9d1c, 0xbb3a'b938, 0xd756'd554},
3208 {0x8706'8504, 0xa322'a120, 0xbf3e'bd3c, 0xdb5a'd958},
3209 {0x8b0a'8908, 0xa726'a524, 0xc342'c140, 0xdf5e'dd5c},
3210 {0x8f0e'8d0c, 0xab2a'a928, 0xc746'c544, 0xe362'e160},
3211 {0x9312'9110, 0xaf2e'ad2c, 0xcb4a'c948, 0xe766'e564},
3212 {0x9716'9514, 0xb332'b130, 0xcf4e'cd4c, 0xeb6a'e968},
3213 {0x9b1a'9918, 0xb736'b534, 0xd352'd150, 0xef6e'ed6c}});
3214 }
3215
TEST_F(Riscv64InterpreterTest,TestVlseg8e32)3216 TEST_F(Riscv64InterpreterTest, TestVlseg8e32) {
3217 TestVlsegXeXX<UInt32, 8, 1>(0xe000e407, // vlseg8e32.v v8, (x1), v0.t
3218 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3219 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3220 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3221 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3222 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3223 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574},
3224 {0x9b1a'9918, 0xbb3a'b938, 0xdb5a'd958, 0xfb7a'f978},
3225 {0x9f1e'9d1c, 0xbf3e'bd3c, 0xdf5e'dd5c, 0xff7e'fd7c}});
3226 }
3227
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul1)3228 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul1) {
3229 TestVlsegXeXX<UInt64, 1, 1>(0x000f407, // vle64.v v8, (x1), v0.t
3230 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908}});
3231 }
3232
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul2)3233 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul2) {
3234 TestVlsegXeXX<UInt64, 1, 2>(0x000f407, // vle64.v v8, (x1), v0.t
3235 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
3236 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918}});
3237 }
3238
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul4)3239 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul4) {
3240 TestVlsegXeXX<UInt64, 1, 4>(0x000f407, // vle64.v v8, (x1), v0.t
3241 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
3242 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
3243 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
3244 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938}});
3245 }
3246
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul8)3247 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul8) {
3248 TestVlsegXeXX<UInt64, 1, 8>(0x000f407, // vle64.v v8, (x1), v0.t
3249 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
3250 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
3251 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
3252 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
3253 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
3254 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
3255 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
3256 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}});
3257 }
3258
TEST_F(Riscv64InterpreterTest,TestVlseg2e64_vlmul1)3259 TEST_F(Riscv64InterpreterTest, TestVlseg2e64_vlmul1) {
3260 TestVlsegXeXX<UInt64, 2, 1>(0x2000f407, // vlseg2e64.v v8, (x1), v0.t
3261 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3262 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918}});
3263 }
3264
TEST_F(Riscv64InterpreterTest,TestVlseg2e64_vlmul2)3265 TEST_F(Riscv64InterpreterTest, TestVlseg2e64_vlmul2) {
3266 TestVlsegXeXX<UInt64, 2, 2>(0x2000f407, // vlseg2e64.v v8, (x1), v0.t
3267 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3268 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
3269 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918},
3270 {0xaf2e'ad2c'ab2a'a928, 0xbf3e'bd3c'bb3a'b938}});
3271 }
3272
TEST_F(Riscv64InterpreterTest,TestVlseg2e64_vlmul4)3273 TEST_F(Riscv64InterpreterTest, TestVlseg2e64_vlmul4) {
3274 TestVlsegXeXX<UInt64, 2, 4>(0x2000f407, // vlseg2e64.v v8, (x1), v0.t
3275 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3276 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
3277 {0xc746'c544'c342'c140, 0xd756'd554'd352'd150},
3278 {0xe766'e564'e362'e160, 0xf776'f574'f372'f170},
3279 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918},
3280 {0xaf2e'ad2c'ab2a'a928, 0xbf3e'bd3c'bb3a'b938},
3281 {0xcf4e'cd4c'cb4a'c948, 0xdf5e'dd5c'db5a'd958},
3282 {0xef6e'ed6c'eb6a'e968, 0xff7e'fd7c'fb7a'f978}});
3283 }
3284
TEST_F(Riscv64InterpreterTest,TestVlseg3e64_vlmul1)3285 TEST_F(Riscv64InterpreterTest, TestVlseg3e64_vlmul1) {
3286 TestVlsegXeXX<UInt64, 3, 1>(0x4000f407, // vlseg3e64.v v8, (x1), v0.t
3287 {{0x8706'8504'8302'8100, 0x9f1e'9d1c'9b1a'9918},
3288 {0x8f0e'8d0c'8b0a'8908, 0xa726'a524'a322'a120},
3289 {0x9716'9514'9312'9110, 0xaf2e'ad2c'ab2a'a928}});
3290 }
3291
TEST_F(Riscv64InterpreterTest,TestVlseg3e64_vlmul2)3292 TEST_F(Riscv64InterpreterTest, TestVlseg3e64_vlmul2) {
3293 TestVlsegXeXX<UInt64, 3, 2>(0x4000f407, // vlseg3e64.v v8, (x1), v0.t
3294 {{0x8706'8504'8302'8100, 0x9f1e'9d1c'9b1a'9918},
3295 {0xb736'b534'b332'b130, 0xcf4e'cd4c'cb4a'c948},
3296 {0x8f0e'8d0c'8b0a'8908, 0xa726'a524'a322'a120},
3297 {0xbf3e'bd3c'bb3a'b938, 0xd756'd554'd352'd150},
3298 {0x9716'9514'9312'9110, 0xaf2e'ad2c'ab2a'a928},
3299 {0xc746'c544'c342'c140, 0xdf5e'dd5c'db5a'd958}});
3300 }
3301
TEST_F(Riscv64InterpreterTest,TestVlseg4e64_vlmul1)3302 TEST_F(Riscv64InterpreterTest, TestVlseg4e64_vlmul1) {
3303 TestVlsegXeXX<UInt64, 4, 1>(0x6000f407, // vlseg4e64.v v8, (x1), v0.t
3304 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3305 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3306 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3307 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938}});
3308 }
3309
TEST_F(Riscv64InterpreterTest,TestVlseg4e64_vlmul2)3310 TEST_F(Riscv64InterpreterTest, TestVlseg4e64_vlmul2) {
3311 TestVlsegXeXX<UInt64, 4, 2>(0x6000f407, // vlseg4e64.v v8, (x1), v0.t
3312 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3313 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3314 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3315 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3316 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3317 {0xd756'd554'd352'd150, 0xf776'f574'f372'f170},
3318 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938},
3319 {0xdf5e'dd5c'db5a'd958, 0xff7e'fd7c'fb7a'f978}});
3320 }
3321
TEST_F(Riscv64InterpreterTest,TestVlseg5e64)3322 TEST_F(Riscv64InterpreterTest, TestVlseg5e64) {
3323 TestVlsegXeXX<UInt64, 5, 1>(0x8000f407, // vlseg5e64.v v8, (x1), v0.t
3324 {{0x8706'8504'8302'8100, 0xaf2e'ad2c'ab2a'a928},
3325 {0x8f0e'8d0c'8b0a'8908, 0xb736'b534'b332'b130},
3326 {0x9716'9514'9312'9110, 0xbf3e'bd3c'bb3a'b938},
3327 {0x9f1e'9d1c'9b1a'9918, 0xc746'c544'c342'c140},
3328 {0xa726'a524'a322'a120, 0xcf4e'cd4c'cb4a'c948}});
3329 }
3330
TEST_F(Riscv64InterpreterTest,TestVlseg6e64)3331 TEST_F(Riscv64InterpreterTest, TestVlseg6e64) {
3332 TestVlsegXeXX<UInt64, 6, 1>(0xa000f407, // vlseg6e64.v v8, (x1), v0.t
3333 {{0x8706'8504'8302'8100, 0xb736'b534'b332'b130},
3334 {0x8f0e'8d0c'8b0a'8908, 0xbf3e'bd3c'bb3a'b938},
3335 {0x9716'9514'9312'9110, 0xc746'c544'c342'c140},
3336 {0x9f1e'9d1c'9b1a'9918, 0xcf4e'cd4c'cb4a'c948},
3337 {0xa726'a524'a322'a120, 0xd756'd554'd352'd150},
3338 {0xaf2e'ad2c'ab2a'a928, 0xdf5e'dd5c'db5a'd958}});
3339 }
3340
TEST_F(Riscv64InterpreterTest,TestVlseg7e64)3341 TEST_F(Riscv64InterpreterTest, TestVlseg7e64) {
3342 TestVlsegXeXX<UInt64, 7, 1>(0xc000f407, // vlseg7e64.v v8, (x1), v0.t
3343 {{0x8706'8504'8302'8100, 0xbf3e'bd3c'bb3a'b938},
3344 {0x8f0e'8d0c'8b0a'8908, 0xc746'c544'c342'c140},
3345 {0x9716'9514'9312'9110, 0xcf4e'cd4c'cb4a'c948},
3346 {0x9f1e'9d1c'9b1a'9918, 0xd756'd554'd352'd150},
3347 {0xa726'a524'a322'a120, 0xdf5e'dd5c'db5a'd958},
3348 {0xaf2e'ad2c'ab2a'a928, 0xe766'e564'e362'e160},
3349 {0xb736'b534'b332'b130, 0xef6e'ed6c'eb6a'e968}});
3350 }
3351
TEST_F(Riscv64InterpreterTest,TestVlseg8e64)3352 TEST_F(Riscv64InterpreterTest, TestVlseg8e64) {
3353 TestVlsegXeXX<UInt64, 8, 1>(0xe000f407, // vlseg8e64.v v8, (x1), v0.t
3354 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3355 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3356 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3357 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3358 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3359 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968},
3360 {0xb736'b534'b332'b130, 0xf776'f574'f372'f170},
3361 {0xbf3e'bd3c'bb3a'b938, 0xff7e'fd7c'fb7a'f978}});
3362 }
3363
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul1)3364 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul1) {
3365 TestVlssegXeXX<UInt8, 1, 1>(0x08208407, // vlse8.v v8, (x1), x2, v0.t
3366 4,
3367 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60}});
3368 }
3369
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul2)3370 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul2) {
3371 TestVlssegXeXX<UInt8, 1, 2>(
3372 0x08208407, // vlse8.v v8, (x1), x2, v0.t
3373 4,
3374 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3375 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124}});
3376 }
3377
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul4)3378 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul4) {
3379 TestVlssegXeXX<UInt8, 1, 4>(
3380 0x08208407, // vlse8.v v8, (x1), x2, v0.t
3381 4,
3382 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3383 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3384 {0, 9, 17, 24, 32, 41, 49, 56, 64, 73, 81, 88, 96, 105, 113, 120},
3385 {128, 137, 145, 152, 160, 169, 177, 184, 192, 201, 209, 216, 224, 233, 241, 248}});
3386 }
3387
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul8)3388 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul8) {
3389 TestVlssegXeXX<UInt8, 1, 8>(
3390 0x08208407, // vlse8.v v8, (x1), x2, v0.t
3391 2,
3392 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
3393 {32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62},
3394 {64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94},
3395 {96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126},
3396 {0, 4, 9, 12, 17, 20, 24, 28, 32, 36, 41, 44, 49, 52, 56, 60},
3397 {64, 68, 73, 76, 81, 84, 88, 92, 96, 100, 105, 108, 113, 116, 120, 124},
3398 {128, 132, 137, 140, 145, 148, 152, 156, 160, 164, 169, 172, 177, 180, 184, 188},
3399 {192, 196, 201, 204, 209, 212, 216, 220, 224, 228, 233, 236, 241, 244, 248, 252}});
3400 }
3401
TEST_F(Riscv64InterpreterTest,TestVlsseg2e8_vlmul1)3402 TEST_F(Riscv64InterpreterTest, TestVlsseg2e8_vlmul1) {
3403 TestVlssegXeXX<UInt8, 2, 1>(
3404 0x28208407, // vlsseg2e8.v v8, (x1), x2, v0.t
3405 4,
3406 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3407 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189}});
3408 }
3409
TEST_F(Riscv64InterpreterTest,TestVlsseg2e8_vlmul2)3410 TEST_F(Riscv64InterpreterTest, TestVlsseg2e8_vlmul2) {
3411 TestVlssegXeXX<UInt8, 2, 2>(
3412 0x28208407, // vlsseg2e8.v v8, (x1), x2, v0.t
3413 4,
3414 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3415 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3416 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3417 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253}});
3418 }
3419
TEST_F(Riscv64InterpreterTest,TestVlsseg2e8_vlmul4)3420 TEST_F(Riscv64InterpreterTest, TestVlsseg2e8_vlmul4) {
3421 TestVlssegXeXX<UInt8, 2, 4>(
3422 0x28208407, // vlsseg2e8.v v8, (x1), x2, v0.t
3423 4,
3424 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3425 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3426 {0, 9, 17, 24, 32, 41, 49, 56, 64, 73, 81, 88, 96, 105, 113, 120},
3427 {128, 137, 145, 152, 160, 169, 177, 184, 192, 201, 209, 216, 224, 233, 241, 248},
3428 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3429 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
3430 {146, 154, 130, 138, 178, 186, 162, 170, 210, 218, 194, 202, 242, 250, 226, 234},
3431 {18, 26, 2, 10, 50, 58, 34, 42, 82, 90, 66, 74, 114, 122, 98, 106}});
3432 }
3433
TEST_F(Riscv64InterpreterTest,TestVlsseg3e8_vlmul1)3434 TEST_F(Riscv64InterpreterTest, TestVlsseg3e8_vlmul1) {
3435 TestVlssegXeXX<UInt8, 3, 1>(
3436 0x48208407, // vlsseg3e8.v v8, (x1), x2, v0.t
3437 4,
3438 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3439 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3440 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62}});
3441 }
3442
TEST_F(Riscv64InterpreterTest,TestVlsseg3e8_vlmul2)3443 TEST_F(Riscv64InterpreterTest, TestVlsseg3e8_vlmul2) {
3444 TestVlssegXeXX<UInt8, 3, 2>(
3445 0x48208407, // vlsseg3e8.v v8, (x1), x2, v0.t
3446 4,
3447 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3448 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3449 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3450 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
3451 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
3452 {66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126}});
3453 }
3454
TEST_F(Riscv64InterpreterTest,TestVlsseg4e8_vlmul1)3455 TEST_F(Riscv64InterpreterTest, TestVlsseg4e8_vlmul1) {
3456 TestVlssegXeXX<UInt8, 4, 1>(
3457 0x68208407, // vlsseg4e8.v v8, (x1), x2, v0.t
3458 4,
3459 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3460 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3461 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
3462 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191}});
3463 }
3464
TEST_F(Riscv64InterpreterTest,TestVlsseg4e8_vlmul2)3465 TEST_F(Riscv64InterpreterTest, TestVlsseg4e8_vlmul2) {
3466 TestVlssegXeXX<UInt8, 4, 2>(
3467 0x68208407, // vlsseg4e8.v v8, (x1), x2, v0.t
3468 4,
3469 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3470 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3471 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3472 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
3473 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
3474 {66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126},
3475 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191},
3476 {195, 199, 203, 207, 211, 215, 219, 223, 227, 231, 235, 239, 243, 247, 251, 255}});
3477 }
3478
TEST_F(Riscv64InterpreterTest,TestVlsseg5e8)3479 TEST_F(Riscv64InterpreterTest, TestVlsseg5e8) {
3480 TestVlssegXeXX<UInt8, 5, 1>(
3481 0x88208407, // vlsseg5e8.v v8, (x1), x2, v0.t
3482 8,
3483 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3484 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3485 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3486 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3487 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124}});
3488 }
3489
TEST_F(Riscv64InterpreterTest,TestVlsseg6e8)3490 TEST_F(Riscv64InterpreterTest, TestVlsseg6e8) {
3491 TestVlssegXeXX<UInt8, 6, 1>(
3492 0xa8208407, // vlsseg6e8.v v8, (x1), x2, v0.t
3493 8,
3494 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3495 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3496 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3497 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3498 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
3499 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253}});
3500 }
3501
TEST_F(Riscv64InterpreterTest,TestVlsseg7e8)3502 TEST_F(Riscv64InterpreterTest, TestVlsseg7e8) {
3503 TestVlssegXeXX<UInt8, 7, 1>(
3504 0xc8208407, // vlsseg7e8.v v8, (x1), x2, v0.t
3505 8,
3506 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3507 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3508 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3509 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3510 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
3511 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253},
3512 {6, 14, 22, 30, 38, 46, 54, 62, 70, 78, 86, 94, 102, 110, 118, 126}});
3513 }
3514
TEST_F(Riscv64InterpreterTest,TestVlsseg8e8)3515 TEST_F(Riscv64InterpreterTest, TestVlsseg8e8) {
3516 TestVlssegXeXX<UInt8, 8, 1>(
3517 0xe8208407, // vlsseg8e8.v v8, (x1), x2, v0.t
3518 8,
3519 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3520 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3521 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3522 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3523 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
3524 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253},
3525 {6, 14, 22, 30, 38, 46, 54, 62, 70, 78, 86, 94, 102, 110, 118, 126},
3526 {135, 143, 151, 159, 167, 175, 183, 191, 199, 207, 215, 223, 231, 239, 247, 255}});
3527 }
3528
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul1)3529 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul1) {
3530 TestVlssegXeXX<UInt16, 1, 1>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3531 8,
3532 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938}});
3533 }
3534
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul2)3535 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul2) {
3536 TestVlssegXeXX<UInt16, 1, 2>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3537 8,
3538 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3539 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978}});
3540 }
3541
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul4)3542 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul4) {
3543 TestVlssegXeXX<UInt16, 1, 4>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3544 8,
3545 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3546 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3547 {0x9200, 0x8211, 0xb220, 0xa231, 0xd240, 0xc251, 0xf260, 0xe271},
3548 {0x1280, 0x0291, 0x32a0, 0x22b1, 0x52c0, 0x42d1, 0x72e0, 0x62f1}});
3549 }
3550
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul8)3551 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul8) {
3552 TestVlssegXeXX<UInt16, 1, 8>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3553 4,
3554 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
3555 {0xa120, 0xa524, 0xa928, 0xad2c, 0xb130, 0xb534, 0xb938, 0xbd3c},
3556 {0xc140, 0xc544, 0xc948, 0xcd4c, 0xd150, 0xd554, 0xd958, 0xdd5c},
3557 {0xe160, 0xe564, 0xe968, 0xed6c, 0xf170, 0xf574, 0xf978, 0xfd7c},
3558 {0x9200, 0x9a09, 0x8211, 0x8a18, 0xb220, 0xba29, 0xa231, 0xaa38},
3559 {0xd240, 0xda49, 0xc251, 0xca58, 0xf260, 0xfa69, 0xe271, 0xea78},
3560 {0x1280, 0x1a89, 0x0291, 0x0a98, 0x32a0, 0x3aa9, 0x22b1, 0x2ab8},
3561 {0x52c0, 0x5ac9, 0x42d1, 0x4ad8, 0x72e0, 0x7ae9, 0x62f1, 0x6af8}});
3562 }
3563
TEST_F(Riscv64InterpreterTest,TestVlsseg2e16_vlmul1)3564 TEST_F(Riscv64InterpreterTest, TestVlsseg2e16_vlmul1) {
3565 TestVlssegXeXX<UInt16, 2, 1>(0x2820d407, // vlsseg2e16.v v8, (x1), x2, v0.t
3566 8,
3567 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3568 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a}});
3569 }
3570
TEST_F(Riscv64InterpreterTest,TestVlsseg2e16_vlmul2)3571 TEST_F(Riscv64InterpreterTest, TestVlsseg2e16_vlmul2) {
3572 TestVlssegXeXX<UInt16, 2, 2>(0x2820d407, // vlsseg2e16.v v8, (x1), x2, v0.t
3573 8,
3574 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3575 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3576 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3577 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a}});
3578 }
3579
TEST_F(Riscv64InterpreterTest,TestVlsseg2e16_vlmul4)3580 TEST_F(Riscv64InterpreterTest, TestVlsseg2e16_vlmul4) {
3581 TestVlssegXeXX<UInt16, 2, 4>(0x2820d407, // vlsseg2e16.v v8, (x1), x2, v0.t
3582 8,
3583 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3584 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3585 {0x9200, 0x8211, 0xb220, 0xa231, 0xd240, 0xc251, 0xf260, 0xe271},
3586 {0x1280, 0x0291, 0x32a0, 0x22b1, 0x52c0, 0x42d1, 0x72e0, 0x62f1},
3587 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3588 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3589 {0x9604, 0x8614, 0xb624, 0xa634, 0xd644, 0xc654, 0xf664, 0xe674},
3590 {0x1684, 0x0694, 0x36a4, 0x26b4, 0x56c4, 0x46d4, 0x76e4, 0x66f4}});
3591 }
3592
TEST_F(Riscv64InterpreterTest,TestVlsseg3e16_vlmul1)3593 TEST_F(Riscv64InterpreterTest, TestVlsseg3e16_vlmul1) {
3594 TestVlssegXeXX<UInt16, 3, 1>(0x4820d407, // vlsseg3e16.v v8, (x1), x2, v0.t
3595 8,
3596 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3597 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3598 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c}});
3599 }
3600
TEST_F(Riscv64InterpreterTest,TestVlsseg3e16_vlmul2)3601 TEST_F(Riscv64InterpreterTest, TestVlsseg3e16_vlmul2) {
3602 TestVlssegXeXX<UInt16, 3, 2>(0x4820d407, // vlsseg3e16.v v8, (x1), x2, v0.t
3603 8,
3604 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3605 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3606 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3607 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3608 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3609 {0xc544, 0xcd4c, 0xd554, 0xdd5c, 0xe564, 0xed6c, 0xf574, 0xfd7c}});
3610 }
3611
TEST_F(Riscv64InterpreterTest,TestVlsseg4e16_vlmul1)3612 TEST_F(Riscv64InterpreterTest, TestVlsseg4e16_vlmul1) {
3613 TestVlssegXeXX<UInt16, 4, 1>(0x6820d407, // vlsseg4e16.v v8, (x1), x2, v0.t
3614 8,
3615 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3616 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3617 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3618 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e}});
3619 }
3620
TEST_F(Riscv64InterpreterTest,TestVlsseg4e16_vlmul2)3621 TEST_F(Riscv64InterpreterTest, TestVlsseg4e16_vlmul2) {
3622 TestVlssegXeXX<UInt16, 4, 2>(0x6820d407, // vlsseg4e16.v v8, (x1), x2, v0.t
3623 8,
3624 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3625 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3626 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3627 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3628 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3629 {0xc544, 0xcd4c, 0xd554, 0xdd5c, 0xe564, 0xed6c, 0xf574, 0xfd7c},
3630 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e},
3631 {0xc746, 0xcf4e, 0xd756, 0xdf5e, 0xe766, 0xef6e, 0xf776, 0xff7e}});
3632 }
3633
TEST_F(Riscv64InterpreterTest,TestVlsseg5e16)3634 TEST_F(Riscv64InterpreterTest, TestVlsseg5e16) {
3635 TestVlssegXeXX<UInt16, 5, 1>(0x8820d407, // vlsseg5e16.v v8, (x1), x2, v0.t
3636 16,
3637 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3638 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3639 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3640 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3641 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978}});
3642 }
3643
TEST_F(Riscv64InterpreterTest,TestVlsseg6e16)3644 TEST_F(Riscv64InterpreterTest, TestVlsseg6e16) {
3645 TestVlssegXeXX<UInt16, 6, 1>(0xa820d407, // vlsseg6e16.v v8, (x1), x2, v0.t
3646 16,
3647 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3648 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3649 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3650 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3651 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3652 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a}});
3653 }
3654
TEST_F(Riscv64InterpreterTest,TestVlsseg7e16)3655 TEST_F(Riscv64InterpreterTest, TestVlsseg7e16) {
3656 TestVlssegXeXX<UInt16, 7, 1>(0xc820d407, // vlsseg7e16.v v8, (x1), x2, v0.t
3657 16,
3658 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3659 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3660 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3661 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3662 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3663 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a},
3664 {0x8d0c, 0x9d1c, 0xad2c, 0xbd3c, 0xcd4c, 0xdd5c, 0xed6c, 0xfd7c}});
3665 }
3666
TEST_F(Riscv64InterpreterTest,TestVlsseg8e16)3667 TEST_F(Riscv64InterpreterTest, TestVlsseg8e16) {
3668 TestVlssegXeXX<UInt16, 8, 1>(0xe820d407, // vlsseg8e16.v v8, (x1), x2, v0.t
3669 16,
3670 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3671 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3672 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3673 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3674 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3675 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a},
3676 {0x8d0c, 0x9d1c, 0xad2c, 0xbd3c, 0xcd4c, 0xdd5c, 0xed6c, 0xfd7c},
3677 {0x8f0e, 0x9f1e, 0xaf2e, 0xbf3e, 0xcf4e, 0xdf5e, 0xef6e, 0xff7e}});
3678 }
3679
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul1)3680 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul1) {
3681 TestVlssegXeXX<UInt32, 1, 1>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3682 16,
3683 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130}});
3684 }
3685
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul2)3686 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul2) {
3687 TestVlssegXeXX<UInt32, 1, 2>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3688 16,
3689 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3690 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170}});
3691 }
3692
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul4)3693 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul4) {
3694 TestVlssegXeXX<UInt32, 1, 4>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3695 16,
3696 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3697 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3698 {0x9604'9200, 0xb624'b220, 0xd644'd240, 0xf664'f260},
3699 {0x1684'1280, 0x36a4'32a0, 0x56c4'52c0, 0x76e4'72e0}});
3700 }
3701
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul8)3702 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul8) {
3703 TestVlssegXeXX<UInt32, 1, 8>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3704 8,
3705 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3706 {0xa322'a120, 0xab2a'a928, 0xb332'b130, 0xbb3a'b938},
3707 {0xc342'c140, 0xcb4a'c948, 0xd352'd150, 0xdb5a'd958},
3708 {0xe362'e160, 0xeb6a'e968, 0xf372'f170, 0xfb7a'f978},
3709 {0x9604'9200, 0x8614'8211, 0xb624'b220, 0xa634'a231},
3710 {0xd644'd240, 0xc654'c251, 0xf664'f260, 0xe674'e271},
3711 {0x1684'1280, 0x0694'0291, 0x36a4'32a0, 0x26b4'22b1},
3712 {0x56c4'52c0, 0x46d4'42d1, 0x76e4'72e0, 0x66f4'62f1}});
3713 }
3714
TEST_F(Riscv64InterpreterTest,TestVlsseg2e32_vlmul1)3715 TEST_F(Riscv64InterpreterTest, TestVlsseg2e32_vlmul1) {
3716 TestVlssegXeXX<UInt32, 2, 1>(0x2820e407, // vlsseg2e32.v v8, (x1), x2, v0.t
3717 16,
3718 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3719 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534}});
3720 }
3721
TEST_F(Riscv64InterpreterTest,TestVlsseg2e32_vlmul2)3722 TEST_F(Riscv64InterpreterTest, TestVlsseg2e32_vlmul2) {
3723 TestVlssegXeXX<UInt32, 2, 2>(0x2820e407, // vlsseg2e32.v v8, (x1), x2, v0.t
3724 16,
3725 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3726 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3727 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3728 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574}});
3729 }
3730
TEST_F(Riscv64InterpreterTest,TestVlsseg2e32_vlmul4)3731 TEST_F(Riscv64InterpreterTest, TestVlsseg2e32_vlmul4) {
3732 TestVlssegXeXX<UInt32, 2, 4>(0x2820e407, // vlsseg2e32.v v8, (x1), x2, v0.t
3733 16,
3734 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3735 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3736 {0x9604'9200, 0xb624'b220, 0xd644'd240, 0xf664'f260},
3737 {0x1684'1280, 0x36a4'32a0, 0x56c4'52c0, 0x76e4'72e0},
3738 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3739 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3740 {0x9e0c'9a09, 0xbe2c'ba29, 0xde4c'da49, 0xfe6c'fa69},
3741 {0x1e8c'1a89, 0x3eac'3aa9, 0x5ecc'5ac9, 0x7eec'7ae9}});
3742 }
3743
TEST_F(Riscv64InterpreterTest,TestVlsseg3e32_vlmul1)3744 TEST_F(Riscv64InterpreterTest, TestVlsseg3e32_vlmul1) {
3745 TestVlssegXeXX<UInt32, 3, 1>(0x4820e407, // vlsseg3e32.v v8, (x1), x2, v0.t
3746 16,
3747 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3748 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3749 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938}});
3750 }
3751
TEST_F(Riscv64InterpreterTest,TestVlsseg3e32_vlmul2)3752 TEST_F(Riscv64InterpreterTest, TestVlsseg3e32_vlmul2) {
3753 TestVlssegXeXX<UInt32, 3, 2>(0x4820e407, // vlsseg3e32.v v8, (x1), x2, v0.t
3754 16,
3755 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3756 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3757 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3758 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3759 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3760 {0xcb4a'c948, 0xdb5a'd958, 0xeb6a'e968, 0xfb7a'f978}});
3761 }
3762
TEST_F(Riscv64InterpreterTest,TestVlsseg4e32_vlmul1)3763 TEST_F(Riscv64InterpreterTest, TestVlsseg4e32_vlmul1) {
3764 TestVlssegXeXX<UInt32, 4, 1>(0x6820e407, // vlsseg4e32.v v8, (x1), x2, v0.t
3765 16,
3766 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3767 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3768 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3769 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c}});
3770 }
3771
TEST_F(Riscv64InterpreterTest,TestVlsseg4e32_vlmul2)3772 TEST_F(Riscv64InterpreterTest, TestVlsseg4e32_vlmul2) {
3773 TestVlssegXeXX<UInt32, 4, 2>(0x6820e407, // vlsseg4e32.v v8, (x1), x2, v0.t
3774 16,
3775 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3776 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3777 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3778 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3779 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3780 {0xcb4a'c948, 0xdb5a'd958, 0xeb6a'e968, 0xfb7a'f978},
3781 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c},
3782 {0xcf4e'cd4c, 0xdf5e'dd5c, 0xef6e'ed6c, 0xff7e'fd7c}});
3783 }
3784
TEST_F(Riscv64InterpreterTest,TestVlsseg5e32)3785 TEST_F(Riscv64InterpreterTest, TestVlsseg5e32) {
3786 TestVlssegXeXX<UInt32, 5, 1>(0x8820e407, // vlsseg5e32.v v8, (x1), x2, v0.t
3787 32,
3788 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3789 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3790 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3791 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3792 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170}});
3793 }
3794
TEST_F(Riscv64InterpreterTest,TestVlsseg6e32)3795 TEST_F(Riscv64InterpreterTest, TestVlsseg6e32) {
3796 TestVlssegXeXX<UInt32, 6, 1>(0xa820e407, // vlsseg6e32.v v8, (x1), x2, v0.t
3797 32,
3798 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3799 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3800 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3801 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3802 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3803 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574}});
3804 }
3805
TEST_F(Riscv64InterpreterTest,TestVlsseg7e32)3806 TEST_F(Riscv64InterpreterTest, TestVlsseg7e32) {
3807 TestVlssegXeXX<UInt32, 7, 1>(0xc820e407, // vlsseg7e32.v v8, (x1), x2, v0.t
3808 32,
3809 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3810 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3811 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3812 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3813 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3814 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574},
3815 {0x9b1a'9918, 0xbb3a'b938, 0xdb5a'd958, 0xfb7a'f978}});
3816 }
3817
TEST_F(Riscv64InterpreterTest,TestVlsseg8e32)3818 TEST_F(Riscv64InterpreterTest, TestVlsseg8e32) {
3819 TestVlssegXeXX<UInt32, 8, 1>(0xe820e407, // vlsseg8e32.v v8, (x1), x2, v0.t
3820 32,
3821 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3822 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3823 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3824 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3825 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3826 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574},
3827 {0x9b1a'9918, 0xbb3a'b938, 0xdb5a'd958, 0xfb7a'f978},
3828 {0x9f1e'9d1c, 0xbf3e'bd3c, 0xdf5e'dd5c, 0xff7e'fd7c}});
3829 }
3830
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul1)3831 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul1) {
3832 TestVlssegXeXX<UInt64, 1, 1>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3833 32,
3834 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120}});
3835 }
3836
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul2)3837 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul2) {
3838 TestVlssegXeXX<UInt64, 1, 2>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3839 32,
3840 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3841 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160}});
3842 }
3843
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul4)3844 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul4) {
3845 TestVlssegXeXX<UInt64, 1, 4>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3846 32,
3847 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3848 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3849 {0x9e0c'9a09'9604'9200, 0xde4c'da49'd644'd240},
3850 {0x1e8c'1a89'1684'1280, 0x5ecc'5ac9'56c4'52c0}});
3851 }
3852
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul8)3853 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul8) {
3854 TestVlssegXeXX<UInt64, 1, 8>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3855 16,
3856 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3857 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
3858 {0xc746'c544'c342'c140, 0xd756'd554'd352'd150},
3859 {0xe766'e564'e362'e160, 0xf776'f574'f372'f170},
3860 {0x9e0c'9a09'9604'9200, 0xbe2c'ba29'b624'b220},
3861 {0xde4c'da49'd644'd240, 0xfe6c'fa69'f664'f260},
3862 {0x1e8c'1a89'1684'1280, 0x3eac'3aa9'36a4'32a0},
3863 {0x5ecc'5ac9'56c4'52c0, 0x7eec'7ae9'76e4'72e0}});
3864 }
3865
TEST_F(Riscv64InterpreterTest,TestVlsseg2e64_vlmul1)3866 TEST_F(Riscv64InterpreterTest, TestVlsseg2e64_vlmul1) {
3867 TestVlssegXeXX<UInt64, 2, 1>(0x2820f407, // vlsseg2e64.v v8, (x1), x2, v0.t
3868 32,
3869 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3870 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928}});
3871 }
3872
TEST_F(Riscv64InterpreterTest,TestVlsseg2e64_vlmul2)3873 TEST_F(Riscv64InterpreterTest, TestVlsseg2e64_vlmul2) {
3874 TestVlssegXeXX<UInt64, 2, 2>(0x2820f407, // vlsseg2e64.v v8, (x1), x2, v0.t
3875 32,
3876 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3877 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3878 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3879 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968}});
3880 }
3881
TEST_F(Riscv64InterpreterTest,TestVlsseg2e64_vlmul4)3882 TEST_F(Riscv64InterpreterTest, TestVlsseg2e64_vlmul4) {
3883 TestVlssegXeXX<UInt64, 2, 4>(0x2820f407, // vlsseg2e64.v v8, (x1), x2, v0.t
3884 32,
3885 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3886 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3887 {0x9e0c'9a09'9604'9200, 0xde4c'da49'd644'd240},
3888 {0x1e8c'1a89'1684'1280, 0x5ecc'5ac9'56c4'52c0},
3889 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3890 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3891 {0x8e1c'8a18'8614'8211, 0xce5c'ca58'c654'c251},
3892 {0x0e9c'0a98'0694'0291, 0x4edc'4ad8'46d4'42d1}});
3893 }
3894
TEST_F(Riscv64InterpreterTest,TestVlsseg3e64_vlmul1)3895 TEST_F(Riscv64InterpreterTest, TestVlsseg3e64_vlmul1) {
3896 TestVlssegXeXX<UInt64, 3, 1>(0x4820f407, // vlsseg3e64.v v8, (x1), x2, v0.t
3897 32,
3898 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3899 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3900 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130}});
3901 }
3902
TEST_F(Riscv64InterpreterTest,TestVlsseg3e64_vlmul2)3903 TEST_F(Riscv64InterpreterTest, TestVlsseg3e64_vlmul2) {
3904 TestVlssegXeXX<UInt64, 3, 2>(0x4820f407, // vlsseg3e64.v v8, (x1), x2, v0.t
3905 32,
3906 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3907 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3908 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3909 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3910 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3911 {0xd756'd554'd352'd150, 0xf776'f574'f372'f170}});
3912 }
3913
TEST_F(Riscv64InterpreterTest,TestVlsseg4e64_vlmul1)3914 TEST_F(Riscv64InterpreterTest, TestVlsseg4e64_vlmul1) {
3915 TestVlssegXeXX<UInt64, 4, 1>(0x6820f407, // vlsseg4e64.v v8, (x1), x2, v0.t
3916 32,
3917 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3918 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3919 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3920 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938}});
3921 }
3922
TEST_F(Riscv64InterpreterTest,TestVlsseg4e64_vlmul2)3923 TEST_F(Riscv64InterpreterTest, TestVlsseg4e64_vlmul2) {
3924 TestVlssegXeXX<UInt64, 4, 2>(0x6820f407, // vlsseg4e64.v v8, (x1), x2, v0.t
3925 32,
3926 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3927 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3928 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3929 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3930 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3931 {0xd756'd554'd352'd150, 0xf776'f574'f372'f170},
3932 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938},
3933 {0xdf5e'dd5c'db5a'd958, 0xff7e'fd7c'fb7a'f978}});
3934 }
3935
TEST_F(Riscv64InterpreterTest,TestVlsseg5e64)3936 TEST_F(Riscv64InterpreterTest, TestVlsseg5e64) {
3937 TestVlssegXeXX<UInt64, 5, 1>(0x8820f407, // vlsseg5e64.v v8, (x1), x2, v0.t
3938 64,
3939 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3940 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3941 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3942 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3943 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160}});
3944 }
3945
TEST_F(Riscv64InterpreterTest,TestVlsseg6e64)3946 TEST_F(Riscv64InterpreterTest, TestVlsseg6e64) {
3947 TestVlssegXeXX<UInt64, 6, 1>(0xa820f407, // vlsseg6e64.v v8, (x1), x2, v0.t
3948 64,
3949 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3950 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3951 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3952 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3953 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3954 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968}});
3955 }
3956
TEST_F(Riscv64InterpreterTest,TestVlsseg7e64)3957 TEST_F(Riscv64InterpreterTest, TestVlsseg7e64) {
3958 TestVlssegXeXX<UInt64, 7, 1>(0xc820f407, // vlsseg7e64.v v8, (x1), x2, v0.t
3959 64,
3960 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3961 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3962 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3963 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3964 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3965 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968},
3966 {0xb736'b534'b332'b130, 0xf776'f574'f372'f170}});
3967 }
3968
TEST_F(Riscv64InterpreterTest,TestVlsseg8e64)3969 TEST_F(Riscv64InterpreterTest, TestVlsseg8e64) {
3970 TestVlssegXeXX<UInt64, 8, 1>(0xe820f407, // vlsseg8e64.v v8, (x1), x2, v0.t
3971 64,
3972 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3973 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3974 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3975 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3976 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3977 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968},
3978 {0xb736'b534'b332'b130, 0xf776'f574'f372'f170},
3979 {0xbf3e'bd3c'bb3a'b938, 0xff7e'fd7c'fb7a'f978}});
3980 }
3981
TEST_F(Riscv64InterpreterTest,TestVlm)3982 TEST_F(Riscv64InterpreterTest, TestVlm) {
3983 TestVlm(0x2b08407, // vlm.v v8, (x1)
3984 {0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143});
3985 }
3986
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul1)3987 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul1) {
3988 VsxsegXeiXX<UInt8, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
3989 {0x0487'8506'0283'0081, 0x0a89'0c8d'8b8f'080e});
3990 }
3991
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul2)3992 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul2) {
3993 VsxsegXeiXX<UInt8, 1, 2>(
3994 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
3995 {0x0487'8506'0283'0081, 0x0a89'0c8d'8b8f'080e, 0x9f93'9b1e'9714'121a, 0x9110'1899'1c95'169d});
3996 }
3997
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul4)3998 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul4) {
3999 VsxsegXeiXX<UInt8, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4000 {0x0487'8506'0283'0081,
4001 0x0a89'0c8d'8b8f'080e,
4002 0x9f93'9b1e'9714'121a,
4003 0x9110'1899'1c95'169d,
4004 0x2ea5'bd2c'30a3'38b9,
4005 0xafad'3e20'a728'b1ab,
4006 0x3626'b722'b5a1'bbbf,
4007 0xa932'2434'b33a'2a3c});
4008 }
4009
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul8)4010 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul8) {
4011 VsxsegXeiXX<UInt8, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4012 {0x0487'8506'0283'0081,
4013 0x0a89'0c8d'8b8f'080e,
4014 0x9f93'9b1e'9714'121a,
4015 0x9110'1899'1c95'169d,
4016 0x2ea5'bd2c'30a3'38b9,
4017 0xafad'3e20'a728'b1ab,
4018 0x3626'b722'b5a1'bbbf,
4019 0xa932'2434'b33a'2a3c,
4020 0x6aed'ddd1'e35c'66c7,
4021 0xd542'72e1'4674'4ed3,
4022 0x78ef'd9e7'7a7e'eb76,
4023 0xfbf9'f5c1'6e5a'c5ff,
4024 0x52cd'c362'6c48'dfd7,
4025 0x4a54'50fd'f3f7'cf68,
4026 0x56cb'e57c'7044'60c9,
4027 0xf1db'6440'58e9'4c5e});
4028 }
4029
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew8_vlmul1)4030 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew8_vlmul1) {
4031 VsxsegXeiXX<UInt8, 2, 1>(
4032 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4033 {0x1202'9383'1000'9181, 0x1404'9787'9585'1606, 0x9b8b'9f8f'1808'1e0e, 0x1a0a'9989'1c0c'9d8d});
4034 }
4035
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew8_vlmul2)4036 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew8_vlmul2) {
4037 VsxsegXeiXX<UInt8, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4038 {0x2202'a383'2000'a181,
4039 0x2404'a787'a585'2606,
4040 0xab8b'af8f'2808'2e0e,
4041 0x2a0a'a989'2c0c'ad8d,
4042 0xb797'3414'3212'3a1a,
4043 0xbf9f'b393'bb9b'3e1e,
4044 0x3c1c'b595'3616'bd9d,
4045 0xb191'3010'3818'b999});
4046 }
4047
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew8_vlmul4)4048 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew8_vlmul4) {
4049 VsxsegXeiXX<UInt8, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4050 {0x4202'c383'4000'c181,
4051 0x4404'c787'c585'4606,
4052 0xcb8b'cf8f'4808'4e0e,
4053 0x4a0a'c989'4c0c'cd8d,
4054 0xd797'5414'5212'5a1a,
4055 0xdf9f'd393'db9b'5e1e,
4056 0x5c1c'd595'5616'dd9d,
4057 0xd191'5010'5818'd999,
4058 0x7030'e3a3'7838'f9b9,
4059 0x6e2e'e5a5'fdbd'6c2c,
4060 0xe7a7'6828'f1b1'ebab,
4061 0xefaf'edad'7e3e'6020,
4062 0xf5b5'e1a1'fbbb'ffbf,
4063 0x7636'6626'f7b7'6222,
4064 0xf3b3'7a3a'6a2a'7c3c,
4065 0xe9a9'7232'6424'7434});
4066 }
4067
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew8_vlmul1)4068 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew8_vlmul1) {
4069 VsxsegXeiXX<UInt8, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4070 {0x9383'2010'00a1'9181,
4071 0x8526'1606'2212'02a3,
4072 0x2414'04a7'9787'a595,
4073 0x9f8f'2818'082e'1e0e,
4074 0x0cad'9d8d'ab9b'8baf,
4075 0x2a1a'0aa9'9989'2c1c});
4076 }
4077
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew8_vlmul2)4078 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew8_vlmul2) {
4079 VsxsegXeiXX<UInt8, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4080 {0xa383'4020'00c1'a181,
4081 0x8546'2606'4222'02c3,
4082 0x4424'04c7'a787'c5a5,
4083 0xaf8f'4828'084e'2e0e,
4084 0x0ccd'ad8d'cbab'8bcf,
4085 0x4a2a'0ac9'a989'4c2c,
4086 0x3414'5232'125a'3a1a,
4087 0x9b5e'3e1e'd7b7'9754,
4088 0xdfbf'9fd3'b393'dbbb,
4089 0xb595'5636'16dd'bd9d,
4090 0x18d9'b999'5c3c'1cd5,
4091 0xd1b1'9150'3010'5838});
4092 }
4093
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew8_vlmul1)4094 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew8_vlmul1) {
4095 VsxsegXeiXX<UInt8, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4096 {0x3020'1000'b1a1'9181,
4097 0x3222'1202'b3a3'9383,
4098 0xb5a5'9585'3626'1606,
4099 0x3424'1404'b7a7'9787,
4100 0x3828'1808'3e2e'1e0e,
4101 0xbbab'9b8b'bfaf'9f8f,
4102 0x3c2c'1c0c'bdad'9d8d,
4103 0x3a2a'1a0a'b9a9'9989});
4104 }
4105
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew8_vlmul2)4106 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew8_vlmul2) {
4107 VsxsegXeiXX<UInt8, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4108 {0x6040'2000'e1c1'a181,
4109 0x6242'2202'e3c3'a383,
4110 0xe5c5'a585'6646'2606,
4111 0x6444'2404'e7c7'a787,
4112 0x6848'2808'6e4e'2e0e,
4113 0xebcb'ab8b'efcf'af8f,
4114 0x6c4c'2c0c'edcd'ad8d,
4115 0x6a4a'2a0a'e9c9'a989,
4116 0x7252'3212'7a5a'3a1a,
4117 0xf7d7'b797'7454'3414,
4118 0xfbdb'bb9b'7e5e'3e1e,
4119 0xffdf'bf9f'f3d3'b393,
4120 0x7656'3616'fddd'bd9d,
4121 0x7c5c'3c1c'f5d5'b595,
4122 0x7858'3818'f9d9'b999,
4123 0xf1d1'b191'7050'3010});
4124 }
4125
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew8)4126 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew8) {
4127 VsxsegXeiXX<UInt8, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4128 {0x2010'00c1'b1a1'9181,
4129 0x02c3'b3a3'9383'4030,
4130 0x3626'1606'4232'2212,
4131 0x9787'c5b5'a595'8546,
4132 0x4434'2414'04c7'b7a7,
4133 0x2818'084e'3e2e'1e0e,
4134 0x8bcf'bfaf'9f8f'4838,
4135 0xbdad'9d8d'cbbb'ab9b,
4136 0x9989'4c3c'2c1c'0ccd,
4137 0x4a3a'2a1a'0ac9'b9a9});
4138 }
4139
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew8)4140 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew8) {
4141 VsxsegXeiXX<UInt8, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4142 {0x1000'd1c1'b1a1'9181,
4143 0xb3a3'9383'5040'3020,
4144 0x5242'3222'1202'd3c3,
4145 0x9585'5646'3626'1606,
4146 0xb7a7'9787'd5c5'b5a5,
4147 0x5444'3424'1404'd7c7,
4148 0x1808'5e4e'3e2e'1e0e,
4149 0xbfaf'9f8f'5848'3828,
4150 0xdbcb'bbab'9b8b'dfcf,
4151 0x1c0c'ddcd'bdad'9d8d,
4152 0xb9a9'9989'5c4c'3c2c,
4153 0x5a4a'3a2a'1a0a'd9c9});
4154 }
4155
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew8)4156 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew8) {
4157 VsxsegXeiXX<UInt8, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4158 {0x00e1'd1c1'b1a1'9181,
4159 0x9383'6050'4030'2010,
4160 0x2212'02e3'd3c3'b3a3,
4161 0x3626'1606'6252'4232,
4162 0xc5b5'a595'8566'5646,
4163 0xd7c7'b7a7'9787'e5d5,
4164 0x6454'4434'2414'04e7,
4165 0x086e'5e4e'3e2e'1e0e,
4166 0x9f8f'6858'4838'2818,
4167 0xab9b'8bef'dfcf'bfaf,
4168 0xbdad'9d8d'ebdb'cbbb,
4169 0x4c3c'2c1c'0ced'ddcd,
4170 0xd9c9'b9a9'9989'6c5c,
4171 0x6a5a'4a3a'2a1a'0ae9});
4172 }
4173
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew8)4174 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew8) {
4175 VsxsegXeiXX<UInt8, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4176 {0xf1e1'd1c1'b1a1'9181,
4177 0x7060'5040'3020'1000,
4178 0xf3e3'd3c3'b3a3'9383,
4179 0x7262'5242'3222'1202,
4180 0x7666'5646'3626'1606,
4181 0xf5e5'd5c5'b5a5'9585,
4182 0xf7e7'd7c7'b7a7'9787,
4183 0x7464'5444'3424'1404,
4184 0x7e6e'5e4e'3e2e'1e0e,
4185 0x7868'5848'3828'1808,
4186 0xffef'dfcf'bfaf'9f8f,
4187 0xfbeb'dbcb'bbab'9b8b,
4188 0xfded'ddcd'bdad'9d8d,
4189 0x7c6c'5c4c'3c2c'1c0c,
4190 0xf9e9'd9c9'b9a9'9989,
4191 0x7a6a'5a4a'3a2a'1a0a});
4192 }
4193
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul1)4194 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul1) {
4195 VsxsegXeiXX<UInt16, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4196 {0x8504'8706'8100'8302, 0x8908'8f0e'8b0a'8d0c});
4197 }
4198
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul2)4199 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul2) {
4200 VsxsegXeiXX<UInt16, 1, 2>(
4201 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4202 {0x8504'8706'8100'8302, 0x8908'8f0e'8b0a'8d0c, 0x9716'9f1e'9110'9d1c, 0x9514'9312'9918'9b1a});
4203 }
4204
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul4)4205 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul4) {
4206 VsxsegXeiXX<UInt16, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4207 {0x8504'8706'8100'8302,
4208 0x8908'8f0e'8b0a'8d0c,
4209 0x9716'9f1e'9110'9d1c,
4210 0x9514'9312'9918'9b1a,
4211 0xaf2e'a928'a524'b534,
4212 0xbf3e'a726'b736'bd3c,
4213 0xb938'ab2a'ad2c'bb3a,
4214 0xa322'a120'b130'b332});
4215 }
4216
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul8)4217 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul8) {
4218 VsxsegXeiXX<UInt16, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4219 {0x8504'8706'8100'8302,
4220 0x8908'8f0e'8b0a'8d0c,
4221 0x9716'9f1e'9110'9d1c,
4222 0x9514'9312'9918'9b1a,
4223 0xaf2e'a928'a524'b534,
4224 0xbf3e'a726'b736'bd3c,
4225 0xb938'ab2a'ad2c'bb3a,
4226 0xa322'a120'b130'b332,
4227 0xe160'c746'f170'f372,
4228 0xdd5c'cb4a'fb7a'd958,
4229 0xcf4e'd150'e362'd756,
4230 0xdf5e'db5a'fd7c'c140,
4231 0xeb6a'c342'f776'ff7e,
4232 0xed6c'cd4c'ef6e'c544,
4233 0xe766'f574'd554'f978,
4234 0xd352'e564'c948'e968});
4235 }
4236
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew16_vlmul1)4237 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew16_vlmul1) {
4238 VsxsegXeiXX<UInt16, 2, 1>(
4239 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4240 {0x9110'8100'9312'8302, 0x9514'8504'9716'8706, 0x9b1a'8b0a'9d1c'8d0c, 0x9918'8908'9f1e'8f0e});
4241 }
4242
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew16_vlmul2)4243 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew16_vlmul2) {
4244 VsxsegXeiXX<UInt16, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4245 {0xa120'8100'a322'8302,
4246 0xa524'8504'a726'8706,
4247 0xab2a'8b0a'ad2c'8d0c,
4248 0xa928'8908'af2e'8f0e,
4249 0xb130'9110'bd3c'9d1c,
4250 0xb736'9716'bf3e'9f1e,
4251 0xb938'9918'bb3a'9b1a,
4252 0xb534'9514'b332'9312});
4253 }
4254
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew16_vlmul4)4255 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew16_vlmul4) {
4256 VsxsegXeiXX<UInt16, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4257 {0xc140'8100'c342'8302,
4258 0xc544'8504'c746'8706,
4259 0xcb4a'8b0a'cd4c'8d0c,
4260 0xc948'8908'cf4e'8f0e,
4261 0xd150'9110'dd5c'9d1c,
4262 0xd756'9716'df5e'9f1e,
4263 0xd958'9918'db5a'9b1a,
4264 0xd554'9514'd352'9312,
4265 0xe564'a524'f574'b534,
4266 0xef6e'af2e'e968'a928,
4267 0xf776'b736'fd7c'bd3c,
4268 0xff7e'bf3e'e766'a726,
4269 0xed6c'ad2c'fb7a'bb3a,
4270 0xf978'b938'eb6a'ab2a,
4271 0xf170'b130'f372'b332,
4272 0xe362'a322'e160'a120});
4273 }
4274
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew16_vlmul1)4275 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew16_vlmul1) {
4276 VsxsegXeiXX<UInt16, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4277 {0x8100'a322'9312'8302,
4278 0x9716'8706'a120'9110,
4279 0xa524'9514'8504'a726,
4280 0x8b0a'ad2c'9d1c'8d0c,
4281 0x9f1e'8f0e'ab2a'9b1a,
4282 0xa928'9918'8908'af2e});
4283 }
4284
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew16_vlmul2)4285 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew16_vlmul2) {
4286 VsxsegXeiXX<UInt16, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4287 {0x8100'c342'a322'8302,
4288 0xa726'8706'c140'a120,
4289 0xc544'a524'8504'c746,
4290 0x8b0a'cd4c'ad2c'8d0c,
4291 0xaf2e'8f0e'cb4a'ab2a,
4292 0xc948'a928'8908'cf4e,
4293 0x9110'dd5c'bd3c'9d1c,
4294 0xbf3e'9f1e'd150'b130,
4295 0xd756'b736'9716'df5e,
4296 0x9918'db5a'bb3a'9b1a,
4297 0xb332'9312'd958'b938,
4298 0xd554'b534'9514'd352});
4299 }
4300
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew16_vlmul1)4301 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew16_vlmul1) {
4302 VsxsegXeiXX<UInt16, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4303 {0xb332'a322'9312'8302,
4304 0xb130'a120'9110'8100,
4305 0xb736'a726'9716'8706,
4306 0xb534'a524'9514'8504,
4307 0xbd3c'ad2c'9d1c'8d0c,
4308 0xbb3a'ab2a'9b1a'8b0a,
4309 0xbf3e'af2e'9f1e'8f0e,
4310 0xb938'a928'9918'8908});
4311 }
4312
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew16_vlmul2)4313 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew16_vlmul2) {
4314 VsxsegXeiXX<UInt16, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4315 {0xe362'c342'a322'8302,
4316 0xe160'c140'a120'8100,
4317 0xe766'c746'a726'8706,
4318 0xe564'c544'a524'8504,
4319 0xed6c'cd4c'ad2c'8d0c,
4320 0xeb6a'cb4a'ab2a'8b0a,
4321 0xef6e'cf4e'af2e'8f0e,
4322 0xe968'c948'a928'8908,
4323 0xfd7c'dd5c'bd3c'9d1c,
4324 0xf170'd150'b130'9110,
4325 0xff7e'df5e'bf3e'9f1e,
4326 0xf776'd756'b736'9716,
4327 0xfb7a'db5a'bb3a'9b1a,
4328 0xf978'd958'b938'9918,
4329 0xf372'd352'b332'9312,
4330 0xf574'd554'b534'9514});
4331 }
4332
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew16)4333 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew16) {
4334 VsxsegXeiXX<UInt16, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4335 {0xb332'a322'9312'8302,
4336 0xa120'9110'8100'c342,
4337 0x9716'8706'c140'b130,
4338 0x8504'c746'b736'a726,
4339 0xc544'b534'a524'9514,
4340 0xbd3c'ad2c'9d1c'8d0c,
4341 0xab2a'9b1a'8b0a'cd4c,
4342 0x9f1e'8f0e'cb4a'bb3a,
4343 0x8908'cf4e'bf3e'af2e,
4344 0xc948'b938'a928'9918});
4345 }
4346
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew16)4347 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew16) {
4348 VsxsegXeiXX<UInt16, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4349 {0xb332'a322'9312'8302,
4350 0x9110'8100'd352'c342,
4351 0xd150'c140'b130'a120,
4352 0xb736'a726'9716'8706,
4353 0x9514'8504'd756'c746,
4354 0xd554'c544'b534'a524,
4355 0xbd3c'ad2c'9d1c'8d0c,
4356 0x9b1a'8b0a'dd5c'cd4c,
4357 0xdb5a'cb4a'bb3a'ab2a,
4358 0xbf3e'af2e'9f1e'8f0e,
4359 0x9918'8908'df5e'cf4e,
4360 0xd958'c948'b938'a928});
4361 }
4362
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew16)4363 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew16) {
4364 VsxsegXeiXX<UInt16, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4365 {0xb332'a322'9312'8302,
4366 0x8100'e362'd352'c342,
4367 0xc140'b130'a120'9110,
4368 0x9716'8706'e160'd150,
4369 0xd756'c746'b736'a726,
4370 0xa524'9514'8504'e766,
4371 0xe564'd554'c544'b534,
4372 0xbd3c'ad2c'9d1c'8d0c,
4373 0x8b0a'ed6c'dd5c'cd4c,
4374 0xcb4a'bb3a'ab2a'9b1a,
4375 0x9f1e'8f0e'eb6a'db5a,
4376 0xdf5e'cf4e'bf3e'af2e,
4377 0xa928'9918'8908'ef6e,
4378 0xe968'd958'c948'b938});
4379 }
4380
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew16)4381 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew16) {
4382 VsxsegXeiXX<UInt16, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4383 {0xb332'a322'9312'8302,
4384 0xf372'e362'd352'c342,
4385 0xb130'a120'9110'8100,
4386 0xf170'e160'd150'c140,
4387 0xb736'a726'9716'8706,
4388 0xf776'e766'd756'c746,
4389 0xb534'a524'9514'8504,
4390 0xf574'e564'd554'c544,
4391 0xbd3c'ad2c'9d1c'8d0c,
4392 0xfd7c'ed6c'dd5c'cd4c,
4393 0xbb3a'ab2a'9b1a'8b0a,
4394 0xfb7a'eb6a'db5a'cb4a,
4395 0xbf3e'af2e'9f1e'8f0e,
4396 0xff7e'ef6e'df5e'cf4e,
4397 0xb938'a928'9918'8908,
4398 0xf978'e968'd958'c948});
4399 }
4400
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul1)4401 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul1) {
4402 VsxsegXeiXX<UInt32, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4403 {0x8302'8100'8706'8504, 0x8b0a'8908'8f0e'8d0c});
4404 }
4405
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul2)4406 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul2) {
4407 VsxsegXeiXX<UInt32, 1, 2>(
4408 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4409 {0x8302'8100'8706'8504, 0x8b0a'8908'8f0e'8d0c, 0x9716'9514'9b1a'9918, 0x9312'9110'9f1e'9d1c});
4410 }
4411
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul4)4412 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul4) {
4413 VsxsegXeiXX<UInt32, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4414 {0x8302'8100'8706'8504,
4415 0x8b0a'8908'8f0e'8d0c,
4416 0x9716'9514'9b1a'9918,
4417 0x9312'9110'9f1e'9d1c,
4418 0xa322'a120'bb3a'b938,
4419 0xaf2e'ad2c'bf3e'bd3c,
4420 0xb332'b130'b736'b534,
4421 0xab2a'a928'a726'a524});
4422 }
4423
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul8)4424 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul8) {
4425 VsxsegXeiXX<UInt32, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4426 {0x8302'8100'8706'8504,
4427 0x8b0a'8908'8f0e'8d0c,
4428 0x9716'9514'9b1a'9918,
4429 0x9312'9110'9f1e'9d1c,
4430 0xa322'a120'bb3a'b938,
4431 0xaf2e'ad2c'bf3e'bd3c,
4432 0xb332'b130'b736'b534,
4433 0xab2a'a928'a726'a524,
4434 0xcb4a'c948'eb6a'e968,
4435 0xdf5e'dd5c'd352'd150,
4436 0xef6e'ed6c'fb7a'f978,
4437 0xff7e'fd7c'cf4e'cd4c,
4438 0xdb5a'd958'f776'f574,
4439 0xf372'f170'd756'd554,
4440 0xe362'e160'e766'e564,
4441 0xc746'c544'c342'c140});
4442 }
4443
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew32_vlmul1)4444 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew32_vlmul1) {
4445 VsxsegXeiXX<UInt32, 2, 1>(
4446 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4447 {0x9716'9514'8706'8504, 0x9312'9110'8302'8100, 0x9f1e'9d1c'8f0e'8d0c, 0x9b1a'9918'8b0a'8908});
4448 }
4449
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew32_vlmul2)4450 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew32_vlmul2) {
4451 VsxsegXeiXX<UInt32, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4452 {0xa726'a524'8706'8504,
4453 0xa322'a120'8302'8100,
4454 0xaf2e'ad2c'8f0e'8d0c,
4455 0xab2a'a928'8b0a'8908,
4456 0xbb3a'b938'9b1a'9918,
4457 0xb736'b534'9716'9514,
4458 0xbf3e'bd3c'9f1e'9d1c,
4459 0xb332'b130'9312'9110});
4460 }
4461
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew32_vlmul4)4462 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew32_vlmul4) {
4463 VsxsegXeiXX<UInt32, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4464 {0xc746'c544'8706'8504,
4465 0xc342'c140'8302'8100,
4466 0xcf4e'cd4c'8f0e'8d0c,
4467 0xcb4a'c948'8b0a'8908,
4468 0xdb5a'd958'9b1a'9918,
4469 0xd756'd554'9716'9514,
4470 0xdf5e'dd5c'9f1e'9d1c,
4471 0xd352'd150'9312'9110,
4472 0xfb7a'f978'bb3a'b938,
4473 0xe362'e160'a322'a120,
4474 0xff7e'fd7c'bf3e'bd3c,
4475 0xef6e'ed6c'af2e'ad2c,
4476 0xf776'f574'b736'b534,
4477 0xf372'f170'b332'b130,
4478 0xe766'e564'a726'a524,
4479 0xeb6a'e968'ab2a'a928});
4480 }
4481
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew32_vlmul1)4482 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew32_vlmul1) {
4483 VsxsegXeiXX<UInt32, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4484 {0x9716'9514'8706'8504,
4485 0x8302'8100'a726'a524,
4486 0xa322'a120'9312'9110,
4487 0x9f1e'9d1c'8f0e'8d0c,
4488 0x8b0a'8908'af2e'ad2c,
4489 0xab2a'a928'9b1a'9918});
4490 }
4491
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew32_vlmul2)4492 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew32_vlmul2) {
4493 VsxsegXeiXX<UInt32, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4494 {0xa726'a524'8706'8504,
4495 0x8302'8100'c746'c544,
4496 0xc342'c140'a322'a120,
4497 0xaf2e'ad2c'8f0e'8d0c,
4498 0x8b0a'8908'cf4e'cd4c,
4499 0xcb4a'c948'ab2a'a928,
4500 0xbb3a'b938'9b1a'9918,
4501 0x9716'9514'db5a'd958,
4502 0xd756'd554'b736'b534,
4503 0xbf3e'bd3c'9f1e'9d1c,
4504 0x9312'9110'df5e'dd5c,
4505 0xd352'd150'b332'b130});
4506 }
4507
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew32_vlmul1)4508 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew32_vlmul1) {
4509 VsxsegXeiXX<UInt32, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4510 {0x9716'9514'8706'8504,
4511 0xb736'b534'a726'a524,
4512 0x9312'9110'8302'8100,
4513 0xb332'b130'a322'a120,
4514 0x9f1e'9d1c'8f0e'8d0c,
4515 0xbf3e'bd3c'af2e'ad2c,
4516 0x9b1a'9918'8b0a'8908,
4517 0xbb3a'b938'ab2a'a928});
4518 }
4519
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew32_vlmul2)4520 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew32_vlmul2) {
4521 VsxsegXeiXX<UInt32, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4522 {0xa726'a524'8706'8504,
4523 0xe766'e564'c746'c544,
4524 0xa322'a120'8302'8100,
4525 0xe362'e160'c342'c140,
4526 0xaf2e'ad2c'8f0e'8d0c,
4527 0xef6e'ed6c'cf4e'cd4c,
4528 0xab2a'a928'8b0a'8908,
4529 0xeb6a'e968'cb4a'c948,
4530 0xbb3a'b938'9b1a'9918,
4531 0xfb7a'f978'db5a'd958,
4532 0xb736'b534'9716'9514,
4533 0xf776'f574'd756'd554,
4534 0xbf3e'bd3c'9f1e'9d1c,
4535 0xff7e'fd7c'df5e'dd5c,
4536 0xb332'b130'9312'9110,
4537 0xf372'f170'd352'd150});
4538 }
4539
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew32)4540 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew32) {
4541 VsxsegXeiXX<UInt32, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4542 {0x9716'9514'8706'8504,
4543 0xb736'b534'a726'a524,
4544 0x8302'8100'c746'c544,
4545 0xa322'a120'9312'9110,
4546 0xc342'c140'b332'b130,
4547 0x9f1e'9d1c'8f0e'8d0c,
4548 0xbf3e'bd3c'af2e'ad2c,
4549 0x8b0a'8908'cf4e'cd4c,
4550 0xab2a'a928'9b1a'9918,
4551 0xcb4a'c948'bb3a'b938});
4552 }
4553
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew32)4554 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew32) {
4555 VsxsegXeiXX<UInt32, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4556 {0x9716'9514'8706'8504,
4557 0xb736'b534'a726'a524,
4558 0xd756'd554'c746'c544,
4559 0x9312'9110'8302'8100,
4560 0xb332'b130'a322'a120,
4561 0xd352'd150'c342'c140,
4562 0x9f1e'9d1c'8f0e'8d0c,
4563 0xbf3e'bd3c'af2e'ad2c,
4564 0xdf5e'dd5c'cf4e'cd4c,
4565 0x9b1a'9918'8b0a'8908,
4566 0xbb3a'b938'ab2a'a928,
4567 0xdb5a'd958'cb4a'c948});
4568 }
4569
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew32)4570 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew32) {
4571 VsxsegXeiXX<UInt32, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4572 {0x9716'9514'8706'8504,
4573 0xb736'b534'a726'a524,
4574 0xd756'd554'c746'c544,
4575 0x8302'8100'e766'e564,
4576 0xa322'a120'9312'9110,
4577 0xc342'c140'b332'b130,
4578 0xe362'e160'd352'd150,
4579 0x9f1e'9d1c'8f0e'8d0c,
4580 0xbf3e'bd3c'af2e'ad2c,
4581 0xdf5e'dd5c'cf4e'cd4c,
4582 0x8b0a'8908'ef6e'ed6c,
4583 0xab2a'a928'9b1a'9918,
4584 0xcb4a'c948'bb3a'b938,
4585 0xeb6a'e968'db5a'd958});
4586 }
4587
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew32)4588 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew32) {
4589 VsxsegXeiXX<UInt32, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4590 {0x9716'9514'8706'8504,
4591 0xb736'b534'a726'a524,
4592 0xd756'd554'c746'c544,
4593 0xf776'f574'e766'e564,
4594 0x9312'9110'8302'8100,
4595 0xb332'b130'a322'a120,
4596 0xd352'd150'c342'c140,
4597 0xf372'f170'e362'e160,
4598 0x9f1e'9d1c'8f0e'8d0c,
4599 0xbf3e'bd3c'af2e'ad2c,
4600 0xdf5e'dd5c'cf4e'cd4c,
4601 0xff7e'fd7c'ef6e'ed6c,
4602 0x9b1a'9918'8b0a'8908,
4603 0xbb3a'b938'ab2a'a928,
4604 0xdb5a'd958'cb4a'c948,
4605 0xfb7a'f978'eb6a'e968});
4606 }
4607
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul1)4608 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul1) {
4609 VsxsegXeiXX<UInt64, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4610 {0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100});
4611 }
4612
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul2)4613 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul2) {
4614 VsxsegXeiXX<UInt64, 1, 2>(
4615 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4616 {0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100, 0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110});
4617 }
4618
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul4)4619 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul4) {
4620 VsxsegXeiXX<UInt64, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4621 {0x8f0e'8d0c'8b0a'8908,
4622 0x8706'8504'8302'8100,
4623 0x9f1e'9d1c'9b1a'9918,
4624 0x9716'9514'9312'9110,
4625 0xb736'b534'b332'b130,
4626 0xaf2e'ad2c'ab2a'a928,
4627 0xbf3e'bd3c'bb3a'b938,
4628 0xa726'a524'a322'a120});
4629 }
4630
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul8)4631 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul8) {
4632 VsxsegXeiXX<UInt64, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4633 {0x8f0e'8d0c'8b0a'8908,
4634 0x8706'8504'8302'8100,
4635 0x9f1e'9d1c'9b1a'9918,
4636 0x9716'9514'9312'9110,
4637 0xb736'b534'b332'b130,
4638 0xaf2e'ad2c'ab2a'a928,
4639 0xbf3e'bd3c'bb3a'b938,
4640 0xa726'a524'a322'a120,
4641 0xf776'f574'f372'f170,
4642 0xc746'c544'c342'c140,
4643 0xff7e'fd7c'fb7a'f978,
4644 0xdf5e'dd5c'db5a'd958,
4645 0xef6e'ed6c'eb6a'e968,
4646 0xe766'e564'e362'e160,
4647 0xcf4e'cd4c'cb4a'c948,
4648 0xd756'd554'd352'd150});
4649 }
4650
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew64_vlmul1)4651 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew64_vlmul1) {
4652 VsxsegXeiXX<UInt64, 2, 1>(
4653 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4654 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918, 0x8706'8504'8302'8100, 0x9716'9514'9312'9110});
4655 }
4656
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew64_vlmul2)4657 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew64_vlmul2) {
4658 VsxsegXeiXX<UInt64, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4659 {0x8f0e'8d0c'8b0a'8908,
4660 0xaf2e'ad2c'ab2a'a928,
4661 0x8706'8504'8302'8100,
4662 0xa726'a524'a322'a120,
4663 0x9f1e'9d1c'9b1a'9918,
4664 0xbf3e'bd3c'bb3a'b938,
4665 0x9716'9514'9312'9110,
4666 0xb736'b534'b332'b130});
4667 }
4668
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew64_vlmul4)4669 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew64_vlmul4) {
4670 VsxsegXeiXX<UInt64, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4671 {0x8f0e'8d0c'8b0a'8908,
4672 0xcf4e'cd4c'cb4a'c948,
4673 0x8706'8504'8302'8100,
4674 0xc746'c544'c342'c140,
4675 0x9f1e'9d1c'9b1a'9918,
4676 0xdf5e'dd5c'db5a'd958,
4677 0x9716'9514'9312'9110,
4678 0xd756'd554'd352'd150,
4679 0xb736'b534'b332'b130,
4680 0xf776'f574'f372'f170,
4681 0xaf2e'ad2c'ab2a'a928,
4682 0xef6e'ed6c'eb6a'e968,
4683 0xbf3e'bd3c'bb3a'b938,
4684 0xff7e'fd7c'fb7a'f978,
4685 0xa726'a524'a322'a120,
4686 0xe766'e564'e362'e160});
4687 }
4688
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew64_vlmul1)4689 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew64_vlmul1) {
4690 VsxsegXeiXX<UInt64, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4691 {0x8f0e'8d0c'8b0a'8908,
4692 0x9f1e'9d1c'9b1a'9918,
4693 0xaf2e'ad2c'ab2a'a928,
4694 0x8706'8504'8302'8100,
4695 0x9716'9514'9312'9110,
4696 0xa726'a524'a322'a120});
4697 }
4698
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew64_vlmul2)4699 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew64_vlmul2) {
4700 VsxsegXeiXX<UInt64, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4701 {0x8f0e'8d0c'8b0a'8908,
4702 0xaf2e'ad2c'ab2a'a928,
4703 0xcf4e'cd4c'cb4a'c948,
4704 0x8706'8504'8302'8100,
4705 0xa726'a524'a322'a120,
4706 0xc746'c544'c342'c140,
4707 0x9f1e'9d1c'9b1a'9918,
4708 0xbf3e'bd3c'bb3a'b938,
4709 0xdf5e'dd5c'db5a'd958,
4710 0x9716'9514'9312'9110,
4711 0xb736'b534'b332'b130,
4712 0xd756'd554'd352'd150});
4713 }
4714
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew64_vlmul1)4715 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew64_vlmul1) {
4716 VsxsegXeiXX<UInt64, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4717 {0x8f0e'8d0c'8b0a'8908,
4718 0x9f1e'9d1c'9b1a'9918,
4719 0xaf2e'ad2c'ab2a'a928,
4720 0xbf3e'bd3c'bb3a'b938,
4721 0x8706'8504'8302'8100,
4722 0x9716'9514'9312'9110,
4723 0xa726'a524'a322'a120,
4724 0xb736'b534'b332'b130});
4725 }
4726
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew64_vlmul2)4727 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew64_vlmul2) {
4728 VsxsegXeiXX<UInt64, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4729 {0x8f0e'8d0c'8b0a'8908,
4730 0xaf2e'ad2c'ab2a'a928,
4731 0xcf4e'cd4c'cb4a'c948,
4732 0xef6e'ed6c'eb6a'e968,
4733 0x8706'8504'8302'8100,
4734 0xa726'a524'a322'a120,
4735 0xc746'c544'c342'c140,
4736 0xe766'e564'e362'e160,
4737 0x9f1e'9d1c'9b1a'9918,
4738 0xbf3e'bd3c'bb3a'b938,
4739 0xdf5e'dd5c'db5a'd958,
4740 0xff7e'fd7c'fb7a'f978,
4741 0x9716'9514'9312'9110,
4742 0xb736'b534'b332'b130,
4743 0xd756'd554'd352'd150,
4744 0xf776'f574'f372'f170});
4745 }
4746
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew64)4747 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew64) {
4748 VsxsegXeiXX<UInt64, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4749 {0x8f0e'8d0c'8b0a'8908,
4750 0x9f1e'9d1c'9b1a'9918,
4751 0xaf2e'ad2c'ab2a'a928,
4752 0xbf3e'bd3c'bb3a'b938,
4753 0xcf4e'cd4c'cb4a'c948,
4754 0x8706'8504'8302'8100,
4755 0x9716'9514'9312'9110,
4756 0xa726'a524'a322'a120,
4757 0xb736'b534'b332'b130,
4758 0xc746'c544'c342'c140});
4759 }
4760
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew64)4761 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew64) {
4762 VsxsegXeiXX<UInt64, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4763 {0x8f0e'8d0c'8b0a'8908,
4764 0x9f1e'9d1c'9b1a'9918,
4765 0xaf2e'ad2c'ab2a'a928,
4766 0xbf3e'bd3c'bb3a'b938,
4767 0xcf4e'cd4c'cb4a'c948,
4768 0xdf5e'dd5c'db5a'd958,
4769 0x8706'8504'8302'8100,
4770 0x9716'9514'9312'9110,
4771 0xa726'a524'a322'a120,
4772 0xb736'b534'b332'b130,
4773 0xc746'c544'c342'c140,
4774 0xd756'd554'd352'd150});
4775 }
4776
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew64)4777 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew64) {
4778 VsxsegXeiXX<UInt64, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4779 {0x8f0e'8d0c'8b0a'8908,
4780 0x9f1e'9d1c'9b1a'9918,
4781 0xaf2e'ad2c'ab2a'a928,
4782 0xbf3e'bd3c'bb3a'b938,
4783 0xcf4e'cd4c'cb4a'c948,
4784 0xdf5e'dd5c'db5a'd958,
4785 0xef6e'ed6c'eb6a'e968,
4786 0x8706'8504'8302'8100,
4787 0x9716'9514'9312'9110,
4788 0xa726'a524'a322'a120,
4789 0xb736'b534'b332'b130,
4790 0xc746'c544'c342'c140,
4791 0xd756'd554'd352'd150,
4792 0xe766'e564'e362'e160});
4793 }
4794
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew64)4795 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew64) {
4796 VsxsegXeiXX<UInt64, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4797 {0x8f0e'8d0c'8b0a'8908,
4798 0x9f1e'9d1c'9b1a'9918,
4799 0xaf2e'ad2c'ab2a'a928,
4800 0xbf3e'bd3c'bb3a'b938,
4801 0xcf4e'cd4c'cb4a'c948,
4802 0xdf5e'dd5c'db5a'd958,
4803 0xef6e'ed6c'eb6a'e968,
4804 0xff7e'fd7c'fb7a'f978,
4805 0x8706'8504'8302'8100,
4806 0x9716'9514'9312'9110,
4807 0xa726'a524'a322'a120,
4808 0xb736'b534'b332'b130,
4809 0xc746'c544'c342'c140,
4810 0xd756'd554'd352'd150,
4811 0xe766'e564'e362'e160,
4812 0xf776'f574'f372'f170});
4813 }
4814
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul1)4815 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul1) {
4816 TestVssegXeXX<UInt8, 1, 1>(0x000008427, // vsse8.v v8, (x1), v0.t
4817 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
4818 }
4819
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul2)4820 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul2) {
4821 TestVssegXeXX<UInt8, 1, 2>(
4822 0x000008427, // vsse8.v v8, (x1), v0.t
4823 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
4824 }
4825
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul4)4826 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul4) {
4827 TestVssegXeXX<UInt8, 1, 4>(0x000008427, // vsse8.v v8, (x1), v0.t
4828 {0x8706'8504'8302'8100,
4829 0x8f0e'8d0c'8b0a'8908,
4830 0x9716'9514'9312'9110,
4831 0x9f1e'9d1c'9b1a'9918,
4832 0xa726'a524'a322'a120,
4833 0xaf2e'ad2c'ab2a'a928,
4834 0xb736'b534'b332'b130,
4835 0xbf3e'bd3c'bb3a'b938});
4836 }
4837
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul8)4838 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul8) {
4839 TestVssegXeXX<UInt8, 1, 8>(0x000008427, // vsse8.v v8, (x1), v0.t
4840 {0x8706'8504'8302'8100,
4841 0x8f0e'8d0c'8b0a'8908,
4842 0x9716'9514'9312'9110,
4843 0x9f1e'9d1c'9b1a'9918,
4844 0xa726'a524'a322'a120,
4845 0xaf2e'ad2c'ab2a'a928,
4846 0xb736'b534'b332'b130,
4847 0xbf3e'bd3c'bb3a'b938,
4848 0xc746'c544'c342'c140,
4849 0xcf4e'cd4c'cb4a'c948,
4850 0xd756'd554'd352'd150,
4851 0xdf5e'dd5c'db5a'd958,
4852 0xe766'e564'e362'e160,
4853 0xef6e'ed6c'eb6a'e968,
4854 0xf776'f574'f372'f170,
4855 0xff7e'fd7c'fb7a'f978});
4856 }
4857
TEST_F(Riscv64InterpreterTest,TestVsseg2e8_vlmul1)4858 TEST_F(Riscv64InterpreterTest, TestVsseg2e8_vlmul1) {
4859 TestVssegXeXX<UInt8, 2, 1>(
4860 0x20008427, // vsseg2e8.v v8, (x1), v0.t
4861 {0x9383'1202'9181'1000, 0x9787'1606'9585'1404, 0x9b8b'1a0a'9989'1808, 0x9f8f'1e0e'9d8d'1c0c});
4862 }
4863
TEST_F(Riscv64InterpreterTest,TestVsseg2e8_vlmul2)4864 TEST_F(Riscv64InterpreterTest, TestVsseg2e8_vlmul2) {
4865 TestVssegXeXX<UInt8, 2, 2>(0x20008427, // vsseg2e8.v v8, (x1), v0.t
4866 {0xa383'2202'a181'2000,
4867 0xa787'2606'a585'2404,
4868 0xab8b'2a0a'a989'2808,
4869 0xaf8f'2e0e'ad8d'2c0c,
4870 0xb393'3212'b191'3010,
4871 0xb797'3616'b595'3414,
4872 0xbb9b'3a1a'b999'3818,
4873 0xbf9f'3e1e'bd9d'3c1c});
4874 }
4875
TEST_F(Riscv64InterpreterTest,TestVsseg2e8_vlmul4)4876 TEST_F(Riscv64InterpreterTest, TestVsseg2e8_vlmul4) {
4877 TestVssegXeXX<UInt8, 2, 4>(0x20008427, // vsseg2e8.v v8, (x1), v0.t
4878 {0xc383'4202'c181'4000,
4879 0xc787'4606'c585'4404,
4880 0xcb8b'4a0a'c989'4808,
4881 0xcf8f'4e0e'cd8d'4c0c,
4882 0xd393'5212'd191'5010,
4883 0xd797'5616'd595'5414,
4884 0xdb9b'5a1a'd999'5818,
4885 0xdf9f'5e1e'dd9d'5c1c,
4886 0xe3a3'6222'e1a1'6020,
4887 0xe7a7'6626'e5a5'6424,
4888 0xebab'6a2a'e9a9'6828,
4889 0xefaf'6e2e'edad'6c2c,
4890 0xf3b3'7232'f1b1'7030,
4891 0xf7b7'7636'f5b5'7434,
4892 0xfbbb'7a3a'f9b9'7838,
4893 0xffbf'7e3e'fdbd'7c3c});
4894 }
4895
TEST_F(Riscv64InterpreterTest,TestVsseg3e8_vlmul1)4896 TEST_F(Riscv64InterpreterTest, TestVsseg3e8_vlmul1) {
4897 TestVssegXeXX<UInt8, 3, 1>(0x40008427, // vsseg3e8.v v8, (x1), v0.t
4898 {0x1202'a191'8120'1000,
4899 0x8524'1404'a393'8322,
4900 0xa797'8726'1606'a595,
4901 0x1a0a'a999'8928'1808,
4902 0x8d2c'1c0c'ab9b'8b2a,
4903 0xaf9f'8f2e'1e0e'ad9d});
4904 }
4905
TEST_F(Riscv64InterpreterTest,TestVsseg3e8_vlmul2)4906 TEST_F(Riscv64InterpreterTest, TestVsseg3e8_vlmul2) {
4907 TestVssegXeXX<UInt8, 3, 2>(0x40008427, // vsseg3e8.v v8, (x1), v0.t
4908 {0x2202'c1a1'8140'2000,
4909 0x8544'2404'c3a3'8342,
4910 0xc7a7'8746'2606'c5a5,
4911 0x2a0a'c9a9'8948'2808,
4912 0x8d4c'2c0c'cbab'8b4a,
4913 0xcfaf'8f4e'2e0e'cdad,
4914 0x3212'd1b1'9150'3010,
4915 0x9554'3414'd3b3'9352,
4916 0xd7b7'9756'3616'd5b5,
4917 0x3a1a'd9b9'9958'3818,
4918 0x9d5c'3c1c'dbbb'9b5a,
4919 0xdfbf'9f5e'3e1e'ddbd});
4920 }
4921
TEST_F(Riscv64InterpreterTest,TestVsseg4e8_vlmul1)4922 TEST_F(Riscv64InterpreterTest, TestVsseg4e8_vlmul1) {
4923 TestVssegXeXX<UInt8, 4, 1>(0x60008427, // vsseg4e8.v v8, (x1), v0.t
4924 {0xb1a1'9181'3020'1000,
4925 0xb3a3'9383'3222'1202,
4926 0xb5a5'9585'3424'1404,
4927 0xb7a7'9787'3626'1606,
4928 0xb9a9'9989'3828'1808,
4929 0xbbab'9b8b'3a2a'1a0a,
4930 0xbdad'9d8d'3c2c'1c0c,
4931 0xbfaf'9f8f'3e2e'1e0e});
4932 }
4933
TEST_F(Riscv64InterpreterTest,TestVsseg4e8_vlmul2)4934 TEST_F(Riscv64InterpreterTest, TestVsseg4e8_vlmul2) {
4935 TestVssegXeXX<UInt8, 4, 2>(0x60008427, // vsseg4e8.v v8, (x1), v0.t
4936 {0xe1c1'a181'6040'2000,
4937 0xe3c3'a383'6242'2202,
4938 0xe5c5'a585'6444'2404,
4939 0xe7c7'a787'6646'2606,
4940 0xe9c9'a989'6848'2808,
4941 0xebcb'ab8b'6a4a'2a0a,
4942 0xedcd'ad8d'6c4c'2c0c,
4943 0xefcf'af8f'6e4e'2e0e,
4944 0xf1d1'b191'7050'3010,
4945 0xf3d3'b393'7252'3212,
4946 0xf5d5'b595'7454'3414,
4947 0xf7d7'b797'7656'3616,
4948 0xf9d9'b999'7858'3818,
4949 0xfbdb'bb9b'7a5a'3a1a,
4950 0xfddd'bd9d'7c5c'3c1c,
4951 0xffdf'bf9f'7e5e'3e1e});
4952 }
4953
TEST_F(Riscv64InterpreterTest,TestVsseg5e8)4954 TEST_F(Riscv64InterpreterTest, TestVsseg5e8) {
4955 TestVssegXeXX<UInt8, 5, 1>(0x80008427, // vsseg5e8.v v8, (x1), v0.t
4956 {0xa191'8140'3020'1000,
4957 0x8342'3222'1202'c1b1,
4958 0x3424'1404'c3b3'a393,
4959 0x1606'c5b5'a595'8544,
4960 0xc7b7'a797'8746'3626,
4961 0xa999'8948'3828'1808,
4962 0x8b4a'3a2a'1a0a'c9b9,
4963 0x3c2c'1c0c'cbbb'ab9b,
4964 0x1e0e'cdbd'ad9d'8d4c,
4965 0xcfbf'af9f'8f4e'3e2e});
4966 }
4967
TEST_F(Riscv64InterpreterTest,TestVsseg6e8)4968 TEST_F(Riscv64InterpreterTest, TestVsseg6e8) {
4969 TestVssegXeXX<UInt8, 6, 1>(0xa0008427, // vsseg6e8.v v8, (x1), v0.t
4970 {0x9181'5040'3020'1000,
4971 0x3222'1202'd1c1'b1a1,
4972 0xd3c3'b3a3'9383'5242,
4973 0x9585'5444'3424'1404,
4974 0x3626'1606'd5c5'b5a5,
4975 0xd7c7'b7a7'9787'5646,
4976 0x9989'5848'3828'1808,
4977 0x3a2a'1a0a'd9c9'b9a9,
4978 0xdbcb'bbab'9b8b'5a4a,
4979 0x9d8d'5c4c'3c2c'1c0c,
4980 0x3e2e'1e0e'ddcd'bdad,
4981 0xdfcf'bfaf'9f8f'5e4e});
4982 }
4983
TEST_F(Riscv64InterpreterTest,TestVsseg7e8)4984 TEST_F(Riscv64InterpreterTest, TestVsseg7e8) {
4985 TestVssegXeXX<UInt8, 7, 1>(0xc0008427, // vsseg7e8.v v8, (x1), v0.t
4986 {0x8160'5040'3020'1000,
4987 0x1202'e1d1'c1b1'a191,
4988 0xa393'8362'5242'3222,
4989 0x3424'1404'e3d3'c3b3,
4990 0xc5b5'a595'8564'5444,
4991 0x5646'3626'1606'e5d5,
4992 0xe7d7'c7b7'a797'8766,
4993 0x8968'5848'3828'1808,
4994 0x1a0a'e9d9'c9b9'a999,
4995 0xab9b'8b6a'5a4a'3a2a,
4996 0x3c2c'1c0c'ebdb'cbbb,
4997 0xcdbd'ad9d'8d6c'5c4c,
4998 0x5e4e'3e2e'1e0e'eddd,
4999 0xefdf'cfbf'af9f'8f6e});
5000 }
5001
TEST_F(Riscv64InterpreterTest,TestVsseg8e8)5002 TEST_F(Riscv64InterpreterTest, TestVsseg8e8) {
5003 TestVssegXeXX<UInt8, 8, 1>(0xe0008427, // vsseg8e8.v v8, (x1), v0.t
5004 {0x7060'5040'3020'1000,
5005 0xf1e1'd1c1'b1a1'9181,
5006 0x7262'5242'3222'1202,
5007 0xf3e3'd3c3'b3a3'9383,
5008 0x7464'5444'3424'1404,
5009 0xf5e5'd5c5'b5a5'9585,
5010 0x7666'5646'3626'1606,
5011 0xf7e7'd7c7'b7a7'9787,
5012 0x7868'5848'3828'1808,
5013 0xf9e9'd9c9'b9a9'9989,
5014 0x7a6a'5a4a'3a2a'1a0a,
5015 0xfbeb'dbcb'bbab'9b8b,
5016 0x7c6c'5c4c'3c2c'1c0c,
5017 0xfded'ddcd'bdad'9d8d,
5018 0x7e6e'5e4e'3e2e'1e0e,
5019 0xffef'dfcf'bfaf'9f8f});
5020 }
5021
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul1)5022 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul1) {
5023 TestVssegXeXX<UInt16, 1, 1>(0x000d427, // vse16.v v8, (x1), v0.t
5024 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
5025 }
5026
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul2)5027 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul2) {
5028 TestVssegXeXX<UInt16, 1, 2>(
5029 0x000d427, // vse16.v v8, (x1), v0.t
5030 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
5031 }
5032
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul4)5033 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul4) {
5034 TestVssegXeXX<UInt16, 1, 4>(0x000d427, // vse16.v v8, (x1), v0.t
5035 {0x8706'8504'8302'8100,
5036 0x8f0e'8d0c'8b0a'8908,
5037 0x9716'9514'9312'9110,
5038 0x9f1e'9d1c'9b1a'9918,
5039 0xa726'a524'a322'a120,
5040 0xaf2e'ad2c'ab2a'a928,
5041 0xb736'b534'b332'b130,
5042 0xbf3e'bd3c'bb3a'b938});
5043 }
5044
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul8)5045 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul8) {
5046 TestVssegXeXX<UInt16, 1, 8>(0x000d427, // vse16.v v8, (x1), v0.t
5047 {0x8706'8504'8302'8100,
5048 0x8f0e'8d0c'8b0a'8908,
5049 0x9716'9514'9312'9110,
5050 0x9f1e'9d1c'9b1a'9918,
5051 0xa726'a524'a322'a120,
5052 0xaf2e'ad2c'ab2a'a928,
5053 0xb736'b534'b332'b130,
5054 0xbf3e'bd3c'bb3a'b938,
5055 0xc746'c544'c342'c140,
5056 0xcf4e'cd4c'cb4a'c948,
5057 0xd756'd554'd352'd150,
5058 0xdf5e'dd5c'db5a'd958,
5059 0xe766'e564'e362'e160,
5060 0xef6e'ed6c'eb6a'e968,
5061 0xf776'f574'f372'f170,
5062 0xff7e'fd7c'fb7a'f978});
5063 }
5064
TEST_F(Riscv64InterpreterTest,TestVsseg2e16_vlmul1)5065 TEST_F(Riscv64InterpreterTest, TestVsseg2e16_vlmul1) {
5066 TestVssegXeXX<UInt16, 2, 1>(
5067 0x2000d427, // vsseg2e16.v v8, (x1), v0.t
5068 {0x9312'8302'9110'8100, 0x9716'8706'9514'8504, 0x9b1a'8b0a'9918'8908, 0x9f1e'8f0e'9d1c'8d0c});
5069 }
5070
TEST_F(Riscv64InterpreterTest,TestVsseg2e16_vlmul2)5071 TEST_F(Riscv64InterpreterTest, TestVsseg2e16_vlmul2) {
5072 TestVssegXeXX<UInt16, 2, 2>(0x2000d427, // vsseg2e16.v v8, (x1), v0.t
5073 {0xa322'8302'a120'8100,
5074 0xa726'8706'a524'8504,
5075 0xab2a'8b0a'a928'8908,
5076 0xaf2e'8f0e'ad2c'8d0c,
5077 0xb332'9312'b130'9110,
5078 0xb736'9716'b534'9514,
5079 0xbb3a'9b1a'b938'9918,
5080 0xbf3e'9f1e'bd3c'9d1c});
5081 }
5082
TEST_F(Riscv64InterpreterTest,TestVsseg2e16_vlmul4)5083 TEST_F(Riscv64InterpreterTest, TestVsseg2e16_vlmul4) {
5084 TestVssegXeXX<UInt16, 2, 4>(0x2000d427, // vsseg2e16.v v8, (x1), v0.t
5085 {0xc342'8302'c140'8100,
5086 0xc746'8706'c544'8504,
5087 0xcb4a'8b0a'c948'8908,
5088 0xcf4e'8f0e'cd4c'8d0c,
5089 0xd352'9312'd150'9110,
5090 0xd756'9716'd554'9514,
5091 0xdb5a'9b1a'd958'9918,
5092 0xdf5e'9f1e'dd5c'9d1c,
5093 0xe362'a322'e160'a120,
5094 0xe766'a726'e564'a524,
5095 0xeb6a'ab2a'e968'a928,
5096 0xef6e'af2e'ed6c'ad2c,
5097 0xf372'b332'f170'b130,
5098 0xf776'b736'f574'b534,
5099 0xfb7a'bb3a'f978'b938,
5100 0xff7e'bf3e'fd7c'bd3c});
5101 }
5102
TEST_F(Riscv64InterpreterTest,TestVsseg3e16_vlmul1)5103 TEST_F(Riscv64InterpreterTest, TestVsseg3e16_vlmul1) {
5104 TestVssegXeXX<UInt16, 3, 1>(0x4000d427, // vsseg3e16.v v8, (x1), v0.t
5105 {0x8302'a120'9110'8100,
5106 0x9514'8504'a322'9312,
5107 0xa726'9716'8706'a524,
5108 0x8b0a'a928'9918'8908,
5109 0x9d1c'8d0c'ab2a'9b1a,
5110 0xaf2e'9f1e'8f0e'ad2c});
5111 }
5112
TEST_F(Riscv64InterpreterTest,TestVsseg3e16_vlmul2)5113 TEST_F(Riscv64InterpreterTest, TestVsseg3e16_vlmul2) {
5114 TestVssegXeXX<UInt16, 3, 2>(0x4000d427, // vsseg3e16.v v8, (x1), v0.t
5115 {0x8302'c140'a120'8100,
5116 0xa524'8504'c342'a322,
5117 0xc746'a726'8706'c544,
5118 0x8b0a'c948'a928'8908,
5119 0xad2c'8d0c'cb4a'ab2a,
5120 0xcf4e'af2e'8f0e'cd4c,
5121 0x9312'd150'b130'9110,
5122 0xb534'9514'd352'b332,
5123 0xd756'b736'9716'd554,
5124 0x9b1a'd958'b938'9918,
5125 0xbd3c'9d1c'db5a'bb3a,
5126 0xdf5e'bf3e'9f1e'dd5c});
5127 }
5128
TEST_F(Riscv64InterpreterTest,TestVsseg4e16_vlmul1)5129 TEST_F(Riscv64InterpreterTest, TestVsseg4e16_vlmul1) {
5130 TestVssegXeXX<UInt16, 4, 1>(0x6000d427, // vsseg4e16.v v8, (x1), v0.t
5131 {0xb130'a120'9110'8100,
5132 0xb332'a322'9312'8302,
5133 0xb534'a524'9514'8504,
5134 0xb736'a726'9716'8706,
5135 0xb938'a928'9918'8908,
5136 0xbb3a'ab2a'9b1a'8b0a,
5137 0xbd3c'ad2c'9d1c'8d0c,
5138 0xbf3e'af2e'9f1e'8f0e});
5139 }
5140
TEST_F(Riscv64InterpreterTest,TestVsseg4e16_vlmul2)5141 TEST_F(Riscv64InterpreterTest, TestVsseg4e16_vlmul2) {
5142 TestVssegXeXX<UInt16, 4, 2>(0x6000d427, // vsseg4e16.v v8, (x1), v0.t
5143 {0xe160'c140'a120'8100,
5144 0xe362'c342'a322'8302,
5145 0xe564'c544'a524'8504,
5146 0xe766'c746'a726'8706,
5147 0xe968'c948'a928'8908,
5148 0xeb6a'cb4a'ab2a'8b0a,
5149 0xed6c'cd4c'ad2c'8d0c,
5150 0xef6e'cf4e'af2e'8f0e,
5151 0xf170'd150'b130'9110,
5152 0xf372'd352'b332'9312,
5153 0xf574'd554'b534'9514,
5154 0xf776'd756'b736'9716,
5155 0xf978'd958'b938'9918,
5156 0xfb7a'db5a'bb3a'9b1a,
5157 0xfd7c'dd5c'bd3c'9d1c,
5158 0xff7e'df5e'bf3e'9f1e});
5159 }
5160
TEST_F(Riscv64InterpreterTest,TestVsseg5e16)5161 TEST_F(Riscv64InterpreterTest, TestVsseg5e16) {
5162 TestVssegXeXX<UInt16, 5, 1>(0x8000d427, // vsseg5e16.v v8, (x1), v0.t
5163 {0xb130'a120'9110'8100,
5164 0xa322'9312'8302'c140,
5165 0x9514'8504'c342'b332,
5166 0x8706'c544'b534'a524,
5167 0xc746'b736'a726'9716,
5168 0xb938'a928'9918'8908,
5169 0xab2a'9b1a'8b0a'c948,
5170 0x9d1c'8d0c'cb4a'bb3a,
5171 0x8f0e'cd4c'bd3c'ad2c,
5172 0xcf4e'bf3e'af2e'9f1e});
5173 }
5174
TEST_F(Riscv64InterpreterTest,TestVsseg6e16)5175 TEST_F(Riscv64InterpreterTest, TestVsseg6e16) {
5176 TestVssegXeXX<UInt16, 6, 1>(0xa000d427, // vsseg6e16.v v8, (x1), v0.t
5177 {0xb130'a120'9110'8100,
5178 0x9312'8302'd150'c140,
5179 0xd352'c342'b332'a322,
5180 0xb534'a524'9514'8504,
5181 0x9716'8706'd554'c544,
5182 0xd756'c746'b736'a726,
5183 0xb938'a928'9918'8908,
5184 0x9b1a'8b0a'd958'c948,
5185 0xdb5a'cb4a'bb3a'ab2a,
5186 0xbd3c'ad2c'9d1c'8d0c,
5187 0x9f1e'8f0e'dd5c'cd4c,
5188 0xdf5e'cf4e'bf3e'af2e});
5189 }
5190
TEST_F(Riscv64InterpreterTest,TestVsseg7e16)5191 TEST_F(Riscv64InterpreterTest, TestVsseg7e16) {
5192 TestVssegXeXX<UInt16, 7, 1>(0xc000d427, // vsseg7e16.v v8, (x1), v0.t
5193 {0xb130'a120'9110'8100,
5194 0x8302'e160'd150'c140,
5195 0xc342'b332'a322'9312,
5196 0x9514'8504'e362'd352,
5197 0xd554'c544'b534'a524,
5198 0xa726'9716'8706'e564,
5199 0xe766'd756'c746'b736,
5200 0xb938'a928'9918'8908,
5201 0x8b0a'e968'd958'c948,
5202 0xcb4a'bb3a'ab2a'9b1a,
5203 0x9d1c'8d0c'eb6a'db5a,
5204 0xdd5c'cd4c'bd3c'ad2c,
5205 0xaf2e'9f1e'8f0e'ed6c,
5206 0xef6e'df5e'cf4e'bf3e});
5207 }
5208
TEST_F(Riscv64InterpreterTest,TestVsseg8e16)5209 TEST_F(Riscv64InterpreterTest, TestVsseg8e16) {
5210 TestVssegXeXX<UInt16, 8, 1>(0xe000d427, // vsseg8e16.v v8, (x1), v0.t
5211 {0xb130'a120'9110'8100,
5212 0xf170'e160'd150'c140,
5213 0xb332'a322'9312'8302,
5214 0xf372'e362'd352'c342,
5215 0xb534'a524'9514'8504,
5216 0xf574'e564'd554'c544,
5217 0xb736'a726'9716'8706,
5218 0xf776'e766'd756'c746,
5219 0xb938'a928'9918'8908,
5220 0xf978'e968'd958'c948,
5221 0xbb3a'ab2a'9b1a'8b0a,
5222 0xfb7a'eb6a'db5a'cb4a,
5223 0xbd3c'ad2c'9d1c'8d0c,
5224 0xfd7c'ed6c'dd5c'cd4c,
5225 0xbf3e'af2e'9f1e'8f0e,
5226 0xff7e'ef6e'df5e'cf4e});
5227 }
5228
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul1)5229 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul1) {
5230 TestVssegXeXX<UInt32, 1, 1>(0x000e427, // vse32.v v8, (x1), v0.t
5231 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
5232 }
5233
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul2)5234 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul2) {
5235 TestVssegXeXX<UInt32, 1, 2>(
5236 0x000e427, // vse32.v v8, (x1), v0.t
5237 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
5238 }
5239
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul4)5240 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul4) {
5241 TestVssegXeXX<UInt32, 1, 4>(0x000e427, // vse32.v v8, (x1), v0.t
5242 {0x8706'8504'8302'8100,
5243 0x8f0e'8d0c'8b0a'8908,
5244 0x9716'9514'9312'9110,
5245 0x9f1e'9d1c'9b1a'9918,
5246 0xa726'a524'a322'a120,
5247 0xaf2e'ad2c'ab2a'a928,
5248 0xb736'b534'b332'b130,
5249 0xbf3e'bd3c'bb3a'b938});
5250 }
5251
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul8)5252 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul8) {
5253 TestVssegXeXX<UInt32, 1, 8>(0x000e427, // vse32.v v8, (x1), v0.t
5254 {0x8706'8504'8302'8100,
5255 0x8f0e'8d0c'8b0a'8908,
5256 0x9716'9514'9312'9110,
5257 0x9f1e'9d1c'9b1a'9918,
5258 0xa726'a524'a322'a120,
5259 0xaf2e'ad2c'ab2a'a928,
5260 0xb736'b534'b332'b130,
5261 0xbf3e'bd3c'bb3a'b938,
5262 0xc746'c544'c342'c140,
5263 0xcf4e'cd4c'cb4a'c948,
5264 0xd756'd554'd352'd150,
5265 0xdf5e'dd5c'db5a'd958,
5266 0xe766'e564'e362'e160,
5267 0xef6e'ed6c'eb6a'e968,
5268 0xf776'f574'f372'f170,
5269 0xff7e'fd7c'fb7a'f978});
5270 }
5271
TEST_F(Riscv64InterpreterTest,TestVsseg2e32_vlmul1)5272 TEST_F(Riscv64InterpreterTest, TestVsseg2e32_vlmul1) {
5273 TestVssegXeXX<UInt32, 2, 1>(
5274 0x2000e427, // vsseg2e32.v v8, (x1), v0.t
5275 {0x9312'9110'8302'8100, 0x9716'9514'8706'8504, 0x9b1a'9918'8b0a'8908, 0x9f1e'9d1c'8f0e'8d0c});
5276 }
5277
TEST_F(Riscv64InterpreterTest,TestVsseg2e32_vlmul2)5278 TEST_F(Riscv64InterpreterTest, TestVsseg2e32_vlmul2) {
5279 TestVssegXeXX<UInt32, 2, 2>(0x2000e427, // vsseg2e32.v v8, (x1), v0.t
5280 {0xa322'a120'8302'8100,
5281 0xa726'a524'8706'8504,
5282 0xab2a'a928'8b0a'8908,
5283 0xaf2e'ad2c'8f0e'8d0c,
5284 0xb332'b130'9312'9110,
5285 0xb736'b534'9716'9514,
5286 0xbb3a'b938'9b1a'9918,
5287 0xbf3e'bd3c'9f1e'9d1c});
5288 }
5289
TEST_F(Riscv64InterpreterTest,TestVsseg2e32_vlmul4)5290 TEST_F(Riscv64InterpreterTest, TestVsseg2e32_vlmul4) {
5291 TestVssegXeXX<UInt32, 2, 4>(0x2000e427, // vsseg2e32.v v8, (x1), v0.t
5292 {0xc342'c140'8302'8100,
5293 0xc746'c544'8706'8504,
5294 0xcb4a'c948'8b0a'8908,
5295 0xcf4e'cd4c'8f0e'8d0c,
5296 0xd352'd150'9312'9110,
5297 0xd756'd554'9716'9514,
5298 0xdb5a'd958'9b1a'9918,
5299 0xdf5e'dd5c'9f1e'9d1c,
5300 0xe362'e160'a322'a120,
5301 0xe766'e564'a726'a524,
5302 0xeb6a'e968'ab2a'a928,
5303 0xef6e'ed6c'af2e'ad2c,
5304 0xf372'f170'b332'b130,
5305 0xf776'f574'b736'b534,
5306 0xfb7a'f978'bb3a'b938,
5307 0xff7e'fd7c'bf3e'bd3c});
5308 }
5309
TEST_F(Riscv64InterpreterTest,TestVsseg3e32_vlmul1)5310 TEST_F(Riscv64InterpreterTest, TestVsseg3e32_vlmul1) {
5311 TestVssegXeXX<UInt32, 3, 1>(0x4000e427, // vsseg3e32.v v8, (x1), v0.t
5312 {0x9312'9110'8302'8100,
5313 0x8706'8504'a322'a120,
5314 0xa726'a524'9716'9514,
5315 0x9b1a'9918'8b0a'8908,
5316 0x8f0e'8d0c'ab2a'a928,
5317 0xaf2e'ad2c'9f1e'9d1c});
5318 }
5319
TEST_F(Riscv64InterpreterTest,TestVsseg3e32_vlmul2)5320 TEST_F(Riscv64InterpreterTest, TestVsseg3e32_vlmul2) {
5321 TestVssegXeXX<UInt32, 3, 2>(0x4000e427, // vsseg3e32.v v8, (x1), v0.t
5322 {0xa322'a120'8302'8100,
5323 0x8706'8504'c342'c140,
5324 0xc746'c544'a726'a524,
5325 0xab2a'a928'8b0a'8908,
5326 0x8f0e'8d0c'cb4a'c948,
5327 0xcf4e'cd4c'af2e'ad2c,
5328 0xb332'b130'9312'9110,
5329 0x9716'9514'd352'd150,
5330 0xd756'd554'b736'b534,
5331 0xbb3a'b938'9b1a'9918,
5332 0x9f1e'9d1c'db5a'd958,
5333 0xdf5e'dd5c'bf3e'bd3c});
5334 }
5335
TEST_F(Riscv64InterpreterTest,TestVsseg4e32_vlmul1)5336 TEST_F(Riscv64InterpreterTest, TestVsseg4e32_vlmul1) {
5337 TestVssegXeXX<UInt32, 4, 1>(0x6000e427, // vsseg4e32.v v8, (x1), v0.t
5338 {0x9312'9110'8302'8100,
5339 0xb332'b130'a322'a120,
5340 0x9716'9514'8706'8504,
5341 0xb736'b534'a726'a524,
5342 0x9b1a'9918'8b0a'8908,
5343 0xbb3a'b938'ab2a'a928,
5344 0x9f1e'9d1c'8f0e'8d0c,
5345 0xbf3e'bd3c'af2e'ad2c});
5346 }
5347
TEST_F(Riscv64InterpreterTest,TestVsseg4e32_vlmul2)5348 TEST_F(Riscv64InterpreterTest, TestVsseg4e32_vlmul2) {
5349 TestVssegXeXX<UInt32, 4, 2>(0x6000e427, // vsseg4e32.v v8, (x1), v0.t
5350 {0xa322'a120'8302'8100,
5351 0xe362'e160'c342'c140,
5352 0xa726'a524'8706'8504,
5353 0xe766'e564'c746'c544,
5354 0xab2a'a928'8b0a'8908,
5355 0xeb6a'e968'cb4a'c948,
5356 0xaf2e'ad2c'8f0e'8d0c,
5357 0xef6e'ed6c'cf4e'cd4c,
5358 0xb332'b130'9312'9110,
5359 0xf372'f170'd352'd150,
5360 0xb736'b534'9716'9514,
5361 0xf776'f574'd756'd554,
5362 0xbb3a'b938'9b1a'9918,
5363 0xfb7a'f978'db5a'd958,
5364 0xbf3e'bd3c'9f1e'9d1c,
5365 0xff7e'fd7c'df5e'dd5c});
5366 }
5367
TEST_F(Riscv64InterpreterTest,TestVsseg5e32)5368 TEST_F(Riscv64InterpreterTest, TestVsseg5e32) {
5369 TestVssegXeXX<UInt32, 5, 1>(0x8000e427, // vsseg5e32.v v8, (x1), v0.t
5370 {0x9312'9110'8302'8100,
5371 0xb332'b130'a322'a120,
5372 0x8706'8504'c342'c140,
5373 0xa726'a524'9716'9514,
5374 0xc746'c544'b736'b534,
5375 0x9b1a'9918'8b0a'8908,
5376 0xbb3a'b938'ab2a'a928,
5377 0x8f0e'8d0c'cb4a'c948,
5378 0xaf2e'ad2c'9f1e'9d1c,
5379 0xcf4e'cd4c'bf3e'bd3c});
5380 }
5381
TEST_F(Riscv64InterpreterTest,TestVsseg6e32)5382 TEST_F(Riscv64InterpreterTest, TestVsseg6e32) {
5383 TestVssegXeXX<UInt32, 6, 1>(0xa000e427, // vsseg6e32.v v8, (x1), v0.t
5384 {0x9312'9110'8302'8100,
5385 0xb332'b130'a322'a120,
5386 0xd352'd150'c342'c140,
5387 0x9716'9514'8706'8504,
5388 0xb736'b534'a726'a524,
5389 0xd756'd554'c746'c544,
5390 0x9b1a'9918'8b0a'8908,
5391 0xbb3a'b938'ab2a'a928,
5392 0xdb5a'd958'cb4a'c948,
5393 0x9f1e'9d1c'8f0e'8d0c,
5394 0xbf3e'bd3c'af2e'ad2c,
5395 0xdf5e'dd5c'cf4e'cd4c});
5396 }
5397
TEST_F(Riscv64InterpreterTest,TestVsseg7e32)5398 TEST_F(Riscv64InterpreterTest, TestVsseg7e32) {
5399 TestVssegXeXX<UInt32, 7, 1>(0xc000e427, // vsseg7e32.v v8, (x1), v0.t
5400 {0x9312'9110'8302'8100,
5401 0xb332'b130'a322'a120,
5402 0xd352'd150'c342'c140,
5403 0x8706'8504'e362'e160,
5404 0xa726'a524'9716'9514,
5405 0xc746'c544'b736'b534,
5406 0xe766'e564'd756'd554,
5407 0x9b1a'9918'8b0a'8908,
5408 0xbb3a'b938'ab2a'a928,
5409 0xdb5a'd958'cb4a'c948,
5410 0x8f0e'8d0c'eb6a'e968,
5411 0xaf2e'ad2c'9f1e'9d1c,
5412 0xcf4e'cd4c'bf3e'bd3c,
5413 0xef6e'ed6c'df5e'dd5c});
5414 }
5415
TEST_F(Riscv64InterpreterTest,TestVsseg8e32)5416 TEST_F(Riscv64InterpreterTest, TestVsseg8e32) {
5417 TestVssegXeXX<UInt32, 8, 1>(0xe000e427, // vsseg8e32.v v8, (x1), v0.t
5418 {0x9312'9110'8302'8100,
5419 0xb332'b130'a322'a120,
5420 0xd352'd150'c342'c140,
5421 0xf372'f170'e362'e160,
5422 0x9716'9514'8706'8504,
5423 0xb736'b534'a726'a524,
5424 0xd756'd554'c746'c544,
5425 0xf776'f574'e766'e564,
5426 0x9b1a'9918'8b0a'8908,
5427 0xbb3a'b938'ab2a'a928,
5428 0xdb5a'd958'cb4a'c948,
5429 0xfb7a'f978'eb6a'e968,
5430 0x9f1e'9d1c'8f0e'8d0c,
5431 0xbf3e'bd3c'af2e'ad2c,
5432 0xdf5e'dd5c'cf4e'cd4c,
5433 0xff7e'fd7c'ef6e'ed6c});
5434 }
5435
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul1)5436 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul1) {
5437 TestVssegXeXX<UInt64, 1, 1>(0x000f427, // vse64.v v8, (x1), v0.t
5438 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
5439 }
5440
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul2)5441 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul2) {
5442 TestVssegXeXX<UInt64, 1, 2>(
5443 0x000f427, // vse64.v v8, (x1), v0.t
5444 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
5445 }
5446
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul4)5447 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul4) {
5448 TestVssegXeXX<UInt64, 1, 4>(0x000f427, // vse64.v v8, (x1), v0.t
5449 {0x8706'8504'8302'8100,
5450 0x8f0e'8d0c'8b0a'8908,
5451 0x9716'9514'9312'9110,
5452 0x9f1e'9d1c'9b1a'9918,
5453 0xa726'a524'a322'a120,
5454 0xaf2e'ad2c'ab2a'a928,
5455 0xb736'b534'b332'b130,
5456 0xbf3e'bd3c'bb3a'b938});
5457 }
5458
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul8)5459 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul8) {
5460 TestVssegXeXX<UInt64, 1, 8>(0x000f427, // vse64.v v8, (x1), v0.t
5461 {0x8706'8504'8302'8100,
5462 0x8f0e'8d0c'8b0a'8908,
5463 0x9716'9514'9312'9110,
5464 0x9f1e'9d1c'9b1a'9918,
5465 0xa726'a524'a322'a120,
5466 0xaf2e'ad2c'ab2a'a928,
5467 0xb736'b534'b332'b130,
5468 0xbf3e'bd3c'bb3a'b938,
5469 0xc746'c544'c342'c140,
5470 0xcf4e'cd4c'cb4a'c948,
5471 0xd756'd554'd352'd150,
5472 0xdf5e'dd5c'db5a'd958,
5473 0xe766'e564'e362'e160,
5474 0xef6e'ed6c'eb6a'e968,
5475 0xf776'f574'f372'f170,
5476 0xff7e'fd7c'fb7a'f978});
5477 }
5478
TEST_F(Riscv64InterpreterTest,TestVsseg2e64_vlmul1)5479 TEST_F(Riscv64InterpreterTest, TestVsseg2e64_vlmul1) {
5480 TestVssegXeXX<UInt64, 2, 1>(
5481 0x2000f427, // vsseg2e64.v v8, (x1), v0.t
5482 {0x8706'8504'8302'8100, 0x9716'9514'9312'9110, 0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918});
5483 }
5484
TEST_F(Riscv64InterpreterTest,TestVsseg2e64_vlmul2)5485 TEST_F(Riscv64InterpreterTest, TestVsseg2e64_vlmul2) {
5486 TestVssegXeXX<UInt64, 2, 2>(0x2000f427, // vsseg2e64.v v8, (x1), v0.t
5487 {0x8706'8504'8302'8100,
5488 0xa726'a524'a322'a120,
5489 0x8f0e'8d0c'8b0a'8908,
5490 0xaf2e'ad2c'ab2a'a928,
5491 0x9716'9514'9312'9110,
5492 0xb736'b534'b332'b130,
5493 0x9f1e'9d1c'9b1a'9918,
5494 0xbf3e'bd3c'bb3a'b938});
5495 }
5496
TEST_F(Riscv64InterpreterTest,TestVsseg2e64_vlmul4)5497 TEST_F(Riscv64InterpreterTest, TestVsseg2e64_vlmul4) {
5498 TestVssegXeXX<UInt64, 2, 4>(0x2000f427, // vsseg2e64.v v8, (x1), v0.t
5499 {0x8706'8504'8302'8100,
5500 0xc746'c544'c342'c140,
5501 0x8f0e'8d0c'8b0a'8908,
5502 0xcf4e'cd4c'cb4a'c948,
5503 0x9716'9514'9312'9110,
5504 0xd756'd554'd352'd150,
5505 0x9f1e'9d1c'9b1a'9918,
5506 0xdf5e'dd5c'db5a'd958,
5507 0xa726'a524'a322'a120,
5508 0xe766'e564'e362'e160,
5509 0xaf2e'ad2c'ab2a'a928,
5510 0xef6e'ed6c'eb6a'e968,
5511 0xb736'b534'b332'b130,
5512 0xf776'f574'f372'f170,
5513 0xbf3e'bd3c'bb3a'b938,
5514 0xff7e'fd7c'fb7a'f978});
5515 }
5516
TEST_F(Riscv64InterpreterTest,TestVsseg3e64_vlmul1)5517 TEST_F(Riscv64InterpreterTest, TestVsseg3e64_vlmul1) {
5518 TestVssegXeXX<UInt64, 3, 1>(0x4000f427, // vsseg3e64.v v8, (x1), v0.t
5519 {0x8706'8504'8302'8100,
5520 0x9716'9514'9312'9110,
5521 0xa726'a524'a322'a120,
5522 0x8f0e'8d0c'8b0a'8908,
5523 0x9f1e'9d1c'9b1a'9918,
5524 0xaf2e'ad2c'ab2a'a928});
5525 }
5526
TEST_F(Riscv64InterpreterTest,TestVsseg3e64_vlmul2)5527 TEST_F(Riscv64InterpreterTest, TestVsseg3e64_vlmul2) {
5528 TestVssegXeXX<UInt64, 3, 2>(0x4000f427, // vsseg3e64.v v8, (x1), v0.t
5529 {0x8706'8504'8302'8100,
5530 0xa726'a524'a322'a120,
5531 0xc746'c544'c342'c140,
5532 0x8f0e'8d0c'8b0a'8908,
5533 0xaf2e'ad2c'ab2a'a928,
5534 0xcf4e'cd4c'cb4a'c948,
5535 0x9716'9514'9312'9110,
5536 0xb736'b534'b332'b130,
5537 0xd756'd554'd352'd150,
5538 0x9f1e'9d1c'9b1a'9918,
5539 0xbf3e'bd3c'bb3a'b938,
5540 0xdf5e'dd5c'db5a'd958});
5541 }
5542
TEST_F(Riscv64InterpreterTest,TestVsseg4e64_vlmul1)5543 TEST_F(Riscv64InterpreterTest, TestVsseg4e64_vlmul1) {
5544 TestVssegXeXX<UInt64, 4, 1>(0x6000f427, // vsseg4e64.v v8, (x1), v0.t
5545 {0x8706'8504'8302'8100,
5546 0x9716'9514'9312'9110,
5547 0xa726'a524'a322'a120,
5548 0xb736'b534'b332'b130,
5549 0x8f0e'8d0c'8b0a'8908,
5550 0x9f1e'9d1c'9b1a'9918,
5551 0xaf2e'ad2c'ab2a'a928,
5552 0xbf3e'bd3c'bb3a'b938});
5553 }
5554
TEST_F(Riscv64InterpreterTest,TestVsseg4e64_vlmul2)5555 TEST_F(Riscv64InterpreterTest, TestVsseg4e64_vlmul2) {
5556 TestVssegXeXX<UInt64, 4, 2>(0x6000f427, // vsseg4e64.v v8, (x1), v0.t
5557 {0x8706'8504'8302'8100,
5558 0xa726'a524'a322'a120,
5559 0xc746'c544'c342'c140,
5560 0xe766'e564'e362'e160,
5561 0x8f0e'8d0c'8b0a'8908,
5562 0xaf2e'ad2c'ab2a'a928,
5563 0xcf4e'cd4c'cb4a'c948,
5564 0xef6e'ed6c'eb6a'e968,
5565 0x9716'9514'9312'9110,
5566 0xb736'b534'b332'b130,
5567 0xd756'd554'd352'd150,
5568 0xf776'f574'f372'f170,
5569 0x9f1e'9d1c'9b1a'9918,
5570 0xbf3e'bd3c'bb3a'b938,
5571 0xdf5e'dd5c'db5a'd958,
5572 0xff7e'fd7c'fb7a'f978});
5573 }
5574
TEST_F(Riscv64InterpreterTest,TestVsseg5e64)5575 TEST_F(Riscv64InterpreterTest, TestVsseg5e64) {
5576 TestVssegXeXX<UInt64, 5, 1>(0x8000f427, // vsseg5e64.v v8, (x1), v0.t
5577 {0x8706'8504'8302'8100,
5578 0x9716'9514'9312'9110,
5579 0xa726'a524'a322'a120,
5580 0xb736'b534'b332'b130,
5581 0xc746'c544'c342'c140,
5582 0x8f0e'8d0c'8b0a'8908,
5583 0x9f1e'9d1c'9b1a'9918,
5584 0xaf2e'ad2c'ab2a'a928,
5585 0xbf3e'bd3c'bb3a'b938,
5586 0xcf4e'cd4c'cb4a'c948});
5587 }
5588
TEST_F(Riscv64InterpreterTest,TestVsseg6e64)5589 TEST_F(Riscv64InterpreterTest, TestVsseg6e64) {
5590 TestVssegXeXX<UInt64, 6, 1>(0xa000f427, // vsseg6e64.v v8, (x1), v0.t
5591 {0x8706'8504'8302'8100,
5592 0x9716'9514'9312'9110,
5593 0xa726'a524'a322'a120,
5594 0xb736'b534'b332'b130,
5595 0xc746'c544'c342'c140,
5596 0xd756'd554'd352'd150,
5597 0x8f0e'8d0c'8b0a'8908,
5598 0x9f1e'9d1c'9b1a'9918,
5599 0xaf2e'ad2c'ab2a'a928,
5600 0xbf3e'bd3c'bb3a'b938,
5601 0xcf4e'cd4c'cb4a'c948,
5602 0xdf5e'dd5c'db5a'd958});
5603 }
5604
TEST_F(Riscv64InterpreterTest,TestVsseg7e64)5605 TEST_F(Riscv64InterpreterTest, TestVsseg7e64) {
5606 TestVssegXeXX<UInt64, 7, 1>(0xc000f427, // vsseg7e64.v v8, (x1), v0.t
5607 {0x8706'8504'8302'8100,
5608 0x9716'9514'9312'9110,
5609 0xa726'a524'a322'a120,
5610 0xb736'b534'b332'b130,
5611 0xc746'c544'c342'c140,
5612 0xd756'd554'd352'd150,
5613 0xe766'e564'e362'e160,
5614 0x8f0e'8d0c'8b0a'8908,
5615 0x9f1e'9d1c'9b1a'9918,
5616 0xaf2e'ad2c'ab2a'a928,
5617 0xbf3e'bd3c'bb3a'b938,
5618 0xcf4e'cd4c'cb4a'c948,
5619 0xdf5e'dd5c'db5a'd958,
5620 0xef6e'ed6c'eb6a'e968});
5621 }
5622
TEST_F(Riscv64InterpreterTest,TestVsseg8e64)5623 TEST_F(Riscv64InterpreterTest, TestVsseg8e64) {
5624 TestVssegXeXX<UInt64, 8, 1>(0xe000f427, // vsseg8e64.v v8, (x1), v0.t
5625 {0x8706'8504'8302'8100,
5626 0x9716'9514'9312'9110,
5627 0xa726'a524'a322'a120,
5628 0xb736'b534'b332'b130,
5629 0xc746'c544'c342'c140,
5630 0xd756'd554'd352'd150,
5631 0xe766'e564'e362'e160,
5632 0xf776'f574'f372'f170,
5633 0x8f0e'8d0c'8b0a'8908,
5634 0x9f1e'9d1c'9b1a'9918,
5635 0xaf2e'ad2c'ab2a'a928,
5636 0xbf3e'bd3c'bb3a'b938,
5637 0xcf4e'cd4c'cb4a'c948,
5638 0xdf5e'dd5c'db5a'd958,
5639 0xef6e'ed6c'eb6a'e968,
5640 0xff7e'fd7c'fb7a'f978});
5641 }
5642
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul1)5643 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul1) {
5644 TestVsssegXeXX<UInt8, 1, 1>(0x8208427, // vsse8.v v8, (x1), x2, v0.t
5645 4,
5646 {0x5555'5581'5555'5500,
5647 0x5555'5583'5555'5502,
5648 0x5555'5585'5555'5504,
5649 0x5555'5587'5555'5506,
5650 0x5555'5589'5555'5508,
5651 0x5555'558b'5555'550a,
5652 0x5555'558d'5555'550c,
5653 0x5555'558f'5555'550e});
5654 }
5655
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul2)5656 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul2) {
5657 TestVsssegXeXX<UInt8, 1, 2>(0x8208427, // vsse8.v v8, (x1), x2, v0.t
5658 4,
5659 {0x5555'5581'5555'5500,
5660 0x5555'5583'5555'5502,
5661 0x5555'5585'5555'5504,
5662 0x5555'5587'5555'5506,
5663 0x5555'5589'5555'5508,
5664 0x5555'558b'5555'550a,
5665 0x5555'558d'5555'550c,
5666 0x5555'558f'5555'550e,
5667 0x5555'5591'5555'5510,
5668 0x5555'5593'5555'5512,
5669 0x5555'5595'5555'5514,
5670 0x5555'5597'5555'5516,
5671 0x5555'5599'5555'5518,
5672 0x5555'559b'5555'551a,
5673 0x5555'559d'5555'551c,
5674 0x5555'559f'5555'551e});
5675 }
5676
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul4)5677 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul4) {
5678 TestVsssegXeXX<UInt8, 1, 4>(
5679 0x8208427, // vlse8.v v8, (x1), x2, v0.t
5680 4,
5681 {0x5555'5581'5555'5500, 0x5555'5583'5555'5502, 0x5555'5585'5555'5504, 0x5555'5587'5555'5506,
5682 0x5555'5589'5555'5508, 0x5555'558b'5555'550a, 0x5555'558d'5555'550c, 0x5555'558f'5555'550e,
5683 0x5555'5591'5555'5510, 0x5555'5593'5555'5512, 0x5555'5595'5555'5514, 0x5555'5597'5555'5516,
5684 0x5555'5599'5555'5518, 0x5555'559b'5555'551a, 0x5555'559d'5555'551c, 0x5555'559f'5555'551e,
5685 0x5555'55a1'5555'5520, 0x5555'55a3'5555'5522, 0x5555'55a5'5555'5524, 0x5555'55a7'5555'5526,
5686 0x5555'55a9'5555'5528, 0x5555'55ab'5555'552a, 0x5555'55ad'5555'552c, 0x5555'55af'5555'552e,
5687 0x5555'55b1'5555'5530, 0x5555'55b3'5555'5532, 0x5555'55b5'5555'5534, 0x5555'55b7'5555'5536,
5688 0x5555'55b9'5555'5538, 0x5555'55bb'5555'553a, 0x5555'55bd'5555'553c, 0x5555'55bf'5555'553e});
5689 }
5690
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul8)5691 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul8) {
5692 TestVsssegXeXX<UInt8, 1, 8>(
5693 0x8208427, // vsse8.v v8, (x1), x2, v0.t
5694 2,
5695 {0x5583'5502'5581'5500, 0x5587'5506'5585'5504, 0x558b'550a'5589'5508, 0x558f'550e'558d'550c,
5696 0x5593'5512'5591'5510, 0x5597'5516'5595'5514, 0x559b'551a'5599'5518, 0x559f'551e'559d'551c,
5697 0x55a3'5522'55a1'5520, 0x55a7'5526'55a5'5524, 0x55ab'552a'55a9'5528, 0x55af'552e'55ad'552c,
5698 0x55b3'5532'55b1'5530, 0x55b7'5536'55b5'5534, 0x55bb'553a'55b9'5538, 0x55bf'553e'55bd'553c,
5699 0x55c3'5542'55c1'5540, 0x55c7'5546'55c5'5544, 0x55cb'554a'55c9'5548, 0x55cf'554e'55cd'554c,
5700 0x55d3'5552'55d1'5550, 0x55d7'5556'55d5'5554, 0x55db'555a'55d9'5558, 0x55df'555e'55dd'555c,
5701 0x55e3'5562'55e1'5560, 0x55e7'5566'55e5'5564, 0x55eb'556a'55e9'5568, 0x55ef'556e'55ed'556c,
5702 0x55f3'5572'55f1'5570, 0x55f7'5576'55f5'5574, 0x55fb'557a'55f9'5578, 0x55ff'557e'55fd'557c});
5703 }
5704
TEST_F(Riscv64InterpreterTest,TestVssseg2e8_vlmul1)5705 TEST_F(Riscv64InterpreterTest, TestVssseg2e8_vlmul1) {
5706 TestVsssegXeXX<UInt8, 2, 1>(0x28208427, // vssseg2e8.v v8, (x1), x2, v0.t
5707 4,
5708 {0x5555'9181'5555'1000,
5709 0x5555'9383'5555'1202,
5710 0x5555'9585'5555'1404,
5711 0x5555'9787'5555'1606,
5712 0x5555'9989'5555'1808,
5713 0x5555'9b8b'5555'1a0a,
5714 0x5555'9d8d'5555'1c0c,
5715 0x5555'9f8f'5555'1e0e});
5716 }
5717
TEST_F(Riscv64InterpreterTest,TestVssseg2e8_vlmul2)5718 TEST_F(Riscv64InterpreterTest, TestVssseg2e8_vlmul2) {
5719 TestVsssegXeXX<UInt8, 2, 2>(0x28208427, // vssseg2e8.v v8, (x1), x2, v0.t
5720 4,
5721 {0x5555'a181'5555'2000,
5722 0x5555'a383'5555'2202,
5723 0x5555'a585'5555'2404,
5724 0x5555'a787'5555'2606,
5725 0x5555'a989'5555'2808,
5726 0x5555'ab8b'5555'2a0a,
5727 0x5555'ad8d'5555'2c0c,
5728 0x5555'af8f'5555'2e0e,
5729 0x5555'b191'5555'3010,
5730 0x5555'b393'5555'3212,
5731 0x5555'b595'5555'3414,
5732 0x5555'b797'5555'3616,
5733 0x5555'b999'5555'3818,
5734 0x5555'bb9b'5555'3a1a,
5735 0x5555'bd9d'5555'3c1c,
5736 0x5555'bf9f'5555'3e1e});
5737 }
5738
TEST_F(Riscv64InterpreterTest,TestVssseg2e8_vlmul4)5739 TEST_F(Riscv64InterpreterTest, TestVssseg2e8_vlmul4) {
5740 TestVsssegXeXX<UInt8, 2, 4>(
5741 0x28208427, // vssseg4e8.v v8, (x1), x2, v0.t
5742 4,
5743 {0x5555'c181'5555'4000, 0x5555'c383'5555'4202, 0x5555'c585'5555'4404, 0x5555'c787'5555'4606,
5744 0x5555'c989'5555'4808, 0x5555'cb8b'5555'4a0a, 0x5555'cd8d'5555'4c0c, 0x5555'cf8f'5555'4e0e,
5745 0x5555'd191'5555'5010, 0x5555'd393'5555'5212, 0x5555'd595'5555'5414, 0x5555'd797'5555'5616,
5746 0x5555'd999'5555'5818, 0x5555'db9b'5555'5a1a, 0x5555'dd9d'5555'5c1c, 0x5555'df9f'5555'5e1e,
5747 0x5555'e1a1'5555'6020, 0x5555'e3a3'5555'6222, 0x5555'e5a5'5555'6424, 0x5555'e7a7'5555'6626,
5748 0x5555'e9a9'5555'6828, 0x5555'ebab'5555'6a2a, 0x5555'edad'5555'6c2c, 0x5555'efaf'5555'6e2e,
5749 0x5555'f1b1'5555'7030, 0x5555'f3b3'5555'7232, 0x5555'f5b5'5555'7434, 0x5555'f7b7'5555'7636,
5750 0x5555'f9b9'5555'7838, 0x5555'fbbb'5555'7a3a, 0x5555'fdbd'5555'7c3c, 0x5555'ffbf'5555'7e3e});
5751 }
5752
TEST_F(Riscv64InterpreterTest,TestVssseg3e8_vlmul1)5753 TEST_F(Riscv64InterpreterTest, TestVssseg3e8_vlmul1) {
5754 TestVsssegXeXX<UInt8, 3, 1>(0x48208427, // vssseg3e8.v v8, (x1), x2, v0.t
5755 4,
5756 {0x55a1'9181'5520'1000,
5757 0x55a3'9383'5522'1202,
5758 0x55a5'9585'5524'1404,
5759 0x55a7'9787'5526'1606,
5760 0x55a9'9989'5528'1808,
5761 0x55ab'9b8b'552a'1a0a,
5762 0x55ad'9d8d'552c'1c0c,
5763 0x55af'9f8f'552e'1e0e});
5764 }
5765
TEST_F(Riscv64InterpreterTest,TestVssseg3e8_vlmul2)5766 TEST_F(Riscv64InterpreterTest, TestVssseg3e8_vlmul2) {
5767 TestVsssegXeXX<UInt8, 3, 2>(0x48208427, // vssseg3e8.v v8, (x1), x2, v0.t
5768 4,
5769 {0x55c1'a181'5540'2000,
5770 0x55c3'a383'5542'2202,
5771 0x55c5'a585'5544'2404,
5772 0x55c7'a787'5546'2606,
5773 0x55c9'a989'5548'2808,
5774 0x55cb'ab8b'554a'2a0a,
5775 0x55cd'ad8d'554c'2c0c,
5776 0x55cf'af8f'554e'2e0e,
5777 0x55d1'b191'5550'3010,
5778 0x55d3'b393'5552'3212,
5779 0x55d5'b595'5554'3414,
5780 0x55d7'b797'5556'3616,
5781 0x55d9'b999'5558'3818,
5782 0x55db'bb9b'555a'3a1a,
5783 0x55dd'bd9d'555c'3c1c,
5784 0x55df'bf9f'555e'3e1e});
5785 }
5786
TEST_F(Riscv64InterpreterTest,TestVssseg4e8_vlmul1)5787 TEST_F(Riscv64InterpreterTest, TestVssseg4e8_vlmul1) {
5788 TestVsssegXeXX<UInt8, 4, 1>(0x68208427, // vssseg4e8.v v8, (x1), x2, v0.t
5789 4,
5790 {0xb1a1'9181'3020'1000,
5791 0xb3a3'9383'3222'1202,
5792 0xb5a5'9585'3424'1404,
5793 0xb7a7'9787'3626'1606,
5794 0xb9a9'9989'3828'1808,
5795 0xbbab'9b8b'3a2a'1a0a,
5796 0xbdad'9d8d'3c2c'1c0c,
5797 0xbfaf'9f8f'3e2e'1e0e});
5798 }
5799
TEST_F(Riscv64InterpreterTest,TestVssseg4e8_vlmul2)5800 TEST_F(Riscv64InterpreterTest, TestVssseg4e8_vlmul2) {
5801 TestVsssegXeXX<UInt8, 4, 2>(0x68208427, // vssseg4e8.v v8, (x1), x2, v0.t
5802 4,
5803 {0xe1c1'a181'6040'2000,
5804 0xe3c3'a383'6242'2202,
5805 0xe5c5'a585'6444'2404,
5806 0xe7c7'a787'6646'2606,
5807 0xe9c9'a989'6848'2808,
5808 0xebcb'ab8b'6a4a'2a0a,
5809 0xedcd'ad8d'6c4c'2c0c,
5810 0xefcf'af8f'6e4e'2e0e,
5811 0xf1d1'b191'7050'3010,
5812 0xf3d3'b393'7252'3212,
5813 0xf5d5'b595'7454'3414,
5814 0xf7d7'b797'7656'3616,
5815 0xf9d9'b999'7858'3818,
5816 0xfbdb'bb9b'7a5a'3a1a,
5817 0xfddd'bd9d'7c5c'3c1c,
5818 0xffdf'bf9f'7e5e'3e1e});
5819 }
5820
TEST_F(Riscv64InterpreterTest,TestVssseg5e8)5821 TEST_F(Riscv64InterpreterTest, TestVssseg5e8) {
5822 TestVsssegXeXX<UInt8, 5, 1>(0x88208427, // vssseg5e8.v v8, (x1), x2, v0.t
5823 8,
5824 {0x5555'5540'3020'1000,
5825 0x5555'55c1'b1a1'9181,
5826 0x5555'5542'3222'1202,
5827 0x5555'55c3'b3a3'9383,
5828 0x5555'5544'3424'1404,
5829 0x5555'55c5'b5a5'9585,
5830 0x5555'5546'3626'1606,
5831 0x5555'55c7'b7a7'9787,
5832 0x5555'5548'3828'1808,
5833 0x5555'55c9'b9a9'9989,
5834 0x5555'554a'3a2a'1a0a,
5835 0x5555'55cb'bbab'9b8b,
5836 0x5555'554c'3c2c'1c0c,
5837 0x5555'55cd'bdad'9d8d,
5838 0x5555'554e'3e2e'1e0e,
5839 0x5555'55cf'bfaf'9f8f});
5840 }
5841
TEST_F(Riscv64InterpreterTest,TestVssseg6e8)5842 TEST_F(Riscv64InterpreterTest, TestVssseg6e8) {
5843 TestVsssegXeXX<UInt8, 6, 1>(0xa8208427, // vssseg6e8.v v8, (x1), x2, v0.t
5844 8,
5845 {0x5555'5040'3020'1000,
5846 0x5555'd1c1'b1a1'9181,
5847 0x5555'5242'3222'1202,
5848 0x5555'd3c3'b3a3'9383,
5849 0x5555'5444'3424'1404,
5850 0x5555'd5c5'b5a5'9585,
5851 0x5555'5646'3626'1606,
5852 0x5555'd7c7'b7a7'9787,
5853 0x5555'5848'3828'1808,
5854 0x5555'd9c9'b9a9'9989,
5855 0x5555'5a4a'3a2a'1a0a,
5856 0x5555'dbcb'bbab'9b8b,
5857 0x5555'5c4c'3c2c'1c0c,
5858 0x5555'ddcd'bdad'9d8d,
5859 0x5555'5e4e'3e2e'1e0e,
5860 0x5555'dfcf'bfaf'9f8f});
5861 }
5862
TEST_F(Riscv64InterpreterTest,TestVssseg7e8)5863 TEST_F(Riscv64InterpreterTest, TestVssseg7e8) {
5864 TestVsssegXeXX<UInt8, 7, 1>(0xc8208427, // vssseg7e8.v v8, (x1), x2, v0.t
5865 8,
5866 {0x5560'5040'3020'1000,
5867 0x55e1'd1c1'b1a1'9181,
5868 0x5562'5242'3222'1202,
5869 0x55e3'd3c3'b3a3'9383,
5870 0x5564'5444'3424'1404,
5871 0x55e5'd5c5'b5a5'9585,
5872 0x5566'5646'3626'1606,
5873 0x55e7'd7c7'b7a7'9787,
5874 0x5568'5848'3828'1808,
5875 0x55e9'd9c9'b9a9'9989,
5876 0x556a'5a4a'3a2a'1a0a,
5877 0x55eb'dbcb'bbab'9b8b,
5878 0x556c'5c4c'3c2c'1c0c,
5879 0x55ed'ddcd'bdad'9d8d,
5880 0x556e'5e4e'3e2e'1e0e,
5881 0x55ef'dfcf'bfaf'9f8f});
5882 }
5883
TEST_F(Riscv64InterpreterTest,TestVssseg8e8)5884 TEST_F(Riscv64InterpreterTest, TestVssseg8e8) {
5885 TestVsssegXeXX<UInt8, 8, 1>(0xe8208427, // vssseg8e8.v v8, (x1), x2, v0.t
5886 8,
5887 {0x7060'5040'3020'1000,
5888 0xf1e1'd1c1'b1a1'9181,
5889 0x7262'5242'3222'1202,
5890 0xf3e3'd3c3'b3a3'9383,
5891 0x7464'5444'3424'1404,
5892 0xf5e5'd5c5'b5a5'9585,
5893 0x7666'5646'3626'1606,
5894 0xf7e7'd7c7'b7a7'9787,
5895 0x7868'5848'3828'1808,
5896 0xf9e9'd9c9'b9a9'9989,
5897 0x7a6a'5a4a'3a2a'1a0a,
5898 0xfbeb'dbcb'bbab'9b8b,
5899 0x7c6c'5c4c'3c2c'1c0c,
5900 0xfded'ddcd'bdad'9d8d,
5901 0x7e6e'5e4e'3e2e'1e0e,
5902 0xffef'dfcf'bfaf'9f8f});
5903 }
5904
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul1)5905 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul1) {
5906 TestVsssegXeXX<UInt16, 1, 1>(0x820d427, // vsse16.v v8, (x1), x2, v0.t
5907 8,
5908 {0x5555'5555'5555'8100,
5909 0x5555'5555'5555'8302,
5910 0x5555'5555'5555'8504,
5911 0x5555'5555'5555'8706,
5912 0x5555'5555'5555'8908,
5913 0x5555'5555'5555'8b0a,
5914 0x5555'5555'5555'8d0c,
5915 0x5555'5555'5555'8f0e});
5916 }
5917
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul2)5918 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul2) {
5919 TestVsssegXeXX<UInt16, 1, 2>(0x820d427, // vsse16.v v8, (x1), x2, v0.t
5920 8,
5921 {0x5555'5555'5555'8100,
5922 0x5555'5555'5555'8302,
5923 0x5555'5555'5555'8504,
5924 0x5555'5555'5555'8706,
5925 0x5555'5555'5555'8908,
5926 0x5555'5555'5555'8b0a,
5927 0x5555'5555'5555'8d0c,
5928 0x5555'5555'5555'8f0e,
5929 0x5555'5555'5555'9110,
5930 0x5555'5555'5555'9312,
5931 0x5555'5555'5555'9514,
5932 0x5555'5555'5555'9716,
5933 0x5555'5555'5555'9918,
5934 0x5555'5555'5555'9b1a,
5935 0x5555'5555'5555'9d1c,
5936 0x5555'5555'5555'9f1e});
5937 }
5938
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul4)5939 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul4) {
5940 TestVsssegXeXX<UInt16, 1, 4>(
5941 0x820d427, // vsse16.v v8, (x1), x2, v0.t
5942 8,
5943 {0x5555'5555'5555'8100, 0x5555'5555'5555'8302, 0x5555'5555'5555'8504, 0x5555'5555'5555'8706,
5944 0x5555'5555'5555'8908, 0x5555'5555'5555'8b0a, 0x5555'5555'5555'8d0c, 0x5555'5555'5555'8f0e,
5945 0x5555'5555'5555'9110, 0x5555'5555'5555'9312, 0x5555'5555'5555'9514, 0x5555'5555'5555'9716,
5946 0x5555'5555'5555'9918, 0x5555'5555'5555'9b1a, 0x5555'5555'5555'9d1c, 0x5555'5555'5555'9f1e,
5947 0x5555'5555'5555'a120, 0x5555'5555'5555'a322, 0x5555'5555'5555'a524, 0x5555'5555'5555'a726,
5948 0x5555'5555'5555'a928, 0x5555'5555'5555'ab2a, 0x5555'5555'5555'ad2c, 0x5555'5555'5555'af2e,
5949 0x5555'5555'5555'b130, 0x5555'5555'5555'b332, 0x5555'5555'5555'b534, 0x5555'5555'5555'b736,
5950 0x5555'5555'5555'b938, 0x5555'5555'5555'bb3a, 0x5555'5555'5555'bd3c, 0x5555'5555'5555'bf3e});
5951 }
5952
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul8)5953 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul8) {
5954 TestVsssegXeXX<UInt16, 1, 8>(
5955 0x820d427, // vsse16.v v8, (x1), x2, v0.t
5956 4,
5957 {0x5555'8302'5555'8100, 0x5555'8706'5555'8504, 0x5555'8b0a'5555'8908, 0x5555'8f0e'5555'8d0c,
5958 0x5555'9312'5555'9110, 0x5555'9716'5555'9514, 0x5555'9b1a'5555'9918, 0x5555'9f1e'5555'9d1c,
5959 0x5555'a322'5555'a120, 0x5555'a726'5555'a524, 0x5555'ab2a'5555'a928, 0x5555'af2e'5555'ad2c,
5960 0x5555'b332'5555'b130, 0x5555'b736'5555'b534, 0x5555'bb3a'5555'b938, 0x5555'bf3e'5555'bd3c,
5961 0x5555'c342'5555'c140, 0x5555'c746'5555'c544, 0x5555'cb4a'5555'c948, 0x5555'cf4e'5555'cd4c,
5962 0x5555'd352'5555'd150, 0x5555'd756'5555'd554, 0x5555'db5a'5555'd958, 0x5555'df5e'5555'dd5c,
5963 0x5555'e362'5555'e160, 0x5555'e766'5555'e564, 0x5555'eb6a'5555'e968, 0x5555'ef6e'5555'ed6c,
5964 0x5555'f372'5555'f170, 0x5555'f776'5555'f574, 0x5555'fb7a'5555'f978, 0x5555'ff7e'5555'fd7c});
5965 }
5966
TEST_F(Riscv64InterpreterTest,TestVssseg2e16_vlmul1)5967 TEST_F(Riscv64InterpreterTest, TestVssseg2e16_vlmul1) {
5968 TestVsssegXeXX<UInt16, 2, 1>(0x2820d427, // vssseg2e16.v v8, (x1), x2, v0.t
5969 8,
5970 {0x5555'5555'9110'8100,
5971 0x5555'5555'9312'8302,
5972 0x5555'5555'9514'8504,
5973 0x5555'5555'9716'8706,
5974 0x5555'5555'9918'8908,
5975 0x5555'5555'9b1a'8b0a,
5976 0x5555'5555'9d1c'8d0c,
5977 0x5555'5555'9f1e'8f0e});
5978 }
5979
TEST_F(Riscv64InterpreterTest,TestVssseg2e16_vlmul2)5980 TEST_F(Riscv64InterpreterTest, TestVssseg2e16_vlmul2) {
5981 TestVsssegXeXX<UInt16, 2, 2>(0x2820d427, // vssseg2e16.v v8, (x1), x2, v0.t
5982 8,
5983 {0x5555'5555'a120'8100,
5984 0x5555'5555'a322'8302,
5985 0x5555'5555'a524'8504,
5986 0x5555'5555'a726'8706,
5987 0x5555'5555'a928'8908,
5988 0x5555'5555'ab2a'8b0a,
5989 0x5555'5555'ad2c'8d0c,
5990 0x5555'5555'af2e'8f0e,
5991 0x5555'5555'b130'9110,
5992 0x5555'5555'b332'9312,
5993 0x5555'5555'b534'9514,
5994 0x5555'5555'b736'9716,
5995 0x5555'5555'b938'9918,
5996 0x5555'5555'bb3a'9b1a,
5997 0x5555'5555'bd3c'9d1c,
5998 0x5555'5555'bf3e'9f1e});
5999 }
6000
TEST_F(Riscv64InterpreterTest,TestVssseg2e16_vlmul4)6001 TEST_F(Riscv64InterpreterTest, TestVssseg2e16_vlmul4) {
6002 TestVsssegXeXX<UInt16, 2, 4>(
6003 0x2820d427, // vssseg2e16.v v8, (x1), x2, v0.t
6004 8,
6005 {0x5555'5555'c140'8100, 0x5555'5555'c342'8302, 0x5555'5555'c544'8504, 0x5555'5555'c746'8706,
6006 0x5555'5555'c948'8908, 0x5555'5555'cb4a'8b0a, 0x5555'5555'cd4c'8d0c, 0x5555'5555'cf4e'8f0e,
6007 0x5555'5555'd150'9110, 0x5555'5555'd352'9312, 0x5555'5555'd554'9514, 0x5555'5555'd756'9716,
6008 0x5555'5555'd958'9918, 0x5555'5555'db5a'9b1a, 0x5555'5555'dd5c'9d1c, 0x5555'5555'df5e'9f1e,
6009 0x5555'5555'e160'a120, 0x5555'5555'e362'a322, 0x5555'5555'e564'a524, 0x5555'5555'e766'a726,
6010 0x5555'5555'e968'a928, 0x5555'5555'eb6a'ab2a, 0x5555'5555'ed6c'ad2c, 0x5555'5555'ef6e'af2e,
6011 0x5555'5555'f170'b130, 0x5555'5555'f372'b332, 0x5555'5555'f574'b534, 0x5555'5555'f776'b736,
6012 0x5555'5555'f978'b938, 0x5555'5555'fb7a'bb3a, 0x5555'5555'fd7c'bd3c, 0x5555'5555'ff7e'bf3e});
6013 }
6014
TEST_F(Riscv64InterpreterTest,TestVssseg3e16_vlmul1)6015 TEST_F(Riscv64InterpreterTest, TestVssseg3e16_vlmul1) {
6016 TestVsssegXeXX<UInt16, 3, 1>(0x4820d427, // vssseg3e16.v v8, (x1), x2, v0.t
6017 8,
6018 {0x5555'a120'9110'8100,
6019 0x5555'a322'9312'8302,
6020 0x5555'a524'9514'8504,
6021 0x5555'a726'9716'8706,
6022 0x5555'a928'9918'8908,
6023 0x5555'ab2a'9b1a'8b0a,
6024 0x5555'ad2c'9d1c'8d0c,
6025 0x5555'af2e'9f1e'8f0e});
6026 }
6027
TEST_F(Riscv64InterpreterTest,TestVssseg3e16_vlmul2)6028 TEST_F(Riscv64InterpreterTest, TestVssseg3e16_vlmul2) {
6029 TestVsssegXeXX<UInt16, 3, 2>(0x4820d427, // vssseg3e16.v v8, (x1), x2, v0.t
6030 8,
6031 {0x5555'c140'a120'8100,
6032 0x5555'c342'a322'8302,
6033 0x5555'c544'a524'8504,
6034 0x5555'c746'a726'8706,
6035 0x5555'c948'a928'8908,
6036 0x5555'cb4a'ab2a'8b0a,
6037 0x5555'cd4c'ad2c'8d0c,
6038 0x5555'cf4e'af2e'8f0e,
6039 0x5555'd150'b130'9110,
6040 0x5555'd352'b332'9312,
6041 0x5555'd554'b534'9514,
6042 0x5555'd756'b736'9716,
6043 0x5555'd958'b938'9918,
6044 0x5555'db5a'bb3a'9b1a,
6045 0x5555'dd5c'bd3c'9d1c,
6046 0x5555'df5e'bf3e'9f1e});
6047 }
6048
TEST_F(Riscv64InterpreterTest,TestVssseg4e16_vlmul1)6049 TEST_F(Riscv64InterpreterTest, TestVssseg4e16_vlmul1) {
6050 TestVsssegXeXX<UInt16, 4, 1>(0x6820d427, // vssseg4e16.v v8, (x1), x2, v0.t
6051 8,
6052 {0xb130'a120'9110'8100,
6053 0xb332'a322'9312'8302,
6054 0xb534'a524'9514'8504,
6055 0xb736'a726'9716'8706,
6056 0xb938'a928'9918'8908,
6057 0xbb3a'ab2a'9b1a'8b0a,
6058 0xbd3c'ad2c'9d1c'8d0c,
6059 0xbf3e'af2e'9f1e'8f0e});
6060 }
6061
TEST_F(Riscv64InterpreterTest,TestVssseg4e16_vlmul2)6062 TEST_F(Riscv64InterpreterTest, TestVssseg4e16_vlmul2) {
6063 TestVsssegXeXX<UInt16, 4, 2>(0x6820d427, // vssseg4e16.v v8, (x1), x2, v0.t
6064 8,
6065 {0xe160'c140'a120'8100,
6066 0xe362'c342'a322'8302,
6067 0xe564'c544'a524'8504,
6068 0xe766'c746'a726'8706,
6069 0xe968'c948'a928'8908,
6070 0xeb6a'cb4a'ab2a'8b0a,
6071 0xed6c'cd4c'ad2c'8d0c,
6072 0xef6e'cf4e'af2e'8f0e,
6073 0xf170'd150'b130'9110,
6074 0xf372'd352'b332'9312,
6075 0xf574'd554'b534'9514,
6076 0xf776'd756'b736'9716,
6077 0xf978'd958'b938'9918,
6078 0xfb7a'db5a'bb3a'9b1a,
6079 0xfd7c'dd5c'bd3c'9d1c,
6080 0xff7e'df5e'bf3e'9f1e});
6081 }
6082
TEST_F(Riscv64InterpreterTest,TestVssseg5e16)6083 TEST_F(Riscv64InterpreterTest, TestVssseg5e16) {
6084 TestVsssegXeXX<UInt16, 5, 1>(0x8820d427, // vssseg5e16.v v8, (x1), x2, v0.t
6085 16,
6086 {0xb130'a120'9110'8100,
6087 0x5555'5555'5555'c140,
6088 0xb332'a322'9312'8302,
6089 0x5555'5555'5555'c342,
6090 0xb534'a524'9514'8504,
6091 0x5555'5555'5555'c544,
6092 0xb736'a726'9716'8706,
6093 0x5555'5555'5555'c746,
6094 0xb938'a928'9918'8908,
6095 0x5555'5555'5555'c948,
6096 0xbb3a'ab2a'9b1a'8b0a,
6097 0x5555'5555'5555'cb4a,
6098 0xbd3c'ad2c'9d1c'8d0c,
6099 0x5555'5555'5555'cd4c,
6100 0xbf3e'af2e'9f1e'8f0e,
6101 0x5555'5555'5555'cf4e});
6102 }
6103
TEST_F(Riscv64InterpreterTest,TestVssseg6e16)6104 TEST_F(Riscv64InterpreterTest, TestVssseg6e16) {
6105 TestVsssegXeXX<UInt16, 6, 1>(0xa820d427, // vssseg6e16.v v8, (x1), x2, v0.t
6106 16,
6107 {0xb130'a120'9110'8100,
6108 0x5555'5555'd150'c140,
6109 0xb332'a322'9312'8302,
6110 0x5555'5555'd352'c342,
6111 0xb534'a524'9514'8504,
6112 0x5555'5555'd554'c544,
6113 0xb736'a726'9716'8706,
6114 0x5555'5555'd756'c746,
6115 0xb938'a928'9918'8908,
6116 0x5555'5555'd958'c948,
6117 0xbb3a'ab2a'9b1a'8b0a,
6118 0x5555'5555'db5a'cb4a,
6119 0xbd3c'ad2c'9d1c'8d0c,
6120 0x5555'5555'dd5c'cd4c,
6121 0xbf3e'af2e'9f1e'8f0e,
6122 0x5555'5555'df5e'cf4e});
6123 }
6124
TEST_F(Riscv64InterpreterTest,TestVssseg7e16)6125 TEST_F(Riscv64InterpreterTest, TestVssseg7e16) {
6126 TestVsssegXeXX<UInt16, 7, 1>(0xc820d427, // vssseg7e16.v v8, (x1), x2, v0.t
6127 16,
6128 {0xb130'a120'9110'8100,
6129 0x5555'e160'd150'c140,
6130 0xb332'a322'9312'8302,
6131 0x5555'e362'd352'c342,
6132 0xb534'a524'9514'8504,
6133 0x5555'e564'd554'c544,
6134 0xb736'a726'9716'8706,
6135 0x5555'e766'd756'c746,
6136 0xb938'a928'9918'8908,
6137 0x5555'e968'd958'c948,
6138 0xbb3a'ab2a'9b1a'8b0a,
6139 0x5555'eb6a'db5a'cb4a,
6140 0xbd3c'ad2c'9d1c'8d0c,
6141 0x5555'ed6c'dd5c'cd4c,
6142 0xbf3e'af2e'9f1e'8f0e,
6143 0x5555'ef6e'df5e'cf4e});
6144 }
6145
TEST_F(Riscv64InterpreterTest,TestVssseg8e16)6146 TEST_F(Riscv64InterpreterTest, TestVssseg8e16) {
6147 TestVsssegXeXX<UInt16, 8, 1>(0xe820d427, // vssseg8e16.v v8, (x1), x2, v0.t
6148 16,
6149 {0xb130'a120'9110'8100,
6150 0xf170'e160'd150'c140,
6151 0xb332'a322'9312'8302,
6152 0xf372'e362'd352'c342,
6153 0xb534'a524'9514'8504,
6154 0xf574'e564'd554'c544,
6155 0xb736'a726'9716'8706,
6156 0xf776'e766'd756'c746,
6157 0xb938'a928'9918'8908,
6158 0xf978'e968'd958'c948,
6159 0xbb3a'ab2a'9b1a'8b0a,
6160 0xfb7a'eb6a'db5a'cb4a,
6161 0xbd3c'ad2c'9d1c'8d0c,
6162 0xfd7c'ed6c'dd5c'cd4c,
6163 0xbf3e'af2e'9f1e'8f0e,
6164 0xff7e'ef6e'df5e'cf4e});
6165 }
6166
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul1)6167 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul1) {
6168 TestVsssegXeXX<UInt32, 1, 1>(0x820e427, // vsse32.v v8, (x1), x2, v0.t
6169 16,
6170 {0x5555'5555'8302'8100,
6171 0x5555'5555'5555'5555,
6172 0x5555'5555'8706'8504,
6173 0x5555'5555'5555'5555,
6174 0x5555'5555'8b0a'8908,
6175 0x5555'5555'5555'5555,
6176 0x5555'5555'8f0e'8d0c});
6177 }
6178
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul2)6179 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul2) {
6180 TestVsssegXeXX<UInt32, 1, 2>(0x820e427, // vsse32.v v8, (x1), x2, v0.t
6181 16,
6182 {0x5555'5555'8302'8100,
6183 0x5555'5555'5555'5555,
6184 0x5555'5555'8706'8504,
6185 0x5555'5555'5555'5555,
6186 0x5555'5555'8b0a'8908,
6187 0x5555'5555'5555'5555,
6188 0x5555'5555'8f0e'8d0c,
6189 0x5555'5555'5555'5555,
6190 0x5555'5555'9312'9110,
6191 0x5555'5555'5555'5555,
6192 0x5555'5555'9716'9514,
6193 0x5555'5555'5555'5555,
6194 0x5555'5555'9b1a'9918,
6195 0x5555'5555'5555'5555,
6196 0x5555'5555'9f1e'9d1c});
6197 }
6198
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul4)6199 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul4) {
6200 TestVsssegXeXX<UInt32, 1, 4>(
6201 0x820e427, // vsse32.v v8, (x1), x2, v0.t
6202 16,
6203 {0x5555'5555'8302'8100, 0x5555'5555'5555'5555, 0x5555'5555'8706'8504, 0x5555'5555'5555'5555,
6204 0x5555'5555'8b0a'8908, 0x5555'5555'5555'5555, 0x5555'5555'8f0e'8d0c, 0x5555'5555'5555'5555,
6205 0x5555'5555'9312'9110, 0x5555'5555'5555'5555, 0x5555'5555'9716'9514, 0x5555'5555'5555'5555,
6206 0x5555'5555'9b1a'9918, 0x5555'5555'5555'5555, 0x5555'5555'9f1e'9d1c, 0x5555'5555'5555'5555,
6207 0x5555'5555'a322'a120, 0x5555'5555'5555'5555, 0x5555'5555'a726'a524, 0x5555'5555'5555'5555,
6208 0x5555'5555'ab2a'a928, 0x5555'5555'5555'5555, 0x5555'5555'af2e'ad2c, 0x5555'5555'5555'5555,
6209 0x5555'5555'b332'b130, 0x5555'5555'5555'5555, 0x5555'5555'b736'b534, 0x5555'5555'5555'5555,
6210 0x5555'5555'bb3a'b938, 0x5555'5555'5555'5555, 0x5555'5555'bf3e'bd3c});
6211 }
6212
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul8)6213 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul8) {
6214 TestVsssegXeXX<UInt32, 1, 8>(
6215 0x820e427, // vsse32.v v8, (x1), x2, v0.t
6216 8,
6217 {0x5555'5555'8302'8100, 0x5555'5555'8706'8504, 0x5555'5555'8b0a'8908, 0x5555'5555'8f0e'8d0c,
6218 0x5555'5555'9312'9110, 0x5555'5555'9716'9514, 0x5555'5555'9b1a'9918, 0x5555'5555'9f1e'9d1c,
6219 0x5555'5555'a322'a120, 0x5555'5555'a726'a524, 0x5555'5555'ab2a'a928, 0x5555'5555'af2e'ad2c,
6220 0x5555'5555'b332'b130, 0x5555'5555'b736'b534, 0x5555'5555'bb3a'b938, 0x5555'5555'bf3e'bd3c,
6221 0x5555'5555'c342'c140, 0x5555'5555'c746'c544, 0x5555'5555'cb4a'c948, 0x5555'5555'cf4e'cd4c,
6222 0x5555'5555'd352'd150, 0x5555'5555'd756'd554, 0x5555'5555'db5a'd958, 0x5555'5555'df5e'dd5c,
6223 0x5555'5555'e362'e160, 0x5555'5555'e766'e564, 0x5555'5555'eb6a'e968, 0x5555'5555'ef6e'ed6c,
6224 0x5555'5555'f372'f170, 0x5555'5555'f776'f574, 0x5555'5555'fb7a'f978, 0x5555'5555'ff7e'fd7c});
6225 }
6226
TEST_F(Riscv64InterpreterTest,TestVssseg2e32_vlmul1)6227 TEST_F(Riscv64InterpreterTest, TestVssseg2e32_vlmul1) {
6228 TestVsssegXeXX<UInt32, 2, 1>(0x2820e427, // vssseg2e32.v v8, (x1), x2, v0.t
6229 16,
6230 {0x9312'9110'8302'8100,
6231 0x5555'5555'5555'5555,
6232 0x9716'9514'8706'8504,
6233 0x5555'5555'5555'5555,
6234 0x9b1a'9918'8b0a'8908,
6235 0x5555'5555'5555'5555,
6236 0x9f1e'9d1c'8f0e'8d0c});
6237 }
6238
TEST_F(Riscv64InterpreterTest,TestVssseg2e32_vlmul2)6239 TEST_F(Riscv64InterpreterTest, TestVssseg2e32_vlmul2) {
6240 TestVsssegXeXX<UInt32, 2, 2>(0x2820e427, // vssseg2e32.v v8, (x1), x2, v0.t
6241 16,
6242 {0xa322'a120'8302'8100,
6243 0x5555'5555'5555'5555,
6244 0xa726'a524'8706'8504,
6245 0x5555'5555'5555'5555,
6246 0xab2a'a928'8b0a'8908,
6247 0x5555'5555'5555'5555,
6248 0xaf2e'ad2c'8f0e'8d0c,
6249 0x5555'5555'5555'5555,
6250 0xb332'b130'9312'9110,
6251 0x5555'5555'5555'5555,
6252 0xb736'b534'9716'9514,
6253 0x5555'5555'5555'5555,
6254 0xbb3a'b938'9b1a'9918,
6255 0x5555'5555'5555'5555,
6256 0xbf3e'bd3c'9f1e'9d1c});
6257 }
6258
TEST_F(Riscv64InterpreterTest,TestVssseg2e32_vlmul4)6259 TEST_F(Riscv64InterpreterTest, TestVssseg2e32_vlmul4) {
6260 TestVsssegXeXX<UInt32, 2, 4>(
6261 0x2820e427, // vssseg2e32.v v8, (x1), x2, v0.t
6262 16,
6263 {0xc342'c140'8302'8100, 0x5555'5555'5555'5555, 0xc746'c544'8706'8504, 0x5555'5555'5555'5555,
6264 0xcb4a'c948'8b0a'8908, 0x5555'5555'5555'5555, 0xcf4e'cd4c'8f0e'8d0c, 0x5555'5555'5555'5555,
6265 0xd352'd150'9312'9110, 0x5555'5555'5555'5555, 0xd756'd554'9716'9514, 0x5555'5555'5555'5555,
6266 0xdb5a'd958'9b1a'9918, 0x5555'5555'5555'5555, 0xdf5e'dd5c'9f1e'9d1c, 0x5555'5555'5555'5555,
6267 0xe362'e160'a322'a120, 0x5555'5555'5555'5555, 0xe766'e564'a726'a524, 0x5555'5555'5555'5555,
6268 0xeb6a'e968'ab2a'a928, 0x5555'5555'5555'5555, 0xef6e'ed6c'af2e'ad2c, 0x5555'5555'5555'5555,
6269 0xf372'f170'b332'b130, 0x5555'5555'5555'5555, 0xf776'f574'b736'b534, 0x5555'5555'5555'5555,
6270 0xfb7a'f978'bb3a'b938, 0x5555'5555'5555'5555, 0xff7e'fd7c'bf3e'bd3c});
6271 }
6272
TEST_F(Riscv64InterpreterTest,TestVssseg3e32_vlmul1)6273 TEST_F(Riscv64InterpreterTest, TestVssseg3e32_vlmul1) {
6274 TestVsssegXeXX<UInt32, 3, 1>(0x4820e427, // vssseg3e32.v v8, (x1), x2, v0.t
6275 16,
6276 {0x9312'9110'8302'8100,
6277 0x5555'5555'a322'a120,
6278 0x9716'9514'8706'8504,
6279 0x5555'5555'a726'a524,
6280 0x9b1a'9918'8b0a'8908,
6281 0x5555'5555'ab2a'a928,
6282 0x9f1e'9d1c'8f0e'8d0c,
6283 0x5555'5555'af2e'ad2c});
6284 }
6285
TEST_F(Riscv64InterpreterTest,TestVssseg3e32_vlmul2)6286 TEST_F(Riscv64InterpreterTest, TestVssseg3e32_vlmul2) {
6287 TestVsssegXeXX<UInt32, 3, 2>(0x4820e427, // vssseg3e32.v v8, (x1), x2, v0.t
6288 16,
6289 {0xa322'a120'8302'8100,
6290 0x5555'5555'c342'c140,
6291 0xa726'a524'8706'8504,
6292 0x5555'5555'c746'c544,
6293 0xab2a'a928'8b0a'8908,
6294 0x5555'5555'cb4a'c948,
6295 0xaf2e'ad2c'8f0e'8d0c,
6296 0x5555'5555'cf4e'cd4c,
6297 0xb332'b130'9312'9110,
6298 0x5555'5555'd352'd150,
6299 0xb736'b534'9716'9514,
6300 0x5555'5555'd756'd554,
6301 0xbb3a'b938'9b1a'9918,
6302 0x5555'5555'db5a'd958,
6303 0xbf3e'bd3c'9f1e'9d1c,
6304 0x5555'5555'df5e'dd5c});
6305 }
6306
TEST_F(Riscv64InterpreterTest,TestVssseg4e32_vlmul1)6307 TEST_F(Riscv64InterpreterTest, TestVssseg4e32_vlmul1) {
6308 TestVsssegXeXX<UInt32, 4, 1>(0x6820e427, // vssseg4e32.v v8, (x1), x2, v0.t
6309 16,
6310 {0x9312'9110'8302'8100,
6311 0xb332'b130'a322'a120,
6312 0x9716'9514'8706'8504,
6313 0xb736'b534'a726'a524,
6314 0x9b1a'9918'8b0a'8908,
6315 0xbb3a'b938'ab2a'a928,
6316 0x9f1e'9d1c'8f0e'8d0c,
6317 0xbf3e'bd3c'af2e'ad2c});
6318 }
6319
TEST_F(Riscv64InterpreterTest,TestVssseg4e32_vlmul2)6320 TEST_F(Riscv64InterpreterTest, TestVssseg4e32_vlmul2) {
6321 TestVsssegXeXX<UInt32, 4, 2>(0x6820e427, // vssseg4e32.v v8, (x1), x2, v0.t
6322 16,
6323 {0xa322'a120'8302'8100,
6324 0xe362'e160'c342'c140,
6325 0xa726'a524'8706'8504,
6326 0xe766'e564'c746'c544,
6327 0xab2a'a928'8b0a'8908,
6328 0xeb6a'e968'cb4a'c948,
6329 0xaf2e'ad2c'8f0e'8d0c,
6330 0xef6e'ed6c'cf4e'cd4c,
6331 0xb332'b130'9312'9110,
6332 0xf372'f170'd352'd150,
6333 0xb736'b534'9716'9514,
6334 0xf776'f574'd756'd554,
6335 0xbb3a'b938'9b1a'9918,
6336 0xfb7a'f978'db5a'd958,
6337 0xbf3e'bd3c'9f1e'9d1c,
6338 0xff7e'fd7c'df5e'dd5c});
6339 }
6340
TEST_F(Riscv64InterpreterTest,TestVssseg5e32)6341 TEST_F(Riscv64InterpreterTest, TestVssseg5e32) {
6342 TestVsssegXeXX<UInt32, 5, 1>(0x8820e427, // vssseg5e32.v v8, (x1), x2, v0.t
6343 32,
6344 {0x9312'9110'8302'8100,
6345 0xb332'b130'a322'a120,
6346 0x5555'5555'c342'c140,
6347 0x5555'5555'5555'5555,
6348 0x9716'9514'8706'8504,
6349 0xb736'b534'a726'a524,
6350 0x5555'5555'c746'c544,
6351 0x5555'5555'5555'5555,
6352 0x9b1a'9918'8b0a'8908,
6353 0xbb3a'b938'ab2a'a928,
6354 0x5555'5555'cb4a'c948,
6355 0x5555'5555'5555'5555,
6356 0x9f1e'9d1c'8f0e'8d0c,
6357 0xbf3e'bd3c'af2e'ad2c,
6358 0x5555'5555'cf4e'cd4c});
6359 }
6360
TEST_F(Riscv64InterpreterTest,TestVssseg6e32)6361 TEST_F(Riscv64InterpreterTest, TestVssseg6e32) {
6362 TestVsssegXeXX<UInt32, 6, 1>(0xa820e427, // vssseg6e32.v v8, (x1), x2, v0.t
6363 32,
6364 {0x9312'9110'8302'8100,
6365 0xb332'b130'a322'a120,
6366 0xd352'd150'c342'c140,
6367 0x5555'5555'5555'5555,
6368 0x9716'9514'8706'8504,
6369 0xb736'b534'a726'a524,
6370 0xd756'd554'c746'c544,
6371 0x5555'5555'5555'5555,
6372 0x9b1a'9918'8b0a'8908,
6373 0xbb3a'b938'ab2a'a928,
6374 0xdb5a'd958'cb4a'c948,
6375 0x5555'5555'5555'5555,
6376 0x9f1e'9d1c'8f0e'8d0c,
6377 0xbf3e'bd3c'af2e'ad2c,
6378 0xdf5e'dd5c'cf4e'cd4c});
6379 }
6380
TEST_F(Riscv64InterpreterTest,TestVssseg7e32)6381 TEST_F(Riscv64InterpreterTest, TestVssseg7e32) {
6382 TestVsssegXeXX<UInt32, 7, 1>(0xc820e427, // vssseg7e32.v v8, (x1), x2, v0.t
6383 32,
6384 {0x9312'9110'8302'8100,
6385 0xb332'b130'a322'a120,
6386 0xd352'd150'c342'c140,
6387 0x5555'5555'e362'e160,
6388 0x9716'9514'8706'8504,
6389 0xb736'b534'a726'a524,
6390 0xd756'd554'c746'c544,
6391 0x5555'5555'e766'e564,
6392 0x9b1a'9918'8b0a'8908,
6393 0xbb3a'b938'ab2a'a928,
6394 0xdb5a'd958'cb4a'c948,
6395 0x5555'5555'eb6a'e968,
6396 0x9f1e'9d1c'8f0e'8d0c,
6397 0xbf3e'bd3c'af2e'ad2c,
6398 0xdf5e'dd5c'cf4e'cd4c,
6399 0x5555'5555'ef6e'ed6c});
6400 }
6401
TEST_F(Riscv64InterpreterTest,TestVssseg8e32)6402 TEST_F(Riscv64InterpreterTest, TestVssseg8e32) {
6403 TestVsssegXeXX<UInt32, 8, 1>(0xe820e427, // vssseg8e32.v v8, (x1), x2, v0.t
6404 32,
6405 {0x9312'9110'8302'8100,
6406 0xb332'b130'a322'a120,
6407 0xd352'd150'c342'c140,
6408 0xf372'f170'e362'e160,
6409 0x9716'9514'8706'8504,
6410 0xb736'b534'a726'a524,
6411 0xd756'd554'c746'c544,
6412 0xf776'f574'e766'e564,
6413 0x9b1a'9918'8b0a'8908,
6414 0xbb3a'b938'ab2a'a928,
6415 0xdb5a'd958'cb4a'c948,
6416 0xfb7a'f978'eb6a'e968,
6417 0x9f1e'9d1c'8f0e'8d0c,
6418 0xbf3e'bd3c'af2e'ad2c,
6419 0xdf5e'dd5c'cf4e'cd4c,
6420 0xff7e'fd7c'ef6e'ed6c});
6421 }
6422
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul1)6423 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul1) {
6424 TestVsssegXeXX<UInt64, 1, 1>(0x820f427, // vsse64.v v8, (x1), x2, v0.t
6425 32,
6426 {0x8706'8504'8302'8100,
6427 0x5555'5555'5555'5555,
6428 0x5555'5555'5555'5555,
6429 0x5555'5555'5555'5555,
6430 0x8f0e'8d0c'8b0a'8908});
6431 }
6432
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul2)6433 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul2) {
6434 TestVsssegXeXX<UInt64, 1, 2>(0x820f427, // vsse64.v v8, (x1), x2, v0.t
6435 32,
6436 {0x8706'8504'8302'8100,
6437 0x5555'5555'5555'5555,
6438 0x5555'5555'5555'5555,
6439 0x5555'5555'5555'5555,
6440 0x8f0e'8d0c'8b0a'8908,
6441 0x5555'5555'5555'5555,
6442 0x5555'5555'5555'5555,
6443 0x5555'5555'5555'5555,
6444 0x9716'9514'9312'9110,
6445 0x5555'5555'5555'5555,
6446 0x5555'5555'5555'5555,
6447 0x5555'5555'5555'5555,
6448 0x9f1e'9d1c'9b1a'9918});
6449 }
6450
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul4)6451 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul4) {
6452 TestVsssegXeXX<UInt64, 1, 4>(
6453 0x820f427, // vsse64.v v8, (x1), x2, v0.t
6454 32,
6455 {0x8706'8504'8302'8100, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6456 0x8f0e'8d0c'8b0a'8908, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6457 0x9716'9514'9312'9110, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6458 0x9f1e'9d1c'9b1a'9918, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6459 0xa726'a524'a322'a120, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6460 0xaf2e'ad2c'ab2a'a928, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6461 0xb736'b534'b332'b130, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6462 0xbf3e'bd3c'bb3a'b938});
6463 }
6464
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul8)6465 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul8) {
6466 TestVsssegXeXX<UInt64, 1, 8>(
6467 0x820f427, // vsse64.v v8, (x1), x2, v0.t
6468 16,
6469 {0x8706'8504'8302'8100, 0x5555'5555'5555'5555, 0x8f0e'8d0c'8b0a'8908, 0x5555'5555'5555'5555,
6470 0x9716'9514'9312'9110, 0x5555'5555'5555'5555, 0x9f1e'9d1c'9b1a'9918, 0x5555'5555'5555'5555,
6471 0xa726'a524'a322'a120, 0x5555'5555'5555'5555, 0xaf2e'ad2c'ab2a'a928, 0x5555'5555'5555'5555,
6472 0xb736'b534'b332'b130, 0x5555'5555'5555'5555, 0xbf3e'bd3c'bb3a'b938, 0x5555'5555'5555'5555,
6473 0xc746'c544'c342'c140, 0x5555'5555'5555'5555, 0xcf4e'cd4c'cb4a'c948, 0x5555'5555'5555'5555,
6474 0xd756'd554'd352'd150, 0x5555'5555'5555'5555, 0xdf5e'dd5c'db5a'd958, 0x5555'5555'5555'5555,
6475 0xe766'e564'e362'e160, 0x5555'5555'5555'5555, 0xef6e'ed6c'eb6a'e968, 0x5555'5555'5555'5555,
6476 0xf776'f574'f372'f170, 0x5555'5555'5555'5555, 0xff7e'fd7c'fb7a'f978});
6477 }
6478
TEST_F(Riscv64InterpreterTest,TestVssseg2e64_vlmul1)6479 TEST_F(Riscv64InterpreterTest, TestVssseg2e64_vlmul1) {
6480 TestVsssegXeXX<UInt64, 2, 1>(0x2820f427, // vssseg2e64.v v8, (x1), x2, v0.t
6481 32,
6482 {0x8706'8504'8302'8100,
6483 0x9716'9514'9312'9110,
6484 0x5555'5555'5555'5555,
6485 0x5555'5555'5555'5555,
6486 0x8f0e'8d0c'8b0a'8908,
6487 0x9f1e'9d1c'9b1a'9918});
6488 }
6489
TEST_F(Riscv64InterpreterTest,TestVssseg2e64_vlmul2)6490 TEST_F(Riscv64InterpreterTest, TestVssseg2e64_vlmul2) {
6491 TestVsssegXeXX<UInt64, 2, 2>(0x2820f427, // vssseg2e64.v v8, (x1), x2, v0.t
6492 32,
6493 {0x8706'8504'8302'8100,
6494 0xa726'a524'a322'a120,
6495 0x5555'5555'5555'5555,
6496 0x5555'5555'5555'5555,
6497 0x8f0e'8d0c'8b0a'8908,
6498 0xaf2e'ad2c'ab2a'a928,
6499 0x5555'5555'5555'5555,
6500 0x5555'5555'5555'5555,
6501 0x9716'9514'9312'9110,
6502 0xb736'b534'b332'b130,
6503 0x5555'5555'5555'5555,
6504 0x5555'5555'5555'5555,
6505 0x9f1e'9d1c'9b1a'9918,
6506 0xbf3e'bd3c'bb3a'b938});
6507 }
6508
TEST_F(Riscv64InterpreterTest,TestVssseg2e64_vlmul4)6509 TEST_F(Riscv64InterpreterTest, TestVssseg2e64_vlmul4) {
6510 TestVsssegXeXX<UInt64, 2, 4>(0x2820f427, // vssseg2e64.v v8, (x1), x2, v0.t
6511 16,
6512 {0x8706'8504'8302'8100,
6513 0xc746'c544'c342'c140,
6514 0x8f0e'8d0c'8b0a'8908,
6515 0xcf4e'cd4c'cb4a'c948,
6516 0x9716'9514'9312'9110,
6517 0xd756'd554'd352'd150,
6518 0x9f1e'9d1c'9b1a'9918,
6519 0xdf5e'dd5c'db5a'd958,
6520 0xa726'a524'a322'a120,
6521 0xe766'e564'e362'e160,
6522 0xaf2e'ad2c'ab2a'a928,
6523 0xef6e'ed6c'eb6a'e968,
6524 0xb736'b534'b332'b130,
6525 0xf776'f574'f372'f170,
6526 0xbf3e'bd3c'bb3a'b938,
6527 0xff7e'fd7c'fb7a'f978});
6528 }
6529
TEST_F(Riscv64InterpreterTest,TestVssseg3e64_vlmul1)6530 TEST_F(Riscv64InterpreterTest, TestVssseg3e64_vlmul1) {
6531 TestVsssegXeXX<UInt64, 3, 1>(0x4820f427, // vssseg3e64.v v8, (x1), x2, v0.t
6532 32,
6533 {0x8706'8504'8302'8100,
6534 0x9716'9514'9312'9110,
6535 0xa726'a524'a322'a120,
6536 0x5555'5555'5555'5555,
6537 0x8f0e'8d0c'8b0a'8908,
6538 0x9f1e'9d1c'9b1a'9918,
6539 0xaf2e'ad2c'ab2a'a928});
6540 }
6541
TEST_F(Riscv64InterpreterTest,TestVssseg3e64_vlmul2)6542 TEST_F(Riscv64InterpreterTest, TestVssseg3e64_vlmul2) {
6543 TestVsssegXeXX<UInt64, 3, 2>(0x4820f427, // vssseg3e64.v v8, (x1), x2, v0.t
6544 32,
6545 {0x8706'8504'8302'8100,
6546 0xa726'a524'a322'a120,
6547 0xc746'c544'c342'c140,
6548 0x5555'5555'5555'5555,
6549 0x8f0e'8d0c'8b0a'8908,
6550 0xaf2e'ad2c'ab2a'a928,
6551 0xcf4e'cd4c'cb4a'c948,
6552 0x5555'5555'5555'5555,
6553 0x9716'9514'9312'9110,
6554 0xb736'b534'b332'b130,
6555 0xd756'd554'd352'd150,
6556 0x5555'5555'5555'5555,
6557 0x9f1e'9d1c'9b1a'9918,
6558 0xbf3e'bd3c'bb3a'b938,
6559 0xdf5e'dd5c'db5a'd958});
6560 }
6561
TEST_F(Riscv64InterpreterTest,TestVssseg4e64_vlmul1)6562 TEST_F(Riscv64InterpreterTest, TestVssseg4e64_vlmul1) {
6563 TestVsssegXeXX<UInt64, 4, 1>(0x6820f427, // vssseg4e64.v v8, (x1), x2, v0.t
6564 32,
6565 {0x8706'8504'8302'8100,
6566 0x9716'9514'9312'9110,
6567 0xa726'a524'a322'a120,
6568 0xb736'b534'b332'b130,
6569 0x8f0e'8d0c'8b0a'8908,
6570 0x9f1e'9d1c'9b1a'9918,
6571 0xaf2e'ad2c'ab2a'a928,
6572 0xbf3e'bd3c'bb3a'b938});
6573 }
6574
TEST_F(Riscv64InterpreterTest,TestVssseg4e64_vlmul2)6575 TEST_F(Riscv64InterpreterTest, TestVssseg4e64_vlmul2) {
6576 TestVsssegXeXX<UInt64, 4, 2>(0x6820f427, // vssseg4e64.v v8, (x1), x2, v0.t
6577 32,
6578 {0x8706'8504'8302'8100,
6579 0xa726'a524'a322'a120,
6580 0xc746'c544'c342'c140,
6581 0xe766'e564'e362'e160,
6582 0x8f0e'8d0c'8b0a'8908,
6583 0xaf2e'ad2c'ab2a'a928,
6584 0xcf4e'cd4c'cb4a'c948,
6585 0xef6e'ed6c'eb6a'e968,
6586 0x9716'9514'9312'9110,
6587 0xb736'b534'b332'b130,
6588 0xd756'd554'd352'd150,
6589 0xf776'f574'f372'f170,
6590 0x9f1e'9d1c'9b1a'9918,
6591 0xbf3e'bd3c'bb3a'b938,
6592 0xdf5e'dd5c'db5a'd958,
6593 0xff7e'fd7c'fb7a'f978});
6594 }
6595
TEST_F(Riscv64InterpreterTest,TestVssseg5e64)6596 TEST_F(Riscv64InterpreterTest, TestVssseg5e64) {
6597 TestVsssegXeXX<UInt64, 5, 1>(0x8820f427, // vssseg5e64.v v8, (x1), x2, v0.t
6598 64,
6599 {0x8706'8504'8302'8100,
6600 0x9716'9514'9312'9110,
6601 0xa726'a524'a322'a120,
6602 0xb736'b534'b332'b130,
6603 0xc746'c544'c342'c140,
6604 0x5555'5555'5555'5555,
6605 0x5555'5555'5555'5555,
6606 0x5555'5555'5555'5555,
6607 0x8f0e'8d0c'8b0a'8908,
6608 0x9f1e'9d1c'9b1a'9918,
6609 0xaf2e'ad2c'ab2a'a928,
6610 0xbf3e'bd3c'bb3a'b938,
6611 0xcf4e'cd4c'cb4a'c948});
6612 }
6613
TEST_F(Riscv64InterpreterTest,TestVssseg6e64)6614 TEST_F(Riscv64InterpreterTest, TestVssseg6e64) {
6615 TestVsssegXeXX<UInt64, 6, 1>(0xa820f427, // vssseg6e64.v v8, (x1), x2, v0.t
6616 64,
6617 {0x8706'8504'8302'8100,
6618 0x9716'9514'9312'9110,
6619 0xa726'a524'a322'a120,
6620 0xb736'b534'b332'b130,
6621 0xc746'c544'c342'c140,
6622 0xd756'd554'd352'd150,
6623 0x5555'5555'5555'5555,
6624 0x5555'5555'5555'5555,
6625 0x8f0e'8d0c'8b0a'8908,
6626 0x9f1e'9d1c'9b1a'9918,
6627 0xaf2e'ad2c'ab2a'a928,
6628 0xbf3e'bd3c'bb3a'b938,
6629 0xcf4e'cd4c'cb4a'c948,
6630 0xdf5e'dd5c'db5a'd958});
6631 }
6632
TEST_F(Riscv64InterpreterTest,TestVssseg7e64)6633 TEST_F(Riscv64InterpreterTest, TestVssseg7e64) {
6634 TestVsssegXeXX<UInt64, 7, 1>(0xc820f427, // vssseg7e64.v v8, (x1), x2, v0.t
6635 64,
6636 {0x8706'8504'8302'8100,
6637 0x9716'9514'9312'9110,
6638 0xa726'a524'a322'a120,
6639 0xb736'b534'b332'b130,
6640 0xc746'c544'c342'c140,
6641 0xd756'd554'd352'd150,
6642 0xe766'e564'e362'e160,
6643 0x5555'5555'5555'5555,
6644 0x8f0e'8d0c'8b0a'8908,
6645 0x9f1e'9d1c'9b1a'9918,
6646 0xaf2e'ad2c'ab2a'a928,
6647 0xbf3e'bd3c'bb3a'b938,
6648 0xcf4e'cd4c'cb4a'c948,
6649 0xdf5e'dd5c'db5a'd958,
6650 0xef6e'ed6c'eb6a'e968});
6651 }
6652
TEST_F(Riscv64InterpreterTest,TestVssseg8e64)6653 TEST_F(Riscv64InterpreterTest, TestVssseg8e64) {
6654 TestVsssegXeXX<UInt64, 8, 1>(0xe820f427, // vssseg8e64.v v8, (x1), x2, v0.t
6655 64,
6656 {0x8706'8504'8302'8100,
6657 0x9716'9514'9312'9110,
6658 0xa726'a524'a322'a120,
6659 0xb736'b534'b332'b130,
6660 0xc746'c544'c342'c140,
6661 0xd756'd554'd352'd150,
6662 0xe766'e564'e362'e160,
6663 0xf776'f574'f372'f170,
6664 0x8f0e'8d0c'8b0a'8908,
6665 0x9f1e'9d1c'9b1a'9918,
6666 0xaf2e'ad2c'ab2a'a928,
6667 0xbf3e'bd3c'bb3a'b938,
6668 0xcf4e'cd4c'cb4a'c948,
6669 0xdf5e'dd5c'db5a'd958,
6670 0xef6e'ed6c'eb6a'e968,
6671 0xff7e'fd7c'fb7a'f978});
6672 }
6673
TEST_F(Riscv64InterpreterTest,TestVsm)6674 TEST_F(Riscv64InterpreterTest, TestVsm) {
6675 TestVsm(0x2b08427, // vsm.v v8, (x1)
6676 {0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143});
6677 }
6678
TEST_F(Riscv64InterpreterTest,TestVectorMaskInstructions)6679 TEST_F(Riscv64InterpreterTest, TestVectorMaskInstructions) {
6680 TestVectorMaskInstruction(128,
6681 intrinsics::InactiveProcessing::kAgnostic,
6682 0x630c2457, // vmandn.mm v8, v16, v24
6683 {0x8102'8504'8102'8100, 0x8102'8504'890a'8908});
6684 TestVectorMaskInstruction(128,
6685 intrinsics::InactiveProcessing::kAgnostic,
6686 0x670c2457, // vmand.mm v8, v16, v24
6687 {0x0604'0000'0200'0000, 0x0e0c'0808'0200'0000});
6688 TestVectorMaskInstruction(128,
6689 intrinsics::InactiveProcessing::kAgnostic,
6690 0x6b0c2457, // vmor.mm v8, v16, v24
6691 {0x8f0e'8f0d'8706'8300, 0x9f1e'9f1c'9f1e'9b19});
6692 TestVectorMaskInstruction(128,
6693 intrinsics::InactiveProcessing::kAgnostic,
6694 0x6f0c2457, // vmxor.mm v8, v16, v24
6695 {0x890a'8f0d'8506'8300, 0x9112'9714'9d1e'9b19});
6696 TestVectorMaskInstruction(128,
6697 intrinsics::InactiveProcessing::kAgnostic,
6698 0x730c2457, // vmorn.mm v8, v16, v24
6699 {0xf7f7'f5f6'fbfb'fdff, 0xefef'edef'ebeb'edee});
6700 TestVectorMaskInstruction(128,
6701 intrinsics::InactiveProcessing::kAgnostic,
6702 0x770c2457, // vmnand.mm v8, v16, v24
6703 {0xf9fb'ffff'fdff'ffff, 0xf1f3'f7f7'fdff'ffff});
6704 TestVectorMaskInstruction(128,
6705 intrinsics::InactiveProcessing::kAgnostic,
6706 0x7b0c2457, // vmnor.mm v8, v16, v24
6707 {0x70f1'70f2'78f9'7cff, 0x60e1'60e3'60e1'64e6});
6708 TestVectorMaskInstruction(128,
6709 intrinsics::InactiveProcessing::kAgnostic,
6710 0x7f0c2457, // vmxnor.mm v8, v16, v24
6711 {0x76f5'70f2'7af9'7cff, 0x6eed'68eb'62e1'64e6});
6712 TestVectorMaskInstruction(0,
6713 intrinsics::InactiveProcessing::kAgnostic,
6714 0x5300a457, // vmsbf.m v8, v16
6715 {0x0000'0000'0000'00ff, 0x0000'0000'0000'0000});
6716 TestVectorMaskInstruction(0,
6717 intrinsics::InactiveProcessing::kAgnostic,
6718 0x53012457, // vmsof.m v8, v16
6719 {0x0000'0000'0000'0100, 0x0000'0000'0000'0000});
6720 TestVectorMaskInstruction(0,
6721 intrinsics::InactiveProcessing::kAgnostic,
6722 0x5301a457, // vmsif.m v8, v16
6723 {0x0000'0000'0000'01ff, 0x0000'0000'0000'0000});
6724 TestVectorMaskInstruction(0,
6725 intrinsics::InactiveProcessing::kAgnostic,
6726 0x5100a457, // vmsbf.m v8, v16, v0.t
6727 {0xd5ad'd6b5'adff'ffff, 0x6af7'57bb'deed'7bb5});
6728 TestVectorMaskInstruction(0,
6729 intrinsics::InactiveProcessing::kAgnostic,
6730 0x51012457, // vmsof.m v8, v16, v0.t
6731 {0xd5ad'd6b5'af6b'b5ad, 0x6af7'57bb'deed'7bb5});
6732 TestVectorMaskInstruction(0,
6733 intrinsics::InactiveProcessing::kAgnostic,
6734 0x5101a457, // vmsif.m v8, v16, v0.t
6735 {0xd5ad'd6b5'afff'ffff, 0x6af7'57bb'deed'7bb5});
6736 TestVectorMaskInstruction(0,
6737 intrinsics::InactiveProcessing::kUndisturbed,
6738 0x5100a457, // vmsbf.m v8, v16, v0.t
6739 {0x5505'5415'05d5'5f57, 0x4055'5511'5445'5115});
6740 TestVectorMaskInstruction(0,
6741 intrinsics::InactiveProcessing::kUndisturbed,
6742 0x51012457, // vmsof.m v8, v16, v0.t
6743 {0x5505'5415'0741'1505, 0x4055'5511'5445'5115});
6744 TestVectorMaskInstruction(0,
6745 intrinsics::InactiveProcessing::kUndisturbed,
6746 0x5101a457, // vmsif.m v8, v16, v0.t
6747 {0x5505'5415'07d5'5f57, 0x4055'5511'5445'5115});
6748 }
6749
TEST_F(Riscv64InterpreterTest,TestVmseq)6750 TEST_F(Riscv64InterpreterTest, TestVmseq) {
6751 TestVectorMaskTargetInstruction(0x610c0457, // Vmseq.vv v8, v16, v24, v0.t
6752 {255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
6753 0x0000'0000'0000'00ff,
6754 0x0000'000f,
6755 0x0003,
6756 kVectorComparisonSource);
6757 TestVectorMaskTargetInstruction(0x6100c457, // Vmseq.vx v8, v16, x1, v0.t
6758 {0, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0},
6759 0x0000'0000'0f00'0000,
6760 0x0000'3000,
6761 0x0040,
6762 kVectorComparisonSource);
6763 TestVectorMaskTargetInstruction(0x610ab457, // Vmseq.vi v8, v16, -0xb, v0.t
6764 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 85, 0, 0, 0, 0},
6765 0x0000'f000'0000'0000,
6766 0x0000'0000,
6767 0x0000,
6768 kVectorComparisonSource);
6769 }
6770
TEST_F(Riscv64InterpreterTest,TestVmfne)6771 TEST_F(Riscv64InterpreterTest, TestVmfne) {
6772 TestVectorMaskTargetInstruction(0x710c1457, // Vmfne.vv v8, v16, v24, v0.t
6773 0xffff'fff8,
6774 0xfffe,
6775 kVectorComparisonSource);
6776 TestVectorMaskTargetInstruction(0x7100d457, // Vmfne.vf v8, v16, f1, v0.t
6777 0xffff'ffbf,
6778 0xffdf,
6779 kVectorComparisonSource);
6780 }
6781
TEST_F(Riscv64InterpreterTest,TestVmsne)6782 TEST_F(Riscv64InterpreterTest, TestVmsne) {
6783 TestVectorMaskTargetInstruction(
6784 0x650c0457, // Vmsne.vv v8, v16, v24, v0.t
6785 {0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
6786 0xffff'ffff'ffff'ff00,
6787 0xffff'fff0,
6788 0xfffc,
6789 kVectorComparisonSource);
6790 TestVectorMaskTargetInstruction(
6791 0x6500c457, // Vmsne.vx v8, v16, x1, v0.t
6792 {255, 255, 255, 255, 255, 255, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255},
6793 0xffff'ffff'f0ff'ffff,
6794 0xffff'cfff,
6795 0xffbf,
6796 kVectorComparisonSource);
6797 TestVectorMaskTargetInstruction(
6798 0x650ab457, // Vmsne.vi v8, v16, -0xb, v0.t
6799 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 170, 255, 255, 255, 255},
6800 0xffff'0fff'ffff'ffff,
6801 0xffff'ffff,
6802 0xffff,
6803 kVectorComparisonSource);
6804 }
6805
TEST_F(Riscv64InterpreterTest,TestVmflt)6806 TEST_F(Riscv64InterpreterTest, TestVmflt) {
6807 TestVectorMaskTargetInstruction(0x6d0c1457, // Vmflt.vv v8, v16, v24, v0.t
6808 0x0000'f000,
6809 0x00c0,
6810 kVectorComparisonSource);
6811 TestVectorMaskTargetInstruction(0x6d00d457, // Vmflt.vf v8, v16, f1, v0.t
6812 0xff00'ff07,
6813 0xf0d1,
6814 kVectorComparisonSource);
6815 }
6816
TEST_F(Riscv64InterpreterTest,TestVmsltu)6817 TEST_F(Riscv64InterpreterTest, TestVmsltu) {
6818 TestVectorMaskTargetInstruction(0x690c0457, // Vmsltu.vv v8, v16, v24, v0.t
6819 {0, 0, 0, 3, 255, 255, 0, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6820 0xffff'0000'f0ff'1000,
6821 0xff00'cf00,
6822 0xf0b0,
6823 kVectorComparisonSource);
6824 TestVectorMaskTargetInstruction(
6825 0x6900c457, // Vmsltu.vx v8, v16, x1, v0.t
6826 {85, 15, 10, 11, 255, 255, 0, 255, 0, 0, 0, 0, 136, 136, 255, 255},
6827 0xffaa'0000'f0ff'3330,
6828 0xff00'cf54,
6829 0xf0b0,
6830 kVectorComparisonSource);
6831 }
6832
TEST_F(Riscv64InterpreterTest,TestVmslt)6833 TEST_F(Riscv64InterpreterTest, TestVmslt) {
6834 TestVectorMaskTargetInstruction(0x6d0c0457, // Vmslt.vv v8, v16, v24, v0.t
6835 {0, 0, 245, 247, 0, 32, 255, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6836 0xffff'0000'ff40'dc00,
6837 0xff00'f0a0,
6838 0xf0cc,
6839 kVectorComparisonSource);
6840 TestVectorMaskTargetInstruction(0x6d00c457, // Vmslt.vx v8, v16, x1, v0.t
6841 {0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 136, 136, 255, 255},
6842 0xffaa'0000'0040'0000,
6843 0xff00'0000,
6844 0xf000,
6845 kVectorComparisonSource);
6846 }
6847
TEST_F(Riscv64InterpreterTest,TestVmfle)6848 TEST_F(Riscv64InterpreterTest, TestVmfle) {
6849 TestVectorMaskTargetInstruction(0x650c1457, // Vmfle.vv v8, v16, v24, v0.t
6850 0x0000'f007,
6851 0x00c1,
6852 kVectorComparisonSource);
6853 TestVectorMaskTargetInstruction(0x6500d457, // Vmfle.vf v8, v16, f1, v0.t
6854 0xff00'ff47,
6855 0xf0f1,
6856 kVectorComparisonSource);
6857 }
6858
TEST_F(Riscv64InterpreterTest,TestVmsleu)6859 TEST_F(Riscv64InterpreterTest, TestVmsleu) {
6860 TestVectorMaskTargetInstruction(
6861 0x710c0457, // Vmsleu.vv v8, v16, v24, v0.t
6862 {255, 255, 0, 3, 255, 255, 0, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6863 0xffff'0000'f0ff'10ff,
6864 0xff00'cf0f,
6865 0xf0b3,
6866 kVectorComparisonSource);
6867 TestVectorMaskTargetInstruction(
6868 0x7100c457, // Vmsleu.vx v8, v16, x1, v0.t
6869 {85, 15, 10, 11, 255, 255, 255, 255, 0, 0, 0, 0, 136, 136, 255, 255},
6870 0xffaa'0000'ffff'3330,
6871 0xff00'ff54,
6872 0xf0f0,
6873 kVectorComparisonSource);
6874 TestVectorMaskTargetInstruction(
6875 0x710ab457, // Vmsleu.vi v8, v16, -0xb, v0.t
6876 {255, 15, 15, 15, 255, 255, 255, 255, 85, 0, 5, 85, 255, 255, 255, 255},
6877 0xffff'f30f'ffff'333f,
6878 0xffff'ff57,
6879 0xffff,
6880 kVectorComparisonSource);
6881 }
6882
TEST_F(Riscv64InterpreterTest,TestVmsle)6883 TEST_F(Riscv64InterpreterTest, TestVmsle) {
6884 TestVectorMaskTargetInstruction(
6885 0x750c0457, // Vmsle.vv v8, v16, v24, v0.t
6886 {255, 255, 245, 247, 0, 32, 255, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6887 0xffff'0000'ff40'dcff,
6888 0xff00'f0af,
6889 0xf0cf,
6890 kVectorComparisonSource);
6891 TestVectorMaskTargetInstruction(0x7500c457, // Vmsle.vx v8, v16, x1, v0.t
6892 {0, 0, 0, 0, 0, 32, 255, 0, 0, 0, 0, 0, 136, 136, 255, 255},
6893 0xffaa'0000'0f40'0000,
6894 0xff00'3000,
6895 0xf040,
6896 kVectorComparisonSource);
6897 TestVectorMaskTargetInstruction(0x750ab457, // Vmsle.vi v8, v16, -0xb
6898 {170, 0, 5, 4, 0, 32, 255, 0, 85, 0, 5, 85, 255, 255, 255, 255},
6899 0xffff'f30f'0f40'000f,
6900 0xffff'3003,
6901 0xff4f,
6902 kVectorComparisonSource);
6903 }
6904
TEST_F(Riscv64InterpreterTest,TestVmfgt)6905 TEST_F(Riscv64InterpreterTest, TestVmfgt) {
6906 TestVectorMaskTargetInstruction(0x7500d457, // Vmfgt.vf v8, v16, f1, v0.t
6907 0x0000'0010,
6908 0x0000,
6909 kVectorComparisonSource);
6910 }
6911
TEST_F(Riscv64InterpreterTest,TestVmsgtu)6912 TEST_F(Riscv64InterpreterTest, TestVmsgtu) {
6913 TestVectorMaskTargetInstruction(
6914 0x7900c457, // Vmsgtu.vx v8, v16, x1, v0.t
6915 {170, 240, 245, 244, 0, 0, 0, 0, 255, 255, 255, 255, 119, 119, 0, 0},
6916 0x0055'ffff'0000'cccf,
6917 0x00ff'00ab,
6918 0x0f0f,
6919 kVectorComparisonSource);
6920 TestVectorMaskTargetInstruction(0x790ab457, // Vmsgtu.vi v8, v16, -0xb, v0.t
6921 {0, 240, 240, 240, 0, 0, 0, 0, 170, 255, 250, 170, 0, 0, 0, 0},
6922 0x0000'0cf0'0000'ccc0,
6923 0x0000'00a8,
6924 0x0000,
6925 kVectorComparisonSource);
6926 }
6927
TEST_F(Riscv64InterpreterTest,TestVmsgt)6928 TEST_F(Riscv64InterpreterTest, TestVmsgt) {
6929 TestVectorMaskTargetInstruction(
6930 0x7d00c457, // Vmsgt.vx v8, v16, x1, v0.t
6931 {255, 255, 255, 255, 255, 223, 0, 255, 255, 255, 255, 255, 119, 119, 0, 0},
6932 0x0055'ffff'f0bf'ffff,
6933 0x00ff'cfff,
6934 0x0fbf,
6935 kVectorComparisonSource);
6936 TestVectorMaskTargetInstruction(
6937 0x7d0ab457, // Vmsgt.vi v8, v16, -0xb, v0.t
6938 {85, 255, 250, 251, 255, 223, 0, 255, 170, 255, 250, 170, 0, 0, 0, 0},
6939 0x0000'0cf0'f0bf'fff0,
6940 0x0000'cffc,
6941 0x00b0,
6942 kVectorComparisonSource);
6943 }
6944
TEST_F(Riscv64InterpreterTest,TestVmfge)6945 TEST_F(Riscv64InterpreterTest, TestVmfge) {
6946 TestVectorMaskTargetInstruction(0x7d00d457, // Vmfge.vf v8, v16, f1, v0.t
6947 0x0000'0050,
6948 0x0020,
6949 kVectorComparisonSource);
6950 }
6951
TEST_F(Riscv64InterpreterTest,TestVfmacc)6952 TEST_F(Riscv64InterpreterTest, TestVfmacc) {
6953 TestVectorFloatInstruction(0xb1881457, // vfmacc.vv v8, v16, v24, v0.t
6954 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6955 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6956 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6957 {0x6a1f'cefd, 0x7629'21c4, 0x6232'9db4, 0x6e3c'70f9},
6958 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6959 {0x5555'5551, 0xd66b'bbc8, 0x5555'5555, 0x5555'5037},
6960 {0xfaad'fde4, 0xff80'0000, 0xf2c2'c69a, 0xfecd'99e3},
6961 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
6962 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6963 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6964 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6965 {0x75b4'9040'f9f1'ea75, 0x6dcb'c6d1'12f0'a99b},
6966 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6967 {0xd614'2330'4af7'4c90, 0x5555'5555'5555'5555},
6968 {0xfff0'0000'0000'0000, 0xfe5b'5815'60f1'ac51},
6969 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
6970 kVectorCalculationsSource);
6971 TestVectorFloatInstruction(0xb100d457, // vfmacc.vf v8, f1, v16, v0.t
6972 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6973 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6974 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6975 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6976 {0x5555'5555, 0x5555'5555, 0x5555'550e, 0x5555'0ca1},
6977 {0x550b'37bf, 0xd895'6354, 0xdc99'df27, 0xe09c'b3a3},
6978 {0xe49f'8677, 0xe8a2'594a, 0xeca5'2c1d, 0xf0a7'fef0},
6979 {0xf4aa'd1c3, 0xf8ad'a496, 0xfcb0'7768, 0xff80'0000}},
6980 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6981 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6982 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6983 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6984 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6985 {0xd780'0dff'a493'9082, 0xdf85'b3a5'4a3b'e0d2},
6986 {0xe790'194a'efe1'8677, 0xef95'bef0'9587'2c1d},
6987 {0xf7a0'2496'3b2c'd1c3, 0xffa5'ca3b'e0d2'7768}},
6988 kVectorCalculationsSource);
6989 }
6990
TEST_F(Riscv64InterpreterTest,TestVfnmacc)6991 TEST_F(Riscv64InterpreterTest, TestVfnmacc) {
6992 TestVectorFloatInstruction(0xb5881457, // vfnmacc.vv v8, v16, v24, v0.t
6993 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
6994 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
6995 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
6996 {0xea1f'cefd, 0xf629'21c4, 0xe232'9db4, 0xee3c'70f9},
6997 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
6998 {0xd555'5551, 0x566b'bbc8, 0xd555'5555, 0xd555'5037},
6999 {0x7aad'fde4, 0x7f80'0000, 0x72c2'c69a, 0x7ecd'99e3},
7000 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7001 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7002 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7003 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7004 {0xf5b4'9040'f9f1'ea75, 0xedcb'c6d1'12f0'a99b},
7005 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7006 {0x5614'2330'4af7'4c90, 0xd555'5555'5555'5555},
7007 {0x7ff0'0000'0000'0000, 0x7e5b'5815'60f1'ac51},
7008 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7009 kVectorCalculationsSource);
7010 TestVectorFloatInstruction(0xb500d457, // vfnmacc.vf v8, f1, v16, v0.t
7011 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7012 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7013 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7014 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7015 {0xd555'5555, 0xd555'5555, 0xd555'550e, 0xd555'0ca1},
7016 {0xd50b'37bf, 0x5895'6354, 0x5c99'df27, 0x609c'b3a3},
7017 {0x649f'8677, 0x68a2'594a, 0x6ca5'2c1d, 0x70a7'fef0},
7018 {0x74aa'd1c3, 0x78ad'a496, 0x7cb0'7768, 0x7f80'0000}},
7019 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7020 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7021 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7022 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7023 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7024 {0x5780'0dff'a493'9082, 0x5f85'b3a5'4a3b'e0d2},
7025 {0x6790'194a'efe1'8677, 0x6f95'bef0'9587'2c1d},
7026 {0x77a0'2496'3b2c'd1c3, 0x7fa5'ca3b'e0d2'7768}},
7027 kVectorCalculationsSource);
7028 }
7029
TEST_F(Riscv64InterpreterTest,TestVfwmacc)7030 TEST_F(Riscv64InterpreterTest, TestVfwmacc) {
7031 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7032 TestWideningVectorFloatInstruction(0xf1881457, // vfwmacc.vv v8, v16, v24, v0.t
7033 {{0x3330'e53c'6480'0000, 0x34b2'786b'bbc5'4900},
7034 {0x3234'1766'da4a'6200, 0x33b5'cab6'2d6c'4800},
7035 {0x3937'92ba'5bd0'8000, 0x3ab9'666a'779a'0d00},
7036 {0x383b'4565'd61f'6600, 0x39bd'3935'e5bd'8800},
7037 {0x3f3f'423b'5522'0000, 0x40c0'ab36'1ab7'e880},
7038 {0x3e41'bab3'e9fa'b500, 0x3fc2'd4dc'5007'e400},
7039 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7040 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7041 kVectorCalculationsSource,
7042 dst_result);
7043 TestWideningVectorFloatInstruction(0xf100d457, // vfwmacc.vf v8, f1, v16, v0.t
7044 {{0xb886'f0ad'0000'0000, 0xb907'a561'b400'0000},
7045 {0xb988'5a16'6800'0000, 0xba09'0ecb'1c00'0000},
7046 {0xba89'c37f'd000'0000, 0xbb0a'7834'8400'0000},
7047 {0xbb8b'2ce9'3800'0000, 0xbc0b'e19d'ec00'0000},
7048 {0xbc8c'9652'a000'0000, 0xbd0d'4b07'5400'0000},
7049 {0xbd8d'ffbc'0800'0000, 0xbe0e'b470'bc00'0000},
7050 {0xbe8f'6925'7000'0000, 0xbf10'0eed'1200'0000},
7051 {0xbf90'6947'6c00'0000, 0xc010'c3a1'c600'0000}},
7052 kVectorCalculationsSource,
7053 dst_result);
7054
7055 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7056 TestWideningVectorFloatInstruction(0xf1881457, // vfwmacc.vv v8, v16, v24, v0.t
7057 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7058 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7059 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7060 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7061 {0x401c'66e3'6f53'baee, 0x40c0'aec2'e784'b54d},
7062 {0x401c'6666'66f4'3c05, 0x401c'fd0d'48e6'a586},
7063 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7064 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7065 kVectorCalculationsSource,
7066 dst_result);
7067 TestWideningVectorFloatInstruction(0xf100d457, // vfwmacc.vf v8, f1, v16, v0.t
7068 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7069 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7070 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7071 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7072 {0x401c'6666'6666'6666, 0x401c'6666'6666'6657},
7073 {0x401c'6666'6666'5766, 0x401c'6666'6657'0c2e},
7074 {0x401c'6666'56b1'd3ae, 0x401c'6656'5779'5466},
7075 {0x401c'55fd'1efa'6666, 0x4007'4589'40cc'cccc}},
7076 kVectorCalculationsSource,
7077 dst_result);
7078 }
7079
TEST_F(Riscv64InterpreterTest,TestVfwnmacc)7080 TEST_F(Riscv64InterpreterTest, TestVfwnmacc) {
7081 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7082 TestWideningVectorFloatInstruction(0xf5881457, // vfwnmacc.vv v8, v16, v24, v0.t
7083 {{0xb330'e53c'6480'0000, 0xb4b2'786b'bbc5'4900},
7084 {0xb234'1766'da4a'6200, 0xb3b5'cab6'2d6c'4800},
7085 {0xb937'92ba'5bd0'8000, 0xbab9'666a'779a'0d00},
7086 {0xb83b'4565'd61f'6600, 0xb9bd'3935'e5bd'8800},
7087 {0xbf3f'423b'5522'0000, 0xc0c0'ab36'1ab7'e880},
7088 {0xbe41'bab3'e9fa'b500, 0xbfc2'd4dc'5007'e400},
7089 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7090 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7091 kVectorCalculationsSource,
7092 dst_result);
7093 TestWideningVectorFloatInstruction(0xf500d457, // vfwnmacc.vf v8, f1, v16, v0.t
7094 {{0x3886'f0ad'0000'0000, 0x3907'a561'b400'0000},
7095 {0x3988'5a16'6800'0000, 0x3a09'0ecb'1c00'0000},
7096 {0x3a89'c37f'd000'0000, 0x3b0a'7834'8400'0000},
7097 {0x3b8b'2ce9'3800'0000, 0x3c0b'e19d'ec00'0000},
7098 {0x3c8c'9652'a000'0000, 0x3d0d'4b07'5400'0000},
7099 {0x3d8d'ffbc'0800'0000, 0x3e0e'b470'bc00'0000},
7100 {0x3e8f'6925'7000'0000, 0x3f10'0eed'1200'0000},
7101 {0x3f90'6947'6c00'0000, 0x4010'c3a1'c600'0000}},
7102 kVectorCalculationsSource,
7103 dst_result);
7104
7105 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7106 TestWideningVectorFloatInstruction(0xf5881457, // vfwnmacc.vv v8, v16, v24, v0.t
7107 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7108 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7109 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7110 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7111 {0xc01c'66e3'6f53'baee, 0xc0c0'aec2'e784'b54d},
7112 {0xc01c'6666'66f4'3c05, 0xc01c'fd0d'48e6'a586},
7113 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7114 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7115 kVectorCalculationsSource,
7116 dst_result);
7117 TestWideningVectorFloatInstruction(0xf500d457, // vfwnmacc.vf v8, f1, v16, v0.t
7118 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7119 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7120 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7121 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7122 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6657},
7123 {0xc01c'6666'6666'5766, 0xc01c'6666'6657'0c2e},
7124 {0xc01c'6666'56b1'd3ae, 0xc01c'6656'5779'5466},
7125 {0xc01c'55fd'1efa'6666, 0xc007'4589'40cc'cccc}},
7126 kVectorCalculationsSource,
7127 dst_result);
7128 }
7129
TEST_F(Riscv64InterpreterTest,TestVfwmsac)7130 TEST_F(Riscv64InterpreterTest, TestVfwmsac) {
7131 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7132 TestWideningVectorFloatInstruction(0xf9881457, // vfwmsac.vv v8, v16, v24, v0.t
7133 {{0x3330'e53c'6480'0000, 0x34b2'786b'bbc5'4900},
7134 {0x3234'1766'da4a'6200, 0x33b5'cab6'2d6c'4800},
7135 {0x3937'92ba'5bd0'8000, 0x3ab9'666a'779a'0d00},
7136 {0x383b'4565'd61f'6600, 0x39bd'3935'e5bd'8800},
7137 {0x3f3f'423b'5522'0000, 0x40c0'ab36'1ab7'e880},
7138 {0x3e41'bab3'e9fa'b500, 0x3fc2'd4dc'5007'e400},
7139 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7140 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7141 kVectorCalculationsSource,
7142 dst_result);
7143 TestWideningVectorFloatInstruction(0xf900d457, // vfwmsac.vf v8, f1, v16, v0.t
7144 {{0xb886'f0ad'0000'0000, 0xb907'a561'b400'0000},
7145 {0xb988'5a16'6800'0000, 0xba09'0ecb'1c00'0000},
7146 {0xba89'c37f'd000'0000, 0xbb0a'7834'8400'0000},
7147 {0xbb8b'2ce9'3800'0000, 0xbc0b'e19d'ec00'0000},
7148 {0xbc8c'9652'a000'0000, 0xbd0d'4b07'5400'0000},
7149 {0xbd8d'ffbc'0800'0000, 0xbe0e'b470'bc00'0000},
7150 {0xbe8f'6925'7000'0000, 0xbf10'0eed'1200'0000},
7151 {0xbf90'6947'6c00'0000, 0xc010'c3a1'c600'0000}},
7152 kVectorCalculationsSource,
7153 dst_result);
7154
7155 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7156 TestWideningVectorFloatInstruction(0xf9881457, // vfwmsac.vv v8, v16, v24, v0.t
7157 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7158 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7159 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7160 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7161 {0xc01c'65e9'5d79'11de, 0x40c0'a7a9'4deb'1bb3},
7162 {0xc01c'6666'65d8'90c7, 0xc01b'cfbf'83e6'2746},
7163 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7164 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7165 kVectorCalculationsSource,
7166 dst_result);
7167 TestWideningVectorFloatInstruction(0xf900d457, // vfwmsac.vf v8, f1, v16, v0.t
7168 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7169 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7170 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7171 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7172 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6675},
7173 {0xc01c'6666'6666'7566, 0xc01c'6666'6675'c09e},
7174 {0xc01c'6666'761a'f91e, 0xc01c'6676'7553'7866},
7175 {0xc01c'76cf'add2'6666, 0xc026'9504'1633'3333}},
7176 kVectorCalculationsSource,
7177 dst_result);
7178 }
7179
TEST_F(Riscv64InterpreterTest,TestVfwnmsac)7180 TEST_F(Riscv64InterpreterTest, TestVfwnmsac) {
7181 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7182 TestWideningVectorFloatInstruction(0xfd881457, // vfwnmsac.vv v8, v16, v24, v0.t
7183 {{0xb330'e53c'6480'0000, 0xb4b2'786b'bbc5'4900},
7184 {0xb234'1766'da4a'6200, 0xb3b5'cab6'2d6c'4800},
7185 {0xb937'92ba'5bd0'8000, 0xbab9'666a'779a'0d00},
7186 {0xb83b'4565'd61f'6600, 0xb9bd'3935'e5bd'8800},
7187 {0xbf3f'423b'5522'0000, 0xc0c0'ab36'1ab7'e880},
7188 {0xbe41'bab3'e9fa'b500, 0xbfc2'd4dc'5007'e400},
7189 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7190 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7191 kVectorCalculationsSource,
7192 dst_result);
7193 TestWideningVectorFloatInstruction(0xfd00d457, // vfwnmsac.vf v8, f1, v16, v0.t
7194 {{0x3886'f0ad'0000'0000, 0x3907'a561'b400'0000},
7195 {0x3988'5a16'6800'0000, 0x3a09'0ecb'1c00'0000},
7196 {0x3a89'c37f'd000'0000, 0x3b0a'7834'8400'0000},
7197 {0x3b8b'2ce9'3800'0000, 0x3c0b'e19d'ec00'0000},
7198 {0x3c8c'9652'a000'0000, 0x3d0d'4b07'5400'0000},
7199 {0x3d8d'ffbc'0800'0000, 0x3e0e'b470'bc00'0000},
7200 {0x3e8f'6925'7000'0000, 0x3f10'0eed'1200'0000},
7201 {0x3f90'6947'6c00'0000, 0x4010'c3a1'c600'0000}},
7202 kVectorCalculationsSource,
7203 dst_result);
7204
7205 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7206 TestWideningVectorFloatInstruction(0xfd881457, // vfwnmsac.vv v8, v16, v24, v0.t
7207 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7208 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7209 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7210 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7211 {0x401c'65e9'5d79'11de, 0xc0c0'a7a9'4deb'1bb3},
7212 {0x401c'6666'65d8'90c7, 0x401b'cfbf'83e6'2746},
7213 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7214 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7215 kVectorCalculationsSource,
7216 dst_result);
7217 TestWideningVectorFloatInstruction(0xfd00d457, // vfwnmsac.vf v8, f1, v16, v0.t
7218 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7219 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7220 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7221 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7222 {0x401c'6666'6666'6666, 0x401c'6666'6666'6675},
7223 {0x401c'6666'6666'7566, 0x401c'6666'6675'c09e},
7224 {0x401c'6666'761a'f91e, 0x401c'6676'7553'7866},
7225 {0x401c'76cf'add2'6666, 0x4026'9504'1633'3333}},
7226 kVectorCalculationsSource,
7227 dst_result);
7228 }
7229
TEST_F(Riscv64InterpreterTest,TestVfmsac)7230 TEST_F(Riscv64InterpreterTest, TestVfmsac) {
7231 TestVectorFloatInstruction(0xb9881457, // vfmsac.vv v8, v16, v24, v0.t
7232 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7233 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7234 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7235 {0x6a1f'cefd, 0x7629'21c4, 0x6232'9db3, 0x6e3c'70f9},
7236 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7237 {0xd555'5559, 0xd6ab'3339, 0xd555'5555, 0xd555'5a73},
7238 {0xfaad'fde4, 0xff80'0000, 0xf2c2'c69a, 0xfecd'99e3},
7239 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
7240 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7241 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7242 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7243 {0x75b4'9040'f9f1'ea75, 0x6dcb'c6d1'12f0'a99b},
7244 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7245 {0xd614'25da'f5a1'f73b, 0xd555'5555'5555'5555},
7246 {0xfff0'0000'0000'0000, 0xfe5b'5815'60f1'ac51},
7247 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
7248 kVectorCalculationsSource);
7249 TestVectorFloatInstruction(0xb900d457, // vfmsac.vf v8, f1, v16, v0.t
7250 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7251 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7252 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7253 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7254 {0xd555'5555, 0xd555'5555, 0xd555'559c, 0xd555'9e09},
7255 {0xd58f'b976, 0xd898'b8aa, 0xdc99'e27d, 0xe09c'b3a6},
7256 {0xe49f'8678, 0xe8a2'594a, 0xeca5'2c1d, 0xf0a7'fef0},
7257 {0xf4aa'd1c3, 0xf8ad'a496, 0xfcb0'7768, 0xff80'0000}},
7258 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7259 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7260 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7261 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7262 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7263 {0xd780'0dff'a498'e5d7, 0xdf85'b3a5'4a3b'e0d2},
7264 {0xe790'194a'efe1'8678, 0xef95'bef0'9587'2c1d},
7265 {0xf7a0'2496'3b2c'd1c3, 0xffa5'ca3b'e0d2'7768}},
7266 kVectorCalculationsSource);
7267 }
7268
TEST_F(Riscv64InterpreterTest,TestVfnmsac)7269 TEST_F(Riscv64InterpreterTest, TestVfnmsac) {
7270 TestVectorFloatInstruction(0xbd881457, // vfnmsac.vv v8, v16, v24, v0.t
7271 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7272 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7273 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7274 {0xea1f'cefd, 0xf629'21c4, 0xe232'9db3, 0xee3c'70f9},
7275 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7276 {0x5555'5559, 0x56ab'3339, 0x5555'5555, 0x5555'5a73},
7277 {0x7aad'fde4, 0x7f80'0000, 0x72c2'c69a, 0x7ecd'99e3},
7278 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7279 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7280 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7281 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7282 {0xf5b4'9040'f9f1'ea75, 0xedcb'c6d1'12f0'a99b},
7283 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7284 {0x5614'25da'f5a1'f73b, 0x5555'5555'5555'5555},
7285 {0x7ff0'0000'0000'0000, 0x7e5b'5815'60f1'ac51},
7286 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7287 kVectorCalculationsSource);
7288 TestVectorFloatInstruction(0xbd00d457, // vfnmsac.vf v8, f1, v16, v0.t
7289 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7290 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7291 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7292 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7293 {0x5555'5555, 0x5555'5555, 0x5555'559c, 0x5555'9e09},
7294 {0x558f'b976, 0x5898'b8aa, 0x5c99'e27d, 0x609c'b3a6},
7295 {0x649f'8678, 0x68a2'594a, 0x6ca5'2c1d, 0x70a7'fef0},
7296 {0x74aa'd1c3, 0x78ad'a496, 0x7cb0'7768, 0x7f80'0000}},
7297 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7298 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7299 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7300 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7301 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7302 {0x5780'0dff'a498'e5d7, 0x5f85'b3a5'4a3b'e0d2},
7303 {0x6790'194a'efe1'8678, 0x6f95'bef0'9587'2c1d},
7304 {0x77a0'2496'3b2c'd1c3, 0x7fa5'ca3b'e0d2'7768}},
7305 kVectorCalculationsSource);
7306 }
7307
TEST_F(Riscv64InterpreterTest,TestVfmadd)7308 TEST_F(Riscv64InterpreterTest, TestVfmadd) {
7309 TestVectorFloatInstruction(0xa1881457, // vfmadd.vv v8, v16, v24, v0.t
7310 {{0x98dd'a63a, 0x9e28'a06a, 0xa0e6'e462, 0xa4ed'95be},
7311 {0xb624'b220, 0xbe2c'ba29, 0xb100'd4ec, 0xb504'308a},
7312 {0xd644'd240, 0xde4c'da49, 0xc654'e5df, 0xce5c'ca7c},
7313 {0xf664'f260, 0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78},
7314 {0xd922'4bb5, 0xdd25'a463, 0xe128'fd11, 0xe52c'55bf},
7315 {0xe92f'ae6d, 0xed33'071b, 0xf136'5fc9, 0xf539'b877},
7316 {0xf93d'1125, 0xfd40'69d3, 0xff80'0000, 0xff80'0000},
7317 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
7318 {{0x9e0c'9a09'9d86'3e2c, 0xa474'5e08'5cb1'b0b0},
7319 {0xbe2c'ba29'b624'b220, 0xb484'68bd'bcbc'6610},
7320 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
7321 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
7322 {0xdcae'5c5b'af03'ac55, 0xe4b4'88dd'dcdc'8630},
7323 {0xecbe'71c6'6f19'1715, 0xf4c4'9393'3ce7'3b90},
7324 {0xfcce'8731'2f2e'81d5, 0xfff0'0000'0000'0000},
7325 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
7326
7327 kVectorCalculationsSource);
7328
7329 TestVectorFloatInstruction(0xa100d457, // vfmadd.vf v8, f1, v16, v0.t
7330 {{0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7331 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7332 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7333 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7334 {0x5696'0000, 0x5696'0000, 0x5695'fffe, 0x5695'fe62},
7335 {0x5694'5a5d, 0xd70b'd554, 0xdb5a'8e58, 0xdf5e'dd11},
7336 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7337 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7338 {{0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7339 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7340 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7341 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7342 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7343 {0xd756'd554'd2da'd150, 0xdf5e'dd5c'db5a'd958},
7344 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7345 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7346
7347 kVectorCalculationsSource);
7348 }
7349
TEST_F(Riscv64InterpreterTest,TestVfnmadd)7350 TEST_F(Riscv64InterpreterTest, TestVfnmadd) {
7351 TestVectorFloatInstruction(0xa5881457, // vfnmadd.vv v8, v16, v24, v0.t
7352 {{0x18dd'a63a, 0x1e28'a06a, 0x20e6'e462, 0x24ed'95be},
7353 {0x3624'b220, 0x3e2c'ba29, 0x3100'd4ec, 0x3504'308a},
7354 {0x5644'd240, 0x5e4c'da49, 0x4654'e5df, 0x4e5c'ca7c},
7355 {0x7664'f260, 0x7e6c'fa69, 0x6674'e271, 0x6e7c'ea78},
7356 {0x5922'4bb5, 0x5d25'a463, 0x6128'fd11, 0x652c'55bf},
7357 {0x692f'ae6d, 0x6d33'071b, 0x7136'5fc9, 0x7539'b877},
7358 {0x793d'1125, 0x7d40'69d3, 0x7f80'0000, 0x7f80'0000},
7359 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7360 {{0x1e0c'9a09'9d86'3e2c, 0x2474'5e08'5cb1'b0b0},
7361 {0x3e2c'ba29'b624'b220, 0x3484'68bd'bcbc'6610},
7362 {0x5e4c'da49'd644'd240, 0x4e5c'ca58'c654'c251},
7363 {0x7e6c'fa69'f664'f260, 0x6e7c'ea78'e674'e271},
7364 {0x5cae'5c5b'af03'ac55, 0x64b4'88dd'dcdc'8630},
7365 {0x6cbe'71c6'6f19'1715, 0x74c4'9393'3ce7'3b90},
7366 {0x7cce'8731'2f2e'81d5, 0x7ff0'0000'0000'0000},
7367 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7368 kVectorCalculationsSource);
7369
7370 TestVectorFloatInstruction(0xa500d457, // vfmadd.vf v8, f1, v16, v0.t
7371 {{0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7372 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7373 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7374 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7375 {0xd696'0000, 0xd696'0000, 0xd695'fffe, 0xd695'fe62},
7376 {0xd694'5a5d, 0x570b'd554, 0x5b5a'8e58, 0x5f5e'dd11},
7377 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7378 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7379 {{0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7380 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7381 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7382 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7383 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7384 {0x5756'd554'd2da'd150, 0x5f5e'dd5c'db5a'd958},
7385 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7386 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7387 kVectorCalculationsSource);
7388 }
7389
TEST_F(Riscv64InterpreterTest,TestVfmsub)7390 TEST_F(Riscv64InterpreterTest, TestVfmsub) {
7391 TestVectorFloatInstruction(0xa9881457, // vfmsub.vv v8, v16, v24, v0.t
7392 {{0x98d5'5d1a, 0x1de1'2750, 0xa0e6'e462, 0xa4ed'95be},
7393 {0x3624'b220, 0x3e2c'ba29, 0xb100'd4e6, 0xb504'2aa4},
7394 {0x5644'd240, 0x5e4c'da49, 0x4654'9ec3, 0x4e5c'ca34},
7395 {0x7664'f260, 0x7e6c'fa69, 0x6674'e271, 0x6e7c'ea78},
7396 {0xd922'4bb5, 0xdd25'a463, 0xe128'fd11, 0xe52c'55bf},
7397 {0xe92f'ae6d, 0xed33'071b, 0xf136'5fc9, 0xf539'b877},
7398 {0xf93d'1125, 0xfd40'69d3, 0xff80'0000, 0xff80'0000},
7399 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
7400 {{0x1e0c'9a09'8e82'e5d4, 0xa474'5e08'5cb1'b0b0},
7401 {0x3e2c'ba29'b624'b220, 0xb484'68bd'bcbc'6610},
7402 {0x5e4c'da49'd644'd240, 0x4e5c'ca58'c654'c251},
7403 {0x7e6c'fa69'f664'f260, 0x6e7c'ea78'e674'e271},
7404 {0xdcae'5c5b'af03'ac55, 0xe4b4'88dd'dcdc'8630},
7405 {0xecbe'71c6'6f19'1715, 0xf4c4'9393'3ce7'3b90},
7406 {0xfcce'8731'2f2e'81d5, 0xfff0'0000'0000'0000},
7407 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
7408 kVectorCalculationsSource);
7409
7410 TestVectorFloatInstruction(0xa900d457, // vfmsub.vf v8, f1, v16, v0.t
7411 {{0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7412 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7413 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7414 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7415 {0x5696'0000, 0x5696'0000, 0x5696'0001, 0x5696'019d},
7416 {0x5697'a5a2, 0x5790'eaaa, 0x5b5b'2458, 0x5f5e'dda7},
7417 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7418 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7419 {{0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7420 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7421 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7422 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7423 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7424 {0x5756'd554'd3ca'd150, 0x5f5e'dd5c'db5a'd958},
7425 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7426 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7427 kVectorCalculationsSource);
7428 }
7429
TEST_F(Riscv64InterpreterTest,TestVfnmsub)7430 TEST_F(Riscv64InterpreterTest, TestVfnmsub) {
7431 TestVectorFloatInstruction(0xad881457, // vfnmsub.vv v8, v16, v24, v0.t
7432 {{0x18d5'5d1a, 0x9de1'2750, 0x20e6'e462, 0x24ed'95be},
7433 {0xb624'b220, 0xbe2c'ba29, 0x3100'd4e6, 0x3504'2aa4},
7434 {0xd644'd240, 0xde4c'da49, 0xc654'9ec3, 0xce5c'ca34},
7435 {0xf664'f260, 0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78},
7436 {0x5922'4bb5, 0x5d25'a463, 0x6128'fd11, 0x652c'55bf},
7437 {0x692f'ae6d, 0x6d33'071b, 0x7136'5fc9, 0x7539'b877},
7438 {0x793d'1125, 0x7d40'69d3, 0x7f80'0000, 0x7f80'0000},
7439 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7440 {{0x9e0c'9a09'8e82'e5d4, 0x2474'5e08'5cb1'b0b0},
7441 {0xbe2c'ba29'b624'b220, 0x3484'68bd'bcbc'6610},
7442 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
7443 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
7444 {0x5cae'5c5b'af03'ac55, 0x64b4'88dd'dcdc'8630},
7445 {0x6cbe'71c6'6f19'1715, 0x74c4'9393'3ce7'3b90},
7446 {0x7cce'8731'2f2e'81d5, 0x7ff0'0000'0000'0000},
7447 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7448 kVectorCalculationsSource);
7449
7450 TestVectorFloatInstruction(0xad00d457, // vfnmsub.vf v8, f1, v16, v0.t
7451 {{0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7452 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7453 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7454 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7455 {0xd696'0000, 0xd696'0000, 0xd696'0001, 0xd696'019d},
7456 {0xd697'a5a2, 0xd790'eaaa, 0xdb5b'2458, 0xdf5e'dda7},
7457 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7458 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7459 {{0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7460 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7461 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7462 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7463 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7464 {0xd756'd554'd3ca'd150, 0xdf5e'dd5c'db5a'd958},
7465 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7466 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7467 kVectorCalculationsSource);
7468 }
7469
TEST_F(Riscv64InterpreterTest,TestVbrev8)7470 TEST_F(Riscv64InterpreterTest, TestVbrev8) {
7471 TestVectorInstruction(
7472 0x49842457, // vbrev8.v v8, v24, v0.t
7473 {{160, 15, 160, 15, 160, 15, 160, 15, 2, 2, 2, 2, 255, 255, 255, 255},
7474 {136, 136, 136, 136, 136, 136, 136, 136, 136, 136, 136, 136, 136, 136, 136, 136},
7475 {143, 255, 143, 255, 143, 255, 143, 255, 143, 255, 143, 255, 143, 255, 143, 255},
7476 {6, 70, 38, 102, 150, 86, 54, 118, 142, 78, 46, 110, 30, 94, 62, 126},
7477 {1, 65, 33, 97, 145, 81, 49, 113, 137, 73, 41, 105, 25, 89, 57, 121},
7478 {5, 69, 37, 101, 149, 85, 53, 117, 141, 77, 45, 109, 29, 93, 61, 125},
7479 {3, 67, 35, 99, 147, 83, 51, 115, 139, 75, 43, 107, 27, 91, 59, 123},
7480 {7, 71, 39, 103, 151, 87, 55, 119, 143, 79, 47, 111, 31, 95, 63, 127}},
7481 {{0x0fa0, 0x0fa0, 0x0fa0, 0x0fa0, 0x0202, 0x0202, 0xffff, 0xffff},
7482 {0x8888, 0x8888, 0x8888, 0x8888, 0x8888, 0x8888, 0x8888, 0x8888},
7483 {0xff8f, 0xff8f, 0xff8f, 0xff8f, 0xff8f, 0xff8f, 0xff8f, 0xff8f},
7484 {0x4606, 0x6626, 0x5696, 0x7636, 0x4e8e, 0x6e2e, 0x5e1e, 0x7e3e},
7485 {0x4101, 0x6121, 0x5191, 0x7131, 0x4989, 0x6929, 0x5919, 0x7939},
7486 {0x4505, 0x6525, 0x5595, 0x7535, 0x4d8d, 0x6d2d, 0x5d1d, 0x7d3d},
7487 {0x4303, 0x6323, 0x5393, 0x7333, 0x4b8b, 0x6b2b, 0x5b1b, 0x7b3b},
7488 {0x4707, 0x6727, 0x5797, 0x7737, 0x4f8f, 0x6f2f, 0x5f1f, 0x7f3f}},
7489 {{0x0fa0'0fa0, 0x0fa0'0fa0, 0x0202'0202, 0xffff'ffff},
7490 {0x8888'8888, 0x8888'8888, 0x8888'8888, 0x8888'8888},
7491 {0xff8f'ff8f, 0xff8f'ff8f, 0xff8f'ff8f, 0xff8f'ff8f},
7492 {0x6626'4606, 0x7636'5696, 0x6e2e'4e8e, 0x7e3e'5e1e},
7493 {0x6121'4101, 0x7131'5191, 0x6929'4989, 0x7939'5919},
7494 {0x6525'4505, 0x7535'5595, 0x6d2d'4d8d, 0x7d3d'5d1d},
7495 {0x6323'4303, 0x7333'5393, 0x6b2b'4b8b, 0x7b3b'5b1b},
7496 {0x6727'4707, 0x7737'5797, 0x6f2f'4f8f, 0x7f3f'5f1f}},
7497 {{0x0fa0'0fa0'0fa0'0fa0, 0xffff'ffff'0202'0202},
7498 {0x8888'8888'8888'8888, 0x8888'8888'8888'8888},
7499 {0xff8f'ff8f'ff8f'ff8f, 0xff8f'ff8f'ff8f'ff8f},
7500 {0x7636'5696'6626'4606, 0x7e3e'5e1e'6e2e'4e8e},
7501 {0x7131'5191'6121'4101, 0x7939'5919'6929'4989},
7502 {0x7535'5595'6525'4505, 0x7d3d'5d1d'6d2d'4d8d},
7503 {0x7333'5393'6323'4303, 0x7b3b'5b1b'6b2b'4b8b},
7504 {0x7737'5797'6727'4707, 0x7f3f'5f1f'6f2f'4f8f}},
7505 kVectorComparisonSource);
7506 }
7507
TEST_F(Riscv64InterpreterTest,TestVfmin)7508 TEST_F(Riscv64InterpreterTest, TestVfmin) {
7509 TestVectorFloatInstruction(0x1100d457, // vfmin.vf v8, v16, f1, v0.t
7510 {{0xf005'f005, 0xf005'f005, 0x4040'4040, 0x40b4'0000},
7511 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7512 {0x4016'4016, 0x4016'4016, 0x0000'0000, 0x4016'8000},
7513 {0xaaaa'aaaa, 0xaaaa'aaaa, 0x1111'1111, 0x1111'1111},
7514 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7515 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7516 {0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb},
7517 {0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9}},
7518 {{0xf005'f005'f005'f005, 0x4016'8000'0000'0000},
7519 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7520 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
7521 {0xaaaa'aaaa'aaaa'aaaa, 0x1111'1111'1111'1111},
7522 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7523 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7524 {0xa9bb'bbbb'a9bb'bbbb, 0xa9bb'bbbb'a9bb'bbbb},
7525 {0xa9a9'a9a9'a9a9'a9a9, 0xa9a9'a9a9'a9a9'a9a9}},
7526 kVectorComparisonSource);
7527 TestVectorFloatInstruction(0x110c1457, // vfmin.vv v8,v16,v24,v0.t
7528 {{0xf005'f005, 0xf005'f005, 0x4040'4040, 0x7fc0'0000},
7529 {0x1111'1111, 0x1111'1111, 0x1111'1111, 0x1111'1111},
7530 {0x4016'4016, 0x4016'4016, 0x0000'0000, 0x4016'8000},
7531 {0xaaaa'aaaa, 0xaaaa'aaaa, 0x1111'1111, 0x1111'1111},
7532 {0x8684'8280, 0x8e8c'8a89, 0x9694'9291, 0x9e9c'9a98},
7533 {0xa6a4'a2a0, 0xaeac'aaa9, 0xb6b4'b2b1, 0xbebc'bab8},
7534 {0xc6c4'c2c0, 0xcecc'cac9, 0xd6d4'd2d1, 0xdedc'dad8},
7535 {0xe6e4'e2e0, 0xeeec'eae9, 0xf6f4'f2f1, 0xfefc'faf8}},
7536 {{0xf005'f005'f005'f005, 0x7ff8'0000'0000'0000},
7537 {0x1111'1111'1111'1111, 0x1111'1111'1111'1111},
7538 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
7539 {0xaaaa'aaaa'aaaa'aaaa, 0x1111'1111'1111'1111},
7540 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
7541 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
7542 {0xcecc'cac9'c6c4'c2c0, 0xdedc'dad8'd6d4'd2d1},
7543 {0xeeec'eae9'e6e4'e2e0, 0xfefc'faf8'f6f4'f2f1}},
7544 kVectorComparisonSource);
7545 }
7546
TEST_F(Riscv64InterpreterTest,TestVfmax)7547 TEST_F(Riscv64InterpreterTest, TestVfmax) {
7548 TestVectorFloatInstruction(0x1900d457, // vfmax.vf v8, v16, f1, v0.t
7549 {{0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7550 {0x40b4'40b4, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7551 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7552 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7553 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7554 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7555 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7556 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000}},
7557 {{0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7558 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7559 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7560 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7561 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7562 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7563 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7564 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000}},
7565 kVectorComparisonSource);
7566 TestVectorFloatInstruction(0x190c1457, // vfmax.vv v8,v16,v24,v0.t
7567 {{0xf005'f005, 0xf005'f005, 0x4040'4040, 0x7fc0'0000},
7568 {0x40b4'40b4, 0x1111'1111, 0x40b4'0000, 0x1111'1111},
7569 {0x4016'4016, 0x4016'4016, 0x0000'0000, 0x4016'8000},
7570 {0x6664'6260, 0x6e6c'6a69, 0x7674'7271, 0x7e7c'7a78},
7571 {0x8684'8280, 0x8e8c'8a89, 0x9694'9291, 0x9e9c'9a98},
7572 {0xa6a4'a2a0, 0xaeac'aaa9, 0xb6b4'b2b1, 0xbebc'bab8},
7573 {0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb},
7574 {0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9}},
7575 {{0xf005'f005'f005'f005, 0x7ff8'0000'0000'0000},
7576 {0x1111'1111'1111'1111, 0x1111'1111'1111'1111},
7577 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
7578 {0x6e6c'6a69'6664'6260, 0x7e7c'7a78'7674'7271},
7579 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
7580 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
7581 {0xa9bb'bbbb'a9bb'bbbb, 0xa9bb'bbbb'a9bb'bbbb},
7582 {0xa9a9'a9a9'a9a9'a9a9, 0xa9a9'a9a9'a9a9'a9a9}},
7583 kVectorComparisonSource);
7584 }
7585
TEST_F(Riscv64InterpreterTest,TestVfsgnj)7586 TEST_F(Riscv64InterpreterTest, TestVfsgnj) {
7587 TestVectorFloatInstruction(0x210c1457, // vfsgnj.vv v8, v16, v24, v0.t
7588 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
7589 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
7590 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
7591 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
7592 {0x4342'c140, 0x4746'c544, 0x4b4a'c948, 0x4f4e'cd4c},
7593 {0x5352'd150, 0x5756'd554, 0x5b5a'd958, 0x5f5e'dd5c},
7594 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7595 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7596 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
7597 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
7598 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
7599 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
7600 {0x4746'c544'c342'c140, 0x4f4e'cd4c'cb4a'c948},
7601 {0x5756'd554'd352'd150, 0x5f5e'dd5c'db5a'd958},
7602 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7603 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7604 kVectorCalculationsSource);
7605 TestVectorFloatInstruction(0x2100d457, // vfsgnj.vf v8, v16, f1, v0.t
7606 {{0x0302'8100, 0x0706'8504, 0x0b0a'8908, 0x0f0e'8d0c},
7607 {0x1312'9110, 0x1716'9514, 0x1b1a'9918, 0x1f1e'9d1c},
7608 {0x2322'a120, 0x2726'a524, 0x2b2a'a928, 0x2f2e'ad2c},
7609 {0x3332'b130, 0x3736'b534, 0x3b3a'b938, 0x3f3e'bd3c},
7610 {0x4342'c140, 0x4746'c544, 0x4b4a'c948, 0x4f4e'cd4c},
7611 {0x5352'd150, 0x5756'd554, 0x5b5a'd958, 0x5f5e'dd5c},
7612 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7613 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7614 {{0x0706'8504'8302'8100, 0x0f0e'8d0c'8b0a'8908},
7615 {0x1716'9514'9312'9110, 0x1f1e'9d1c'9b1a'9918},
7616 {0x2726'a524'a322'a120, 0x2f2e'ad2c'ab2a'a928},
7617 {0x3736'b534'b332'b130, 0x3f3e'bd3c'bb3a'b938},
7618 {0x4746'c544'c342'c140, 0x4f4e'cd4c'cb4a'c948},
7619 {0x5756'd554'd352'd150, 0x5f5e'dd5c'db5a'd958},
7620 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7621 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7622 kVectorCalculationsSource);
7623 TestVectorFloatInstruction(0x250c1457, // vfsgnjn.vv v8, v16, v24, v0.t
7624 {{0x0302'8100, 0x0706'8504, 0x0b0a'8908, 0x0f0e'8d0c},
7625 {0x1312'9110, 0x1716'9514, 0x1b1a'9918, 0x1f1e'9d1c},
7626 {0x2322'a120, 0x2726'a524, 0x2b2a'a928, 0x2f2e'ad2c},
7627 {0x3332'b130, 0x3736'b534, 0x3b3a'b938, 0x3f3e'bd3c},
7628 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7629 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7630 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7631 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7632 {{0x0706'8504'8302'8100, 0x0f0e'8d0c'8b0a'8908},
7633 {0x1716'9514'9312'9110, 0x1f1e'9d1c'9b1a'9918},
7634 {0x2726'a524'a322'a120, 0x2f2e'ad2c'ab2a'a928},
7635 {0x3736'b534'b332'b130, 0x3f3e'bd3c'bb3a'b938},
7636 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7637 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7638 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7639 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7640 kVectorCalculationsSource);
7641 TestVectorFloatInstruction(0x2500d457, // vfsgnjn.vf v8, v16, f1, v0.t
7642 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
7643 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
7644 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
7645 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
7646 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7647 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7648 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7649 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7650 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
7651 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
7652 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
7653 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
7654 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7655 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7656 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7657 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7658 kVectorCalculationsSource);
7659 TestVectorFloatInstruction(0x290c1457, // vfsgnjx.vv v8, v16, v24, v0.t
7660 {{0x0302'8100, 0x0706'8504, 0x0b0a'8908, 0x0f0e'8d0c},
7661 {0x1312'9110, 0x1716'9514, 0x1b1a'9918, 0x1f1e'9d1c},
7662 {0x2322'a120, 0x2726'a524, 0x2b2a'a928, 0x2f2e'ad2c},
7663 {0x3332'b130, 0x3736'b534, 0x3b3a'b938, 0x3f3e'bd3c},
7664 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7665 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7666 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7667 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7668 {{0x0706'8504'8302'8100, 0x0f0e'8d0c'8b0a'8908},
7669 {0x1716'9514'9312'9110, 0x1f1e'9d1c'9b1a'9918},
7670 {0x2726'a524'a322'a120, 0x2f2e'ad2c'ab2a'a928},
7671 {0x3736'b534'b332'b130, 0x3f3e'bd3c'bb3a'b938},
7672 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7673 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7674 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7675 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7676 kVectorCalculationsSource);
7677 TestVectorFloatInstruction(0x2900d457, // vfsgnjx.vf v8, v16, f1, v0.t
7678 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
7679 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
7680 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
7681 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
7682 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7683 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7684 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7685 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7686 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
7687 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
7688 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
7689 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
7690 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7691 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7692 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7693 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7694 kVectorCalculationsSource);
7695 }
7696
7697 // Note that the expected test outputs for v[f]merge.vXm are identical to those for v[f]mv.v.X.
7698 // This happens because v[f]merge.vXm is just a v[f]mv.v.X with mask (second operand is not used
7699 // by v[f]mv.v.X but the difference between v[f]merge.vXm and v[f]mv.v.X is captured in masking
7700 // logic within TestVectorInstruction itself via the parameter TestVectorInstructionMode::kVMerge
7701 // for V[f]merge/V[f]mv).
TEST_F(Riscv64InterpreterTest,TestVmerge)7702 TEST_F(Riscv64InterpreterTest, TestVmerge) {
7703 TestVectorMergeFloatInstruction(0x5d00d457, // Vfmerge.vfm v8, v16, f1, v0
7704 {{0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7705 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7706 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7707 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7708 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7709 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7710 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7711 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000}},
7712 {{0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7713 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7714 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7715 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7716 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7717 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7718 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7719 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000}},
7720 kVectorCalculationsSource);
7721 TestVectorMergeInstruction(
7722 0x5d0c0457, // Vmerge.vvm v8, v16, v24, v0
7723 {{0, 146, 4, 150, 9, 154, 12, 158, 17, 130, 20, 134, 24, 138, 28, 142},
7724 {32, 178, 36, 182, 41, 186, 44, 190, 49, 162, 52, 166, 56, 170, 60, 174},
7725 {64, 210, 68, 214, 73, 218, 76, 222, 81, 194, 84, 198, 88, 202, 92, 206},
7726 {96, 242, 100, 246, 105, 250, 108, 254, 113, 226, 116, 230, 120, 234, 124, 238},
7727 {128, 18, 132, 22, 137, 26, 140, 30, 145, 2, 148, 6, 152, 10, 156, 14},
7728 {160, 50, 164, 54, 169, 58, 172, 62, 177, 34, 180, 38, 184, 42, 188, 46},
7729 {192, 82, 196, 86, 201, 90, 204, 94, 209, 66, 212, 70, 216, 74, 220, 78},
7730 {224, 114, 228, 118, 233, 122, 236, 126, 241, 98, 244, 102, 248, 106, 252, 110}},
7731 {{0x9200, 0x9604, 0x9a09, 0x9e0c, 0x8211, 0x8614, 0x8a18, 0x8e1c},
7732 {0xb220, 0xb624, 0xba29, 0xbe2c, 0xa231, 0xa634, 0xaa38, 0xae3c},
7733 {0xd240, 0xd644, 0xda49, 0xde4c, 0xc251, 0xc654, 0xca58, 0xce5c},
7734 {0xf260, 0xf664, 0xfa69, 0xfe6c, 0xe271, 0xe674, 0xea78, 0xee7c},
7735 {0x1280, 0x1684, 0x1a89, 0x1e8c, 0x0291, 0x0694, 0x0a98, 0x0e9c},
7736 {0x32a0, 0x36a4, 0x3aa9, 0x3eac, 0x22b1, 0x26b4, 0x2ab8, 0x2ebc},
7737 {0x52c0, 0x56c4, 0x5ac9, 0x5ecc, 0x42d1, 0x46d4, 0x4ad8, 0x4edc},
7738 {0x72e0, 0x76e4, 0x7ae9, 0x7eec, 0x62f1, 0x66f4, 0x6af8, 0x6efc}},
7739 {{0x9604'9200, 0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18},
7740 {0xb624'b220, 0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38},
7741 {0xd644'd240, 0xde4c'da49, 0xc654'c251, 0xce5c'ca58},
7742 {0xf664'f260, 0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78},
7743 {0x1684'1280, 0x1e8c'1a89, 0x0694'0291, 0x0e9c'0a98},
7744 {0x36a4'32a0, 0x3eac'3aa9, 0x26b4'22b1, 0x2ebc'2ab8},
7745 {0x56c4'52c0, 0x5ecc'5ac9, 0x46d4'42d1, 0x4edc'4ad8},
7746 {0x76e4'72e0, 0x7eec'7ae9, 0x66f4'62f1, 0x6efc'6af8}},
7747 {{0x9e0c'9a09'9604'9200, 0x8e1c'8a18'8614'8211},
7748 {0xbe2c'ba29'b624'b220, 0xae3c'aa38'a634'a231},
7749 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
7750 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
7751 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
7752 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
7753 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
7754 {0x7eec'7ae9'76e4'72e0, 0x6efc'6af8'66f4'62f1}},
7755 kVectorCalculationsSource);
7756 TestVectorMergeInstruction(
7757 0x5d00c457, // Vmerge.vxm v8, v16, x1, v0
7758 {{170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7759 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7760 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7761 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7762 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7763 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7764 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
7765 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170}},
7766 {{0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7767 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7768 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7769 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7770 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7771 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7772 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
7773 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa}},
7774 {{0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7775 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7776 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7777 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7778 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7779 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7780 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
7781 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa}},
7782 {{0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7783 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7784 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7785 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7786 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7787 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7788 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
7789 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa}},
7790 kVectorCalculationsSource);
7791 TestVectorMergeInstruction(
7792 0x5d0ab457, // Vmerge.vim v8, v16, -0xb, v0
7793 {{245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7794 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7795 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7796 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7797 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7798 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7799 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
7800 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245}},
7801 {{0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7802 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7803 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7804 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7805 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7806 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7807 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
7808 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5}},
7809 {{0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7810 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7811 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7812 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7813 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7814 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7815 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
7816 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5}},
7817 {{0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7818 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7819 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7820 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7821 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7822 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7823 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
7824 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5}},
7825 kVectorCalculationsSource);
7826 }
7827
TEST_F(Riscv64InterpreterTest,TestVslide1down)7828 TEST_F(Riscv64InterpreterTest, TestVslide1down) {
7829 // Where the element at the top gets inserted will depend on VLMUL so we use
7830 // TestVectorPermutationInstruction instead of TestVectorInstruction.
7831
7832 // VLMUL = 0
7833 TestVectorPermutationInstruction(
7834 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
7835 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 0xaa}, {}, {}, {}, {}, {}, {}, {}},
7836 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0xaaaa},
7837 {},
7838 {},
7839 {},
7840 {},
7841 {},
7842 {},
7843 {}},
7844 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0xaaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
7845 {{0x1e1c'1a18'1614'1211, 0xaaaa'aaaa'aaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
7846 kVectorCalculationsSourceLegacy,
7847 /*vlmul=*/0,
7848 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
7849 /*skip=*/0,
7850 /*ignore_vma_for_last=*/true,
7851 /*last_elem_is_x1=*/true);
7852
7853 // VLMUL = 1
7854 TestVectorPermutationInstruction(
7855 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
7856 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 32},
7857 {34, 36, 38, 41, 42, 44, 46, 49, 50, 52, 54, 56, 58, 60, 62, 0xaa},
7858 {},
7859 {},
7860 {},
7861 {},
7862 {},
7863 {}},
7864 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0x2220},
7865 {0x2624, 0x2a29, 0x2e2c, 0x3231, 0x3634, 0x3a38, 0x3e3c, 0xaaaa},
7866 {},
7867 {},
7868 {},
7869 {},
7870 {},
7871 {}},
7872 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0x2624'2220},
7873 {0x2e2c'2a29, 0x3634'3231, 0x3e3c'3a38, 0xaaaa'aaaa},
7874 {},
7875 {},
7876 {},
7877 {},
7878 {},
7879 {}},
7880 {{0x1e1c'1a18'1614'1211, 0x2e2c'2a29'2624'2220},
7881 {0x3e3c'3a38'3634'3231, 0xaaaa'aaaa'aaaa'aaaa},
7882 {},
7883 {},
7884 {},
7885 {},
7886 {},
7887 {}},
7888 kVectorCalculationsSourceLegacy,
7889 /*vlmul=*/1,
7890 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
7891 /*skip=*/0,
7892 /*ignore_vma_for_last=*/true,
7893 /*last_elem_is_x1=*/true);
7894
7895 // VLMUL = 2
7896 TestVectorPermutationInstruction(
7897 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
7898 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 32},
7899 {34, 36, 38, 41, 42, 44, 46, 49, 50, 52, 54, 56, 58, 60, 62, 64},
7900 {66, 68, 70, 73, 74, 76, 78, 81, 82, 84, 86, 88, 90, 92, 94, 96},
7901 {98, 100, 102, 105, 106, 108, 110, 113, 114, 116, 118, 120, 122, 124, 126, 0xaa},
7902 {},
7903 {},
7904 {},
7905 {}},
7906 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0x2220},
7907 {0x2624, 0x2a29, 0x2e2c, 0x3231, 0x3634, 0x3a38, 0x3e3c, 0x4240},
7908 {0x4644, 0x4a49, 0x4e4c, 0x5251, 0x5654, 0x5a58, 0x5e5c, 0x6260},
7909 {0x6664, 0x6a69, 0x6e6c, 0x7271, 0x7674, 0x7a78, 0x7e7c, 0xaaaa},
7910 {},
7911 {},
7912 {},
7913 {}},
7914 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0x2624'2220},
7915 {0x2e2c'2a29, 0x3634'3231, 0x3e3c'3a38, 0x4644'4240},
7916 {0x4e4c'4a49, 0x5654'5251, 0x5e5c'5a58, 0x6664'6260},
7917 {0x6e6c'6a69, 0x7674'7271, 0x7e7c'7a78, 0xaaaa'aaaa},
7918 {},
7919 {},
7920 {},
7921 {}},
7922 {{0x1e1c'1a18'1614'1211, 0x2e2c'2a29'2624'2220},
7923 {0x3e3c'3a38'3634'3231, 0x4e4c'4a49'4644'4240},
7924 {0x5e5c'5a58'5654'5251, 0x6e6c'6a69'6664'6260},
7925 {0x7e7c'7a78'7674'7271, 0xaaaa'aaaa'aaaa'aaaa},
7926 {},
7927 {},
7928 {},
7929 {}},
7930 kVectorCalculationsSourceLegacy,
7931 /*vlmul=*/2,
7932 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
7933 /*skip=*/0,
7934 /*ignore_vma_for_last=*/true,
7935 /*last_elem_is_x1=*/true);
7936
7937 // VLMUL = 3
7938 TestVectorPermutationInstruction(
7939 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
7940 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 32},
7941 {34, 36, 38, 41, 42, 44, 46, 49, 50, 52, 54, 56, 58, 60, 62, 64},
7942 {66, 68, 70, 73, 74, 76, 78, 81, 82, 84, 86, 88, 90, 92, 94, 96},
7943 {98, 100, 102, 105, 106, 108, 110, 113, 114, 116, 118, 120, 122, 124, 126, 128},
7944 {130, 132, 134, 137, 138, 140, 142, 145, 146, 148, 150, 152, 154, 156, 158, 160},
7945 {162, 164, 166, 169, 170, 172, 174, 177, 178, 180, 182, 184, 186, 188, 190, 192},
7946 {194, 196, 198, 201, 202, 204, 206, 209, 210, 212, 214, 216, 218, 220, 222, 224},
7947 {226, 228, 230, 233, 234, 236, 238, 241, 242, 244, 246, 248, 250, 252, 254, 0xaa}},
7948 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0x2220},
7949 {0x2624, 0x2a29, 0x2e2c, 0x3231, 0x3634, 0x3a38, 0x3e3c, 0x4240},
7950 {0x4644, 0x4a49, 0x4e4c, 0x5251, 0x5654, 0x5a58, 0x5e5c, 0x6260},
7951 {0x6664, 0x6a69, 0x6e6c, 0x7271, 0x7674, 0x7a78, 0x7e7c, 0x8280},
7952 {0x8684, 0x8a89, 0x8e8c, 0x9291, 0x9694, 0x9a98, 0x9e9c, 0xa2a0},
7953 {0xa6a4, 0xaaa9, 0xaeac, 0xb2b1, 0xb6b4, 0xbab8, 0xbebc, 0xc2c0},
7954 {0xc6c4, 0xcac9, 0xcecc, 0xd2d1, 0xd6d4, 0xdad8, 0xdedc, 0xe2e0},
7955 {0xe6e4, 0xeae9, 0xeeec, 0xf2f1, 0xf6f4, 0xfaf8, 0xfefc, 0xaaaa}},
7956 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0x2624'2220},
7957 {0x2e2c'2a29, 0x3634'3231, 0x3e3c'3a38, 0x4644'4240},
7958 {0x4e4c'4a49, 0x5654'5251, 0x5e5c'5a58, 0x6664'6260},
7959 {0x6e6c'6a69, 0x7674'7271, 0x7e7c'7a78, 0x8684'8280},
7960 {0x8e8c'8a89, 0x9694'9291, 0x9e9c'9a98, 0xa6a4'a2a0},
7961 {0xaeac'aaa9, 0xb6b4'b2b1, 0xbebc'bab8, 0xc6c4'c2c0},
7962 {0xcecc'cac9, 0xd6d4'd2d1, 0xdedc'dad8, 0xe6e4'e2e0},
7963 {0xeeec'eae9, 0xf6f4'f2f1, 0xfefc'faf8, 0xaaaa'aaaa}},
7964 {{0x1e1c'1a18'1614'1211, 0x2e2c'2a29'2624'2220},
7965 {0x3e3c'3a38'3634'3231, 0x4e4c'4a49'4644'4240},
7966 {0x5e5c'5a58'5654'5251, 0x6e6c'6a69'6664'6260},
7967 {0x7e7c'7a78'7674'7271, 0x8e8c'8a89'8684'8280},
7968 {0x9e9c'9a98'9694'9291, 0xaeac'aaa9'a6a4'a2a0},
7969 {0xbebc'bab8'b6b4'b2b1, 0xcecc'cac9'c6c4'c2c0},
7970 {0xdedc'dad8'd6d4'd2d1, 0xeeec'eae9'e6e4'e2e0},
7971 {0xfefc'faf8'f6f4'f2f1, 0xaaaa'aaaa'aaaa'aaaa}},
7972 kVectorCalculationsSourceLegacy,
7973 /*vlmul=*/3,
7974 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
7975 /*skip=*/0,
7976 /*ignore_vma_for_last=*/true,
7977 /*last_elem_is_x1=*/true);
7978
7979 // VLMUL = 4
7980 TestVectorPermutationInstruction(0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
7981 {{}, {}, {}, {}, {}, {}, {}, {}},
7982 {{}, {}, {}, {}, {}, {}, {}, {}},
7983 {{}, {}, {}, {}, {}, {}, {}, {}},
7984 {{}, {}, {}, {}, {}, {}, {}, {}},
7985 kVectorCalculationsSourceLegacy,
7986 /*vlmul=*/4,
7987 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
7988 /*skip=*/0,
7989 /*ignore_vma_for_last=*/true,
7990 /*last_elem_is_x1=*/true);
7991
7992 // VLMUL = 5
7993 TestVectorPermutationInstruction(
7994 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
7995 {{2, 0xaa, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
7996 {{0xaaaa, 0, 0, 0, 0, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
7997 {{}, {}, {}, {}, {}, {}, {}, {}},
7998 {{}, {}, {}, {}, {}, {}, {}, {}},
7999 kVectorCalculationsSourceLegacy,
8000 /*vlmul=*/5,
8001 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8002 /*skip=*/0,
8003 /*ignore_vma_for_last=*/true,
8004 /*last_elem_is_x1=*/true);
8005
8006 // VLMUL = 6
8007 TestVectorPermutationInstruction(
8008 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8009 {{2, 4, 6, 0xaa, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8010 {{0x0604, 0xaaaa, 0, 0, 0, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8011 {{0xaaaa'aaaa, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8012 {{}, {}, {}, {}, {}, {}, {}, {}},
8013 kVectorCalculationsSourceLegacy,
8014 /*vlmul=*/6,
8015 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8016 /*skip=*/0,
8017 /*ignore_vma_for_last=*/true,
8018 /*last_elem_is_x1=*/true);
8019
8020 // VLMUL = 7
8021 TestVectorPermutationInstruction(
8022 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8023 {{2, 4, 6, 9, 10, 12, 14, 0xaa, 0, 0, 0, 0, 0, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8024 {{0x0604, 0x0a09, 0x0e0c, 0xaaaa, 0, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8025 {{0x0e0c'0a09, 0xaaaa'aaaa, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8026 {{0xaaaa'aaaa'aaaa'aaaa, 0}, {}, {}, {}, {}, {}, {}, {}},
8027 kVectorCalculationsSourceLegacy,
8028 /*vlmul=*/7,
8029 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8030 /*skip=*/0,
8031 /*ignore_vma_for_last=*/true,
8032 /*last_elem_is_x1=*/true);
8033 }
8034
TEST_F(Riscv64InterpreterTest,TestVfslide1up)8035 TEST_F(Riscv64InterpreterTest, TestVfslide1up) {
8036 TestVectorFloatInstruction(0x3980d457, // vfslide1up.vf v8, v24, f1, v0.t
8037 {{0x40b4'0000, 0x9604'9200, 0x9e0c'9a09, 0x8614'8211},
8038 {0x8e1c'8a18, 0xb624'b220, 0xbe2c'ba29, 0xa634'a231},
8039 {0xae3c'aa38, 0xd644'd240, 0xde4c'da49, 0xc654'c251},
8040 {0xce5c'ca58, 0xf664'f260, 0xfe6c'fa69, 0xe674'e271},
8041 {0xee7c'ea78, 0x1684'1280, 0x1e8c'1a89, 0x0694'0291},
8042 {0x0e9c'0a98, 0x36a4'32a0, 0x3eac'3aa9, 0x26b4'22b1},
8043 {0x2ebc'2ab8, 0x56c4'52c0, 0x5ecc'5ac9, 0x46d4'42d1},
8044 {0x4edc'4ad8, 0x76e4'72e0, 0x7eec'7ae9, 0x66f4'62f1}},
8045 {{0x4016'8000'0000'0000, 0x9e0c'9a09'9604'9200},
8046 {0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8047 {0xae3c'aa38'a634'a231, 0xde4c'da49'd644'd240},
8048 {0xce5c'ca58'c654'c251, 0xfe6c'fa69'f664'f260},
8049 {0xee7c'ea78'e674'e271, 0x1e8c'1a89'1684'1280},
8050 {0x0e9c'0a98'0694'0291, 0x3eac'3aa9'36a4'32a0},
8051 {0x2ebc'2ab8'26b4'22b1, 0x5ecc'5ac9'56c4'52c0},
8052 {0x4edc'4ad8'46d4'42d1, 0x7eec'7ae9'76e4'72e0}},
8053 kVectorCalculationsSource);
8054 }
8055
TEST_F(Riscv64InterpreterTest,TestVfslide1down)8056 TEST_F(Riscv64InterpreterTest, TestVfslide1down) {
8057 // Where the element at the top gets inserted will depend on VLMUL so we use
8058 // TestVectorFloatPermutationInstruction instead of TestVectorFloatInstruction.
8059
8060 // VLMUL = 0
8061 TestVectorFloatPermutationInstruction(
8062 0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8063 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0x40b4'0000}, {}, {}, {}, {}, {}, {}, {}},
8064 {{0x8e1c'8a18'8614'8211, 0x4016'8000'0000'0000}, {}, {}, {}, {}, {}, {}, {}},
8065 kVectorCalculationsSource,
8066 /*vlmul=*/0,
8067 /*skip=*/0,
8068 /*ignore_vma_for_last=*/true,
8069 /*last_elem_is_f1=*/true);
8070
8071 // VLMUL = 1
8072 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8073 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0xb624'b220},
8074 {0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38, 0x40b4'0000},
8075 {},
8076 {},
8077 {},
8078 {},
8079 {},
8080 {}},
8081 {{0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8082 {0xae3c'aa38'a634'a231, 0x4016'8000'0000'0000},
8083 {},
8084 {},
8085 {},
8086 {},
8087 {},
8088 {}},
8089 kVectorCalculationsSource,
8090 /*vlmul=*/1,
8091 /*skip=*/0,
8092 /*ignore_vma_for_last=*/true,
8093 /*last_elem_is_f1=*/true);
8094
8095 // VLMUL = 2
8096 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8097 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0xb624'b220},
8098 {0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38, 0xd644'd240},
8099 {0xde4c'da49, 0xc654'c251, 0xce5c'ca58, 0xf664'f260},
8100 {0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78, 0x40b4'0000},
8101 {},
8102 {},
8103 {},
8104 {}},
8105 {{0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8106 {0xae3c'aa38'a634'a231, 0xde4c'da49'd644'd240},
8107 {0xce5c'ca58'c654'c251, 0xfe6c'fa69'f664'f260},
8108 {0xee7c'ea78'e674'e271, 0x4016'8000'0000'0000},
8109 {},
8110 {},
8111 {},
8112 {}},
8113 kVectorCalculationsSource,
8114 /*vlmul=*/2,
8115 /*skip=*/0,
8116 /*ignore_vma_for_last=*/true,
8117 /*last_elem_is_f1=*/true);
8118
8119 // VLMUL = 3
8120 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8121 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0xb624'b220},
8122 {0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38, 0xd644'd240},
8123 {0xde4c'da49, 0xc654'c251, 0xce5c'ca58, 0xf664'f260},
8124 {0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78, 0x1684'1280},
8125 {0x1e8c'1a89, 0x0694'0291, 0x0e9c'0a98, 0x36a4'32a0},
8126 {0x3eac'3aa9, 0x26b4'22b1, 0x2ebc'2ab8, 0x56c4'52c0},
8127 {0x5ecc'5ac9, 0x46d4'42d1, 0x4edc'4ad8, 0x76e4'72e0},
8128 {0x7eec'7ae9, 0x66f4'62f1, 0x6efc'6af8, 0x40b4'0000}},
8129 {{0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8130 {0xae3c'aa38'a634'a231, 0xde4c'da49'd644'd240},
8131 {0xce5c'ca58'c654'c251, 0xfe6c'fa69'f664'f260},
8132 {0xee7c'ea78'e674'e271, 0x1e8c'1a89'1684'1280},
8133 {0x0e9c'0a98'0694'0291, 0x3eac'3aa9'36a4'32a0},
8134 {0x2ebc'2ab8'26b4'22b1, 0x5ecc'5ac9'56c4'52c0},
8135 {0x4edc'4ad8'46d4'42d1, 0x7eec'7ae9'76e4'72e0},
8136 {0x6efc'6af8'66f4'62f1, 0x4016'8000'0000'0000}},
8137 kVectorCalculationsSource,
8138 /*vlmul=*/3,
8139 /*skip=*/0,
8140 /*ignore_vma_for_last=*/true,
8141 /*last_elem_is_f1=*/true);
8142
8143 // VLMUL = 4
8144 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8145 {{}, {}, {}, {}, {}, {}, {}, {}},
8146 {{}, {}, {}, {}, {}, {}, {}, {}},
8147 kVectorCalculationsSource,
8148 /*vlmul=*/4,
8149 /*skip=*/0,
8150 /*ignore_vma_for_last=*/true,
8151 /*last_elem_is_f1=*/true);
8152
8153 // VLMUL = 5
8154 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8155 {{}, {}, {}, {}, {}, {}, {}, {}},
8156 {{}, {}, {}, {}, {}, {}, {}, {}},
8157 kVectorCalculationsSource,
8158 /*vlmul=*/5,
8159 /*skip=*/0,
8160 /*ignore_vma_for_last=*/true,
8161 /*last_elem_is_f1=*/true);
8162
8163 // VLMUL = 6
8164 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8165 {{0x40b4'0000, 0, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8166 {{}, {}, {}, {}, {}, {}, {}, {}},
8167 kVectorCalculationsSource,
8168 /*vlmul=*/6,
8169 /*skip=*/0,
8170 /*ignore_vma_for_last=*/true,
8171 /*last_elem_is_f1=*/true);
8172
8173 // VLMUL = 7
8174 TestVectorFloatPermutationInstruction(
8175 0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8176 {{0x9e0c'9a09, 0x40b4'0000, 0, 0}, {}, {}, {}, {}, {}, {}, {}},
8177 {{0x4016'8000'0000'0000, 0}, {}, {}, {}, {}, {}, {}, {}},
8178 kVectorCalculationsSource,
8179 /*vlmul=*/7,
8180 /*skip=*/0,
8181 /*ignore_vma_for_last=*/true,
8182 /*last_elem_is_f1=*/true);
8183 }
8184
TEST_F(Riscv64InterpreterTest,TestVseXX)8185 TEST_F(Riscv64InterpreterTest, TestVseXX) {
8186 TestVseXX(0x8427, // vse8.v v8, (x1), v0.t
8187 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
8188 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
8189 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
8190 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191},
8191 {64, 193, 66, 195, 68, 197, 70, 199, 72, 201, 74, 203, 76, 205, 78, 207},
8192 {80, 209, 82, 211, 84, 213, 86, 215, 88, 217, 90, 219, 92, 221, 94, 223},
8193 {96, 225, 98, 227, 100, 229, 102, 231, 104, 233, 106, 235, 108, 237, 110, 239},
8194 {112, 241, 114, 243, 116, 245, 118, 247, 120, 249, 122, 251, 124, 253, 126, 255}},
8195 {},
8196 {},
8197 {},
8198 0,
8199 kVectorCalculationsSourceLegacy);
8200 TestVseXX(0xd427, // vse16.v v8, (x1), v0.t
8201 {},
8202 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
8203 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
8204 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
8205 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e},
8206 {0xc140, 0xc342, 0xc544, 0xc746, 0xc948, 0xcb4a, 0xcd4c, 0xcf4e},
8207 {0xd150, 0xd352, 0xd554, 0xd756, 0xd958, 0xdb5a, 0xdd5c, 0xdf5e},
8208 {0xe160, 0xe362, 0xe564, 0xe766, 0xe968, 0xeb6a, 0xed6c, 0xef6e},
8209 {0xf170, 0xf372, 0xf574, 0xf776, 0xf978, 0xfb7a, 0xfd7c, 0xff7e}},
8210 {},
8211 {},
8212 1,
8213 kVectorCalculationsSourceLegacy);
8214 TestVseXX(0xe427, // vse32.v v8, (x1), v0.t
8215 {},
8216 {},
8217 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
8218 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
8219 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
8220 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
8221 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
8222 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
8223 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
8224 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
8225 {},
8226 2,
8227 kVectorCalculationsSourceLegacy);
8228 TestVseXX(0xf427, // vse64.v v8, (x1), v0.t
8229 {},
8230 {},
8231 {},
8232 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
8233 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
8234 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
8235 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
8236 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
8237 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
8238 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
8239 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
8240 3,
8241 kVectorCalculationsSourceLegacy);
8242 }
8243
TEST_F(Riscv64InterpreterTest,TestVleXX)8244 TEST_F(Riscv64InterpreterTest, TestVleXX) {
8245 TestVleXX(0x8407, // vle8.v v8, (x1), v0.t
8246 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
8247 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
8248 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
8249 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191},
8250 {64, 193, 66, 195, 68, 197, 70, 199, 72, 201, 74, 203, 76, 205, 78, 207},
8251 {80, 209, 82, 211, 84, 213, 86, 215, 88, 217, 90, 219, 92, 221, 94, 223},
8252 {96, 225, 98, 227, 100, 229, 102, 231, 104, 233, 106, 235, 108, 237, 110, 239},
8253 {112, 241, 114, 243, 116, 245, 118, 247, 120, 249, 122, 251, 124, 253, 126, 255}},
8254 {},
8255 {},
8256 {},
8257 0,
8258 kVectorCalculationsSourceLegacy);
8259 TestVleXX(0xd407, // vle16.v v8, (x1), v0.t
8260 {},
8261 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
8262 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
8263 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
8264 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e},
8265 {0xc140, 0xc342, 0xc544, 0xc746, 0xc948, 0xcb4a, 0xcd4c, 0xcf4e},
8266 {0xd150, 0xd352, 0xd554, 0xd756, 0xd958, 0xdb5a, 0xdd5c, 0xdf5e},
8267 {0xe160, 0xe362, 0xe564, 0xe766, 0xe968, 0xeb6a, 0xed6c, 0xef6e},
8268 {0xf170, 0xf372, 0xf574, 0xf776, 0xf978, 0xfb7a, 0xfd7c, 0xff7e}},
8269 {},
8270 {},
8271 1,
8272 kVectorCalculationsSourceLegacy);
8273 TestVleXX(0xe407, // vle32.v v8, (x1), v0.t
8274 {},
8275 {},
8276 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
8277 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
8278 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
8279 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
8280 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
8281 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
8282 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
8283 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
8284 {},
8285 2,
8286 kVectorCalculationsSourceLegacy);
8287 TestVleXX(0xf407, // vle64.v v8, (x1), v0.t
8288 {},
8289 {},
8290 {},
8291 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
8292 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
8293 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
8294 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
8295 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
8296 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
8297 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
8298 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
8299 3,
8300 kVectorCalculationsSourceLegacy);
8301 }
8302
TEST_F(Riscv64InterpreterTest,TestVleXXff)8303 TEST_F(Riscv64InterpreterTest, TestVleXXff) {
8304 TestVleXXff(0x1008407, 6, 0, 6); // vle8ff.v v8, (x1), v0.t
8305 TestVleXXff(0x1008407, 8, 0, 8);
8306 TestVleXXff(0x1008407, 16, 0, 16);
8307 TestVleXXff(0x1008407, 32, 0, 32);
8308 TestVleXXff(0x1008407, 255, 0, 128); // All 128 bytes accessible.
8309
8310 TestVleXXff(0x100d407, 6, 1, 3); // vle16ff.v v8, (x1), v0.t
8311 TestVleXXff(0x100d407, 8, 1, 4);
8312 TestVleXXff(0x100d407, 16, 1, 8);
8313 TestVleXXff(0x100d407, 32, 1, 16);
8314
8315 TestVleXXff(0x100e407, 6, 2, 1); // vle32ff.v v8, (x1), v0.t
8316 TestVleXXff(0x100e407, 8, 2, 2);
8317 TestVleXXff(0x100e407, 16, 2, 4);
8318 TestVleXXff(0x100e407, 32, 2, 8);
8319 TestVleXXff(0x100e407, 64, 2, 16);
8320
8321 TestVleXXff(0x100f407, 8, 3, 1); // vle64ff.v v8, (x1), v0.t
8322 TestVleXXff(0x100f407, 16, 3, 2);
8323 TestVleXXff(0x100f407, 32, 3, 4);
8324 TestVleXXff(0x100f407, 64, 3, 8);
8325
8326 TestVleXXff(0x100f407, 6, 3, 16, true); // Should raise exception and not change VL
8327 }
8328
TEST_F(Riscv64InterpreterTest,TestVcpopm)8329 TEST_F(Riscv64InterpreterTest, TestVcpopm) {
8330 TestVXmXXsInstruction(
8331 0x410820d7, // vcpop.m x1, v16, v0.t
8332 { 0, /* default value when vl=0 */
8333 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2,
8334 2, 3, 3, 3, 3, 3, 3, 3, 4, 5, 5, 5, 5, 5, 5, 6,
8335 6, 6, 7, 7, 7, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 10,
8336 10, 11, 12, 12, 12, 12, 12, 12, 13, 14, 15, 15, 15, 15, 15, 16,
8337 16, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 19, 19, 19, 19, 20,
8338 20, 21, 21, 22, 22, 22, 22, 22, 23, 24, 24, 25, 25, 25, 25, 26,
8339 26, 26, 27, 28, 28, 28, 28, 28, 29, 29, 30, 31, 31, 31, 31, 32,
8340 32, 33, 34, 35, 35, 35, 35, 35, 36, 37, 38, 39, 39, 39, 39, 40},
8341 { 0, /* default value when vl=0 */
8342 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2,
8343 2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 5,
8344 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 8,
8345 8, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 11, 11, 11, 12,
8346 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14,
8347 14, 14, 14, 15, 15, 15, 15, 15, 15, 16, 16, 17, 17, 17, 17, 18,
8348 18, 18, 18, 19, 19, 19, 19, 19, 20, 20, 21, 21, 21, 21, 21, 21,
8349 21, 22, 23, 23, 23, 23, 23, 23, 23, 24, 24, 25, 25, 25, 25, 25},
8350 kVectorCalculationsSourceLegacy[0]);
8351 }
8352
TEST_F(Riscv64InterpreterTest,TestVfirstm)8353 TEST_F(Riscv64InterpreterTest, TestVfirstm) {
8354 TestVXmXXsInstruction(
8355 0x4108a0d7, // vfirst.m x1, v16, v0.t
8356 { [0 ... 8] = ~0ULL,
8357 [9 ... 128] = 8 },
8358 { [0 ... 8] = ~0ULL,
8359 [9 ... 128] = 8 },
8360 kVectorCalculationsSourceLegacy[0]);
8361 }
8362
8363 // For Vrgather the expectations for different VLMULs are very different, i.e. different vlmax
8364 // values produce different results for the same src. So we have to call each of them explicitly.
8365 // To produce none-all-zero expected_results, all registers index vectors(v24) have first half
8366 // masked to have valid indexes (< vlmax); x1 is masked to be < vlmax; uimm is accordingly to be 0,
8367 // 1 or 3.
TEST_F(Riscv64InterpreterTest,TestVrgather)8368 TEST_F(Riscv64InterpreterTest, TestVrgather) {
8369 // VLMUL = 0
8370 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8371 {{0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8372 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8373 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8374 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8375 {0, 2, 4, 6, 137, 10, 12, 14, 0, 2, 0, 6, 0, 10, 0, 14},
8376 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8377 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8378 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0}},
8379 {{0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8380 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8381 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8382 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8383 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8384 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8385 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8386 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000}},
8387 {{0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8388 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8389 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8390 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8391 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8392 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8393 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8394 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000}},
8395 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8396 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8397 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8398 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8399 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8400 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8401 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8402 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
8403 /*vlmul=*/0,
8404 kVectorCalculationsSource);
8405
8406 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8407 {{10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8408 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8409 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8410 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8411 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8412 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8413 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8414 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}},
8415 {{0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8416 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8417 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8418 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8419 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8420 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8421 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8422 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504}},
8423 {{0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8424 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8425 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8426 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8427 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8428 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8429 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8430 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908}},
8431 {{0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8432 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8433 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8434 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8435 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8436 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8437 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8438 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100}},
8439 /*vlmul=*/0,
8440 kVectorCalculationsSource);
8441 TestVectorRegisterGather(
8442 0x3100b457, // vrgather.vi v8,v16,1,v0.t
8443 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8444 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8445 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8446 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8447 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8448 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8449 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8450 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
8451 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8452 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8453 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8454 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8455 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8456 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8457 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8458 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
8459 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8460 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8461 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8462 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8463 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8464 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8465 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8466 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
8467 {{0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8468 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8469 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8470 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8471 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8472 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8473 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8474 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908}},
8475 /*vlmul=*/0,
8476 kVectorCalculationsSource);
8477
8478 // VLMUL = 1
8479 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8480 {{0, 18, 4, 22, 137, 26, 12, 30, 145, 0, 20, 0, 24, 0, 28, 0},
8481 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8482 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8483 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8484 {0, 18, 4, 22, 137, 26, 12, 30, 0, 2, 0, 6, 0, 10, 0, 14},
8485 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8486 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8487 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0}},
8488 {{0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8489 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8490 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8491 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8492 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8493 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8494 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8495 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000}},
8496 {{0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8497 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8498 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8499 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8500 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8501 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8502 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8503 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000}},
8504 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8505 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8506 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8507 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8508 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8509 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8510 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8511 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
8512 /*vlmul=*/1,
8513 kVectorCalculationsSource);
8514 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8515 {{10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8516 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8517 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8518 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8519 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8520 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8521 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8522 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}},
8523 {{0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8524 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8525 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8526 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8527 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8528 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8529 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8530 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514}},
8531 {{0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8532 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8533 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8534 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8535 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8536 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8537 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8538 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908}},
8539 {{0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8540 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8541 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8542 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8543 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8544 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8545 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8546 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110}},
8547 /*vlmul=*/1,
8548 kVectorCalculationsSource);
8549 TestVectorRegisterGather(
8550 0x3100b457, // vrgather.vi v8,v16,1,v0.t
8551 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8552 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8553 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8554 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8555 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8556 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8557 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8558 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
8559 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8560 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8561 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8562 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8563 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8564 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8565 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8566 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
8567 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8568 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8569 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8570 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8571 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8572 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8573 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8574 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
8575 {{0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8576 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8577 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8578 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8579 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8580 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8581 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8582 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908}},
8583 /*vlmul=*/1,
8584 kVectorCalculationsSource);
8585
8586 // VLMUL = 2
8587 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8588 {{0, 18, 4, 22, 137, 26, 12, 30, 145, 0, 20, 0, 24, 0, 28, 0},
8589 {32, 50, 36, 54, 169, 58, 44, 62, 177, 0, 52, 0, 56, 0, 60, 0},
8590 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8591 {32, 50, 36, 54, 169, 58, 44, 62, 0, 0, 0, 0, 0, 0, 0, 0},
8592 {0, 18, 4, 22, 137, 26, 12, 30, 0, 2, 0, 6, 0, 10, 0, 14},
8593 {32, 50, 36, 54, 169, 58, 44, 62, 0, 34, 0, 38, 0, 42, 0, 46},
8594 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
8595 {32, 50, 36, 54, 169, 58, 44, 62, 0, 0, 0, 0, 0, 0, 0, 0}},
8596 {{0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8597 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8598 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8599 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8600 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8601 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8602 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8603 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000}},
8604 {{0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8605 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8606 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8607 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8608 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8609 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8610 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8611 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000}},
8612 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8613 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8614 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8615 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8616 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8617 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8618 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8619 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
8620 /*vlmul=*/2,
8621 kVectorCalculationsSource);
8622 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8623 {{42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8624 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8625 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8626 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8627 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8628 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8629 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8630 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42}},
8631 {{0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8632 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8633 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8634 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8635 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8636 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8637 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
8638 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514}},
8639 {{0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8640 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8641 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8642 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8643 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8644 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8645 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8646 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928}},
8647 {{0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8648 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8649 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8650 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8651 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8652 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8653 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
8654 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110}},
8655 /*vlmul=*/2,
8656 kVectorCalculationsSource);
8657 TestVectorRegisterGather(
8658 0x3100b457, // vrgather.vi v8,v16,1,v0.t
8659 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8660 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8661 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8662 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8663 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8664 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8665 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8666 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
8667 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8668 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8669 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8670 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8671 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8672 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8673 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8674 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
8675 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8676 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8677 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8678 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8679 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8680 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8681 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
8682 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
8683 {{0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8684 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8685 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8686 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8687 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8688 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8689 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
8690 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908}},
8691 /*vlmul=*/2,
8692 kVectorCalculationsSource);
8693
8694 // VLMUL = 3
8695 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8696 {{0, 18, 4, 22, 137, 26, 12, 30, 145, 0, 20, 0, 24, 0, 28, 0},
8697 {32, 50, 36, 54, 169, 58, 44, 62, 177, 0, 52, 0, 56, 0, 60, 0},
8698 {64, 82, 68, 86, 201, 90, 76, 94, 209, 0, 84, 0, 88, 0, 92, 0},
8699 {96, 114, 100, 118, 233, 122, 108, 126, 241, 0, 116, 0, 120, 0, 124, 0},
8700 {0, 18, 4, 22, 137, 26, 12, 30, 0, 2, 0, 6, 0, 10, 0, 14},
8701 {32, 50, 36, 54, 169, 58, 44, 62, 0, 34, 0, 38, 0, 42, 0, 46},
8702 {64, 82, 68, 86, 201, 90, 76, 94, 0, 66, 0, 70, 0, 74, 0, 78},
8703 {96, 114, 100, 118, 233, 122, 108, 126, 0, 98, 0, 102, 0, 106, 0, 110}},
8704 {{0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8705 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000},
8706 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8707 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000},
8708 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8709 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000},
8710 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
8711 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000}},
8712 {{0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8713 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8714 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8715 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8716 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8717 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8718 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
8719 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000}},
8720 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8721 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8722 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8723 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8724 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8725 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8726 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8727 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
8728 /*vlmul=*/3,
8729 kVectorCalculationsSource);
8730 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8731 {{42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8732 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8733 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8734 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8735 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8736 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8737 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
8738 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42}},
8739 {{0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8740 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8741 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8742 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8743 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8744 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8745 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
8746 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554}},
8747 {{0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8748 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8749 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8750 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8751 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8752 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8753 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
8754 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928}},
8755 {{0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8756 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8757 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8758 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8759 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8760 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8761 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
8762 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150}},
8763 /*vlmul=*/3,
8764 kVectorCalculationsSource);
8765 TestVectorRegisterGather(
8766 0x3101b457, // vrgather.vi v8,v16,3,v0.t
8767 {{131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8768 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8769 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8770 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8771 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8772 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8773 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
8774 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131}},
8775 {{0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8776 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8777 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8778 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8779 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8780 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8781 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
8782 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706}},
8783 {{0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8784 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8785 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8786 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8787 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8788 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8789 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
8790 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c}},
8791 {{0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8792 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8793 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8794 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8795 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8796 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8797 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
8798 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918}},
8799 /*vlmul=*/3,
8800 kVectorCalculationsSource);
8801
8802 // VLMUL = 5
8803 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8804 {{0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8805 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8806 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8807 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8808 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8809 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8810 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8811 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
8812 {{0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8813 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8814 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8815 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8816 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8817 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8818 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8819 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000}},
8820 {},
8821 {},
8822 /*vlmul=*/5,
8823 kVectorCalculationsSource);
8824 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8825 {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8826 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8827 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8828 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8829 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8830 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8831 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
8832 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
8833 {{0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8834 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8835 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8836 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8837 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8838 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8839 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8840 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100}},
8841 {},
8842 {},
8843 /*vlmul=*/5,
8844 kVectorCalculationsSource);
8845 TestVectorRegisterGather(
8846 0x3100b457, // vrgather.vi v8,v16,1,v0.t
8847 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8848 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8849 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8850 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8851 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8852 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8853 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8854 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
8855 {{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8856 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8857 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8858 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8859 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8860 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8861 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
8862 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}},
8863 {},
8864 {},
8865 /*vlmul=*/5,
8866 kVectorCalculationsSource);
8867
8868 // VLMUL = 6
8869 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8870 {{0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
8871 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
8872 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
8873 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
8874 {0, 2, 0, 2, 129, 2, 0, 2, 0, 2, 0, 0, 0, 0, 0, 0},
8875 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
8876 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
8877 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}},
8878 {{0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8879 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8880 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8881 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8882 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8883 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8884 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8885 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000}},
8886 {{0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8887 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8888 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8889 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8890 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8891 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8892 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
8893 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000}},
8894 {},
8895 /*vlmul=*/6,
8896 kVectorCalculationsSource);
8897 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8898 {{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8899 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8900 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8901 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8902 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8903 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8904 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8905 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}},
8906 {{0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8907 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8908 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8909 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8910 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8911 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8912 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
8913 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100}},
8914 {{0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8915 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8916 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8917 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8918 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8919 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8920 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
8921 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100}},
8922 {},
8923 /*vlmul=*/6,
8924 kVectorCalculationsSource);
8925 TestVectorRegisterGather(
8926 0x3100b457, // vrgather.vi v8,v16,1,v0.t
8927 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8928 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8929 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8930 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8931 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8932 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8933 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8934 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
8935 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8936 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8937 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8938 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8939 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8940 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8941 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
8942 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
8943 {{0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8944 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8945 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8946 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8947 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8948 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8949 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
8950 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000}},
8951 {},
8952 /*vlmul=*/6,
8953 kVectorCalculationsSource);
8954
8955 // VLMUL = 7
8956 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8957 {{0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
8958 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
8959 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
8960 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
8961 {0, 2, 4, 6, 129, 2, 4, 6, 0, 2, 0, 6, 0, 0, 0, 0},
8962 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
8963 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
8964 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0}},
8965 {{0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8966 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8967 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8968 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8969 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8970 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8971 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
8972 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000}},
8973 {{0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8974 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8975 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8976 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8977 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8978 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8979 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8980 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000}},
8981 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8982 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8983 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8984 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8985 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8986 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8987 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8988 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
8989 /*vlmul=*/7,
8990 kVectorCalculationsSource);
8991 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8992 {{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8993 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8994 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8995 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8996 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8997 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8998 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
8999 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}},
9000 {{0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9001 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9002 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9003 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9004 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9005 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9006 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9007 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504}},
9008 {{0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9009 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9010 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9011 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9012 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9013 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9014 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9015 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100}},
9016 {{0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9017 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9018 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9019 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9020 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9021 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9022 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9023 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100}},
9024 /*vlmul=*/7,
9025 kVectorCalculationsSource);
9026 TestVectorRegisterGather(
9027 0x3100b457, // vrgather.vi v8,v16,1,v0.t
9028 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9029 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9030 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9031 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9032 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9033 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9034 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9035 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9036 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9037 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9038 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9039 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9040 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9041 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9042 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9043 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
9044 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9045 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9046 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9047 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9048 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9049 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9050 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9051 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
9052 {{0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9053 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9054 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9055 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9056 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9057 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9058 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9059 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000}},
9060 /*vlmul=*/7,
9061 kVectorCalculationsSource);
9062 }
9063
TEST_F(Riscv64InterpreterTest,TestVadc)9064 TEST_F(Riscv64InterpreterTest, TestVadc) {
9065 TestVectorCarryInstruction(
9066 0x410c0457, // vadc.vvm v8,v16,v24,v0
9067 {{1, 19, 7, 26, 13, 32, 18, 38, 26, 11, 31, 17, 37, 24, 42, 30},
9068 {49, 68, 54, 74, 61, 80, 67, 85, 74, 59, 79, 66, 84, 72, 90, 78},
9069 {97, 115, 103, 121, 110, 128, 114, 134, 121, 108, 127, 113, 133, 119, 139, 126},
9070 {145, 163, 151, 170, 157, 176, 162, 182, 170, 155, 175, 161, 181, 167, 187, 174},
9071 {193, 211, 199, 217, 206, 224, 210, 230, 218, 204, 222, 210, 229, 216, 235, 221},
9072 {241, 3, 247, 10, 253, 16, 3, 22, 9, 252, 15, 2, 21, 7, 27, 14},
9073 {33, 52, 38, 58, 46, 64, 50, 70, 58, 44, 63, 49, 69, 55, 75, 61},
9074 {81, 100, 87, 105, 94, 112, 99, 118, 105, 92, 110, 98, 116, 104, 123, 109}},
9075 {{0x1301, 0x1906, 0x1f0e, 0x2513, 0x0b19, 0x111f, 0x1724, 0x1d2b},
9076 {0x4331, 0x4936, 0x4f3e, 0x5542, 0x3b4a, 0x414f, 0x4754, 0x4d5b},
9077 {0x7361, 0x7967, 0x7f6d, 0x8573, 0x6b79, 0x717f, 0x7785, 0x7d8a},
9078 {0xa391, 0xa996, 0xaf9e, 0xb5a3, 0x9ba9, 0xa1af, 0xa7b4, 0xadbb},
9079 {0xd3c1, 0xd9c6, 0xdfce, 0xe5d2, 0xcbda, 0xd1df, 0xd7e4, 0xddeb},
9080 {0x03f0, 0x09f7, 0x0ffe, 0x1602, 0xfc0a, 0x020e, 0x0815, 0x0e1b},
9081 {0x3421, 0x3a26, 0x402e, 0x4633, 0x2c39, 0x323f, 0x3844, 0x3e4b},
9082 {0x6451, 0x6a56, 0x705e, 0x7662, 0x5c6a, 0x626e, 0x6875, 0x6e7b}},
9083 {{0x1907'1301, 0x2513'1f0d, 0x111f'0b1a, 0x1d2b'1725},
9084 {0x4937'4330, 0x5543'4f3e, 0x414f'3b49, 0x4d5b'4755},
9085 {0x7967'7361, 0x8573'7f6d, 0x717f'6b7a, 0x7d8b'7784},
9086 {0xa997'a391, 0xb5a3'af9e, 0xa1af'9ba9, 0xadbb'a7b5},
9087 {0xd9c6'd3c1, 0xe5d2'dfce, 0xd1de'cbd9, 0xddea'd7e5},
9088 {0x09f7'03f0, 0x1603'0ffe, 0x020e'fc0a, 0x0e1b'0814},
9089 {0x3a27'3421, 0x4633'402d, 0x323f'2c3a, 0x3e4b'3845},
9090 {0x6a57'6450, 0x7663'705e, 0x626f'5c69, 0x6e7b'6875}},
9091 {{0x2513'1f0e'1907'1301, 0x1d2b'1725'111f'0b19},
9092 {0x5543'4f3e'4937'4331, 0x4d5b'4755'414f'3b4a},
9093 {0x8573'7f6e'7967'7360, 0x7d8b'7785'717f'6b7a},
9094 {0xb5a3'af9e'a997'a390, 0xadbb'a7b5'a1af'9baa},
9095 {0xe5d2'dfcd'd9c6'd3c1, 0xddea'd7e4'd1de'cbd9},
9096 {0x1603'0ffe'09f7'03f1, 0x0e1b'0815'020e'fc09},
9097 {0x4633'402e'3a27'3421, 0x3e4b'3845'323f'2c3a},
9098 {0x7663'705e'6a57'6450, 0x6e7b'6875'626f'5c6a}},
9099 kVectorCalculationsSource);
9100
9101 TestVectorCarryInstruction(
9102 0x4100c457, // vadc.vxm v8,v16,x1,v0
9103 {{171, 43, 173, 46, 174, 48, 176, 50, 179, 51, 181, 53, 183, 56, 184, 58},
9104 {187, 60, 188, 62, 190, 64, 193, 65, 195, 67, 197, 70, 198, 72, 200, 74},
9105 {203, 75, 205, 77, 207, 80, 208, 82, 210, 84, 213, 85, 215, 87, 217, 90},
9106 {219, 91, 221, 94, 222, 96, 224, 98, 227, 99, 229, 101, 231, 103, 233, 106},
9107 {235, 107, 237, 109, 239, 112, 240, 114, 243, 116, 244, 118, 247, 120, 249, 121},
9108 {251, 123, 253, 126, 254, 128, 1, 130, 2, 132, 5, 134, 7, 135, 9, 138},
9109 {11, 140, 12, 142, 15, 144, 16, 146, 19, 148, 21, 149, 23, 151, 25, 153},
9110 {27, 156, 29, 157, 31, 160, 33, 162, 34, 164, 36, 166, 38, 168, 41, 169}},
9111 {{0x2bab, 0x2dac, 0x2faf, 0x31b1, 0x33b2, 0x35b5, 0x37b6, 0x39b9},
9112 {0x3bbb, 0x3dbc, 0x3fbf, 0x41c0, 0x43c3, 0x45c5, 0x47c6, 0x49c9},
9113 {0x4bcb, 0x4dcd, 0x4fce, 0x51d1, 0x53d2, 0x55d5, 0x57d7, 0x59d8},
9114 {0x5bdb, 0x5ddc, 0x5fdf, 0x61e1, 0x63e2, 0x65e5, 0x67e6, 0x69e9},
9115 {0x6beb, 0x6dec, 0x6fef, 0x71f0, 0x73f3, 0x75f5, 0x77f6, 0x79f9},
9116 {0x7bfa, 0x7dfd, 0x7fff, 0x8200, 0x8403, 0x8604, 0x8807, 0x8a09},
9117 {0x8c0b, 0x8e0c, 0x900f, 0x9211, 0x9412, 0x9615, 0x9816, 0x9a19},
9118 {0x9c1b, 0x9e1c, 0xa01f, 0xa220, 0xa423, 0xa624, 0xa827, 0xaa29}},
9119 {{0x2dad'2bab, 0x31b1'2fae, 0x35b5'33b3, 0x39b9'37b7},
9120 {0x3dbd'3bba, 0x41c1'3fbf, 0x45c5'43c2, 0x49c9'47c7},
9121 {0x4dcd'4bcb, 0x51d1'4fce, 0x55d5'53d3, 0x59d9'57d6},
9122 {0x5ddd'5bdb, 0x61e1'5fdf, 0x65e5'63e2, 0x69e9'67e7},
9123 {0x6ded'6beb, 0x71f1'6fef, 0x75f5'73f2, 0x79f9'77f7},
9124 {0x7dfd'7bfa, 0x8201'7fff, 0x8605'8403, 0x8a09'8806},
9125 {0x8e0d'8c0b, 0x9211'900e, 0x9615'9413, 0x9a19'9817},
9126 {0x9e1d'9c1a, 0xa221'a01f, 0xa625'a422, 0xaa29'a827}},
9127 {{0x31b1'2faf'2dad'2bab, 0x39b9'37b7'35b5'33b2},
9128 {0x41c1'3fbf'3dbd'3bbb, 0x49c9'47c7'45c5'43c3},
9129 {0x51d1'4fcf'4dcd'4bca, 0x59d9'57d7'55d5'53d3},
9130 {0x61e1'5fdf'5ddd'5bda, 0x69e9'67e7'65e5'63e3},
9131 {0x71f1'6fef'6ded'6beb, 0x79f9'77f7'75f5'73f2},
9132 {0x8201'7fff'7dfd'7bfb, 0x8a09'8807'8605'8402},
9133 {0x9211'900f'8e0d'8c0b, 0x9a19'9817'9615'9413},
9134 {0xa221'a01f'9e1d'9c1a, 0xaa29'a827'a625'a423}},
9135 kVectorCalculationsSource);
9136
9137 TestVectorCarryInstruction(
9138 0x4105b457, // vadc.vim v8,v16,0xb,v0
9139 {{12, 140, 14, 143, 15, 145, 17, 147, 20, 148, 22, 150, 24, 153, 25, 155},
9140 {28, 157, 29, 159, 31, 161, 34, 162, 36, 164, 38, 167, 39, 169, 41, 171},
9141 {44, 172, 46, 174, 48, 177, 49, 179, 51, 181, 54, 182, 56, 184, 58, 187},
9142 {60, 188, 62, 191, 63, 193, 65, 195, 68, 196, 70, 198, 72, 200, 74, 203},
9143 {76, 204, 78, 206, 80, 209, 81, 211, 84, 213, 85, 215, 88, 217, 90, 218},
9144 {92, 220, 94, 223, 95, 225, 98, 227, 99, 229, 102, 231, 104, 232, 106, 235},
9145 {108, 237, 109, 239, 112, 241, 113, 243, 116, 245, 118, 246, 120, 248, 122, 250},
9146 {124, 253, 126, 254, 128, 1, 130, 3, 131, 5, 133, 7, 135, 9, 138, 10}},
9147 {{0x810c, 0x830d, 0x8510, 0x8712, 0x8913, 0x8b16, 0x8d17, 0x8f1a},
9148 {0x911c, 0x931d, 0x9520, 0x9721, 0x9924, 0x9b26, 0x9d27, 0x9f2a},
9149 {0xa12c, 0xa32e, 0xa52f, 0xa732, 0xa933, 0xab36, 0xad38, 0xaf39},
9150 {0xb13c, 0xb33d, 0xb540, 0xb742, 0xb943, 0xbb46, 0xbd47, 0xbf4a},
9151 {0xc14c, 0xc34d, 0xc550, 0xc751, 0xc954, 0xcb56, 0xcd57, 0xcf5a},
9152 {0xd15b, 0xd35e, 0xd560, 0xd761, 0xd964, 0xdb65, 0xdd68, 0xdf6a},
9153 {0xe16c, 0xe36d, 0xe570, 0xe772, 0xe973, 0xeb76, 0xed77, 0xef7a},
9154 {0xf17c, 0xf37d, 0xf580, 0xf781, 0xf984, 0xfb85, 0xfd88, 0xff8a}},
9155 {{0x8302'810c, 0x8706'850f, 0x8b0a'8914, 0x8f0e'8d18},
9156 {0x9312'911b, 0x9716'9520, 0x9b1a'9923, 0x9f1e'9d28},
9157 {0xa322'a12c, 0xa726'a52f, 0xab2a'a934, 0xaf2e'ad37},
9158 {0xb332'b13c, 0xb736'b540, 0xbb3a'b943, 0xbf3e'bd48},
9159 {0xc342'c14c, 0xc746'c550, 0xcb4a'c953, 0xcf4e'cd58},
9160 {0xd352'd15b, 0xd756'd560, 0xdb5a'd964, 0xdf5e'dd67},
9161 {0xe362'e16c, 0xe766'e56f, 0xeb6a'e974, 0xef6e'ed78},
9162 {0xf372'f17b, 0xf776'f580, 0xfb7a'f983, 0xff7e'fd88}},
9163 {{0x8706'8504'8302'810c, 0x8f0e'8d0c'8b0a'8913},
9164 {0x9716'9514'9312'911c, 0x9f1e'9d1c'9b1a'9924},
9165 {0xa726'a524'a322'a12b, 0xaf2e'ad2c'ab2a'a934},
9166 {0xb736'b534'b332'b13b, 0xbf3e'bd3c'bb3a'b944},
9167 {0xc746'c544'c342'c14c, 0xcf4e'cd4c'cb4a'c953},
9168 {0xd756'd554'd352'd15c, 0xdf5e'dd5c'db5a'd963},
9169 {0xe766'e564'e362'e16c, 0xef6e'ed6c'eb6a'e974},
9170 {0xf776'f574'f372'f17b, 0xff7e'fd7c'fb7a'f984}},
9171 kVectorCalculationsSource);
9172 }
9173
TEST_F(Riscv64InterpreterTest,TestVsbc)9174 TEST_F(Riscv64InterpreterTest, TestVsbc) {
9175 TestVectorCarryInstruction(
9176 0x490c0457, // vsb.vvm v8,v16,v24,v0
9177 {{255, 17, 1, 18, 5, 20, 6, 22, 8, 249, 9, 251, 11, 252, 14, 254},
9178 {15, 32, 18, 34, 21, 36, 21, 39, 24, 9, 25, 10, 28, 12, 30, 14},
9179 {31, 49, 33, 51, 36, 52, 38, 54, 41, 24, 41, 27, 43, 29, 45, 30},
9180 {47, 65, 49, 66, 53, 68, 54, 70, 56, 41, 57, 43, 59, 45, 61, 46},
9181 {63, 81, 65, 83, 68, 84, 70, 86, 72, 56, 74, 58, 75, 60, 77, 63},
9182 {79, 97, 81, 98, 85, 100, 85, 102, 89, 72, 89, 74, 91, 77, 93, 78},
9183 {95, 112, 98, 114, 100, 116, 102, 118, 104, 88, 105, 91, 107, 93, 109, 95},
9184 {111, 128, 113, 131, 116, 132, 117, 134, 121, 104, 122, 106, 124, 108, 125, 111}},
9185 {{0x10ff, 0x1302, 0x1504, 0x1705, 0xf909, 0xfb09, 0xfd0c, 0xff0d},
9186 {0x210f, 0x2312, 0x2514, 0x2716, 0x0918, 0x0b19, 0x0d1c, 0x0f1d},
9187 {0x311f, 0x3321, 0x3525, 0x3725, 0x1929, 0x1b29, 0x1d2b, 0x1f2e},
9188 {0x412f, 0x4332, 0x4534, 0x4735, 0x2939, 0x2b39, 0x2d3c, 0x2f3d},
9189 {0x513f, 0x5342, 0x5544, 0x5746, 0x3948, 0x3b49, 0x3d4c, 0x3f4d},
9190 {0x6150, 0x6351, 0x6554, 0x6756, 0x4958, 0x4b5a, 0x4d5b, 0x4f5d},
9191 {0x715f, 0x7362, 0x7564, 0x7765, 0x5969, 0x5b69, 0x5d6c, 0x5f6d},
9192 {0x816f, 0x8372, 0x8574, 0x8776, 0x6978, 0x6b7a, 0x6d7b, 0x6f7d}},
9193 {{0x1302'10ff, 0x1706'1505, 0xfb09'f908, 0xff0d'fd0b},
9194 {0x2312'2110, 0x2716'2514, 0x0b1a'0919, 0x0f1e'0d1b},
9195 {0x3322'311f, 0x3726'3525, 0x1b2a'1928, 0x1f2e'1d2c},
9196 {0x4332'412f, 0x4736'4534, 0x2b3a'2939, 0x2f3e'2d3b},
9197 {0x5341'513f, 0x5745'5544, 0x3b49'3949, 0x3f4d'3d4b},
9198 {0x6351'6150, 0x6755'6554, 0x4b59'4958, 0x4f5d'4d5c},
9199 {0x7361'715f, 0x7765'7565, 0x5b69'5968, 0x5f6d'5d6b},
9200 {0x8371'8170, 0x8775'8574, 0x6b79'6979, 0x6f7d'6d7b}},
9201 {{0x1706'1505'1302'10ff, 0xff0d'fd0b'fb09'f909},
9202 {0x2716'2515'2312'210f, 0x0f1e'0d1c'0b1a'0918},
9203 {0x3726'3525'3322'3120, 0x1f2e'1d2c'1b2a'1928},
9204 {0x4736'4535'4332'4130, 0x2f3e'2d3c'2b3a'2938},
9205 {0x5745'5544'5341'513f, 0x3f4d'3d4b'3b49'3949},
9206 {0x6755'6554'6351'614f, 0x4f5d'4d5b'4b59'4959},
9207 {0x7765'7564'7361'715f, 0x5f6d'5d6b'5b69'5968},
9208 {0x8775'8574'8371'8170, 0x6f7d'6d7b'6b79'6978}},
9209 kVectorCalculationsSource);
9210
9211 TestVectorCarryInstruction(
9212 0x4900c457, // vsbc.vxm v8,v16,x1,v0
9213 {{169, 41, 167, 38, 166, 36, 164, 34, 161, 33, 159, 31, 157, 28, 156, 26},
9214 {153, 24, 152, 22, 150, 20, 147, 19, 145, 17, 143, 14, 142, 12, 140, 10},
9215 {137, 9, 135, 7, 133, 4, 132, 2, 130, 0, 127, 255, 125, 253, 123, 250},
9216 {121, 249, 119, 246, 118, 244, 116, 242, 113, 241, 111, 239, 109, 237, 107, 234},
9217 {105, 233, 103, 231, 101, 228, 100, 226, 97, 224, 96, 222, 93, 220, 91, 219},
9218 {89, 217, 87, 214, 86, 212, 83, 210, 82, 208, 79, 206, 77, 205, 75, 202},
9219 {73, 200, 72, 198, 69, 196, 68, 194, 65, 192, 63, 191, 61, 189, 59, 187},
9220 {57, 184, 55, 183, 53, 180, 51, 178, 50, 176, 48, 174, 46, 172, 43, 171}},
9221 {{0x29a9, 0x27a8, 0x25a5, 0x23a3, 0x21a2, 0x1f9f, 0x1d9e, 0x1b9b},
9222 {0x1999, 0x1798, 0x1595, 0x1394, 0x1191, 0x0f8f, 0x0d8e, 0x0b8b},
9223 {0x0989, 0x0787, 0x0586, 0x0383, 0x0182, 0xff7f, 0xfd7d, 0xfb7c},
9224 {0xf979, 0xf778, 0xf575, 0xf373, 0xf172, 0xef6f, 0xed6e, 0xeb6b},
9225 {0xe969, 0xe768, 0xe565, 0xe364, 0xe161, 0xdf5f, 0xdd5e, 0xdb5b},
9226 {0xd95a, 0xd757, 0xd555, 0xd354, 0xd151, 0xcf50, 0xcd4d, 0xcb4b},
9227 {0xc949, 0xc748, 0xc545, 0xc343, 0xc142, 0xbf3f, 0xbd3e, 0xbb3b},
9228 {0xb939, 0xb738, 0xb535, 0xb334, 0xb131, 0xaf30, 0xad2d, 0xab2b}},
9229 {{0x27a8'29a9, 0x23a4'25a6, 0x1fa0'21a1, 0x1b9c'1d9d},
9230 {0x1798'199a, 0x1394'1595, 0x0f90'1192, 0x0b8c'0d8d},
9231 {0x0788'0989, 0x0384'0586, 0xff80'0181, 0xfb7b'fd7e},
9232 {0xf777'f979, 0xf373'f575, 0xef6f'f172, 0xeb6b'ed6d},
9233 {0xe767'e969, 0xe363'e565, 0xdf5f'e162, 0xdb5b'dd5d},
9234 {0xd757'd95a, 0xd353'd555, 0xcf4f'd151, 0xcb4b'cd4e},
9235 {0xc747'c949, 0xc343'c546, 0xbf3f'c141, 0xbb3b'bd3d},
9236 {0xb737'b93a, 0xb333'b535, 0xaf2f'b132, 0xab2b'ad2d}},
9237 {{0x23a4'25a6'27a8'29a9, 0x1b9c'1d9e'1fa0'21a2},
9238 {0x1394'1596'1798'1999, 0x0b8c'0d8e'0f90'1191},
9239 {0x0384'0586'0788'098a, 0xfb7b'fd7d'ff80'0181},
9240 {0xf373'f575'f777'f97a, 0xeb6b'ed6d'ef6f'f171},
9241 {0xe363'e565'e767'e969, 0xdb5b'dd5d'df5f'e162},
9242 {0xd353'd555'd757'd959, 0xcb4b'cd4d'cf4f'd152},
9243 {0xc343'c545'c747'c949, 0xbb3b'bd3d'bf3f'c141},
9244 {0xb333'b535'b737'b93a, 0xab2b'ad2d'af2f'b131}},
9245 kVectorCalculationsSource);
9246 }
9247 } // namespace
9248
9249 } // namespace berberis
9250