1 /************************************************************************** 2 * 3 * Copyright 2008 VMware, Inc. 4 * Copyright 2009-2010 VMware, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 **************************************************************************/ 28 29 #ifndef P_SHADER_TOKENS_H 30 #define P_SHADER_TOKENS_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 struct tgsi_header 38 { 39 unsigned HeaderSize : 8; 40 unsigned BodySize : 24; 41 }; 42 43 enum tgsi_processor_type { 44 TGSI_PROCESSOR_FRAGMENT, 45 TGSI_PROCESSOR_VERTEX, 46 TGSI_PROCESSOR_GEOMETRY, 47 TGSI_PROCESSOR_TESS_CTRL, 48 TGSI_PROCESSOR_TESS_EVAL, 49 TGSI_PROCESSOR_COMPUTE, 50 }; 51 52 struct tgsi_processor 53 { 54 unsigned Processor : 4; /* TGSI_PROCESSOR_ */ 55 unsigned Padding : 28; 56 }; 57 58 enum tgsi_token_type { 59 TGSI_TOKEN_TYPE_DECLARATION, 60 TGSI_TOKEN_TYPE_IMMEDIATE, 61 TGSI_TOKEN_TYPE_INSTRUCTION, 62 TGSI_TOKEN_TYPE_PROPERTY, 63 }; 64 65 struct tgsi_token 66 { 67 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_x */ 68 unsigned NrTokens : 8; /**< UINT */ 69 unsigned Padding : 20; 70 }; 71 72 enum tgsi_file_type { 73 TGSI_FILE_NULL =0, 74 TGSI_FILE_CONSTANT =1, 75 TGSI_FILE_INPUT =2, 76 TGSI_FILE_OUTPUT =3, 77 TGSI_FILE_TEMPORARY =4, 78 TGSI_FILE_SAMPLER =5, 79 TGSI_FILE_ADDRESS =6, 80 TGSI_FILE_IMMEDIATE =7, 81 TGSI_FILE_PREDICATE =8, 82 TGSI_FILE_SYSTEM_VALUE =9, 83 TGSI_FILE_IMAGE =10, 84 TGSI_FILE_SAMPLER_VIEW =11, 85 TGSI_FILE_BUFFER, 86 TGSI_FILE_MEMORY, 87 TGSI_FILE_HW_ATOMIC, 88 TGSI_FILE_COUNT /**< how many TGSI_FILE_ types */ 89 }; 90 91 92 #define TGSI_WRITEMASK_NONE 0x00 93 #define TGSI_WRITEMASK_X 0x01 94 #define TGSI_WRITEMASK_Y 0x02 95 #define TGSI_WRITEMASK_XY 0x03 96 #define TGSI_WRITEMASK_Z 0x04 97 #define TGSI_WRITEMASK_XZ 0x05 98 #define TGSI_WRITEMASK_YZ 0x06 99 #define TGSI_WRITEMASK_XYZ 0x07 100 #define TGSI_WRITEMASK_W 0x08 101 #define TGSI_WRITEMASK_XW 0x09 102 #define TGSI_WRITEMASK_YW 0x0A 103 #define TGSI_WRITEMASK_XYW 0x0B 104 #define TGSI_WRITEMASK_ZW 0x0C 105 #define TGSI_WRITEMASK_XZW 0x0D 106 #define TGSI_WRITEMASK_YZW 0x0E 107 #define TGSI_WRITEMASK_XYZW 0x0F 108 109 enum tgsi_interpolate_mode { 110 TGSI_INTERPOLATE_CONSTANT, 111 TGSI_INTERPOLATE_LINEAR, 112 TGSI_INTERPOLATE_PERSPECTIVE, 113 TGSI_INTERPOLATE_COLOR, /* special color case for smooth/flat */ 114 TGSI_INTERPOLATE_COUNT, 115 }; 116 117 enum tgsi_interpolate_loc { 118 TGSI_INTERPOLATE_LOC_CENTER, 119 TGSI_INTERPOLATE_LOC_CENTROID, 120 TGSI_INTERPOLATE_LOC_SAMPLE, 121 TGSI_INTERPOLATE_LOC_COUNT, 122 }; 123 124 #define TGSI_CYLINDRICAL_WRAP_X (1 << 0) 125 #define TGSI_CYLINDRICAL_WRAP_Y (1 << 1) 126 #define TGSI_CYLINDRICAL_WRAP_Z (1 << 2) 127 #define TGSI_CYLINDRICAL_WRAP_W (1 << 3) 128 129 enum tgsi_memory_type { 130 TGSI_MEMORY_TYPE_GLOBAL, /* OpenCL global */ 131 TGSI_MEMORY_TYPE_SHARED, /* OpenCL local / GLSL shared */ 132 TGSI_MEMORY_TYPE_PRIVATE, /* OpenCL private */ 133 TGSI_MEMORY_TYPE_INPUT, /* OpenCL kernel input params */ 134 TGSI_MEMORY_TYPE_COUNT, 135 }; 136 137 struct tgsi_declaration 138 { 139 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_DECLARATION */ 140 unsigned NrTokens : 8; /**< UINT */ 141 unsigned File : 4; /**< one of TGSI_FILE_x */ 142 unsigned UsageMask : 4; /**< bitmask of TGSI_WRITEMASK_x flags */ 143 unsigned Dimension : 1; /**< any extra dimension info? */ 144 unsigned Semantic : 1; /**< BOOL, any semantic info? */ 145 unsigned Interpolate : 1; /**< any interpolation info? */ 146 unsigned Invariant : 1; /**< invariant optimization? */ 147 unsigned Local : 1; /**< optimize as subroutine local variable? */ 148 unsigned Array : 1; /**< extra array info? */ 149 unsigned Atomic : 1; /**< atomic only? for TGSI_FILE_BUFFER */ 150 unsigned MemType : 2; /**< TGSI_MEMORY_TYPE_x for TGSI_FILE_MEMORY */ 151 unsigned Padding : 3; 152 }; 153 154 struct tgsi_declaration_range 155 { 156 unsigned First : 16; /**< UINT */ 157 unsigned Last : 16; /**< UINT */ 158 }; 159 160 struct tgsi_declaration_dimension 161 { 162 unsigned Index2D:16; /**< UINT */ 163 unsigned Padding:16; 164 }; 165 166 struct tgsi_declaration_interp 167 { 168 unsigned Interpolate : 4; /**< one of TGSI_INTERPOLATE_x */ 169 unsigned Location : 2; /**< one of TGSI_INTERPOLATE_LOC_x */ 170 unsigned CylindricalWrap:4; /**< TGSI_CYLINDRICAL_WRAP_x flags */ 171 unsigned Padding : 22; 172 }; 173 174 enum tgsi_semantic { 175 TGSI_SEMANTIC_POSITION, 176 TGSI_SEMANTIC_COLOR, 177 TGSI_SEMANTIC_BCOLOR, /**< back-face color */ 178 TGSI_SEMANTIC_FOG, 179 TGSI_SEMANTIC_PSIZE, 180 TGSI_SEMANTIC_GENERIC, 181 TGSI_SEMANTIC_NORMAL, 182 TGSI_SEMANTIC_FACE, 183 TGSI_SEMANTIC_EDGEFLAG, 184 TGSI_SEMANTIC_PRIMID, 185 TGSI_SEMANTIC_INSTANCEID, /**< doesn't include start_instance */ 186 TGSI_SEMANTIC_VERTEXID, 187 TGSI_SEMANTIC_STENCIL, 188 TGSI_SEMANTIC_CLIPDIST, 189 TGSI_SEMANTIC_CLIPVERTEX, 190 TGSI_SEMANTIC_GRID_SIZE, /**< grid size in blocks */ 191 TGSI_SEMANTIC_BLOCK_ID, /**< id of the current block */ 192 TGSI_SEMANTIC_BLOCK_SIZE, /**< block size in threads */ 193 TGSI_SEMANTIC_THREAD_ID, /**< block-relative id of the current thread */ 194 TGSI_SEMANTIC_TEXCOORD, /**< texture or sprite coordinates */ 195 TGSI_SEMANTIC_PCOORD, /**< point sprite coordinate */ 196 TGSI_SEMANTIC_VIEWPORT_INDEX, /**< viewport index */ 197 TGSI_SEMANTIC_LAYER, /**< layer (rendertarget index) */ 198 TGSI_SEMANTIC_CULLDIST, 199 TGSI_SEMANTIC_SAMPLEID, 200 TGSI_SEMANTIC_SAMPLEPOS, 201 TGSI_SEMANTIC_SAMPLEMASK, 202 TGSI_SEMANTIC_INVOCATIONID, 203 TGSI_SEMANTIC_VERTEXID_NOBASE, 204 TGSI_SEMANTIC_BASEVERTEX, 205 TGSI_SEMANTIC_PATCH, /**< generic per-patch semantic */ 206 TGSI_SEMANTIC_TESSCOORD, /**< coordinate being processed by tess */ 207 TGSI_SEMANTIC_TESSOUTER, /**< outer tessellation levels */ 208 TGSI_SEMANTIC_TESSINNER, /**< inner tessellation levels */ 209 TGSI_SEMANTIC_VERTICESIN, /**< number of input vertices */ 210 TGSI_SEMANTIC_HELPER_INVOCATION, /**< current invocation is helper */ 211 TGSI_SEMANTIC_COUNT, /**< number of semantic values */ 212 }; 213 214 struct tgsi_declaration_semantic 215 { 216 unsigned Name : 8; /**< one of TGSI_SEMANTIC_x */ 217 unsigned Index : 16; /**< UINT */ 218 unsigned StreamX : 2; /**< vertex stream (for GS output) */ 219 unsigned StreamY : 2; 220 unsigned StreamZ : 2; 221 unsigned StreamW : 2; 222 }; 223 224 struct tgsi_declaration_image { 225 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */ 226 unsigned Raw : 1; 227 unsigned Writable : 1; 228 unsigned Format : 10; /**< one of PIPE_FORMAT_ */ 229 unsigned Padding : 12; 230 }; 231 232 enum tgsi_return_type { 233 TGSI_RETURN_TYPE_UNORM = 0, 234 TGSI_RETURN_TYPE_SNORM, 235 TGSI_RETURN_TYPE_SINT, 236 TGSI_RETURN_TYPE_UINT, 237 TGSI_RETURN_TYPE_FLOAT, 238 TGSI_RETURN_TYPE_COUNT 239 }; 240 241 struct tgsi_declaration_sampler_view { 242 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */ 243 unsigned ReturnTypeX : 6; /**< one of enum tgsi_return_type */ 244 unsigned ReturnTypeY : 6; /**< one of enum tgsi_return_type */ 245 unsigned ReturnTypeZ : 6; /**< one of enum tgsi_return_type */ 246 unsigned ReturnTypeW : 6; /**< one of enum tgsi_return_type */ 247 }; 248 249 struct tgsi_declaration_array { 250 unsigned ArrayID : 10; 251 unsigned Padding : 22; 252 }; 253 254 /* 255 * Special resources that don't need to be declared. They map to the 256 * GLOBAL/LOCAL/PRIVATE/INPUT compute memory spaces. 257 */ 258 #define TGSI_RESOURCE_GLOBAL 0x7fff 259 #define TGSI_RESOURCE_LOCAL 0x7ffe 260 #define TGSI_RESOURCE_PRIVATE 0x7ffd 261 #define TGSI_RESOURCE_INPUT 0x7ffc 262 263 enum tgsi_imm_type { 264 TGSI_IMM_FLOAT32, 265 TGSI_IMM_UINT32, 266 TGSI_IMM_INT32, 267 TGSI_IMM_FLOAT64, 268 TGSI_IMM_UINT64, 269 TGSI_IMM_INT64, 270 }; 271 272 struct tgsi_immediate 273 { 274 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_IMMEDIATE */ 275 unsigned NrTokens : 14; /**< UINT */ 276 unsigned DataType : 4; /**< one of TGSI_IMM_x */ 277 unsigned Padding : 10; 278 }; 279 280 union tgsi_immediate_data 281 { 282 float Float; 283 unsigned Uint; 284 int Int; 285 }; 286 287 enum tgsi_property_name { 288 TGSI_PROPERTY_GS_INPUT_PRIM, 289 TGSI_PROPERTY_GS_OUTPUT_PRIM, 290 TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES, 291 TGSI_PROPERTY_FS_COORD_ORIGIN, 292 TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, 293 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 294 TGSI_PROPERTY_FS_DEPTH_LAYOUT, 295 TGSI_PROPERTY_VS_PROHIBIT_UCPS, 296 TGSI_PROPERTY_GS_INVOCATIONS, 297 TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, 298 TGSI_PROPERTY_TCS_VERTICES_OUT, 299 TGSI_PROPERTY_TES_PRIM_MODE, 300 TGSI_PROPERTY_TES_SPACING, 301 TGSI_PROPERTY_TES_VERTEX_ORDER_CW, 302 TGSI_PROPERTY_TES_POINT_MODE, 303 TGSI_PROPERTY_NUM_CLIPDIST_ENABLED, 304 TGSI_PROPERTY_NUM_CULLDIST_ENABLED, 305 TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 306 TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 307 TGSI_PROPERTY_NEXT_SHADER, 308 TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 309 TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 310 TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 311 TGSI_PROPERTY_MUL_ZERO_WINS, 312 TGSI_PROPERTY_VS_BLIT_SGPRS_AMD, 313 TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, 314 TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE, 315 TGSI_PROPERTY_FS_BLEND_EQUATION_ADVANCED, 316 TGSI_PROPERTY_SEPARABLE_PROGRAM, 317 TGSI_PROPERTY_COUNT, 318 }; 319 320 struct tgsi_property { 321 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_PROPERTY */ 322 unsigned NrTokens : 8; /**< UINT */ 323 unsigned PropertyName : 8; /**< one of TGSI_PROPERTY */ 324 unsigned Padding : 12; 325 }; 326 327 enum tgsi_fs_coord_origin { 328 TGSI_FS_COORD_ORIGIN_UPPER_LEFT, 329 TGSI_FS_COORD_ORIGIN_LOWER_LEFT, 330 }; 331 332 enum tgsi_fs_coord_pixcenter { 333 TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 334 TGSI_FS_COORD_PIXEL_CENTER_INTEGER, 335 }; 336 337 enum tgsi_fs_depth_layout { 338 TGSI_FS_DEPTH_LAYOUT_NONE, 339 TGSI_FS_DEPTH_LAYOUT_ANY, 340 TGSI_FS_DEPTH_LAYOUT_GREATER, 341 TGSI_FS_DEPTH_LAYOUT_LESS, 342 TGSI_FS_DEPTH_LAYOUT_UNCHANGED, 343 }; 344 345 struct tgsi_property_data { 346 unsigned Data; 347 }; 348 349 /* TGSI opcodes. 350 * 351 * For more information on semantics of opcodes and 352 * which APIs are known to use which opcodes, see 353 * gallium/docs/source/tgsi.rst 354 */ 355 /* VIRGLRENDERER specific - DON'T SYNC WITH MESA 356 * OR REMOVE OPCODES - FILL in and REWRITE tgsi_info 357 * accordingly. 358 */ 359 enum tgsi_opcode { 360 TGSI_OPCODE_ARL = 0, 361 TGSI_OPCODE_MOV = 1, 362 TGSI_OPCODE_LIT = 2, 363 TGSI_OPCODE_RCP = 3, 364 TGSI_OPCODE_RSQ = 4, 365 TGSI_OPCODE_EXP = 5, 366 TGSI_OPCODE_LOG = 6, 367 TGSI_OPCODE_MUL = 7, 368 TGSI_OPCODE_ADD = 8, 369 TGSI_OPCODE_DP3 = 9, 370 TGSI_OPCODE_DP4 = 10, 371 TGSI_OPCODE_DST = 11, 372 TGSI_OPCODE_MIN = 12, 373 TGSI_OPCODE_MAX = 13, 374 TGSI_OPCODE_SLT = 14, 375 TGSI_OPCODE_SGE = 15, 376 TGSI_OPCODE_MAD = 16, 377 TGSI_OPCODE_SUB = 17, 378 TGSI_OPCODE_LRP = 18, 379 TGSI_OPCODE_FMA = 19, 380 TGSI_OPCODE_SQRT = 20, 381 /* gap */ 382 TGSI_OPCODE_FRC = 24, 383 /* gap */ 384 TGSI_OPCODE_FLR = 26, 385 TGSI_OPCODE_ROUND = 27, 386 TGSI_OPCODE_EX2 = 28, 387 TGSI_OPCODE_LG2 = 29, 388 TGSI_OPCODE_POW = 30, 389 TGSI_OPCODE_XPD = 31, 390 /* gap */ 391 TGSI_OPCODE_ABS = 33, 392 /* gap */ 393 TGSI_OPCODE_DPH = 35, 394 TGSI_OPCODE_COS = 36, 395 TGSI_OPCODE_DDX = 37, 396 TGSI_OPCODE_DDY = 38, 397 TGSI_OPCODE_KILL = 39 /* unconditional */, 398 TGSI_OPCODE_PK2H = 40, 399 TGSI_OPCODE_PK2US = 41, 400 TGSI_OPCODE_PK4B = 42, 401 TGSI_OPCODE_PK4UB = 43, 402 /* gap */ 403 TGSI_OPCODE_SEQ = 45, 404 /* gap */ 405 TGSI_OPCODE_SGT = 47, 406 TGSI_OPCODE_SIN = 48, 407 TGSI_OPCODE_SLE = 49, 408 TGSI_OPCODE_SNE = 50, 409 /* gap */ 410 TGSI_OPCODE_TEX = 52, 411 TGSI_OPCODE_TXD = 53, 412 TGSI_OPCODE_TXP = 54, 413 TGSI_OPCODE_UP2H = 55, 414 TGSI_OPCODE_UP2US = 56, 415 TGSI_OPCODE_UP4B = 57, 416 TGSI_OPCODE_UP4UB = 58, 417 /* gap */ 418 TGSI_OPCODE_ARR = 61, 419 /* gap */ 420 TGSI_OPCODE_CAL = 63, 421 TGSI_OPCODE_RET = 64, 422 TGSI_OPCODE_SSG = 65 /* SGN */, 423 TGSI_OPCODE_CMP = 66, 424 TGSI_OPCODE_SCS = 67, 425 TGSI_OPCODE_TXB = 68, 426 TGSI_OPCODE_FBFETCH = 69, 427 TGSI_OPCODE_DIV = 70, 428 TGSI_OPCODE_DP2 = 71, 429 TGSI_OPCODE_TXL = 72, 430 TGSI_OPCODE_BRK = 73, 431 TGSI_OPCODE_IF = 74, 432 TGSI_OPCODE_UIF = 75, 433 /* gap */ 434 TGSI_OPCODE_ELSE = 77, 435 TGSI_OPCODE_ENDIF = 78, 436 TGSI_OPCODE_DDX_FINE = 79, 437 TGSI_OPCODE_DDY_FINE = 80, 438 /* gap */ 439 TGSI_OPCODE_CEIL = 83, 440 TGSI_OPCODE_I2F = 84, 441 TGSI_OPCODE_NOT = 85, 442 TGSI_OPCODE_TRUNC = 86, 443 TGSI_OPCODE_SHL = 87, 444 /* gap */ 445 TGSI_OPCODE_AND = 89, 446 TGSI_OPCODE_OR = 90, 447 TGSI_OPCODE_MOD = 91, 448 TGSI_OPCODE_XOR = 92, 449 /* gap */ 450 TGSI_OPCODE_TXF = 94, 451 TGSI_OPCODE_TXQ = 95, 452 TGSI_OPCODE_CONT = 96, 453 TGSI_OPCODE_EMIT = 97, 454 TGSI_OPCODE_ENDPRIM = 98, 455 TGSI_OPCODE_BGNLOOP = 99, 456 TGSI_OPCODE_BGNSUB = 100, 457 TGSI_OPCODE_ENDLOOP = 101, 458 TGSI_OPCODE_ENDSUB = 102, 459 /* gap */ 460 TGSI_OPCODE_TXQS = 104, 461 TGSI_OPCODE_RESQ = 105, 462 /* gap */ 463 TGSI_OPCODE_NOP = 107, 464 465 TGSI_OPCODE_FSEQ = 108, 466 TGSI_OPCODE_FSGE = 109, 467 TGSI_OPCODE_FSLT = 110, 468 TGSI_OPCODE_FSNE = 111, 469 470 TGSI_OPCODE_MEMBAR = 112, 471 /* gap */ 472 TGSI_OPCODE_KILL_IF = 116 /* conditional kill */, 473 TGSI_OPCODE_END = 117 /* aka HALT */, 474 TGSI_OPCODE_DFMA = 118, 475 TGSI_OPCODE_F2I = 119, 476 TGSI_OPCODE_IDIV = 120, 477 TGSI_OPCODE_IMAX = 121, 478 TGSI_OPCODE_IMIN = 122, 479 TGSI_OPCODE_INEG = 123, 480 TGSI_OPCODE_ISGE = 124, 481 TGSI_OPCODE_ISHR = 125, 482 TGSI_OPCODE_ISLT = 126, 483 TGSI_OPCODE_F2U = 127, 484 TGSI_OPCODE_U2F = 128, 485 TGSI_OPCODE_UADD = 129, 486 TGSI_OPCODE_UDIV = 130, 487 TGSI_OPCODE_UMAD = 131, 488 TGSI_OPCODE_UMAX = 132, 489 TGSI_OPCODE_UMIN = 133, 490 TGSI_OPCODE_UMOD = 134, 491 TGSI_OPCODE_UMUL = 135, 492 TGSI_OPCODE_USEQ = 136, 493 TGSI_OPCODE_USGE = 137, 494 TGSI_OPCODE_USHR = 138, 495 TGSI_OPCODE_USLT = 139, 496 TGSI_OPCODE_USNE = 140, 497 TGSI_OPCODE_SWITCH = 141, 498 TGSI_OPCODE_CASE = 142, 499 TGSI_OPCODE_DEFAULT = 143, 500 TGSI_OPCODE_ENDSWITCH = 144, 501 502 /* resource related opcodes */ 503 TGSI_OPCODE_SAMPLE = 145, 504 TGSI_OPCODE_SAMPLE_I = 146, 505 TGSI_OPCODE_SAMPLE_I_MS = 147, 506 TGSI_OPCODE_SAMPLE_B = 148, 507 TGSI_OPCODE_SAMPLE_C = 149, 508 TGSI_OPCODE_SAMPLE_C_LZ = 150, 509 TGSI_OPCODE_SAMPLE_D = 151, 510 TGSI_OPCODE_SAMPLE_L = 152, 511 TGSI_OPCODE_GATHER4 = 153, 512 TGSI_OPCODE_SVIEWINFO = 154, 513 TGSI_OPCODE_SAMPLE_POS = 155, 514 TGSI_OPCODE_SAMPLE_INFO = 156, 515 516 TGSI_OPCODE_UARL = 157, 517 TGSI_OPCODE_UCMP = 158, 518 TGSI_OPCODE_IABS = 159, 519 TGSI_OPCODE_ISSG = 160, 520 521 TGSI_OPCODE_LOAD = 161, 522 TGSI_OPCODE_STORE = 162, 523 /* gap */ 524 TGSI_OPCODE_BARRIER = 166, 525 526 TGSI_OPCODE_ATOMUADD = 167, 527 TGSI_OPCODE_ATOMXCHG = 168, 528 TGSI_OPCODE_ATOMCAS = 169, 529 TGSI_OPCODE_ATOMAND = 170, 530 TGSI_OPCODE_ATOMOR = 171, 531 TGSI_OPCODE_ATOMXOR = 172, 532 TGSI_OPCODE_ATOMUMIN = 173, 533 TGSI_OPCODE_ATOMUMAX = 174, 534 TGSI_OPCODE_ATOMIMIN = 175, 535 TGSI_OPCODE_ATOMIMAX = 176, 536 537 /* to be used for shadow cube map compares */ 538 TGSI_OPCODE_TEX2 = 177, 539 TGSI_OPCODE_TXB2 = 178, 540 TGSI_OPCODE_TXL2 = 179, 541 542 TGSI_OPCODE_IMUL_HI = 180, 543 TGSI_OPCODE_UMUL_HI = 181, 544 545 TGSI_OPCODE_TG4 = 182, 546 547 TGSI_OPCODE_LODQ = 183, 548 549 TGSI_OPCODE_IBFE = 184, 550 TGSI_OPCODE_UBFE = 185, 551 TGSI_OPCODE_BFI = 186, 552 TGSI_OPCODE_BREV = 187, 553 TGSI_OPCODE_POPC = 188, 554 TGSI_OPCODE_LSB = 189, 555 TGSI_OPCODE_IMSB = 190, 556 TGSI_OPCODE_UMSB = 191, 557 558 TGSI_OPCODE_INTERP_CENTROID = 192, 559 TGSI_OPCODE_INTERP_SAMPLE = 193, 560 TGSI_OPCODE_INTERP_OFFSET = 194, 561 562 /* sm5 marked opcodes are supported in D3D11 optionally - also DMOV, DMOVC */ 563 TGSI_OPCODE_F2D = 195 /* SM5 */, 564 TGSI_OPCODE_D2F = 196, 565 TGSI_OPCODE_DABS = 197, 566 TGSI_OPCODE_DNEG = 198 /* SM5 */, 567 TGSI_OPCODE_DADD = 199 /* SM5 */, 568 TGSI_OPCODE_DMUL = 200 /* SM5 */, 569 TGSI_OPCODE_DMAX = 201 /* SM5 */, 570 TGSI_OPCODE_DMIN = 202 /* SM5 */, 571 TGSI_OPCODE_DSLT = 203 /* SM5 */, 572 TGSI_OPCODE_DSGE = 204 /* SM5 */, 573 TGSI_OPCODE_DSEQ = 205 /* SM5 */, 574 TGSI_OPCODE_DSNE = 206 /* SM5 */, 575 TGSI_OPCODE_DRCP = 207 /* eg, cayman */, 576 TGSI_OPCODE_DSQRT = 208 /* eg, cayman also has DRSQ */, 577 TGSI_OPCODE_DMAD = 209, 578 TGSI_OPCODE_DFRAC = 210 /* eg, cayman */, 579 TGSI_OPCODE_DLDEXP = 211 /* eg, cayman */, 580 TGSI_OPCODE_DFRACEXP = 212 /* eg, cayman */, 581 TGSI_OPCODE_D2I = 213, 582 TGSI_OPCODE_I2D = 214, 583 TGSI_OPCODE_D2U = 215, 584 TGSI_OPCODE_U2D = 216, 585 TGSI_OPCODE_DRSQ = 217 /* eg, cayman also has DRSQ */, 586 TGSI_OPCODE_DTRUNC = 218 /* nvc0 */, 587 TGSI_OPCODE_DCEIL = 219 /* nvc0 */, 588 TGSI_OPCODE_DFLR = 220 /* nvc0 */, 589 TGSI_OPCODE_DROUND = 221 /* nvc0 */, 590 TGSI_OPCODE_DSSG = 222, 591 TGSI_OPCODE_DDIV = 223, 592 TGSI_OPCODE_CLOCK = 224, 593 594 /* opcodes for ARB_gpu_shader_int64 */ 595 TGSI_OPCODE_I64ABS = 225, 596 TGSI_OPCODE_I64NEG = 226, 597 TGSI_OPCODE_I64SSG = 227, 598 TGSI_OPCODE_I64SLT = 228, 599 TGSI_OPCODE_I64SGE = 229, 600 TGSI_OPCODE_I64MIN = 230, 601 TGSI_OPCODE_I64MAX = 231, 602 TGSI_OPCODE_I64SHR = 232, 603 TGSI_OPCODE_I64DIV = 233, 604 TGSI_OPCODE_I64MOD = 234, 605 TGSI_OPCODE_F2I64 = 235, 606 TGSI_OPCODE_U2I64 = 236, 607 TGSI_OPCODE_I2I64 = 237, 608 TGSI_OPCODE_D2I64 = 238, 609 TGSI_OPCODE_I642F = 239, 610 TGSI_OPCODE_I642D = 240, 611 612 TGSI_OPCODE_U64ADD = 241, 613 TGSI_OPCODE_U64MUL = 242, 614 TGSI_OPCODE_U64SEQ = 243, 615 TGSI_OPCODE_U64SNE = 244, 616 TGSI_OPCODE_U64SLT = 245, 617 TGSI_OPCODE_U64SGE = 246, 618 TGSI_OPCODE_U64MIN = 247, 619 TGSI_OPCODE_U64MAX = 248, 620 TGSI_OPCODE_U64SHL = 249, 621 TGSI_OPCODE_U64SHR = 250, 622 TGSI_OPCODE_U64DIV = 251, 623 TGSI_OPCODE_U64MOD = 252, 624 TGSI_OPCODE_F2U64 = 253, 625 TGSI_OPCODE_D2U64 = 254, 626 TGSI_OPCODE_U642F = 255, 627 TGSI_OPCODE_U642D = 256, 628 629 TGSI_OPCODE_LAST = 257, 630 }; 631 632 /** 633 * Opcode is the operation code to execute. A given operation defines the 634 * semantics how the source registers (if any) are interpreted and what is 635 * written to the destination registers (if any) as a result of execution. 636 * 637 * NumDstRegs and NumSrcRegs is the number of destination and source registers, 638 * respectively. For a given operation code, those numbers are fixed and are 639 * present here only for convenience. 640 * 641 * Saturate controls how are final results in destination registers modified. 642 */ 643 644 /* 645 * VIRGLRENDERER specific - 646 * we no long keep this in sync with mesa, we had to increase the NrTokens 647 * as mesa can remove old opcodes, but the renderer cannot. 648 */ 649 struct tgsi_instruction 650 { 651 unsigned Type : 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */ 652 unsigned NrTokens : 9; /* UINT */ 653 unsigned Opcode : 8; /* TGSI_OPCODE_ */ 654 unsigned Saturate : 1; /* BOOL */ 655 unsigned NumDstRegs : 2; /* UINT */ 656 unsigned NumSrcRegs : 4; /* UINT */ 657 unsigned Label : 1; 658 unsigned Texture : 1; 659 unsigned Memory : 1; 660 unsigned Precise : 1; 661 }; 662 663 /* 664 * If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows. 665 * 666 * If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows. 667 * if texture instruction has a number of offsets, 668 * then tgsi_instruction::Texture::NumOffset of tgsi_texture_offset follow. 669 * 670 * Then, tgsi_instruction::NumDstRegs of tgsi_dst_register follow. 671 * 672 * Then, tgsi_instruction::NumSrcRegs of tgsi_src_register follow. 673 * 674 * tgsi_instruction::NrTokens contains the total number of words that make the 675 * instruction, including the instruction word. 676 */ 677 678 enum tgsi_swizzle { 679 TGSI_SWIZZLE_X, 680 TGSI_SWIZZLE_Y, 681 TGSI_SWIZZLE_Z, 682 TGSI_SWIZZLE_W, 683 }; 684 685 struct tgsi_instruction_label 686 { 687 unsigned Label : 24; /* UINT */ 688 unsigned Padding : 8; 689 }; 690 691 enum tgsi_texture_type { 692 TGSI_TEXTURE_BUFFER, 693 TGSI_TEXTURE_1D, 694 TGSI_TEXTURE_2D, 695 TGSI_TEXTURE_3D, 696 TGSI_TEXTURE_CUBE, 697 TGSI_TEXTURE_RECT, 698 TGSI_TEXTURE_SHADOW1D, 699 TGSI_TEXTURE_SHADOW2D, 700 TGSI_TEXTURE_SHADOWRECT, 701 TGSI_TEXTURE_1D_ARRAY, 702 TGSI_TEXTURE_2D_ARRAY, 703 TGSI_TEXTURE_SHADOW1D_ARRAY, 704 TGSI_TEXTURE_SHADOW2D_ARRAY, 705 TGSI_TEXTURE_SHADOWCUBE, 706 TGSI_TEXTURE_2D_MSAA, 707 TGSI_TEXTURE_2D_ARRAY_MSAA, 708 TGSI_TEXTURE_CUBE_ARRAY, 709 TGSI_TEXTURE_SHADOWCUBE_ARRAY, 710 TGSI_TEXTURE_UNKNOWN, 711 TGSI_TEXTURE_COUNT, 712 }; 713 714 struct tgsi_instruction_texture 715 { 716 unsigned Texture : 8; /* TGSI_TEXTURE_ */ 717 unsigned NumOffsets : 4; 718 unsigned Padding : 20; 719 }; 720 721 /* for texture offsets in GLSL and DirectX. 722 * Generally these always come from TGSI_FILE_IMMEDIATE, 723 * however DX11 appears to have the capability to do 724 * non-constant texture offsets. 725 */ 726 struct tgsi_texture_offset 727 { 728 int Index : 16; 729 unsigned File : 4; /**< one of TGSI_FILE_x */ 730 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */ 731 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */ 732 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */ 733 unsigned Padding : 6; 734 }; 735 736 /** 737 * File specifies the register array to access. 738 * 739 * Index specifies the element number of a register in the register file. 740 * 741 * If Indirect is TRUE, Index should be offset by the X component of the indirect 742 * register that follows. The register can be now fetched into local storage 743 * for further processing. 744 * 745 * If Negate is TRUE, all components of the fetched register are negated. 746 * 747 * The fetched register components are swizzled according to SwizzleX, SwizzleY, 748 * SwizzleZ and SwizzleW. 749 * 750 */ 751 752 struct tgsi_src_register 753 { 754 unsigned File : 4; /* TGSI_FILE_ */ 755 unsigned Indirect : 1; /* BOOL */ 756 unsigned Dimension : 1; /* BOOL */ 757 int Index : 16; /* SINT */ 758 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_ */ 759 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_ */ 760 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_ */ 761 unsigned SwizzleW : 2; /* TGSI_SWIZZLE_ */ 762 unsigned Absolute : 1; /* BOOL */ 763 unsigned Negate : 1; /* BOOL */ 764 }; 765 766 /** 767 * If tgsi_src_register::Indirect is TRUE, tgsi_ind_register follows. 768 * 769 * File, Index and Swizzle are handled the same as in tgsi_src_register. 770 * 771 * If ArrayID is zero the whole register file might be indirectly addressed, 772 * if not only the Declaration with this ArrayID is accessed by this operand. 773 * 774 */ 775 776 struct tgsi_ind_register 777 { 778 unsigned File : 4; /* TGSI_FILE_ */ 779 int Index : 16; /* SINT */ 780 unsigned Swizzle : 2; /* TGSI_SWIZZLE_ */ 781 unsigned ArrayID : 10; /* UINT */ 782 }; 783 784 /** 785 * If tgsi_src_register::Dimension is TRUE, tgsi_dimension follows. 786 */ 787 788 struct tgsi_dimension 789 { 790 unsigned Indirect : 1; /* BOOL */ 791 unsigned Dimension : 1; /* BOOL */ 792 unsigned Padding : 14; 793 int Index : 16; /* SINT */ 794 }; 795 796 struct tgsi_dst_register 797 { 798 unsigned File : 4; /* TGSI_FILE_ */ 799 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */ 800 unsigned Indirect : 1; /* BOOL */ 801 unsigned Dimension : 1; /* BOOL */ 802 int Index : 16; /* SINT */ 803 unsigned Padding : 6; 804 }; 805 806 #define TGSI_MEMORY_COHERENT (1 << 0) 807 #define TGSI_MEMORY_RESTRICT (1 << 1) 808 #define TGSI_MEMORY_VOLATILE (1 << 2) 809 810 /** 811 * Specifies the type of memory access to do for the LOAD/STORE instruction. 812 */ 813 struct tgsi_instruction_memory 814 { 815 unsigned Qualifier : 3; /* TGSI_MEMORY_ */ 816 unsigned Texture : 8; /* only for images: TGSI_TEXTURE_ */ 817 unsigned Format : 10; /* only for images: PIPE_FORMAT_ */ 818 unsigned Padding : 11; 819 }; 820 821 #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0) 822 #define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1) 823 #define TGSI_MEMBAR_SHADER_IMAGE (1 << 2) 824 #define TGSI_MEMBAR_SHARED (1 << 3) 825 #define TGSI_MEMBAR_THREAD_GROUP (1 << 4) 826 827 #ifdef __cplusplus 828 } 829 #endif 830 831 #endif /* P_SHADER_TOKENS_H */ 832