1 /*
2 * Copyright (c) 2023, Google, Inc. All rights reserved
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <arch/arm64/sregs.h>
25 #include <arch/arm64.h>
26 #include <arch/ops.h>
27 #include <inttypes.h>
28 #include <stdbool.h>
29
arch_sve_supported(void)30 bool arch_sve_supported(void) {
31 uint64_t v = ARM64_READ_SYSREG(id_aa64pfr0_el1);
32 return ((v >> ID_AA64PFR0_EL1_SVE_SHIFT) & ID_AA64PFR0_EL1_SVE_MASK) ==
33 ID_AA64PFR0_EL1_SVE_SUPPORTED;
34 }
35
arch_disable_sve(void)36 uint64_t arch_disable_sve(void) {
37 uint64_t v = ARM64_READ_SYSREG(cpacr_el1);
38 uint64_t v_tmp = v & (CPACR_EL1_ZEN_SVE_DISABLE << CPACR_EL1_ZEN_SHIFT);
39 v_tmp = v_tmp & (CPACR_EL1_FPEN_SVE_DISABLE << CPACR_EL1_FPEN_SHIFT);
40
41 ARM64_WRITE_SYSREG(cpacr_el1, v_tmp);
42
43 return v;
44 }
45
arch_enable_sve(void)46 uint64_t arch_enable_sve(void) {
47 uint64_t v = ARM64_READ_SYSREG(cpacr_el1);
48
49 arch_disable_sve();
50 uint64_t v_tmp = v | (CPACR_EL1_ZEN_SVE_ENABLE << CPACR_EL1_ZEN_SHIFT);
51 v_tmp = v_tmp | (CPACR_EL1_FPEN_SVE_ENABLE << CPACR_EL1_FPEN_SHIFT);
52
53 ARM64_WRITE_SYSREG(cpacr_el1, v_tmp);
54
55 return v;
56 }
57
58