1 /*
2 * Copyright (c) 2015 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <debug.h>
24 #include <arch.h>
25 #include <arch/ops.h>
26 #include <arch/arm.h>
27 #include <kernel/thread.h>
28 #include <kernel/debug.h>
29 #include <platform.h>
30 #include <arch/arm/cm.h>
31
32 #if ARM_WITH_CACHE
33
34 /* cache flushing routines for cortex-m cores that support it */
35
arch_disable_cache(uint flags)36 void arch_disable_cache(uint flags)
37 {
38 if (flags & DCACHE)
39 SCB_DisableDCache();
40
41 if (flags & ICACHE)
42 SCB_DisableICache();
43 }
44
arch_enable_cache(uint flags)45 void arch_enable_cache(uint flags)
46 {
47 if (flags & DCACHE)
48 SCB_EnableDCache();
49
50 if (flags & ICACHE)
51 SCB_EnableICache();
52 }
53
54 /* clean (writeback) data in the data cache on the range */
arch_clean_cache_range(addr_t start,size_t len)55 void arch_clean_cache_range(addr_t start, size_t len)
56 {
57 addr_t end = start + len;
58
59 /* align the start address on CACHE_LINE boundary */
60 start &= ~(CACHE_LINE - 1);
61
62 SCB_CleanDCache_by_Addr((uint32_t *)start, end - start);
63 }
64
65 /* clean (writeback) and then evict data from the data cache on the range */
arch_clean_invalidate_cache_range(addr_t start,size_t len)66 void arch_clean_invalidate_cache_range(addr_t start, size_t len)
67 {
68 addr_t end = start + len;
69
70 /* align the start address on CACHE_LINE boundary */
71 start &= ~(CACHE_LINE - 1);
72
73 SCB_CleanInvalidateDCache_by_Addr((uint32_t *)start, end - start);
74 }
75
76 /* evict data from the data cache on the range */
arch_invalidate_cache_range(addr_t start,size_t len)77 void arch_invalidate_cache_range(addr_t start, size_t len)
78 {
79 addr_t end = start + len;
80
81 /* align the start address on CACHE_LINE boundary */
82 start &= ~(CACHE_LINE - 1);
83
84 SCB_InvalidateDCache_by_Addr((uint32_t *)start, end - start);
85 }
86
87 /*
88 * clean (writeback) data on the range and then throw away the instruction cache,
89 * ensuring that new instructions fetched from the range are not stale.
90 */
arch_sync_cache_range(addr_t start,size_t len)91 void arch_sync_cache_range(addr_t start, size_t len)
92 {
93 /* flush the dcache and invalidate the icache, ensuring fresh instructions */
94 arch_clean_cache_range(start, len);
95 SCB_InvalidateICache();
96 }
97
98 #else
99
100 /* doesn't support cache flush, just nop */
101
arch_disable_cache(uint flags)102 void arch_disable_cache(uint flags)
103 {
104 }
105
arch_enable_cache(uint flags)106 void arch_enable_cache(uint flags)
107 {
108 }
109
110 /* clean (writeback) data in the data cache on the range */
arch_clean_cache_range(addr_t start,size_t len)111 void arch_clean_cache_range(addr_t start, size_t len)
112 {
113 }
114
115 /* clean (writeback) and then evict data from the data cache on the range */
arch_clean_invalidate_cache_range(addr_t start,size_t len)116 void arch_clean_invalidate_cache_range(addr_t start, size_t len)
117 {
118 }
119
120 /* evict data from the data cache on the range */
arch_invalidate_cache_range(addr_t start,size_t len)121 void arch_invalidate_cache_range(addr_t start, size_t len)
122 {
123 }
124
125 /*
126 * clean (writeback) data on the range and then throw away the instruction cache,
127 * ensuring that new instructions fetched from the range are not stale.
128 */
arch_sync_cache_range(addr_t start,size_t len)129 void arch_sync_cache_range(addr_t start, size_t len)
130 {
131 }
132
133 #endif // !ARM_WITH_CACHE
134
135