1 /*
2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/arm/gicv2.h>
14 #include <lib/mmio.h>
15 #include <lib/psci/psci.h>
16 #include <plat/arm/common/plat_arm.h>
17 #include <plat/common/platform.h>
18
19 #include <plat_private.h>
20 #include "pm_client.h"
21 #include "zynqmp_pm_api_sys.h"
22
23 static uintptr_t zynqmp_sec_entry;
24
zynqmp_cpu_standby(plat_local_state_t cpu_state)25 static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
26 {
27 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
28
29 dsb();
30 wfi();
31 }
32
zynqmp_pwr_domain_on(u_register_t mpidr)33 static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
34 {
35 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
36 const struct pm_proc *proc;
37 uint32_t buff[3];
38 enum pm_ret_status ret;
39
40 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
41
42 if (cpu_id == -1) {
43 return PSCI_E_INTERN_FAIL;
44 }
45
46 proc = pm_get_proc(cpu_id);
47 if (proc == NULL) {
48 return PSCI_E_INTERN_FAIL;
49 }
50
51 /* Check the APU proc status before wakeup */
52 ret = pm_get_node_status(proc->node_id, buff);
53 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) {
54 return PSCI_E_INTERN_FAIL;
55 }
56
57 /* Clear power down request */
58 pm_client_wakeup(proc);
59
60 /* Send request to PMU to wake up selected APU CPU core */
61 pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
62
63 return PSCI_E_SUCCESS;
64 }
65
zynqmp_pwr_domain_off(const psci_power_state_t * target_state)66 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
67 {
68 uint32_t cpu_id = plat_my_core_pos();
69 const struct pm_proc *proc = pm_get_proc(cpu_id);
70
71 if (proc == NULL) {
72 return;
73 }
74
75 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
76 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
77 __func__, i, target_state->pwr_domain_state[i]);
78 }
79
80 /* Prevent interrupts from spuriously waking up this cpu */
81 gicv2_cpuif_disable();
82
83 /*
84 * Send request to PMU to power down the appropriate APU CPU
85 * core.
86 * According to PSCI specification, CPU_off function does not
87 * have resume address and CPU core can only be woken up
88 * invoking CPU_on function, during which resume address will
89 * be set.
90 */
91 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
92 }
93
zynqmp_pwr_domain_suspend(const psci_power_state_t * target_state)94 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
95 {
96 uint32_t state;
97 uint32_t cpu_id = plat_my_core_pos();
98 const struct pm_proc *proc = pm_get_proc(cpu_id);
99
100 if (proc == NULL) {
101 return;
102 }
103
104 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
105 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
106 __func__, i, target_state->pwr_domain_state[i]);
107
108 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
109 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
110
111 /* Send request to PMU to suspend this core */
112 pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
113
114 /* APU is to be turned off */
115 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
116 /* disable coherency */
117 plat_arm_interconnect_exit_coherency();
118 }
119 }
120
zynqmp_pwr_domain_on_finish(const psci_power_state_t * target_state)121 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
122 {
123 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
124 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
125 __func__, i, target_state->pwr_domain_state[i]);
126 }
127 plat_arm_gic_pcpu_init();
128 gicv2_cpuif_enable();
129 }
130
zynqmp_pwr_domain_suspend_finish(const psci_power_state_t * target_state)131 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
132 {
133 uint32_t cpu_id = plat_my_core_pos();
134 const struct pm_proc *proc = pm_get_proc(cpu_id);
135
136 if (proc == NULL) {
137 return;
138 }
139
140 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
141 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
142 __func__, i, target_state->pwr_domain_state[i]);
143 }
144
145 /* Clear the APU power control register for this cpu */
146 pm_client_wakeup(proc);
147
148 /* enable coherency */
149 plat_arm_interconnect_enter_coherency();
150 /* APU was turned off */
151 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
152 plat_arm_gic_init();
153 } else {
154 gicv2_cpuif_enable();
155 gicv2_pcpu_distif_init();
156 }
157 }
158
159 /*******************************************************************************
160 * ZynqMP handlers to shutdown/reboot the system
161 ******************************************************************************/
162
zynqmp_system_off(void)163 static void __dead2 zynqmp_system_off(void)
164 {
165 /* disable coherency */
166 plat_arm_interconnect_exit_coherency();
167
168 /* Send the power down request to the PMU */
169 pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
170 pm_get_shutdown_scope());
171
172 while (1) {
173 wfi();
174 }
175 }
176
zynqmp_system_reset(void)177 static void __dead2 zynqmp_system_reset(void)
178 {
179 /* disable coherency */
180 plat_arm_interconnect_exit_coherency();
181
182 /* Send the system reset request to the PMU */
183 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
184 pm_get_shutdown_scope());
185
186 while (1) {
187 wfi();
188 }
189 }
190
zynqmp_validate_power_state(uint32_t power_state,psci_power_state_t * req_state)191 static int32_t zynqmp_validate_power_state(uint32_t power_state,
192 psci_power_state_t *req_state)
193 {
194 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
195
196 uint32_t pstate = psci_get_pstate_type(power_state);
197
198 assert(req_state);
199
200 /* Sanity check the requested state */
201 if (pstate == PSTATE_TYPE_STANDBY) {
202 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
203 } else {
204 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
205 }
206 /* We expect the 'state id' to be zero */
207 if (psci_get_pstate_id(power_state)) {
208 return PSCI_E_INVALID_PARAMS;
209 }
210
211 return PSCI_E_SUCCESS;
212 }
213
zynqmp_get_sys_suspend_power_state(psci_power_state_t * req_state)214 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
215 {
216 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
217 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
218 }
219
220 /*******************************************************************************
221 * Export the platform handlers to enable psci to invoke them
222 ******************************************************************************/
223 static const struct plat_psci_ops zynqmp_psci_ops = {
224 .cpu_standby = zynqmp_cpu_standby,
225 .pwr_domain_on = zynqmp_pwr_domain_on,
226 .pwr_domain_off = zynqmp_pwr_domain_off,
227 .pwr_domain_suspend = zynqmp_pwr_domain_suspend,
228 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish,
229 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish,
230 .system_off = zynqmp_system_off,
231 .system_reset = zynqmp_system_reset,
232 .validate_power_state = zynqmp_validate_power_state,
233 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
234 };
235
236 /*******************************************************************************
237 * Export the platform specific power ops.
238 ******************************************************************************/
plat_setup_psci_ops(uintptr_t sec_entrypoint,const struct plat_psci_ops ** psci_ops)239 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
240 const struct plat_psci_ops **psci_ops)
241 {
242 zynqmp_sec_entry = sec_entrypoint;
243
244 *psci_ops = &zynqmp_psci_ops;
245
246 return 0;
247 }
248