1 /*
2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * Versal IPI agent registers access management
10 */
11
12 #include <lib/utils_def.h>
13
14 #include <ipi.h>
15 #include <plat_ipi.h>
16
17 /* versal ipi configuration table */
18 static const struct ipi_config versal_ipi_table[] = {
19 /* PMC IPI */
20 [IPI_ID_PMC] = {
21 .ipi_bit_mask = PMC_IPI_TRIG_BIT,
22 .ipi_reg_base = PMC_REG_BASE,
23 .secure_only = IPI_SECURE_MASK,
24 },
25
26 /* A72 IPI */
27 [IPI_ID_APU] = {
28 .ipi_bit_mask = IPI0_TRIG_BIT,
29 .ipi_reg_base = IPI0_REG_BASE,
30 .secure_only = 0U,
31 },
32
33 /* RPU0 IPI */
34 [IPI_ID_RPU0] = {
35 .ipi_bit_mask = IPI1_TRIG_BIT,
36 .ipi_reg_base = IPI1_REG_BASE,
37 .secure_only = 0U,
38 },
39
40 /* RPU1 IPI */
41 [IPI_ID_RPU1] = {
42 .ipi_bit_mask = IPI2_TRIG_BIT,
43 .ipi_reg_base = IPI2_REG_BASE,
44 .secure_only = 0U,
45 },
46
47 /* IPI3 IPI */
48 [IPI_ID_3] = {
49 .ipi_bit_mask = IPI3_TRIG_BIT,
50 .ipi_reg_base = IPI3_REG_BASE,
51 .secure_only = 0U,
52 },
53
54 /* IPI4 IPI */
55 [IPI_ID_4] = {
56 .ipi_bit_mask = IPI4_TRIG_BIT,
57 .ipi_reg_base = IPI4_REG_BASE,
58 .secure_only = 0U,
59 },
60
61 /* IPI5 IPI */
62 [IPI_ID_5] = {
63 .ipi_bit_mask = IPI5_TRIG_BIT,
64 .ipi_reg_base = IPI5_REG_BASE,
65 .secure_only = 0U,
66 },
67 };
68
69 /* versal_ipi_config_table_init() - Initialize versal IPI configuration data.
70 * @ipi_config_table: IPI configuration table.
71 * @ipi_total: Total number of IPI available.
72 *
73 */
versal_ipi_config_table_init(void)74 void versal_ipi_config_table_init(void)
75 {
76 ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table));
77 }
78