1 /* 2 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_PRIVATE_H 10 #define PLAT_PRIVATE_H 11 12 #include <bl31/interrupt_mgmt.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 15 typedef struct versal_intr_info_type_el3 { 16 uint32_t id; 17 interrupt_type_handler_t handler; 18 } versal_intr_info_type_el3_t; 19 20 uint32_t get_uart_clk(void); 21 void versal_config_setup(void); 22 23 const mmap_region_t *plat_get_mmap(void); 24 25 extern uint32_t cpu_clock, platform_id, platform_version; 26 27 void board_detection(void); 28 void plat_versal_gic_driver_init(void); 29 void plat_versal_gic_init(void); 30 void plat_versal_gic_cpuif_enable(void); 31 void plat_versal_gic_cpuif_disable(void); 32 void plat_versal_gic_pcpu_init(void); 33 void plat_versal_gic_save(void); 34 void plat_versal_gic_resume(void); 35 36 uint32_t versal_calc_core_pos(u_register_t mpidr); 37 /* 38 * Register handler to specific GIC entrance 39 * for INTR_TYPE_EL3 type of interrupt 40 */ 41 int32_t request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); 42 43 #endif /* PLAT_PRIVATE_H */ 44