1/*
2 * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef PLAT_MACROS_S
9#define PLAT_MACROS_S
10
11#include <drivers/arm/gic_common.h>
12#include <drivers/arm/gicv2.h>
13#include <drivers/arm/gicv3.h>
14
15#include "../include/platform_def.h"
16
17.section .rodata.gic_reg_name, "aS"
18/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
19gicc_regs:
20	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
21
22/* Applicable only to GICv3 with SRE enabled */
23icc_regs:
24	.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
25
26/* Registers common to both GICv2 and GICv3 */
27gicd_pend_reg:
28	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
29newline:
30	.asciz "\n"
31spacer:
32	.asciz ":\t\t0x"
33
34	/* ---------------------------------------------
35	 * The below utility macro prints out relevant GIC
36	 * registers whenever an unhandled exception is
37	 * taken in BL31 on Versal platform.
38	 * Expects: GICD base in x16, GICC base in x17
39	 * Clobbers: x0 - x10, sp
40	 * ---------------------------------------------
41	 */
42	.macro versal_print_gic_regs
43	/* Check for GICv3 system register access */
44	mrs	x7, id_aa64pfr0_el1
45	ubfx	x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
46	cmp	x7, #1
47	b.ne	print_gicv2
48
49	/* Check for SRE enable */
50	mrs	x8, ICC_SRE_EL3
51	tst	x8, #ICC_SRE_SRE_BIT
52	b.eq	print_gicv2
53
54	/* Load the icc reg list to x6 */
55	adr	x6, icc_regs
56	/* Load the icc regs to gp regs used by str_in_crash_buf_print */
57	mrs	x8, ICC_HPPIR0_EL1
58	mrs	x9, ICC_HPPIR1_EL1
59	mrs	x10, ICC_CTLR_EL3
60	/* Store to the crash buf and print to console */
61	bl	str_in_crash_buf_print
62	b	print_gic_common
63
64print_gicv2:
65	/* Load the gicc reg list to x6 */
66	adr	x6, gicc_regs
67	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
68	ldr	w8, [x17, #GICC_HPPIR]
69	ldr	w9, [x17, #GICC_AHPPIR]
70	ldr	w10, [x17, #GICC_CTLR]
71	/* Store to the crash buf and print to console */
72	bl	str_in_crash_buf_print
73
74print_gic_common:
75	/* Print the GICD_ISPENDR regs */
76	add	x7, x16, #GICD_ISPENDR
77	adr	x4, gicd_pend_reg
78	bl	asm_print_str
79gicd_ispendr_loop:
80	sub	x4, x7, x16
81	cmp	x4, #0x280
82	b.eq	exit_print_gic_regs
83	bl	asm_print_hex
84
85	adr	x4, spacer
86	bl	asm_print_str
87
88	ldr	x4, [x7], #8
89	bl	asm_print_hex
90
91	adr	x4, newline
92	bl	asm_print_str
93	b	gicd_ispendr_loop
94exit_print_gic_regs:
95	.endm
96
97	/* ---------------------------------------------
98	 * The below required platform porting macro
99	 * prints out relevant GIC and CCI registers
100	 * whenever an unhandled exception is taken in
101	 * BL31.
102	 * Clobbers: x0 - x10, x16, x17, sp
103	 * ---------------------------------------------
104	 */
105	.macro plat_crash_print_regs
106	mov_imm	x17, PLAT_ARM_GICD_BASE
107	mov_imm	x16, PLAT_ARM_GICR_BASE
108	versal_print_gic_regs
109	.endm
110
111#endif /* PLAT_MACROS_S */
112