1 /*
2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <platform_def.h>
8 
9 #include <assert.h>
10 #include <common/bl_common.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gicv3.h>
13 #include <lib/utils.h>
14 #include <lib/mmio.h>
15 #include <plat/common/platform.h>
16 
17 #include <k3_gicv3.h>
18 
19 /* The GICv3 driver only needs to be initialized in EL3 */
20 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
21 
22 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
23 static gicv3_dist_ctx_t dist_ctx;
24 
25 static const interrupt_prop_t k3_interrupt_props[] = {
26 	PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
27 	PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
28 };
29 
k3_mpidr_to_core_pos(unsigned long mpidr)30 static unsigned int k3_mpidr_to_core_pos(unsigned long mpidr)
31 {
32 	return (unsigned int)plat_core_pos_by_mpidr(mpidr);
33 }
34 
35 gicv3_driver_data_t k3_gic_data = {
36 	.rdistif_num = PLATFORM_CORE_COUNT,
37 	.rdistif_base_addrs = rdistif_base_addrs,
38 	.interrupt_props = k3_interrupt_props,
39 	.interrupt_props_num = ARRAY_SIZE(k3_interrupt_props),
40 	.mpidr_to_core_pos = k3_mpidr_to_core_pos,
41 };
42 
k3_gic_driver_init(uintptr_t gic_base)43 void k3_gic_driver_init(uintptr_t gic_base)
44 {
45 	/* GIC Distributor is always at the base of the IP */
46 	uintptr_t gicd_base = gic_base;
47 	/* GIC Redistributor base is run-time detected */
48 	uintptr_t gicr_base = 0;
49 
50 	for (unsigned int gicr_shift = 18; gicr_shift < 21; gicr_shift++) {
51 		uintptr_t gicr_check = gic_base + BIT(gicr_shift);
52 		uint32_t iidr = mmio_read_32(gicr_check + GICR_IIDR);
53 		if (iidr != 0) {
54 			/* Found the GICR base */
55 			gicr_base = gicr_check;
56 			break;
57 		}
58 	}
59 	/* Assert if we have not found the GICR base */
60 	assert(gicr_base != 0);
61 
62 	/*
63 	 * The GICv3 driver is initialized in EL3 and does not need
64 	 * to be initialized again in SEL1. This is because the S-EL1
65 	 * can use GIC system registers to manage interrupts and does
66 	 * not need GIC interface base addresses to be configured.
67 	 */
68 	k3_gic_data.gicd_base = gicd_base;
69 	k3_gic_data.gicr_base = gicr_base;
70 	gicv3_driver_init(&k3_gic_data);
71 }
72 
k3_gic_init(void)73 void k3_gic_init(void)
74 {
75 	gicv3_distif_init();
76 	gicv3_rdistif_init(plat_my_core_pos());
77 	gicv3_cpuif_enable(plat_my_core_pos());
78 }
79 
k3_gic_cpuif_enable(void)80 void k3_gic_cpuif_enable(void)
81 {
82 	gicv3_cpuif_enable(plat_my_core_pos());
83 }
84 
k3_gic_cpuif_disable(void)85 void k3_gic_cpuif_disable(void)
86 {
87 	gicv3_cpuif_disable(plat_my_core_pos());
88 }
89 
k3_gic_pcpu_init(void)90 void k3_gic_pcpu_init(void)
91 {
92 	gicv3_rdistif_init(plat_my_core_pos());
93 }
94 
k3_gic_save_context(void)95 void k3_gic_save_context(void)
96 {
97 	for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
98 		gicv3_rdistif_save(i, &rdist_ctx[i]);
99 	}
100 	gicv3_distif_save(&dist_ctx);
101 }
102 
k3_gic_restore_context(void)103 void k3_gic_restore_context(void)
104 {
105 	gicv3_distif_init_restore(&dist_ctx);
106 	for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
107 		gicv3_rdistif_init_restore(i, &rdist_ctx[i]);
108 	}
109 }
110