1 /*
2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP2_DEF_H
8 #define STM32MP2_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #ifndef __ASSEMBLER__
12 #include <drivers/st/bsec.h>
13 #endif
14 #include <drivers/st/stm32mp25_rcc.h>
15 #include <dt-bindings/clock/stm32mp25-clks.h>
16 #include <dt-bindings/clock/stm32mp25-clksrc.h>
17 #include <dt-bindings/reset/stm32mp25-resets.h>
18
19 #ifndef __ASSEMBLER__
20 #include <boot_api.h>
21 #include <stm32mp2_private.h>
22 #include <stm32mp_common.h>
23 #include <stm32mp_dt.h>
24 #include <stm32mp_shared_resources.h>
25 #endif
26
27 /*******************************************************************************
28 * STM32MP2 memory map related constants
29 ******************************************************************************/
30 #define STM32MP_SYSRAM_BASE U(0x0E000000)
31 #define STM32MP_SYSRAM_SIZE U(0x00040000)
32
33 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
34 #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
35
36 /* DDR configuration */
37 #define STM32MP_DDR_BASE U(0x80000000)
38 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
39
40 /* DDR power initializations */
41 #ifndef __ASSEMBLER__
42 enum ddr_type {
43 STM32MP_DDR3,
44 STM32MP_DDR4,
45 STM32MP_LPDDR4
46 };
47 #endif
48
49 /* Section used inside TF binaries */
50 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
51 /* 512 Octets reserved for header */
52 #define STM32MP_HEADER_SIZE U(0x00000200)
53 #define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \
54 STM32MP_PARAM_LOAD_SIZE)
55
56 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
57 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
58
59 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
60 STM32MP_PARAM_LOAD_SIZE + \
61 STM32MP_HEADER_SIZE)
62
63 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
64 (STM32MP_PARAM_LOAD_SIZE + \
65 STM32MP_HEADER_SIZE))
66
67 #define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */
68
69 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
70 STM32MP_SEC_SYSRAM_SIZE - \
71 STM32MP_BL2_SIZE)
72
73 /* BL2 and BL32/sp_min require 4 tables */
74 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
75
76 /*
77 * MAX_MMAP_REGIONS is usually:
78 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
79 */
80 #define MAX_MMAP_REGIONS 6
81
82 /* DTB initialization value */
83 #define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
84
85 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
86 STM32MP_BL2_DTB_SIZE)
87
88 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
89 #define STM32MP_BL33_MAX_SIZE U(0x400000)
90
91 /*******************************************************************************
92 * STM32MP2 RCC
93 ******************************************************************************/
94 #define RCC_BASE U(0x44200000)
95
96 /*******************************************************************************
97 * STM32MP2 PWR
98 ******************************************************************************/
99 #define PWR_BASE U(0x44210000)
100
101 /*******************************************************************************
102 * STM32MP2 GPIO
103 ******************************************************************************/
104 #define GPIOA_BASE U(0x44240000)
105 #define GPIOB_BASE U(0x44250000)
106 #define GPIOC_BASE U(0x44260000)
107 #define GPIOD_BASE U(0x44270000)
108 #define GPIOE_BASE U(0x44280000)
109 #define GPIOF_BASE U(0x44290000)
110 #define GPIOG_BASE U(0x442A0000)
111 #define GPIOH_BASE U(0x442B0000)
112 #define GPIOI_BASE U(0x442C0000)
113 #define GPIOJ_BASE U(0x442D0000)
114 #define GPIOK_BASE U(0x442E0000)
115 #define GPIOZ_BASE U(0x46200000)
116 #define GPIO_BANK_OFFSET U(0x10000)
117
118 #define STM32MP_GPIOS_PIN_MAX_COUNT 16
119 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
120
121 /*******************************************************************************
122 * STM32MP2 UART
123 ******************************************************************************/
124 #define USART1_BASE U(0x40330000)
125 #define USART2_BASE U(0x400E0000)
126 #define USART3_BASE U(0x400F0000)
127 #define UART4_BASE U(0x40100000)
128 #define UART5_BASE U(0x40110000)
129 #define USART6_BASE U(0x40220000)
130 #define UART7_BASE U(0x40370000)
131 #define UART8_BASE U(0x40380000)
132 #define UART9_BASE U(0x402C0000)
133 #define STM32MP_NB_OF_UART U(9)
134
135 /* For UART crash console */
136 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
137 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
138 #define STM32MP_DEBUG_USART_BASE USART2_BASE
139 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
140 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
141 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
142 #define DEBUG_UART_TX_GPIO_PORT 4
143 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
144 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
145 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
146 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
147 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
148 #define DEBUG_UART_RST_REG RCC_USART2CFGR
149 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
150 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
151 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
152
153 /*******************************************************************************
154 * STM32MP2 SDMMC
155 ******************************************************************************/
156 #define STM32MP_SDMMC1_BASE U(0x48220000)
157 #define STM32MP_SDMMC2_BASE U(0x48230000)
158 #define STM32MP_SDMMC3_BASE U(0x48240000)
159
160 /*******************************************************************************
161 * STM32MP2 BSEC / OTP
162 ******************************************************************************/
163 /*
164 * 367 available OTPs, the other are masked
165 * - ECIES key: 368 to 375 (only readable by bootrom)
166 * - HWKEY: 376 to 383 (never reloadable or readable)
167 */
168 #define STM32MP2_OTP_MAX_ID U(0x16F)
169 #define STM32MP2_MID_OTP_START U(0x80)
170 #define STM32MP2_UPPER_OTP_START U(0x100)
171
172 /* OTP labels */
173 #define PART_NUMBER_OTP "part-number-otp"
174 #define PACKAGE_OTP "package-otp"
175 #define HCONF1_OTP "otp124"
176 #define NAND_OTP "otp16"
177 #define NAND2_OTP "otp20"
178 #define BOARD_ID_OTP "board-id"
179 #define UID_OTP "uid-otp"
180 #define LIFECYCLE2_OTP "otp18"
181 #define PKH_OTP "otp144"
182 #define ENCKEY_OTP "otp260"
183
184 /* OTP mask */
185 /* PACKAGE */
186 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
187 #define PACKAGE_OTP_PKG_SHIFT U(0)
188
189 /* IWDG OTP */
190 #define HCONF1_OTP_IWDG_HW_POS U(0)
191 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
192 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
193
194 /* NAND OTP */
195 /* NAND parameter storage flag */
196 #define NAND_PARAM_STORED_IN_OTP BIT_32(31)
197
198 /* NAND page size in bytes */
199 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
200 #define NAND_PAGE_SIZE_SHIFT U(29)
201 #define NAND_PAGE_SIZE_2K U(0)
202 #define NAND_PAGE_SIZE_4K U(1)
203 #define NAND_PAGE_SIZE_8K U(2)
204
205 /* NAND block size in pages */
206 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
207 #define NAND_BLOCK_SIZE_SHIFT U(27)
208 #define NAND_BLOCK_SIZE_64_PAGES U(0)
209 #define NAND_BLOCK_SIZE_128_PAGES U(1)
210 #define NAND_BLOCK_SIZE_256_PAGES U(2)
211
212 /* NAND number of block (in unit of 256 blocks) */
213 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
214 #define NAND_BLOCK_NB_SHIFT U(19)
215 #define NAND_BLOCK_NB_UNIT U(256)
216
217 /* NAND bus width in bits */
218 #define NAND_WIDTH_MASK BIT_32(18)
219 #define NAND_WIDTH_SHIFT U(18)
220
221 /* NAND number of ECC bits per 512 bytes */
222 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
223 #define NAND_ECC_BIT_NB_SHIFT U(15)
224 #define NAND_ECC_BIT_NB_UNSET U(0)
225 #define NAND_ECC_BIT_NB_1_BITS U(1)
226 #define NAND_ECC_BIT_NB_4_BITS U(2)
227 #define NAND_ECC_BIT_NB_8_BITS U(3)
228 #define NAND_ECC_ON_DIE U(4)
229
230 /* NAND number of planes */
231 #define NAND_PLANE_BIT_NB_MASK BIT_32(14)
232
233 /* NAND2 OTP */
234 #define NAND2_PAGE_SIZE_SHIFT U(16)
235
236 /* NAND2 config distribution */
237 #define NAND2_CONFIG_DISTRIB BIT_32(0)
238 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
239 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
240
241 /* MONOTONIC OTP */
242 #define MAX_MONOTONIC_VALUE U(32)
243
244 /* UID OTP */
245 #define UID_WORD_NB U(3)
246
247 /* Lifecycle OTP */
248 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
249
250 /*******************************************************************************
251 * STM32MP2 TAMP
252 ******************************************************************************/
253 #define PLAT_MAX_TAMP_INT U(5)
254 #define PLAT_MAX_TAMP_EXT U(3)
255 #define TAMP_BASE U(0x46010000)
256 #define TAMP_SMCR (TAMP_BASE + U(0x20))
257 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
258 #define TAMP_BKP_REG_CLK CK_BUS_RTC
259 #define TAMP_BKP_SEC_NUMBER U(10)
260 #define TAMP_COUNTR U(0x40)
261
262 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)263 static inline uintptr_t tamp_bkpr(uint32_t idx)
264 {
265 return TAMP_BKP_REGISTER_BASE + (idx << 2);
266 }
267 #endif
268
269 /*******************************************************************************
270 * STM32MP2 DDRCTRL
271 ******************************************************************************/
272 #define DDRCTRL_BASE U(0x48040000)
273
274 /*******************************************************************************
275 * STM32MP2 DDRDBG
276 ******************************************************************************/
277 #define DDRDBG_BASE U(0x48050000)
278
279 /*******************************************************************************
280 * STM32MP2 DDRPHYC
281 ******************************************************************************/
282 #define DDRPHYC_BASE U(0x48C00000)
283
284 /*******************************************************************************
285 * Miscellaneous STM32MP1 peripherals base address
286 ******************************************************************************/
287 #define BSEC_BASE U(0x44000000)
288 #define DBGMCU_BASE U(0x4A010000)
289 #define HASH_BASE U(0x42010000)
290 #define RTC_BASE U(0x46000000)
291 #define STGEN_BASE U(0x48080000)
292 #define SYSCFG_BASE U(0x44230000)
293
294 /*******************************************************************************
295 * REGULATORS
296 ******************************************************************************/
297 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
298 #define PLAT_NB_RDEVS U(19)
299 /* 2 FIXED */
300 #define PLAT_NB_FIXED_REGUS U(2)
301 /* No GPIO regu */
302 #define PLAT_NB_GPIO_REGUS U(0)
303
304 /*******************************************************************************
305 * Device Tree defines
306 ******************************************************************************/
307 #define DT_BSEC_COMPAT "st,stm32mp25-bsec"
308 #define DT_DDR_COMPAT "st,stm32mp2-ddr"
309 #define DT_PWR_COMPAT "st,stm32mp25-pwr"
310 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
311 #define DT_UART_COMPAT "st,stm32h7-uart"
312
313 #endif /* STM32MP2_DEF_H */
314